High-Speed CMOS Logic Dual Monostable Multivibrator with Reset De
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CD54HC221, CD74HC221, CD74HCT221
High-Speed CMOS Logic Dual Monostable Multivibrator with Reset
Description
'HC221 CD74HCT221 dual monostable multivibrators with reset. external resistor (RX) external capacitor (CX) control timing accuracy circuit. Adjustment provides wide range output pulse widths from terminals. Pulse triggering input occurs particular voltage level related rise fall time trigger pulse. Once triggered, outputs independent further trigger inputs output pulse terminated level Reset pin. Trailing Edge triggering leading-edge-triggering inputs provided triggering from either edge input pulse. power reset. either Mono used each input unused device) must terminated either high low. minimum value external resistance, typically 500. minimum value external capacitance, 0pF. calculation pulse width RXCX 4.5V.
Features
Overriding RESET Terminates Output Pulse
/Title (CD74 HC221 CD74 HCT22 /Subject (High Speed CMOS Logic Dual Monos table Multi-
Triggering from Leading Trailing Edge Buffered Outputs Separate Resets Wide Range Output-Pulse Widths Schmitt Trigger Inputs Fanout (Over Temperature Range) Standard Outputs LSTTL Loads Driver Outputs LSTTL Loads Wide Operating Temperature Range -55oC 125oC Balanced Propagation Delay Transition Times Significant Power Reduction Compared LSTTL Logic Types Operation High Noise Immunity: 30%, Types 4.5V 5.5V Operation Direct LSTTL Input Logic Compatibility, VIL= 0.8V (Max), (Min) CMOS Input Compatibility, VOL,
Ordering Information
PART NUMBER CD54HC221F3A CD74HC221E CD74HC221M CD74HC221MT CD74HC221M96 TEMP. RANGE (oC) PACKAGE CERDIP PDIP SOIC SOIC SOIC TSSOP TSSOP TSSOP PDIP SOIC SOIC SOIC
Pinout
CD54HC221 (CERDIP) CD74HC221 (PDIP, SOIC, SOP, TSSOP) CD74HCT221 (PDIP, SOIC) VIEW
2CXRX 1CXRX
CD74HC221NSR CD74HC221PW CD74HC221PWR CD74HC221PWT CD74HCT221E CD74HCT221M CD74HCT221MT CD74HCT221M96
NOTE: When ordering, entire part number. suffixes denote tape reel. suffix denotes small-quantity reel 250.
CAUTION: These devices sensitive electrostatic discharge. Users should follow proper Handling Procedures. Copyright
2003, Texas Instruments Incorporated
CD54HC221, CD74HC221, CD74HCT221 Functional Diagram
2CXRX MONO MONO 1CXRX
TRUTH TABLE INPUTS (Note (Note OUTPUTS
High Voltage Level, Voltage Level, Irrelevant, Transition from High Level, Transition from High Level, High Level Pulse, Level Pulse NOTE: this combination reset input must following sequence must used: must high low; then must high. reset input goes from lowto-high device will triggered.
CD54HC221, CD74HC221, CD74HCT221 Logic Diagram
(10) (11) RESET MIRROR VOLTAGE MASK MAIN PULLDOWN (12) (13)
RXCX
CD54HC221, CD74HC221, CD74HCT221
Absolute Maximum Ratings
Supply Voltage, -0.5V Input Diode Current, -0.5V 0.5V .±20mA Output Diode Current, -0.5V 0.5V .±20mA Drain Current, Output, -0.5V 0.5V. .±25mA Output Source Sink Current Output Pin, -0.5V 0.5V .±25mA Ground Current, .±50mA
Thermal Information
Package Thermal Impedance, (see Note (PDIP) Package 67oC/W (SOIC) Package. 73oC/W (SOP) Package 64oC/W (TSSOP) Package 108oC/W Maximum Junction Temperature (Plastic Package) 150oC Maximum Storage Temperature Range .-65oC 150oC Maximum Lead Temperature (Soldering 10s) 300oC (SOIC Lead Tips Only)
Operating Conditions
Temperature Range, -55oC 125oC Supply Voltage Range, Types Types .4.5V 5.5V Input Output Voltage, Input Rise Fall Time, Inputs 1000ns (Max) 4.5V. 500ns (Max) 400ns (Max) Input Rise Fall Time, Input Unlimited (Max) 4.5V. Unlimited (Max) Unlimited (Max)
CAUTION: Stresses above those listed "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied.
NOTE: package thermal impedance calculated accordance with JESD 51-7.
Electrical Specifications
TEST CONDITIONS PARAMETER TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads -0.02 -0.02 -0.02 -5.2 0.02 0.02 0.02 3.15 3.98 5.48 1.35 0.26 0.26 3.15 3.84 5.34 1.35 0.33 0.33 3.15 1.35 SYMBOL (mA) 25oC -40oC 85oC -55oC 125oC UNITS
CD54HC221, CD74HC221, CD74HCT221
Electrical Specifications
(Continued) TEST CONDITIONS PARAMETER Input Leakage Current Quiescent Device Current TYPES High Level Input Voltage Level Input Voltage High Level Output Voltage CMOS Loads High Level Output Voltage Loads Level Output Voltage CMOS Loads Level Output Voltage Loads Input Leakage Current Quiescent Device Current Additional Quiescent Device Current Input Pin: Unit Load NOTE: dual-supply systems theoretical worst case 2.4V, 5.5V) specification 1.8mA. (Note -2.1 -0.02 SYMBOL (mA) 25oC ±0.1 -40oC 85oC -55oC 125oC UNITS
3.98
3.84
0.02
0.26
0.33
±0.1
Input Loading Table
INPUT Inputs UNIT LOADS
NOTE: Unit Load limit specified Electrical Table, e.g., 360µA 25oC.
Prerequisite Switching Function
25oC PARAMETER TYPES Input Pulse Width Input Pulse Width SYMBOL -40oC 85oC -55oC 125oC UNITS
CD54HC221, CD74HC221, CD74HCT221
Prerequisite Switching Function
PARAMETER Input Pulse Width Reset SYMBOL (Continued) 25oC Recovery Time Output Pulse Width 0.1µF Output Pulse Width 28pF, 1000pF, 1000pF, TYPES Input Pulse Width Input Pulse Width Input Pulse Width Reset Recovery Time Output Pulse Width 0.1µF Output Pulse Width 28pF, 1000pF, 1000pF, -40oC 85oC -55oC 125oC UNITS
Switching Specifications Input
TEST CONDITIONS 25oC -40oC 85oC -55oC 125oC UNITS
PARAMETER TYPES Propagation Delay, Trigger
SYMBOL
tPLH
50pF 50pF 50pF 15pF
Propagation Delay, Trigger
tPHL
50pF 50pF 50pF 15pF
CD54HC221, CD74HC221, CD74HCT221
Switching Specifications Input
(Continued) 25oC Propagation Delay, tPHL 50pF Output Transition Time tTLH, tTHL 50pF Input Capacitance Pulse Width Match Between Circuits Same Package 1000pF, Power Dissipation Capacitance (Notes TYPES Propagation Delay, Trigger Propagation Delay, Trigger Propagation Delay, Propagation Delay, Output Transition Time tPLH 50pF 15pF tPHL 50pF 15pF tPLH tPHL tTLH, tTHL 50pF 50pF 50pF Input Capacitance Pulse Width Match Between Circuits Same Package 1000pF, Power Dissipation Capacitance (Notes NOTES: used determine dynamic power consumption, multivibrator. (CPD VCC2 where input frequency, output frequency, output load capacitance, supply voltage. -40oC 85oC -55oC 125oC UNITS
PARAMETER Propagation Delay,
SYMBOL tPLH
TEST CONDITIONS 50pF
CD54HC221, CD74HC221, CD74HCT221 Test Circuits Waveforms
trCL CLOCK tfCL CLOCK trCL tfCL 2.7V 0.3V 1.3V 0.3V 1.3V 1.3V
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
NOTE: Outputs should switching from accordance with device truth table. fMAX, input duty cycle 50%. FIGURE CLOCK PULSE RISE FALL TIMES PULSE WIDTH
INPUT
INPUT 2.7V 1.3V 0.3V
tTLH
tTHL
tTLH tPHL tPLH
tTHL
INVERTING OUTPUT
INVERTING OUTPUT tPHL tPLH
1.3V
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
FIGURE TRANSITION TIMES PROPAGATION DELAY TIMES, COMBINATION LOGIC
CD54HC221, CD74HC221, CD74HCT221 Typical Performance Curves
PULSE WIDTH (µs) FACTOR 25oC
AMBIENT TEMPERATURE (oC)
VCC, SUPPLY VOLTAGE
FIGURE HC/HCT221 OUTPUT PULSE WIDTH TEMPERATURE
FIGURE HC/HCT221 FACTOR SUPPLY VOLTAGE
PULSE WIDTH (µs) 100K PULSE WIDTH (µs)
4.5V TIMING CAPACITANCE (pF) TIMING CAPACITANCE (pF) 100K
FIGURE HC221 OUTPUT PULSE WIDTH
FIGURE HC/HCT221 OUTPUT PULSE WIDTH
CD54HC221, CD74HC221, CD74HCT221
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
PACKAGING INFORMATION
Orderable Device 5962-8780501EA CD54HC221F CD54HC221F3A CD74HC221E CD74HC221EE4 CD74HC221M CD74HC221M96 CD74HC221M96E4 CD74HC221M96G4 CD74HC221ME4 CD74HC221MG4 CD74HC221MT CD74HC221MTE4 CD74HC221MTG4 CD74HC221NSR CD74HC221NSRE4 CD74HC221NSRG4 CD74HC221PW CD74HC221PWE4 CD74HC221PWG4 CD74HC221PWR CD74HC221PWRE4 CD74HC221PWRG4 CD74HC221PWT CD74HC221PWTE4 CD74HC221PWTG4 Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE Package Type CDIP CDIP CDIP PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP TSSOP Package Drawing Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br) Lead/Ball Finish SNPB SNPB SNPB NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU Peak Temp Type Type Type Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) 2000 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
Addendum-Page
PACKAGE OPTION ADDENDUM
www.ti.com
18-Sep-2008
Orderable Device CD74HCT221E CD74HCT221EE4 CD74HCT221M CD74HCT221M96 CD74HCT221M96E4 CD74HCT221M96G4 CD74HCT221ME4 CD74HCT221MG4 CD74HCT221MT CD74HCT221MTE4 CD74HCT221MTG4
Status ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type PDIP PDIP SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC SOIC
Package Drawing
Pins Package Plan Pb-Free (RoHS) Pb-Free (RoHS) Green (RoHS Sb/Br)
Lead/Ball Finish NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU NIPDAU
Peak Temp Type Type Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM Level-1-260C-UNLIM
2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) 2500 Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br) Green (RoHS Sb/Br)
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Pb-Free (RoHS Exempt): This component RoHS exemption either lead-based flip-chip solder bumps used between package, lead-based adhesive used between leadframe. component otherwise considered Pb-Free (RoHS compatible) defined above. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
TAPE REEL INFORMATION
*All dimensions nominal
Device
Package Package Pins Type Drawing SOIC TSSOP SOIC
Reel Reel Diameter Width (mm) (mm) 330.0 330.0 330.0 330.0 16.4 16.4 12.4 16.4
(mm)
(mm)
(mm)
(mm) 12.0
Pin1 (mm) Quadrant 16.0 16.0 12.0 16.0
CD74HC221M96 CD74HC221NSR CD74HC221PWR CD74HCT221M96
2500 2000 2000 2500
10.3 10.5 10.3
Pack Materials-Page
PACKAGE MATERIALS INFORMATION
www.ti.com
19-Mar-2008
*All dimensions nominal
Device CD74HC221M96 CD74HC221NSR CD74HC221PWR CD74HCT221M96
Package Type SOIC TSSOP SOIC
Package Drawing
Pins
2500 2000 2000 2500
Length (mm) 333.2 346.0 346.0 333.2
Width (mm) 345.9 346.0 346.0 345.9
Height (mm) 28.6 33.0 29.0 28.6
Pack Materials-Page
MECHANICAL DATA
MTSS001C JANUARY 1995 REVISED FEBRUARY 1999
(R-PDSO-G**)
PINS SHOWN
PLASTIC SMALL-OUTLINE PACKAGE
0,65
0,30 0,19
0,10
0,15 4,50 4,30 6,60 6,20 Gage Plane 0,25 0,75 0,50
Seating Plane 1,20 0,15 0,05 0,10
PINS
3,10
5,10
5,10
6,60
7,90
9,80
2,90
4,90
4,90
6,40
7,70
9,60
4040064/F 01/97 NOTES: linear dimensions millimeters. This drawing subject change without notice. Body dimensions include mold flash protrusion exceed 0,15. Falls within JEDEC MO-153
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DALLAS, TEXAS 75265
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