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PIC16F193X / LF193X Data Sheet
28 / 40 / 44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology
PIC16F193X / LF193X Data Sheet
28 / 40 / 44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver and nanoWatt XLP Technology
Preliminary
DS41364B
DS41364B-page ii
Preliminary
PIC16F193X / LF193X
28 / 40 / 44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with LCD Driver with nano Watt XLP Technology
Devices Included In This Data Sheet:
PIC16F193X Devices: · PIC16F1933 · PIC16F1936 · PIC16F1938 PIC16LF193X Devices: · PIC16LF1933 · PIC16LF1936 · PIC16LF1938 · PIC16LF1934 · PIC16LF1937 · PIC16LF1939 · PIC16F1934 · PIC16F1937 · PIC16F1939
PIC16LF193X Low-Power Features:
· Standby Current: - 60 nA @ 1.8V, typical · Operating Current: - 7.0 A @ 32 kHz, 1.8V, typical - 150 A @ 1 MHz, 1.8V, typical · Timer1 Oscillator Current: - 600 nA @ 32 kHz, 1.8V, typical · Low-Power Watchdog Timer Current: - 500 nA @ 1.8V, typical
Peripheral Features:
· Up to 35 I / O Pins and 1 Input-only pin: - High-current source / sink for direct LED drive - Individually programmable Interrupt-on-pin change pins - Individually programmable weak pull-ups · Integrated LCD Controller: - Up to 96 segments - Variable clock input - Contrast control - Internal voltage reference selections · Capacitive Sensing Module (mTouchTM) - Up to 16 selectable channels · A / D Converter: - 10-bit resolution and up to 14 channels - Selectable 1.024 / 2.048 / 4.096V voltage reference · Timer0: 8-Bit Timer / Counter with 8-Bit Programmable Prescaler · Enhanced Timer1 - Dedicated low-power 32 kHz oscillator driver - 16-bit timer / counter with prescaler - External Gate Input mode with toggle and single shot modes - Interrupt-on-gate completion · Timer2, 4, 6: 8-Bit Timer / Counter with 8-Bit Period Register, Prescaler and Postscaler · Two Capture, Compare, PWM Modules (CCP) - 16-bit Capture, max. resolution 125 ns - 16-bit Compare, max. resolution 125 ns - 10-bit PWM, max. frequency 31.25 kHz · Three Enhanced Capture, Compare, PWM modules (ECCP) - 3 PWM time-base options - Auto-shutdown and auto-restart - PWM steering - Programmable Dead-band Delay
High-Performance RISC CPU:
· Only 49 Instructions to Learn: - All single-cycle instructions except branches · Operating Speed: - DC - 32 MHz oscillator / clock input - DC - 125 ns instruction cycle · Up to 16K x 14 Words of Flash Program Memory · Up to 1024 Bytes of Data Memory (RAM) · Interrupt Capability with automatic context saving · 16-Level Deep Hardware Stack · Direct, Indirect and Relative Addressing modes · Processor Read Access to Program Memory · Pinout Compatible to other 28 / 40-pin PIC16CXXX and PIC16FXXX Microcontrollers
Special Microcontroller Features:
Preliminary
DS41364B-page 1
PIC16F193X / LF193X
Peripheral Features (Continued):
· Master Synchronous Serial Port (MSSP) with SPI and I2 C with: - 7-bit address masking - SMBUS / PMBUS compatibility - Auto-wake-up on start · Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) - RS-232, RS 485 and LIN compatible - Auto-Baud Detect · SR Latch (555 Timer): - Multiple Set / Reset input options · 2 Comparators: - Rail-to-rail inputs / outputs - Power mode control - Software enable hysteresis · Voltage Reference module: - Fixed Voltage Reference (FVR) with 1.024V, 2.048V and 4.096V output levels - 5-bit rail-to-rail resistive DAC with positive and negative reference selection
PIC16F193X / LF193X Family Types
Program Memory Flash (words) Data EEPROM (bytes) SRAM (bytes) Comparators CapSense (ch) 10-bit A / D (ch) I2C / SPI EUSART
Timers 8 / 16-bit
Device
PIC16F1933 PIC16LF1933 PIC16F1934 PIC16LF1934 PIC16F1936 PIC16LF1936 PIC16F1937 PIC16LF1937
Yes Yes Yes Yes Yes Yes
PIC16F1938 16384 PIC16LF1938 PIC16F1939 16384 PIC16LF1939 Note 1:
COM3 and SEG15 share the same physical pin on PIC16F1933 / 1936 / 1938 / PIC16LF1933 / 1936 / 1938, therefore, SEG15 is not available when using 1 / 4 multiplex displays.
DS41364B-page 2
Preliminary
PIC16F193X / LF193X
Pin Diagram - 28-Pin SPDIP / SOIC / SSOP (PIC16F1933 / 1936 / 1938, PIC16LF1933 / 1936 / 1938)
28-pin SPDIP, SOIC, SSOP
VPP / MCLR / RE3 SEG12 / VCAP / SS / SRNQ / C2OUT / C12IN0- / AN0 / RA0 SEG7 / C12IN1- / AN1 / RA1 COM2 / DACOUT / VREF- / C2IN+ / AN2 / RA2 SEG15 / COM3 / VREF+ / C1IN+ / AN3 / RA3 SEG4 / CCP5 / SRQ / T0CKI / CPS6 / C1OUT / RA4 SEG5 / VCAP(2) / SS(1) / SRNQ(1) / CPS7 / C2OUT(1) / AN4 / RA5 VSS SEG2 / CLKIN / OSC1 / RA7 SEG1 / VCAP(2) / CLKOUT / OSC2 / RA6 P2B(1) / T1CKI / T1OSO / RC0 P2A(1) / CCP2(1) / T1OSI / RC1 SEG3 / P1A / CCP1 / RC2 SEG6 / SCL / SCK / RC3
1 2 3 PIC16F1933 / 1936 / 1938 4 5 6 7 8 9 10 11 12 13 14 PIC16LF1933 / 1936 / 1938
RB7 / ICSPDAT / ICDDAT / SEG13 RB6 / ICSPCLK / ICDCLK / SEG14 RB5 / AN13 / CPS5 / P2B(1) / CCP3(1) / P3A(1) / T1G(1) / COM1 RB4 / AN11 / CPS4 / P1D / COM0 RB3 / AN9 / C12IN2- / CPS3 / CCP2(1) / P2A(1) / VLCD3 RB2 / AN8 / CPS2 / P1B / VLCD2 RB1 / AN10 / C12IN3- / CPS1 / P1C / VLCD1 RB0 / AN12 / CPS0 / CCP4 / SRI / INT / SEG0 VDD VSS RC7 / RX / DT / P3B / SEG8 RC6 / TX / CK / CCP3(1) / P3A(1) / SEG9 RC5 / SDO / SEG10 RC4 / SDI / SDA / T1G(1) / SEG11
Pin function is selectable via the APFCON register. PIC16F193X devices only.
Preliminary
DS41364B-page 3
PIC16F193X / LF193X
Pin Diagram - 28-Pin QFN (PIC16F1933 / 1936 / 1938, PIC16LF1933 / 1936 / 1938)
28-pin QFN
RA1 / AN1 / C12IN1- / SEG7 RA0 / AN0 / C12IN0- / C2OUT(1) / SRNQ(1) / SS(1) / VCAP(2) / SEG12
RE3 / MCLR / VPP RB7 / ICSPDAT / ICDDAT / SEG13 RB6 / ICSPCLK / ICDCLK / SEG14 RB5 / AN13 / CPS5 / P2B(1) / CCP3(1) / P3A(1) / T1G(1) / COM1 RB4 / AN11 / CPS4 / P1D / COM0
COM2 / DACOUT / VREF- / C2IN+ / AN2 / RA2 SEG15 / COM3 / VREF+ / C1IN+ / AN3 / RA3 SEG4 / CCP5 / SRQ / T0CKI / CPS6 / C1OUT / RA4 SEG5(1) / VCAP(2) / SS(1) / SRNQ / CPS7 / C2OUT(1) / AN4 / RA5 VSS SEG2 / CLKIN / OSC1 / RA7 SEG1 / VCAP(2) / CLKOUT / OSC2 / RA6
Pin function is selectable via the APFCON register. PIC16F193X devices only.
DS41364B-page 4
Preliminary
SEG3 / P1A / CCP1 / RC2 SEG6 / SCL / SCK / RC3 SEG11 / T1G(1) / SDA / SDI / RC4 SEG10 / SDO / RC5 SEG9 / P3A(1) / CCP3(1) / CK / TX / RC6
P2B(1) / T1CKI / T1OSO / RC0
(1)P2A / (1)CCP2 / T1OSI / RC1
1 21 2 20 3 PIC16F1933 / 1936 / 1938 19 4 PIC16LF1933 / 1936 / 1938 18 5 17 6 16 7 15
RB3 / AN9 / C12IN2- / CPS3 / CCP2(1) / P2A(1) / VLCD3 RB2 / AN8 / CPS2 / P1B / VLCD2 RB1 / AN10 / C12IN3- / CPS1 / P1C / VLCD1 RB0 / AN12 / CPS0 / CCP4 / SRI / INT / SEG0 VDD VSS RC7 / RX / DT / P3B / SEG8
PIC16F193X / LF193X
TABLE 1:
28-Pin QFN 28-Pin SIP I / O
28-PIN SUMMARY (PIC16F1933 / 1936 / 1938, PIC16LF1933 / 1936 / 1938)
Comparator Cap Sense SR Latch EUSART Interrupt ANSEL Pull-up Timers MSSP Basic VCAP(2) - - - - VCAP(2) OSC2 / CLKOUT VCAP(2) OSC1 / CLKIN - - - - - - ICSPCLK / ICDCLK ICSPDAT / ICDDAT - - - - - - - - MCLR / VPP VDD VSS CCP LCD SEG12 SEG7 COM2 SEG15 / COM3 SEG4 SEG5 SEG1 A / D AN0 AN1 AN2 / VREFAN3 / VREF+ - AN4 -
RA0 RA1 RA2 RA3 RA4 RA5 RA6
C12IN0- / C2OUT(1) C12IN1C2IN+ / DACOUT C1IN+ C1OUT C2OUT(1) -
SRNQ(1) - - - SRQ SRNQ(1) -
SS(1) - - - - SS(1) -
RA7 RB0 RB1 RB2 RB3 RB4 RB5
- AN12 AN10 AN8 AN9 AN11 AN13
- CPS0 CPS1 CPS2 CPS3 CPS4 CPS5
- - C12IN3- C12IN2- -
- CCP4 P1C P1B CCP2(1) / P2A(1) P1D P2B(1) CCP3(1) / P3A(1) - - P2B(1) CCP2(1) / P2A(1) CCP1 / P1A - - - CCP3(1) P3A(1) P3B - - -
SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1
- INT / IOC IOC IOC IOC IOC IOC
RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RE3 VDD Vss Note
- - T1OSO / T1CKI T1OSI - - T1G(1) - - - - - -
SEG14 SEG13 - - SEG3 SEG6 SEG11 SEG10 SEG9 SEG8 - - -
Pin functions can be moved using the APFCON register. PIC16F193X devices only.
Preliminary
DS41364B-page 5
PIC16F193X / LF193X
Pin Diagram - 40-Pin PDIP (PIC16F1934 / 1937 / 1939, PIC16LF1934 / 1937 / 1939)
40-Pin PDIP
VPP / MCLR / RE3 SEG12 / VCAP(2) / SS(1) / SRNQ(1) / C2OUT(1) / C12IN0- / AN0 / RA0 SEG7 / C12IN1- / AN1 / RA1 COM2 / DACOUT / VREF- / C2IN+ / AN2 / RA2 SEG15 / VREF+ / C1IN+ / AN3 / RA3 SEG4 / SRQ / T0CKI / CPS6 / C1OUT / RA4 SEG5 / VCAP(2) / SS(1) / SRNQ(1) / CPS7 / C2OUT(1) / AN4 / RA5 SEG21 / CCP3(1) / P3A(1) / AN5 / RE0 SEG22 / P3B / AN6 / RE1 SEG23 / CCP5 / AN7 / RE2 VDD VSS SEG2 / CLKIN / OSC1 / RA7 SEG1 / V
CAP(2) / CLKOUT / OSC2 / RA6
1 2 3 4 5 6 PIC16F1934 / 1937 / 1939 PIC16LF1934 / 1937 / 1939 7 8 9 10 11 12 13 14 15 16 17 18 19 20
RB7 / ICSPDAT / ICDDAT / SEG13 RB6 / ICSPCLK / ICDCLK / SEG14 RB5 / AN13 / CPS5 / CCP3(1) / P3A(1) / T1G(1) / COM1 RB4 / AN11 / CPS4 / COM0 RB3 / AN9 / C12IN2- / CPS3 / CCP2(1) / P2A(1) / VLCD3 RB2 / AN8 / CPS2 / VLCD2 RB1 / AN10 / C12IN3- / CPS1 / VLCD1 RB0 / AN12 / CPS0 / SRI / INT / SEG0 VDD VSS RD7 / CPS15 / P1D / SEG20 RD6 / CPS14 / P1C / SEG19 RD5 / CPS13 / P1B / SEG18 RD4 / CPS12 / P2D / SEG17 RC7 / RX / DT / SEG8 RC6 / TX / CK / SEG9 RC5 / SDO / SEG10 RC4 / SDI / SDA / T1G(1) / SEG11 RD3 / CPS11 / P2C / SEG16 RD2 / CPS10 / P2B(1)
(1) / T1CKI / T1OSO / RC0
P2A(1) / CCP2(1) / T1OSI / RC1 SEG3 / P1A / CCP1 / RC2 SEG6 / SCK / SCL / RC3 COM3 / CPS8 / RD0 CCP4 / CPS9 / RD1
Pin function is selectable via the APFCON register. PIC16F193X devices only.
DS41364B-page 6
Preliminary
PIC16F193X / LF193X
Pin Diagram - 44-Pin QFN (PIC16F1934 / 1937 / 1939, PIC16LF1934 / 1937 / 1939)
RC6 / TX / CK / SEG9 RC5 / SDO / SEG10 RC4 / SDI / SDA / T1G(1) / SEG11 RD3 / CPS11 / P2C / SEG16 RD2 / CPS10 / P2B(1) RD1 / CPS9 / CCP4 RD0 / CPS8 / COM3 RC3 / SCL / SCK / SEG6 RC2 / CCP1 / P1A / SEG3 RC1 / T1OSI / CCP2(1) / P2A(1) RC0 / T1OSO / T1CKI / P2B(1) 44 43 42 41 40 39 38 37 36 35 34 44-pin QFN
Pin function is selectable via the APFCON register. PIC16F193X devices only.
VLCD3 / P2A(1) / CCP2(1) / CPS3 / C12IN2- / AN9 / RB3 NC COM0 / CPS4 / AN11 / RB4 COM1 / T1G(1) / P3A(1) / CCP3(1) / CPS5 / AN13 / RB5 SEG14 / ICDCLK / ICSPCLK / RB6 SEG13 / ICDDAT / ICSPDAT / RB7 VPP / MCLR / RE3 (2) / SS(1) / SRNQ(1) / C2OUT(1) / C12IN0- / AN0 / RA0 SEG12 / VCAP SEG7 / C12IN1- / AN1 / RA1 COM2 / DACOUT / VREF- / C2IN+ / AN2 / RA2 SEG15VREF+ / C1IN+ / AN3 / RA3
SEG8 / DT / RX / RC7 SEG17 / P2D / CPS12 / RD4 SEG18 / P1B / CPS13 / RD5 SEG19 / P1C / CPS14 / RD6 SEG20 / P1D / CPS15 / RD7 VSS VDD VDD SEG0 / INT / SRI / CPS0 / AN12 / RB0 VLCD1 / CPS1 / C12IN3- / AN10 / RB1 VLCD2 / CPS2 / AN8 / RB2
1 33 2 32 3 31 4 30 5 PIC16F1934 / 1937 / 1939 29 6 PIC16LF1934 / 1937 / 1939 28 7 27 8 26 9 25 10 24 11 23
RA6 / OSC2 / CLKOUT / VCAP(2) / SEG1 RA7 / OSC1 / CLKIN / SEG2 VSS VSS NC VDD RE2 / AN7 / CCP5 / SEG23 RE1 / AN6 / P3B / SEG22 RE0 / AN5 / CCP3(1) / P3A(1) / SEG21 RA5 / AN4 / C2OUT(1) / CPS7 / SRNQ(1) / SS(1) / VCAP(2) / SEG5 RA4 / C1OUT / CPS6 / T0CKI / SRQ / SEG4
Preliminary
DS41364B-page 7
PIC16F193X / LF193X
Pin Diagram - 44-Pin TQFP (PIC16F1934 / 1937 / 1939, PIC16LF1934 / 1937 / 1939)
44-pin TQFP RC6 / TX / CK / SEG9 RC5 / SDO / SEG10 RC4 / SDI / SDA / T1G(1) / SEG11 RD3 / CPS11 / P2C / SEG16 RD2 / CPS10 / P2B(1) RD1 / CPS9 / CCP4 RD0 / CPS8 / COM3 RC3 / SCL / SCK / SEG6 RC2 / CCP1 / P1A / SEG3 RC1 / T1OSI / CCP2(1) / P2A(1) NC 44 43 42 41 40 39 38 37 36 35 34
Pin function is selectable via the APFCON register. PIC16F193X devices only.
NC NC COM0 / CPS4 / AN11 / RB4 (1) / P3A(1) / CCP3(1) / CPS5 / AN13 / RB5 COM1 / T1G SEG14 / ICDCLK / ICSPCLK / RB6 SEG13 / ICDDAT / ICSPDAT / RB7 VPP / MCLR / RE3 SEG12 / VCAP(2) / SS(1) / SRNQ(1) / C2OUT(1) / C12IN0- / AN0 / RA0 SEG7 / C12IN1- / AN1 / RA1 COM2 / DACOUT / VREF- / C2IN+ / AN2 / RA2 SEG15 / VREF+ / C1IN+ / AN3 / RA3
SEG8 / DT / RX / RC7 SEG17 / P2D / CPS12 / RD4 SEG18 / P1B / CPS13 / RD5 SEG19 / P1C / CPS14 / RD6 SEG20 / P1D / CPS15 / RD7 VSS VDD SEG0 / INT / SRI / CPS0 / AN12 / RB0 VLCD1 / CPS1 / C12IN3- / AN10 / RB1 VLCD2 / CPS2 / AN8 / RB2 VLCD3 / P2A(1) / CCP2(1) / CPS3 / C12IN2- / AN9 / RB3
1 2 3 4 5 PIC16F1934 / 1937 / 1939 6 PIC16LF1934 / 1937 / 1939 7 8 9 10 11
NC RC0 / T1OSO / T1CKI / P2B(1) RA6 / OSC2 / CLKOUT / VCAP(2) / SEG1 RA7 / OSC1 / CLKIN / SEG2 VSS VDD RE2 / AN7 / CCP5 / SEG23 RE1 / AN6 / P3B / SEG22 RE0 / AN5 / CCP3(1) / P3A(1) / SEG21 RA5 / AN4 / C2OUT(1) / CPS7 / SRNQ(1) / SS(1) / VCAP(2) / SEG5 RA4 / C1OUT / CPS6 / T0CKI / SRQ / SEG4
DS41364B-page 8
Preliminary
PIC16F193X / LF193X
TABLE 2:
44-Pin TQFP 40-Pin PDIP 44-Pin QFN I / O
40 / 44-PIN SUMMARY(PIC16F1934 / 1937 / 1939, PIC16LF1934 / 1937 / 1939)
Comparator Cap Sense SR Latch EUSART Interrupt ANSEL Pull-up Timers MSSP Basic VCAP - - - - VCAP OSC2 / CLKOUT VCAP OSC1 / CLKIN - - - - - - ICSPCLK / ICDCLK ICSPDAT / ICDDAT - - - - - - - - - - - - - - - - - - - MCLR / VPP VDD VSS CCP LCD SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG1 A / D AN0 AN1 AN2 / VREFAN3 / VREF+ - AN4 -
RA0 RA1 RA2 RA3 RA4 RA5 RA6
C12IN0- / C2OUT(1) C12IN1C2IN+ / DACOUT C1IN+ C1OUT C2OUT(1) -
SRNQ(1) - - - SRQ SRNQ(1) -
SS(1) - - - - SS(1) -
RA7 RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 RD0 RD1 RD2 RD3 RD4 RD5 RD6 RD7 RE0 RE1 RE2 RE3 VDD Vss
- CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 - - - - - - - - - - CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15 - - - - - -
- - - - CCP2(1) / P2A(1) - CCP3(1) / P3A(1) - - P2B(1) CCP2(1) / P2A(1) CCP1 / P1A - - - - - - CCP4 P2B(1) P2C P2D P1B P1C P1D CCP3(1) P3A(1) P3B CCP5 - - -
SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1 SEG14 SEG13 - - SEG3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 - - SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23 - - -
Note 1:
Pin functions can be moved using the APFCON register.
Preliminary
DS41364B-page 9
PIC16F193X / LF193X
Table of Contents
DS41364B-page 10
Preliminary
PIC16F193X / LF193X
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Preliminary
DS41364B-page 11
PIC16F193X / LF193X
NOTES:
DS41364B-page 12
Preliminary
PIC16F193X / LF193X
1.0 DEVICE OVERVIEW
The PIC16F193X / LF193X devices are described within this data sheet. They are available in 28 / 40 / 44-pin packages. Figure 1-1 shows a block diagram of the PIC16F193X / LF193X devices. Table 1-1 shows the pinout descriptions.
FIGURE 1-1:
PIC16F193X / LF193X BLOCK DIAGRAM
Configuration 15 Program Counter Flash Program Memory MUX Data Bus 8
PORTA RA0 RA1 RA2 RA3 RA4 RA5 RA6 RA7 PORTB RB0 RB1 RB2 RB3 RB4 RB5 RB6 RB7 RC0 RC1 RC2 RC3 RC4 RC5 RC6 RC7 PORTD RD0 RC1 RD1 RD2 RD3 RD4 RD5 RD6 RD7 PORTE RE0 RE1 RE2 RE3 / MCLR
16-LevelStack 8 Level Stack (13-bit) (15-bit) Program Memory Read (PMR) 7
Program Bus
9 Addr MUX 12
RAM Addr
Instruction Reg Instruction reg Direct Addr 15
Indirect Addr
FSR0 Reg FSR reg FSR1 Reg FSR reg 15 8 3 STATUS reg STATUS Reg PORTC
Power-up Timer Instruction Decode & Decode and Control OSC1 / CLKIN OSC2 / CLKOUT Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset 8
Internal Oscillator Block VDD VSS
Timer0
Timer1
Data EEPROM 256 bytes
Comparators
Addressable EUSART
SR Latch
Preliminary
DS41364B-page 13
PIC16F193X / LF193X
1.1 Enhanced Mid-range CPU
PIC16F193X / LF193X devices contain an enhanced mid-range 8-bit CPU core. The CPU has 49 instructions. Interrupt capability includes automatic context saving. The hardware stack is 16 levels deep and has Overflow and Underflow Reset capability. Direct, indirect, and relative addressing modes are available. Two File Select Registers (FSRs) provide the ability to read program and data memory. During interrupts, certain registers are automatically saved in shadow registers and restored when returning from the interrupt. This saves stack space and user code. See Section 4.5 "Context Saving", for more information.
16-LEVEL STACK WITH OVERFLOW AND UNDERFLOW RESET
The PIC16F193X / LF193X devices have an external stack memory 15 bits wide and 16 deep. During normal operation, the stack is assumed to be 16 words deep. If enabled, a Stack Overflow or Underflow will set the appropriate bit (STKOVF or STKUNF) in the PCON register, and cause a software Reset. See section Section 2.4 "Stack" for more details.
FILE SELECT REGISTERS
There are two 16-bit File Select Registers (FSR). FSRs can access all file registers and program memory, which allows one data pointer for all memory. When an FSR points to program memory, there is 1 additional instruction cycle in instructions using INDF to allow the data to be fetched. There are also new instructions to support the FSRs. See Section 2.5 "Indirect Addressing, INDF and FSR Registers" for more details.
INSTRUCTION SET
There are 48 instructions for the enhanced mid-range CPU to support the features of the CPU. See Section 26.0 "Instruction Set Summary" for more details.
DS41364B-page 14
Preliminary
PIC16F193X / LF193X
TABLE 1-1: PIC16F193X / LF193X PINOUT DESCRIPTION
Function RA0 AN0 C12IN0C2OUT SRNQ SS VCAP SEG12 RA1 / AN1 / C12IN1- / SEG7 RA1 AN1 C12IN1SEG7 RA2 / AN2 / C2IN+ / VREF- / CVREF / COM2 RA2 AN2 C2IN+ VREFCVREF COM2 RA3 / AN3 / C1IN+ / VREF+ / COM3(3) / SEG15 RA3 AN3 C1IN+ VREF+ COM3(3) SEG15 RA4 / C1OUT / CPS6 / T0CKI / SRQ / CCP5 / SEG4 RA4 Input Type TTL AN
Name RA0 / AN0 / C12IN0- / C2OUT(1) / SRNQ(1) / SS(1) / VCAP(2) / SEG12
Output Type CMOS General purpose I / O. -
Description
A / D Channel 0 input.
Comparator C1 or C2 negative input.
- - ST Power - TTL AN
CMOS Comparator C2 output. CMOS SR Latch inverting output. - Power AN -
Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. A / D Channel 1 input.
Comparator C1 or C2 negative input.
CMOS General purpose I / O.
LCD Analog output. A / D Channel 2 input.
Comparator C2 positive input.
CMOS General purpose I / O.
A / D Negative Voltage Reference input. Comparator Voltage Reference output. LCD Analog output. A / D Channel 3 input.
Comparator C1 positive input.
CMOS General purpose I / O.
A / D Voltage Reference input. LCD Analog output. LCD Analog output.
CMOS General purpose I / O.
C1OUT
CPS6 T0CKI SRQ CCP5 SEG4
CMOS Comparator C1 output.
- - Capacitive sensing input 6. Timer0 clock input.
CMOS SR Latch non-inverting output. CMOS Capture / Compare / PWM5. AN - - - Power AN LCD Analog output. A / D Channel 4 input. Capacitive sensing input 7. Slave Select input. Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. CMOS General purpose I / O.
RA5 / AN4 / C2OUT(1) / CPS7 / SRNQ(1) / SS(1) / VCAP(2) / SEG5
RA5 AN4
C2OUT
CPS7 SRNQ SS VCAP SEG5
AN - ST Power -
CMOS Comparator C2 output.
CMOS SR Latch inverting output.
Preliminary
DS41364B-page 15
PIC16F193X / LF193X
TABLE 1-1: PIC16F193X / LF193X PINOUT DESCRIPTION (CONTINUED)
Function RA6 OSC2 CLKOUT VCAP SEG1 RA7 / OSC1 / CLKIN / SEG2 RA7 OSC1 CLKIN SEG2 RB0 / AN12 / CPS0 / CCP4 / SRI / INT / SEG0 RB0 AN12 CPS0 CCP4 SRI INT SEG0 RB1 / AN10 / C12IN3- / CPS1 / P1C / VLCD1 RB1 AN10 C12IN3CPS1 P1C VLCD1 RB2 / AN8 / CPS2 / P1B / VLCD2 RB2 AN8 CPS2 P1B VLCD2 RB3 / AN9 / C12IN2- / CPS3 / CCP2(1) / P2A(1) / VLCD3 RB3 AN9 C12IN2CPS3 CCP2 P2A VLCD3 Input Type TTL - - Power - TTL XTAL CMOS - TTL AN AN ST - ST - TTL AN
Name RA6 / OSC2 / CLKOUT / VCAP(2) / SEG1
Output Type CMOS General purpose I / O. XTAL Power AN - - AN
Description
Crystal / Resonator (LP, XT, HS modes). Filter capacitor for Voltage Regulator (PIC16F193X only). LCD Analog output. Crystal / Resonator (LP, XT, HS modes). External clock input (EC mode). LCD Analog output.
CMOS FOSC / 4 output.
CMOS General purpose I / O.
CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. - - ST - AN A / D Channel 12 input. Capacitive sensing input 0. SR Latch input. External interrupt. LCD analog output.
CMOS Capture / Compare / PWM4.
CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. -
A / D Channel 10 input.
Comparator C1 or C2 negative input.
Capacitive sensing input 1. LCD analog input.
CMOS PWM output. CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. - - - A / D Channel 8 input. Capacitive sensing input 2. LCD analog input.
CMOS PWM output. CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. -
A / D Channel 9 input.
Comparator C1 or C2 negative input.
Capacitive sensing input 3.
CMOS Capture / Compare / PWM2. CMOS PWM output. - LCD analog input.
DS41364B-page 16
Preliminary
PIC16F193X / LF193X
TABLE 1-1: PIC16F193X / LF193X PINOUT DESCRIPTION (CONTINUED)
Function RB4 AN11 CPS4 P1D COM0 RB5 / AN13 / CPS5 / P2B / CCP3(1) / P3A(1) / T1G(1) / COM1 RB5 AN13 CPS5 P2B CCP3 P3A T1G COM1 RB6 / ICSPCLK / ICDCLK / SEG14 RB6 ICSPCLK ICDCLK SEG14 RB7 / ICSPDAT / ICDDAT / SEG13 RB7 ICSPDAT ICDDAT SEG13 RC0 / T1OSO / T1CKI / P2B
Name RB4 / AN11 / CPS4 / P1D / COM0
Input Type TTL AN AN - - TTL AN AN - ST - ST - TTL ST ST - TTL ST ST - ST XTAL ST - ST XTAL ST - ST ST - - ST ST I2C -
Output Type
Description
CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. - - AN A / D Channel 11 input. Capacitive sensing input 4. LCD Analog output.
CMOS PWM output. CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. - - A / D Channel 13 input. Capacitive sensing input 5.
CMOS PWM output. CMOS Capture / Compare / PWM3. CMOS PWM output. - AN Timer1 Gate input. LCD Analog output.
CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. - - AN Serial Programming Clock. In-Circuit Debug Clock. LCD Analog output.
CMOS General purpose I / O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSP Data I / O. CMOS In-Circuit Data I / O. AN XTAL - LCD Analog output. Timer1 oscillator connection. Timer1 clock input. CMOS General purpose I / O.
RC0 T1OSO T1CKI P2B
CMOS PWM output. CMOS General purpose I / O. XTAL Timer1 oscillator connection. CMOS Capture / Compare / PWM2. CMOS PWM output. CMOS General purpose I / O. CMOS Capture / Compare / PWM1. CMOS PWM output. AN LCD Analog output. CMOS General purpose I / O. CMOS SPI clock. OD AN I2C clock. LCD Analog output.
RC1 / T1OSI / CCP2
RC1 T1OSI CCP2 P2A
RC2 / CCP1 / P1A / SEG3
RC2 CCP1 P1A SEG3
RC3 / SCK / SCL / SEG6
RC3 SCK SCL SEG6
Preliminary
DS41364B-page 17
PIC16F193X / LF193X
TABLE 1-1: PIC16F193X / LF193X PINOUT DESCRIPTION (CONTINUED)
Function RC4 SDI SDA T1G SEG11 RC5 / SDO / SEG10 RC5 SDO SEG10 RC6 / TX / CK / CCP3 / P3A / SEG9 RC6 TX CK CCP3 P3A SEG9 RC7 / RX / DT / P3B / SEG8 RC7 RX DT P3B SEG8 RD0(4) / CPS8 / COM3 RD0 CPS8 COM3 RD1(4) / CPS9 / CCP4 RD1 CPS9 CCP4 RD2(4) / CPS10 / P2B RD2 CPS10 P2B RD3(4) / CPS11 / P2C / SEG16 RD3 CPS11 P2C SEG16 RD4(4) / CPS12 / P2D / SEG17 RD4 CPS12 P2D SEG17 RD5(4) / CPS13 / P1B / SEG18 RD5 CPS13 P1D SEG18 Input Type ST ST I2C ST - ST - - ST - ST ST - - ST ST ST - - ST AN - ST AN ST ST AN - ST AN - - ST AN - - ST AN - - Output Type CMOS General purpose I / O. - OD - AN SPI data input. I2C data input / output. Timer1 Gate input. LCD Analog output. Description Name RC4 / SDI / SDA / T1G(1) / SEG11
CMOS General purpose I / O. CMOS SPI data output. AN LCD Analog output. CMOS General purpose I / O. CMOS USART asynchronous transmit. CMOS USART synchronous clock. CMOS Capture / Compare / PWM3. CMOS PWM output. AN - LCD Analog output. USART asynchronous input. CMOS General purpose I / O. CMOS USART synchronous data. CMOS PWM output. AN - AN - LCD Analog output. Capacitive sensing input 8. LCD analog output. Capacitive sensing input 9. CMOS General purpose I / O.
CMOS General purpose I / O. CMOS Capture / Compare / PWM4. CMOS General purpose I / O. - Capacitive sensing input 10. CMOS PWM output. CMOS General purpose I / O. - AN - AN - AN Capacitive sensing input 11. LCD analog output. Capacitive sensing input 12. LCD analog output. Capacitive sensing input 13. LCD analog output. CMOS PWM output. CMOS General purpose I / O. CMOS PWM output. CMOS General purpose I / O. CMOS PWM output.
DS41364B-page 18
Preliminary
PIC16F193X / LF193X
TABLE 1-1: PIC16F193X / LF193X PINOUT DESCRIPTION (CONTINUED)
Function RD6 CPS14 P1C SEG19 RD7(4) / CPS15 / P1D / SEG20 RD7 CPS15 P1D SEG20 RE0(5) / AN5 / P3A(1) / CCP3(1) / SEG21 RE0 AN5 P3A CCP3 SEG21 RE1
Name RD6(4) / CPS14 / P1C / SEG19
Input Type ST AN - - ST AN - - ST AN - ST - ST AN - - ST AN ST - TTL ST HV Power Power
Output Type CMOS General purpose I / O. - AN - AN -
Description
Capacitive sensing input 14. LCD analog output. Capacitive sensing input 15. LCD analog output. A / D Channel 5 input.
CMOS PWM output. CMOS General purpose I / O. CMOS PWM output. CMOS General purpose I / O. CMOS PWM output. CMOS Capture / Compare / PWM3. AN - AN - AN - - - - - LCD analog output. A / D Channel 6 input. LCD analog output. A / D Channel 7 input. LCD analog output. General purpose input. Master Clear with internal pull-up. Programming voltage. Positive supply. Ground reference. CMOS General purpose I / O. CMOS PWM output. CMOS General purpose I / O. CMOS Capture / Compare / PWM5.
RE1 AN6 P3B SEG22
/ AN7 / CCP5 / SEG23
RE2 AN7 CCP5 SEG23
RE3 / MCLR / VPP
RE3 MCLR VPP
VDD VSS
Preliminary
DS41364B-page 19
PIC16F193X / LF193X
NOTES:
DS41364B-page 20
Preliminary
PIC16F193X / LF193X
MEMORY ORGANIZATION
Program Memory Organization
The enhanced mid-range core has a 15-bit program counter capable of addressing 32K x 14 program memory space. Table 2-1 shows the memory sizes implemented for the PIC16F193X / LF193X device family. Accessing a location above these boundaries will cause a wrap-around within the implemented memory space. The Reset vector is at 0000h and the interrupt vector is at 0004h (see Figures 2-1, 2-2 and 2-3).
TABLE 2-1:
DEVICE SIZES AND ADDRESSES
Device Program Memory Space (Words) 4, 096 4, 096 8, 192 8, 192 16, 384 16, 384 Last Program Memory Address 0FFFh 0FFFh 1FFFh 1FFFh 3FFFh 3FFFh
PIC16F1933 / PIC16LF1933 PIC16F1934 / PIC16LF1934 PIC16F1936 / PIC16LF1936 PIC16F1937 / PIC16LF1937 PIC16F1938 / PIC16LF1938 PIC16F1939 / PIC16LF1939
Preliminary
DS41364B-page 21
PIC16F193X / LF193X
FIGURE 2-1: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1933 / PIC16LF1933 / PIC16F1934 / PIC16LF1934
FIGURE 2-2:
PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1936 / PIC16LF1936 / PIC16F1937 / PIC16LF1937
CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE
Stack Level 0 Stack Level 1 Stack Level 15 Reset Vector 0000h
Interrupt Vector On-chip Program Memory Page 0
0004h 0005h 07FFh 0800h
Interrupt Vector Page 0
0004h 0005h 07FFh 0800h
Page 1 Rollover to Page 0 0FFFh 1000h On-chip Program Memory
Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Rollover to Page 0 1FFFh 2000h
Rollover to Page 1
7FFFh
Rollover to Page 3
7FFFh
DS41364B-page 22
Preliminary
PIC16F193X / LF193X
FIGURE 2-3: PROGRAM MEMORY MAP AND STACK FOR THE PIC16F1938 / PIC16LF1938 / PIC16F1939 / PIC16LF1939
READING PROGRAM MEMORY AS DATA
There are two methods of accessing constants in program memory. The first method is to use tables of RETLW instructions. The second method is to set an FSR to point to the program memory.
RETLW Instruction
The RETLW instruction can be used to provide access to tables of constants. The recommended way to create such a table is shown in Example 2-1.
EXAMPLE 2-1:
constants brw retlw retlw retlw retlw
RETLW INSTRUCTION
Interrupt Vector On-chip Program Memory Page 0
0004h 0005h 07FFh 0800h
DATA1 DATA2 DATA3 DATA4
Page 1 0FFFh 1000h Page 2 17FFh 1800h Page 3 Page 4 1FFFh 2000h
The BRW instruction makes this type of table very simple to implement. If your code must remain portable with previous generations of microcontrollers, then the BRW instruction is not available so the older table read method must be used.
Indirect Read with FSR
Page 7 Rollover to Page 0
3FFFh 4000h
Rollover to Page 7
The program memory can be accessed as data by setting bit 7 of the FSRxH register and reading the matching INDFx register. The MOVIW instruction will place the lower 8 bits of the addressed word in the W register. Writes to the program memory cannot be performed via the INDF registers. Instructions that access the program memory via the FSR require one extra instruction cycle to complete. Example 2-2 demonstrates accessing the program memory via an FSR.
7FFFh
EXAMPLE 2-2:
ACCESSING PROGRAM MEMORY VIA FSR
bsf FSR1H, 7 moviw 0INDF1 THE PROGRAM MEMORY IS IN W
Preliminary
DS41364B-page 23
PIC16F193X / LF193X
2.2 Data Memory Organization
GENERAL PURPOSE REGISTER FILE
The general purpose register file is an 8-bit RAM memory for use by your application. There are up to 80 bytes of GPR in each data memory bank.
SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by the application to control the desired operation of peripheral functions in the device. The Special Function Registers can be classified into two sets: core and peripheral. The Special Function Registers associated with the "core" are described in the following sections. The registers associated with the operation of the peripherals are described in the appropriate peripheral chapter of this data sheet.
DS41364B-page 24
Preliminary
TABLE 2-2:
BANK 0
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 - TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON - CPSCON0 CPSCON1
PIC16F1933 / 1934 MEMORY MAP, BANKS 0-7
BANK 1
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 - OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 - General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page 25
PIC16F193X / LF193X
BANK 2
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 - APFCON - - General Purpose Register 80 Bytes 1EFh 1F0h
BANK 3
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB - ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 - - RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCTR 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK 4
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - WPUB - - WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 - - - - - - - - 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK 5
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON - CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h
BANK 6
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON - CCPR4L CCPR4H CCP4CON - CCPR5L CCPR5H CCP5CON - 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK 7
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - IOCBP IOCBN IOCBF - - - - - - - - -
Preliminary
06Fh 070h
General Purpose Register 96 Bytes
Accesses 70h - 7Fh
07Fh Legend: Note 1:
Not available on PIC16F1933 / 1936 / 1938 / PIC16LF1933 / 1936 / 1938.
TABLE 2-3:
BANK 8
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - TMR4 PR4 T4CON - - - - TMR6 PR6 T6CON -
PIC16F1933 / 1934 MEMORY MAP, BANKS 8-15
BANK 9
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page 26
PIC16F193X / LF193X
BANK 10
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK 11
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK 12
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK 13
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK 14
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
BANK 15
INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh - 78Ch - 78Dh - 78Eh - 78Fh - 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
Preliminary
TABLE 2-4:
BANK 0
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 - TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 TxCON - CPSCON0 CPSCON1
PIC16F1936 / 1937 MEMORY MAP, BANKS 0-7
BANK 1
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 - OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 - General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page 27
PIC16F193X / LF193X
BANK 2
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 - APFCON - - General Purpose Register 80 Bytes 1EFh 1F0h
BANK 3
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB - ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 - - RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK 4
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - WPUB - - WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 - - - - - - - - General Purpose Register 80 Bytes 2EFh 2F0h Accesses 70h - 7Fh 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK 5
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON - CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register 80 Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh
BANK 6
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON - CCPR4L CCPR4H CCP4CON - CCPR5L CCPR5H CCP5CON 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh
BANK 7
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - IOCBP IOCBN IOCBF - - - - - - - - -
Preliminary
06Fh 070h
General Purpose Register 96 Bytes
Accesses 70h - 7Fh
07Fh Legend: Note 1:
Not available on PIC16F1933 / 1936 / 1938 / PIC16LF1933 / 1936 / 1938.
TABLE 2-5:
BANK 8
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - TMR4 PR4 T4CON - - - - TMR6 PR6 T6CON -
PIC16F1936 / 1937 MEMORY MAP, BANKS 8-15
BANK 9
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page 28
PIC16F193X / LF193X
BANK 10
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK 11
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK 12
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK 13
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK 14
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
BANK 15
INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh - 78Ch - 78Dh - 78Eh - 78Fh - 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
Preliminary
TABLE 2-6:
BANK 0
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 - TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON - CPSCON0 CPSCON1
PIC16F1938 / 1939 MEMORY MAP, BANKS 0-7
BANK 1
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 - OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 - General Purpose Register 80 Bytes 0EFh 0F0h Accesses 70h - 7Fh 16Fh 170h Accesses 70h - 7Fh 17Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page 29
PIC16F193X / LF193X
BANK 2
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 - APFCON - - General Purpose Register 80 Bytes 1EFh 1F0h
BANK 3
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON ANSELA ANSELB - ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 - - RC1REG TX1REG SPBRGL1 SPBRGH1 RCSTA1 TXSTA1 BAUDCTL1 General Purpose Register 80 Bytes 26Fh 270h Accesses 70h - 7Fh 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK 4
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - WPUB - - WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 - - - - - - - - General Purpose Register 80 Bytes 2EFh 2F0h Accesses 70h - 7Fh 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK 5
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON - CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register 80 Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h 32Fh 330h 36Fh 370h Accesses 70h - 7Fh 37Fh
BANK 6
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON - CCPR4L CCPR4H CCP4CON - CCPR5L CCPR5H CCP5CON - General Purpose Register 80 Bytes 3EFh 3F0h Accesses 70h - 7Fh 3FFh 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK 7
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - IOCBP IOCBN IOCBF - - - - - - - - - General Purpose Register 80 Bytes
Preliminary
06Fh 070h
General Purpose Register 96 Bytes
Accesses 70h - 7Fh
07Fh Legend: Note 1:
TABLE 2-7:
BANK 8
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - TMR4 PR4 T4CON - - - - TMR6 PR6 T6CON - General Purpose Register 80 Bytes 46Fh 470h Accesses 70h - 7Fh 47Fh Legend:
PIC16F1938 / 1939 MEMORY MAP, BANKS 8-15
BANK 9
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - General Purpose Register 80 Bytes 4EFh 4F0h Accesses 70h - 7Fh 4FFh 57Fh 56Fh 570h Accesses 70h - 7Fh 5FFh 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page 30
PIC16F193X / LF193X
BANK 10
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - General Purpose Register 80 Bytes 5EFh 5F0h 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK 11
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - General Purpose Register 80 Bytes
BANK 12
BANK 13
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK 14
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
BANK 15
INDF0 780h INDF1 781h PCL 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h BSR 788h WREG 789h PCLATH 78Ah INTCON 78Bh - 78Ch - 78Dh - 78Eh - 78Fh - 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah See Table 2-10 or 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
Preliminary
Accesses 70h - 7Fh
TABLE 2-8:
BANK 16
800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
PIC16F193X / LF193X MEMORY MAP, BANKS 16-23
BANK 17
880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h
BANK 18
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h
BANK 19
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h
BANK 20
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h
BANK 21
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h
BANK 22
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h
BANK 23
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
Preliminary
DS41364B-page 31
PIC16F193X / LF193X
Accesses 70h - 7Fh
TABLE 2-9:
C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - -
PIC16F193X / LF193X MEMORY MAP, BANKS 24-31
BANK 25
C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h
DS41364B-page 32
PIC16F193X / LF193X
BANK 24
BANK 26
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h
BANK 27
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h
BANK 28
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h
BANK 29
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h
BANK 30
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON - - - - - - - - - - - - - - - - - - - - F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h
BANK 31
INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG PCLATH INTCON
Preliminary
See Table 2-12
PIC16F193X / LF193X
TABLE 2-10: PIC16F1933 / 1936 / 1938 MEMORY MAP, BANK 15
Bank 15
791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL - - LCDSE0 LCDSE1 - - - - - - LCDDATA0 LCDDATA1 - LCDDATA3 LCDDATA4 - LCDDATA6 LCDDATA7 - LCDDATA9 LCDDATA10 - - - - - - - - - - - - - 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h
TABLE 2-11:
PIC16F1934 / 1937 / 1939 MEMORY MAP, BANK 15
Bank 15
LCDCON LCDPS LCDREF LCDCST LCDRL - - LCDSE0 LCDSE1 LCDSE2 - - - - - LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11 - - - - - - - - - - - -
Preliminary
DS41364B-page 33
PIC16F193X / LF193X
TABLE 2-12: PIC16F193X / LF193X MEMORY MAP, BANK 31
Bank 31
DS41364B-page 34
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 0 000h(2) 001h(2) 002h(2) 003h(2) 004h(2) 005h(2) 006h(2) 007h(2) 008h(2) 009h(2) 00Bh(2) 00Ch 00Dh 00Eh 00Fh(3) 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RE2(3) CCP1IF LCDIF - RE1(3) TMR2IF - TMR4IF RE0(3) TMR1IF CCP2IF - -- xxxx -- uuuu 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0- - Name
SPECIAL FUNCTION REGISTER SUMMARY
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
00Ah(1, 2) PCLATH INTCON PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 PR2 T2CON - CPSCON0 CPSCON1
PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read - TMR1GIF OSFIF - - ADIF C2IF CCP5IF - RCIF C1IF CCP4IF - TXIF EEIF CCP3IF RE3 SSPIF BCLIF TMR6IF
Unimplemented Timer0 Module Register Holding Register for the Least Significant Byte of the 16-bit TMR1 Register Holding Register for the Most Significant Byte of the 16-bit TMR1 Register TMR1CS1 TMR1CS0 TMR1GE T1GPOL T1CKPS1 T1G T1CKPS0 T1GSPM T1OSCEN T1GGO / DONE T1SYNC T1GVAL - T1GSS1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000 - -
Timer 2 Module Register Timer 2 Period Register - T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
Unimplemented CPSON - - - - - - - CPSRNG1 CPSRNG0 CPSOUT CPSCH3 CPSCH2 CPSCH1 T0XCS
CPSCH0 -- 0000 -- 0000
Preliminary
DS41364B-page 35
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 1 080h(2) 081h(2) 082h(2) 083h(2) 084h(2) 085h(2) 086h(2) 087h(2) 088h(2) 089h(2) 08Bh(2) 08Ch 08Dh 08Eh 08Fh(3) 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 - TXIE EEIE CCP3IE TRISE3 SSPIE BCLIE TMR6IE TRISE2(3) TRISE1(3) TRISE0(3) -- 1111 -- 1111 CCP1IE LCDIE - TMR2IE - TMR4IE TMR1IE CCP2IE - 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0- T0CS - WDTPS4 TUN5 IRCF2 OSTS T0SE - WDTPS3 TUN4 IRCF1 HFIOFR PSA RMCLR WDTPS2 TUN3 IRCF0 HFIOFL PS2 RI WDTPS1 TUN2 - MFIOFR PS1 POR PS0 BOR - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register - TMR1GIE OSFIE - - ADIE C2IE CCP5IE - RCIE C1IE CCP4IE
Unimplemented WPUEN STKOVF - - SPLLEN T1OSCR INTEDG STKUNF - - IRCF3 PLLR
1111 1111 1111 1111 00- 11qq qq- qquu
WDTPS0 SWDTEN -01 0110 -01 0110 TUN1 SCS1 LFIOFR TUN0 SCS0 HFIOFR -00 0000 -00 0000 0011 1-00 0011 1-00 00q0 0q0- qqqq qq0xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
A / D Result Register Low A / D Result Register High - ADFM CHS4 ADCS2 CHS3 ADCS1 CHS2 ADCS0 CHS1 - CHS0 ADNREF GO / DONE ADON
ADPREF1 ADPREF0 0000 -000 0000 -000 - -
Unimplemented
DS41364B-page 36
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 2 100h(2) 101h(2) 102h(2) 103h(2) 104h(2) 105h(2) 106h(2) 107h(2) 108h(2) 109h(2) 10Bh(2) 10Ch 10Dh 10Eh 10Fh(3) 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu - C1OE C1PCH1 C2OE C2PCH1 - - TSEN DACOE -SRCLK1 SRSC2E - C1POL C1PCH0 C2POL C2PCH0 - - TSRNG -DACR4 SRCLK0 SRSC1E LATE3 - - - - - - CDAFVR1 DACPSS1 DACR3 SRQEN SRRPE LATE2(3) C1SP - C2SP - - - LATE1(3) C1HYS C1NCH1 C2HYS C2NCH1 LATE0(3) -- -xxx -- -uuu C1SYNC 0000 -100 0000 -100 C1NCH0 0000 -00 0000 -00 C2SYNC 0000 -100 0000 -100 C2NCH0 0000 -00 0000 -00 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
10Ah(1, 2) PCLATH INTCON LATA LATB LATC LATD LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 - APFCON - -
PORTA Data Latch PORTB Data Latch PORTC Data Latch PORTD Data Latch - C1ON C1INTP C2ON C2INTP - SBOREN FVREN DACEN -SRLEN SRSPE - C1OUT C1INTN C2OUT C2INTN - - FVRRDY DACLPS -SRCLK2 SRSCKE
MC2OUT MC1OUT -- -00 -- -00 - BORRDY 1-- --q u-- --u ADFVR0 0q00 0000 0q00 0000 DACNSS 000- 00-0 000- 00-0 DACR0 SRPR --0 0000 --0 0000 0000 0000 0000 0000
CDAFVR0 ADFVR1 DACPSS0 DACR2 SRNQEN SRRCKE -DACR1 SRPS SRRC2E
SRRC1E 0000 0000 0000 0000 - -
Unimplemented - CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL
CCP2SEL -000 0000 -000 0000 - - - -
Unimplemented Unimplemented
Preliminary
DS41364B-page 37
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 3 180h(2) 181h(2) 182h(2) 183h(2) 184h(2) 185h(2) 186h(2) 187h(2) 188h(2) 189h(2) 18Bh(2) 18Ch 18Dh 18Eh 18Fh(3) 190h(3) 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF ANSA1 ANSB1 IOCIF ANSA0 ANSB0 0000 000x 0000 000u -11 1111 -11 1111 -11 1111 -11 1111 - ANSD5 - ANSD4 - ANSD3 - ANSD2 ANSE2 ANSD1 ANSE1 ANSD0 ANSE0 - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE - - Unimplemented ANSD7 - ANSD6 - Write Buffer for the upper 7 bits of the Program Counter PEIE - - TMR0IE ANSA5 ANSB5 INTE ANSA4 ANSB4 IOCIE ANSA3 ANSB3 TMR0IF ANSA2 ANSB2
18Ah(1, 2) PCLATH INTCON ANSELA ANSELB - ANSELD ANSELE EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 - - RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON
1111 1111 1111 1111 -- -111 -- -111 0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu -xx xxxx -uu uuuu
EEPROM / Program Memory Address Register Low Byte - EEPROM / Program Memory Address Register High Byte
EEPROM / Program Memory Read Data Register Low Byte - EEPGD - CFGS EEPROM / Program Memory Read Data Register High Byte LWLO FREE WRERR WREN WR RD
0000 x000 0000 q000 0000 0000 0000 0000 - - - -
EEPROM control register 2 Unimplemented Unimplemented USART Receive Data Register USART Transmit Data Register BRG7 BRG15 SPEN CSRC ABDOVF BRG6 BRG14 RX9 TX9 RCIDL BRG5 BRG13 SREN TXEN - BRG4 BRG12 CREN SYNC SCKP BRG3 BRG11 ADDEN SENDB BRG16 BRG2 BRG10 FERR BRGH - BRG1 BRG9 OERR TRMT WUE BRG0 BRG8 RX9D TX9D ABDEN
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00
DS41364B-page 38
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 4 200h(2) 201h(2) 202h(2) 203h(2) 204h(2) 205h(2) 206h(2) 207h(2) 208h(2) 209h(2) 20Bh(2) 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
20Ah(1, 2) PCLATH INTCON - WPUB - - WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 - - - - - - - -
Unimplemented WPUB7 WPUB6
Unimplemented Unimplemented - - - - WPUE3 - - -
-- 1-- -- 1-xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer / Transmit Register ADD7 MSK7 SMP WCOL GCEN ACKTIM ADD6 MSK6 CKE SSPOV ACKSTAT PCIE ADD5 MSK5 D / A SSPEN ACKDT SCIE ADD4 MSK4 P CKP ACKEN BOEN ADD3 MSK3 S SSPM3 RCEN SDAHT ADD2 MSK2 R / W SSPM2 PEN SBCDE ADD1 MSK1 UA SSPM1 RSEN AHEN ADD0 MSK0 BF SSPM0 SEN DHEN
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
Preliminary
DS41364B-page 39
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 5 280h(2) 281h(2) 282h(2) 283h(2) 284h(2) 285h(2) 286h(2) 287h(2) 288h(2) 289h(2) 28Bh(2) 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - - - - - - - - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
28Ah(1, 2) PCLATH INTCON - - - - - CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON - CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture / Compare / PWM Register 1 (LSB) Capture / Compare / PWM Register 1 (MSB) P1M1 P1RSEN P1M0 P1DC6 DC1B1 P1DC5 CCP1AS1 - DC1B0 P1DC4 CCP1AS0 STR1SYNC CCP1M3 P1DC3 PSS1AC1 STR1D CCP1M2 P1DC2 CCP1M1 P1DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 P1DC0 0000 0000 0000 0000
CCP1ASE CCP1AS2 - Unimplemented -
PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 STR1C STR1B STR1A --0 0001 --0 0001 - -
Capture / Compare / PWM Register 2 (LSB) Capture / Compare / PWM Register 2 (MSB) P2M1 P2RSEN P2M0 P2DC6 DC2B1 P2DC5 CCP2AS1 - C3TSEL1 - DC2B0 P2DC4 CCP2AS0 STR2SYNC C3TSEL0 - CCP2M3 P2DC3 PSS2AC1 STR2D C2TSEL1 - CCP2M2 P2DC2 CCP2M1 P2DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 0000 0000 0000 0000 P2DC0 0000 0000 0000 0000
CCP2ASE CCP2AS2 - C4TSEL1 - - C4TSEL0 -
PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 STR2C STR2B STR2A --0 0001 --0 0001
C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 - C5TSEL1 C5TSEL0 -- -00 -- -00
DS41364B-page 40
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 6 300h(2) 301h(2) 302h(2) 303h(2) 304h(2) 305h(2) 306h(2) 307h(2) 308h(2) 309h(2) 30Bh(2) 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - - - - - - - - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
30Ah(1, 2) PCLATH INTCON - - - - - CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON - CCPR4L CCPR4H CCP4CON - CCPR5L CCPR5H CCP5CON -
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture / Compare / PWM Register 3 (LSB) Capture / Compare / PWM Register 3 (MSB) P3M1 P3RSEN P3M0 P3DC6 DC3B1 P3DC5 CCP3AS1 - DC3B0 P3DC4 CCP3AS0 STR3SYNC CCP3M3 P3DC3 PSS3AC1 STR3D CCP3M2 P3DC2 CCP3M1 P3DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M0 0000 0000 0000 0000 P3DC0 0000 0000 0000 0000
CCP3ASE CCP3AS2 - Unimplemented -
PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000 STR3C STR3B STR3A --0 0001 --0 0001 - -
Capture / Compare / PWM Register 4 (LSB) Capture / Compare / PWM Register 4 (MSB) - Unimplemented Capture / Compare / PWM Register 5 (LSB) Capture / Compare / PWM Register 5 (MSB) - Unimplemented - DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 - DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M0 -00 0000 -00 0000 - -
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP5M0 -00 0000 -00 0000 - -
Preliminary
DS41364B-page 41
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 7 380h(2) 381h(2) 382h(2) 383h(2) 384h(2) 385h(2) 386h(2) 387h(2) 388h(2) 389h(2) 38Bh(2) 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - - - - - - - IOCBP5 IOCBN5 IOCBF5 IOCBP4 IOCBN4 IOCBF4 IOCBP3 IOCBN3 IOCBF3 IOCBP2 IOCBN2 IOCBF2 IOCBP1 IOCBN1 IOCBF1 IOCBP0 IOCBN0 IOCBF0 - - - - - - - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
38Ah(1, 2) PCLATH INTCON - - - - - - - - IOCBP IOCBN IOCBF - - - - - - - - -
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented IOCBP7 IOCBN7 IOCBF7 IOCBP6 IOCBN6 IOCBF6
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
DS41364B-page 42
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 8 400h(2) 401h(2) 402h(2) 403h(2) 404h(2) 405h(2) 406h(2) 407h(2) 408h(2) 409h(2) 40Bh(2) 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - - - - - - - - - - - - - - - - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
40Ah(1, 2) PCLATH INTCON - - - - - - - - - TMR4 PR4 T4CON - - - - TMR6 PR6 T6CON -
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Timer 4 Module Register Timer 4 Period Register -
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
0000 0000 0000 0000 1111 1111 1111 1111 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000 - - - - - - - -
Unimplemented Unimplemented Unimplemented Unimplemented Timer 6 Module Register Timer 6 Period Register -
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0
0000 0000 0000 0000 1111 1111 1111 1111 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000 - -
Unimplemented
Preliminary
DS41364B-page 43
PIC16F193X / LF193X
TABLE 2-13:
Address Banks 9-14 x00h / x80h(2) x00h / x81h(2) x02h / x82h(2) x03h / x83h(2) x04h / x84h(2) x05h / x85h(2) x06h / x86h(2) x07h / x87h(2) x08h / x88h(2) x09h / x89h(2) INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
x0Ah / PCLATH x8Ah(1), (2) x0Bh / x8Bh(2) x0Ch / x8Ch - x1Fh / x9Fh Legend: Note 1: 2: 3: INTCON -
Unimplemented
DS41364B-page 44
Preliminary
PIC16F193X / LF193X
TABLE 2-13:
Address Bank 15 780h(2) 781h(2) 782h(2) 783h(2) 784h(2) 785h(2) 786h(2) 787h(2) 788h(2) 789h(2) 78Bh(2) 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h Legend: Note 1: 2: 3: INDF0 INDF1 PCL STATUS FSR0L FSR0H FSR1L FSR1H BSR WREG Addressing this location uses contents of FSR0H / FSR0L to address data memory (not a physical register) Addressing this location uses contents of FSR1H / FSR1L to address data memory (not a physical register) Program Counter (PC) Least Significant Byte - - - TO PD Z DC C xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 --1 1000 --q quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 --0 0000 --0 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u - - - - - WERR LCDA LCDIRI - LRLBP1 - WA - - LRLBP0 CS1 LP3 VLCD3PE - - CS0 LP2 LMUX1 LP1 LMUX0 LP0 - - - - - - Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Value on: POR, BOR Value on all other Resets
Indirect Data Memory Address 0 Low Pointer Indirect Data Memory Address 0 High Pointer Indirect Data Memory Address 1 Low Pointer Indirect Data Memory Address 1 High Pointer - - - BSR4
Working Register - GIE Write Buffer for the upper 7 bits of the Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
78Ah(1, 2) PCLATH INTCON - - - - - LCDCON LCDPS LCDREF LCDCST LCDRL - - LCDSE0 LCDSE1 LCDSE2(3) - - - - - LCDDATA0 LCDDATA1 LCDDATA2(3) LCDDATA3 LCDDATA4 LCDDATA5(3)
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented LCDEN WFT LCDIRE - LRLAP1 SLPEN BIASMD LCDIRS - LRLAP0
VLCD2PE VLCD1PE
LCDCST2 LCDCST1 LCDCST0 -- -000 -- -000 LRLAT2 LRLAT1 LRLAT0 0000 -000 0000 -000 - - - -
Unimplemented Unimplemented SE7 SE15 SE23 SE6 SE14 SE22 SE5 SE13 SE21 SE4 SE12 SE20 SE3 SE11 SE19 SE2 SE10 SE18 SE1 SE9 SE17 SE0 SE8 SE16
0000 0000 uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu - - - - - - - - - -
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
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