28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver nano
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PIC16F193X/LF193X Data Sheet
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver nanoWatt XLPTechnology
2009 Microchip Technology Inc.
DS41364B
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Microchip received ISO/TS-16949:2002 certification worldwide headquarters, design wafer fabrication facilities Chandler Tempe, Arizona; Gresham, Oregon design centers California India. Company's quality system processes procedures PIC® MCUs dsPIC® DSCs, KEELOQ® code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory analog products. addition, Microchip's quality system design manufacture development systems 9001:2000 certified.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
28/40/44-Pin Flash-Based, 8-Bit CMOS Microcontrollers with Driver with nano Watt XLPTechnology
Devices Included This Data Sheet:
PIC16F193X Devices: PIC16F1933 PIC16F1936 PIC16F1938 PIC16LF193X Devices: PIC16LF1933 PIC16LF1936 PIC16LF1938 PIC16LF1934 PIC16LF1937 PIC16LF1939 PIC16F1934 PIC16F1937 PIC16F1939
PIC16LF193X Low-Power Features:
Standby Current: 1.8V, typical Operating Current: kHz, 1.8V, typical MHz, 1.8V, typical Timer1 Oscillator Current: kHz, 1.8V, typical Low-Power Watchdog Timer Current: 1.8V, typical
Peripheral Features:
Pins Input-only pin: High-current source/sink direct drive Individually programmable Interrupt-on-pin change pins Individually programmable weak pull-ups Integrated Controller: segments Variable clock input Contrast control Internal voltage reference selections Capacitive Sensing Module (mTouchTM) selectable channels Converter: 10-bit resolution channels Selectable 1.024/2.048/4.096V voltage reference Timer0: 8-Bit Timer/Counter with 8-Bit Programmable Prescaler Enhanced Timer1 Dedicated low-power oscillator driver 16-bit timer/counter with prescaler External Gate Input mode with toggle single shot modes Interrupt-on-gate completion Timer2, 8-Bit Timer/Counter with 8-Bit Period Register, Prescaler Postscaler Capture, Compare, Modules (CCP) 16-bit Capture, max. resolution 16-bit Compare, max. resolution 10-bit PWM, max. frequency 31.25 Three Enhanced Capture, Compare, modules (ECCP) time-base options Auto-shutdown auto-restart steering Programmable Dead-band Delay
High-Performance RISC CPU:
Only Instructions Learn: single-cycle instructions except branches Operating Speed: oscillator/clock input instruction cycle Words Flash Program Memory 1024 Bytes Data Memory (RAM) Interrupt Capability with automatic context saving 16-Level Deep Hardware Stack Direct, Indirect Relative Addressing modes Processor Read Access Program Memory Pinout Compatible other 28/40-pin PIC16CXXX PIC16FXXX Microcontrollers
Special Microcontroller Features:
Precision Internal Oscillator: Factory calibrated ±1%, typical Software selectable frequency range from Power-Saving Sleep mode Power-on Reset (POR) Power-up Timer (PWRT) Oscillator Start-up Timer (OST) Brown-out Reset (BOR) Selectable between trip points Disable Sleep option Multiplexed Master Clear with Pull-up/Input Programmable Code Protection High Endurance Flash/EEPROM cell: 100,000 write Flash endurance 1,000,000 write EEPROM endurance Flash/Data EEPROM retention: years Wide Operating Voltage Range: 1.8V-5.5V (PIC16F193X) 1.8V-3.6V (PIC16LF193X)
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DS41364B-page
PIC16F193X/LF193X
Peripheral Features (Continued):
Master Synchronous Serial Port (MSSP) with Cwith: 7-bit address masking SMBUS/PMBUScompatibility Auto-wake-up start Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) RS-232, compatible Auto-Baud Detect Latch (555 Timer): Multiple Set/Reset input options Comparators: Rail-to-rail inputs/outputs Power mode control Software enable hysteresis Voltage Reference module: Fixed Voltage Reference (FVR) with 1.024V, 2.048V 4.096V output levels 5-bit rail-to-rail resistive with positive negative reference selection
PIC16F193X/LF193X Family Types
Program Memory Flash (words) Data EEPROM (bytes) SRAM (bytes) Comparators CapSense (ch) 10-bit (ch) I2CTM/SPI EUSART
Timers 8/16-bit
Device
ECCP
I/O's
PIC16F1933 PIC16LF1933 PIC16F1934 PIC16LF1934 PIC16F1936 PIC16LF1936 PIC16F1937 PIC16LF1937
4096 4096 8192 8192
1024 1024
16(1)/4 24/4 16(1)/4 24/4 16(1)/4 24/4
PIC16F1938 16384 PIC16LF1938 PIC16F1939 16384 PIC16LF1939 Note
COM3 SEG15 share same physical therefore, SEG15 available when using multiplex displays.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
Diagram 28-Pin SPDIP/SOIC/SSOP (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
28-pin SPDIP, SOIC, SSOP
VPP/MCLR/RE3 SEG12/VCAP /SRNQ /C2OUT /C12IN0-/AN0/RA0 SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG2/CLKIN/OSC1/RA7 SEG1/VCAP(2)/CLKOUT/OSC2/RA6 P2B(1)/T1CKI/T1OSO/RC0 P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3
PIC16F1933/1936/1938 PIC16LF1933/1936/1938
RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB4/AN11/CPS4/P1D/COM0 RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 RC7/RX/DT/P3B/SEG8 RC6/TX/CK/CCP3(1)/P3A(1)/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11
Note
function selectable APFCON register. PIC16F193X devices only.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
Diagram 28-Pin (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
28-pin
RA1/AN1/C12IN1-/SEG7
RE3/MCLR/VPP RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB4/AN11/CPS4/P1D/COM0
COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/COM3/VREF+/C1IN+/AN3/RA3 SEG2/CLKIN/OSC1/RA7 SEG1/VCAP(2)/CLKOUT/OSC2/RA6
Note
function selectable APFCON register. PIC16F193X devices only.
DS41364B-page
SEG3/P1A/CCP1/RC2 SEG6/SCL/SCK/RC3 SEG11/T1G(1)/SDA/SDI/RC4 SEG10/SDO/RC5 SEG9/P3A(1)/CCP3(1)/CK/TX/RC6
P2B(1)/T1CKI/T1OSO/RC0
(1)P2A/(1)CCP2/T1OSI/RC1
PIC16F1933/1936/1938 PIC16LF1933/1936/1938
RB2/AN8/CPS2/P1B/VLCD2 RB1/AN10/C12IN3-/CPS1/P1C/VLCD1 RB0/AN12/CPS0/CCP4/SRI/INT/SEG0 RC7/RX/DT/P3B/SEG8
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE
28-Pin 28-Pin
28-PIN SUMMARY (PIC16F1933/1936/1938, PIC16LF1933/1936/1938)
Comparator Sense Latch EUSART Interrupt ANSEL Pull-up Timers MSSP Basic VCAP(2) VCAP(2) OSC2/ CLKOUT VCAP(2) OSC1/ CLKIN ICSPCLK/ ICDCLK ICSPDAT/ ICDDAT MCLR/VPP SEG12 SEG7 COM2 SEG15/ COM3 SEG4 SEG5 SEG1 AN2/ VREFAN3/ VREF+
CPS6 CPS7
C12IN0-/ C2OUT(1) C12IN1C2IN+/ DACOUT C1IN+ C1OUT C2OUT(1)
SRNQ(1) SRNQ(1)
T0CKI
CCP5
SS(1) SS(1)
AN12 AN10 AN11 AN13
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5
C12IN3- C12IN2-
T1G(1)
CCP4 CCP2(1)/ P2A(1) P2B(1) CCP3(1)/ P3A(1) P2B(1) CCP2(1)/ P2A(1) CCP1/ CCP3(1) P3A(1)
SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1
INT/
Note
T1OSO/ T1CKI T1OSI T1G(1)
TX/CK RX/DT
SCK/SCL SDI/SDA
SEG14 SEG13 SEG3 SEG6 SEG11 SEG10 SEG9 SEG8
functions moved using APFCON register. PIC16F193X devices only.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
Diagram 40-Pin PDIP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
40-Pin PDIP
VPP/MCLR/RE3 SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/VREF+/C1IN+/AN3/RA3 SEG4/SRQ/T0CKI/CPS6/C1OUT/RA4 SEG21/CCP3(1)/P3A(1)/AN5/RE0 SEG22/P3B/AN6/RE1 SEG23/CCP5/AN7/RE2 SEG2/CLKIN/OSC1/RA7 SEG1/V
CAP(2)/CLKOUT/OSC2/RA6
PIC16F1934/1937/1939 PIC16LF1934/1937/1939
RB7/ICSPDAT/ICDDAT/SEG13 RB6/ICSPCLK/ICDCLK/SEG14 RB4/AN11/CPS4/COM0 RB2/AN8/CPS2/VLCD2 RB1/AN10/C12IN3-/CPS1/VLCD1 RB0/AN12/CPS0/SRI/INT/SEG0 RD7/CPS15/P1D/SEG20 RD6/CPS14/P1C/SEG19 RD5/CPS13/P1B/SEG18 RD4/CPS12/P2D/SEG17 RC7/RX/DT/SEG8 RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1)
(1)/T1CKI/T1OSO/RC0
P2A(1)/CCP2(1)/T1OSI/RC1 SEG3/P1A/CCP1/RC2 SEG6/SCK/SCL/RC3 COM3/CPS8/RD0 CCP4/CPS9/RD1
Note
function selectable APFCON register. PIC16F193X devices only.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
Diagram 44-Pin (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1) RC0/T1OSO/T1CKI/P2B(1) 44-pin
Note
function selectable APFCON register. PIC16F193X devices only.
2009 Microchip Technology Inc.
COM0/CPS4/AN11/RB4 SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 SEG12/VCAP SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15VREF+/C1IN+/AN3/RA3
SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2
PIC16F1934/1937/1939 PIC16LF1934/1937/1939
RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
DS41364B-page
PIC16F193X/LF193X
Diagram 44-Pin TQFP (PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
44-pin TQFP RC6/TX/CK/SEG9 RC5/SDO/SEG10 RC4/SDI/SDA/T1G(1)/SEG11 RD3/CPS11/P2C/SEG16 RD2/CPS10/P2B(1) RD1/CPS9/CCP4 RD0/CPS8/COM3 RC3/SCL/SCK/SEG6 RC2/CCP1/P1A/SEG3 RC1/T1OSI/CCP2(1)/P2A(1)
Note
function selectable APFCON register. PIC16F193X devices only.
COM0/CPS4/AN11/RB4 COM1/T1G SEG14/ICDCLK/ICSPCLK/RB6 SEG13/ICDDAT/ICSPDAT/RB7 VPP/MCLR/RE3 SEG7/C12IN1-/AN1/RA1 COM2/DACOUT/VREF-/C2IN+/AN2/RA2 SEG15/VREF+/C1IN+/AN3/RA3
SEG8/DT/RX/RC7 SEG17/P2D/CPS12/RD4 SEG18/P1B/CPS13/RD5 SEG19/P1C/CPS14/RD6 SEG20/P1D/CPS15/RD7 SEG0/INT/SRI/CPS0/AN12/RB0 VLCD1/CPS1/C12IN3-/AN10/RB1 VLCD2/CPS2/AN8/RB2
PIC16F1934/1937/1939 PIC16LF1934/1937/1939
RC0/T1OSO/T1CKI/P2B(1) RA6/OSC2/CLKOUT/VCAP(2)/SEG1 RA7/OSC1/CLKIN/SEG2 RE2/AN7/CCP5/SEG23 RE1/AN6/P3B/SEG22 RE0/AN5/CCP3(1)/P3A(1)/SEG21 RA4/C1OUT/CPS6/T0CKI/SRQ/SEG4
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2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE
44-Pin TQFP 40-Pin PDIP 44-Pin
40/44-PIN SUMMARY(PIC16F1934/1937/1939, PIC16LF1934/1937/1939)
Comparator Sense Latch EUSART Interrupt ANSEL Pull-up Timers MSSP Basic VCAP VCAP OSC2/ CLKOUT VCAP OSC1/ CLKIN ICSPCLK/ ICDCLK ICSPDAT/ ICDDAT MCLR/VPP SEG12 SEG7 COM2 SEG15 SEG4 SEG5 SEG1 AN2/ VREFAN3/ VREF+
CPS6 CPS7
C12IN0-/ C2OUT(1) C12IN1C2IN+/ DACOUT C1IN+ C1OUT C2OUT(1)
SRNQ(1) SRNQ(1)
T0CKI
SS(1) SS(1)
7,8,
AN12 AN10 AN11 AN13
CPS0 CPS1 CPS2 CPS3 CPS4 CPS5 CPS8 CPS9 CPS10 CPS11 CPS12 CPS13 CPS14 CPS15
C12IN3- C12IN2-
T1G(1) T1OSO/ T1CKI T1OSI T1G(1)
CCP2(1)/ P2A(1) CCP3(1)/ P3A(1) P2B(1) CCP2(1)/ P2A(1) CCP1/ CCP4 P2B(1) CCP3(1) P3A(1) CCP5
TX/CK RX/DT
SCK/SCL SDI/SDA
SEG2 SEG0 VLCD1 VLCD2 VLCD3 COM0 COM1 SEG14 SEG13 SEG3 SEG6 SEG11 SEG10 SEG9 SEG8 COM3 SEG16 SEG17 SEG18 SEG19 SEG20 SEG21 SEG22 SEG23
INT/
6,30,
Note
functions moved using APFCON register.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
Table Contents
Device Overview Memory Organization 10.0 Device Configuration Oscillator Module (With Fail-Safe Clock Monitor). Resets Interrupts 24.0 Power-Down Mode (Sleep) 23.0 Data EEPROM Flash Program Memory Control Ports Interrupt-on-Change 14.0 Fixed Voltage Reference (FVR) 11.0 Analog-to-Digital Converter (ADC) Module 13.0 Digital-to-Analog Converter (DAC) Module 12.0 Comparator Module. Latch. 15.0 Timer0 Module 16.0 Timer1 Module 17.0 Timer2/4/6 Modules. 19.0 Capture/Compare/PWM (ECCP1, ECCP2, ECCP3, CCP4, CCP5) Modules 22.0 Master Synchronous Serial Port (MSSP) Module 20.0 Enhanced Universal Synchronous Asynchronous Receiver Transmitter (EUSART) 18.0 Capacitive Sensing Module 21.0 Liquid Crystal Display (LCD) Driver Module 25.0 In-Circuit Serial Programming(ICSPTM) Dropout (LDO) Voltage Regulator 26.0 Instruction Summary 28.0 Electrical Specifications. 29.0 Characteristics Graphs Tables 27.0 Development Support. 30.0 Packaging Information. Appendix Revision History. Appendix Device Differences. Index Microchip Site Customer Change Notification Service Customer Support Reader Response Product Identification System.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
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Most Current Data Sheet
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Errata
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2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
NOTES:
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
DEVICE OVERVIEW
PIC16F193X/LF193X devices described within this data sheet. They available 28/40/44-pin packages. Figure shows block diagram PIC16F193X/LF193X devices. Table shows pinout descriptions.
FIGURE 1-1:
PIC16F193X/LF193X BLOCK DIAGRAM
Configuration Program Counter Flash Program Memory Data
PORTA PORTB PORTD PORTE RE3/MCLR
16-LevelStack Level Stack (13-bit) (15-bit) Program Memory Read (PMR)
Program
Addr
Addr
Instruction Instruction Direct Addr
Indirect Addr
FSR0 FSR1 STATUS STATUS PORTC
Power-up Timer Instruction Decode Decode Control OSC1/CLKIN OSC2/CLKOUT Timing Generation Oscillator Start-up Timer Power-on Reset Watchdog Timer Brown-out Reset
Internal Oscillator Block
Timer0
Timer1
Timer2/4/6
Timer1
Data EEPROM bytes
Comparators
CCP4/5
ECCP1/2/3
MSSP
Addressable EUSART
Latch
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
Enhanced Mid-range
PIC16F193X/LF193X devices contain enhanced mid-range 8-bit core. instructions. Interrupt capability includes automatic context saving. hardware stack levels deep Overflow Underflow Reset capability. Direct, indirect, relative addressing modes available. File Select Registers (FSRs) provide ability read program data memory. During interrupts, certain registers automatically saved shadow registers restored when returning from interrupt. This saves stack space user code. Section "Context Saving", more information.
1.1.1
16-LEVEL STACK WITH OVERFLOW UNDERFLOW RESET
PIC16F193X/LF193X devices have external stack memory bits wide deep. During normal operation, stack assumed words deep. enabled, Stack Overflow Underflow will appropriate (STKOVF STKUNF) PCON register, cause software Reset. section Section "Stack" more details.
1.1.2
FILE SELECT REGISTERS
There 16-bit File Select Registers (FSR). FSRs access file registers program memory, which allows data pointer memory. When points program memory, there additional instruction cycle instructions using INDF allow data fetched. There also instructions support FSRs. Section "Indirect Addressing, INDF Registers" more details.
1.1.3
INSTRUCTION
There instructions enhanced mid-range support features CPU. Section 26.0 "Instruction Summary" more details.
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PIC16F193X/LF193X
TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION
Function C12IN0C2OUT SRNQ VCAP SEG12 RA1/AN1/C12IN1-/SEG7 C12IN1SEG7 RA2/AN2/C2IN+/VREF-/CVREF/ COM2 C2IN+ VREFCVREF COM2 RA3/AN3/C1IN+/VREF+/ COM3(3)/SEG15 C1IN+ VREF+ COM3(3) SEG15 RA4/C1OUT/CPS6/T0CKI/SRQ/ CCP5/SEG4 Input Type
Name RA0/AN0/C12IN0-/C2OUT(1)/ SRNQ(1)/SS(1)/VCAP(2)/SEG12
Output Type CMOS General purpose I/O.
Description
Channel input.
Comparator negative input.
Power
CMOS Comparator output. CMOS Latch inverting output. Power
Slave Select input. Filter capacitor Voltage Regulator (PIC16F193X only). Analog output. Channel input.
Comparator negative input.
CMOS General purpose I/O.
Analog output. Channel input.
Comparator positive input.
CMOS General purpose I/O.
Negative Voltage Reference input. Comparator Voltage Reference output. Analog output. Channel input.
Comparator positive input.
CMOS General purpose I/O.
Voltage Reference input. Analog output. Analog output.
CMOS General purpose I/O.
C1OUT
CPS6 T0CKI CCP5 SEG4
CMOS Comparator output.
Capacitive sensing input Timer0 clock input.
CMOS Latch non-inverting output. CMOS Capture/Compare/PWM5. Power Analog output. Channel input. Capacitive sensing input Slave Select input. Filter capacitor Voltage Regulator (PIC16F193X only). Analog output. CMOS General purpose I/O.
RA5/AN4/C2OUT(1)/CPS7/ SRNQ(1)/SS(1)/VCAP(2)/SEG5
C2OUT
CPS7 SRNQ VCAP SEG5
Power
CMOS Comparator output.
CMOS Latch inverting output.
Legend: Analog input output CMOS CMOS compatible input output Open Drain compatible input Schmitt Trigger input with CMOS levels I2C= Schmitt Trigger input with High Voltage XTAL Crystal levels Note function selectable APFCON register. PIC16F193X devices only. devices only. PORTD available devices only. RE<2:0> available devices only
2009 Microchip Technology Inc.
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PIC16F193X/LF193X
TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Function OSC2 CLKOUT VCAP SEG1 RA7/OSC1/CLKIN/SEG2 OSC1 CLKIN SEG2 RB0/AN12/CPS0/CCP4/SRI/INT/ SEG0 AN12 CPS0 CCP4 SEG0 RB1/AN10/C12IN3-/CPS1/P1C/ VLCD1 AN10 C12IN3CPS1 VLCD1 RB2/AN8/CPS2/P1B/VLCD2 CPS2 VLCD2 RB3/AN9/C12IN2-/CPS3/ CCP2(1)/P2A(1)/VLCD3 C12IN2CPS3 CCP2 VLCD3 Input Type Power XTAL CMOS
Name RA6/OSC2/CLKOUT/VCAP(2)/ SEG1
Output Type CMOS General purpose I/O. XTAL Power
Description
Crystal/Resonator (LP, modes). Filter capacitor Voltage Regulator (PIC16F193X only). Analog output. Crystal/Resonator (LP, modes). External clock input mode). Analog output.
CMOS FOSC/4 output.
CMOS General purpose I/O.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Capacitive sensing input Latch input. External interrupt. analog output.
CMOS Capture/Compare/PWM4.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
Channel input.
Comparator negative input.
Capacitive sensing input analog input.
CMOS output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Capacitive sensing input analog input.
CMOS output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up.
Channel input.
Comparator negative input.
Capacitive sensing input
CMOS Capture/Compare/PWM2. CMOS output. analog input.
Legend: Analog input output CMOS CMOS compatible input output Open Drain compatible input Schmitt Trigger input with CMOS levels I2C= Schmitt Trigger input with High Voltage XTAL Crystal levels Note function selectable APFCON register. PIC16F193X devices only. devices only. PORTD available devices only. RE<2:0> available devices only
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Function AN11 CPS4 COM0 RB5/AN13/CPS5/P2B/CCP3(1)/ P3A(1)/T1G(1)/COM1 AN13 CPS5 CCP3 COM1 RB6/ICSPCLK/ICDCLK/SEG14 ICSPCLK ICDCLK SEG14 RB7/ICSPDAT/ICDDAT/SEG13 ICSPDAT ICDDAT SEG13 RC0/T1OSO/T1CKI/P2B
Name RB4/AN11/CPS4/P1D/COM0
Input Type XTAL XTAL
Output Type
Description
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Capacitive sensing input Analog output.
CMOS output. CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Channel input. Capacitive sensing input
CMOS output. CMOS Capture/Compare/PWM3. CMOS output. Timer1 Gate input. Analog output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. Serial Programming Clock. In-Circuit Debug Clock. Analog output.
CMOS General purpose I/O. Individually controlled interrupt-on-change. Individually enabled pull-up. CMOS ICSPData I/O. CMOS In-Circuit Data I/O. XTAL Analog output. Timer1 oscillator connection. Timer1 clock input. CMOS General purpose I/O.
T1OSO T1CKI
CMOS output. CMOS General purpose I/O. XTAL Timer1 oscillator connection. CMOS Capture/Compare/PWM2. CMOS output. CMOS General purpose I/O. CMOS Capture/Compare/PWM1. CMOS output. Analog output. CMOS General purpose I/O. CMOS clock. I2Cclock. Analog output.
RC1/T1OSI/CCP2
/P2A
T1OSI CCP2
RC2/CCP1/P1A/SEG3
CCP1 SEG3
RC3/SCK/SCL/SEG6
SEG6
Legend: Analog input output CMOS CMOS compatible input output Open Drain compatible input Schmitt Trigger input with CMOS levels I2C= Schmitt Trigger input with High Voltage XTAL Crystal levels Note function selectable APFCON register. PIC16F193X devices only. devices only. PORTD available devices only. RE<2:0> available devices only
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Function SEG11 RC5/SDO/SEG10 SEG10 RC6/TX/CK/CCP3/P3A/SEG9 CCP3 SEG9 RC7/RX/DT/P3B/SEG8 SEG8 RD0(4)/CPS8/COM3 CPS8 COM3 RD1(4)/CPS9/CCP4 CPS9 CCP4 RD2(4)/CPS10/P2B CPS10 RD3(4)/CPS11/P2C/SEG16 CPS11 SEG16 RD4(4)/CPS12/P2D/SEG17 CPS12 SEG17 RD5(4)/CPS13/P1B/SEG18 CPS13 SEG18 Input Type Output Type CMOS General purpose I/O. data input. I2Cdata input/output. Timer1 Gate input. Analog output. Description Name RC4/SDI/SDA/T1G(1)/SEG11
CMOS General purpose I/O. CMOS data output. Analog output. CMOS General purpose I/O. CMOS USART asynchronous transmit. CMOS USART synchronous clock. CMOS Capture/Compare/PWM3. CMOS output. Analog output. USART asynchronous input. CMOS General purpose I/O. CMOS USART synchronous data. CMOS output. Analog output. Capacitive sensing input analog output. Capacitive sensing input CMOS General purpose I/O.
CMOS General purpose I/O. CMOS Capture/Compare/PWM4. CMOS General purpose I/O. Capacitive sensing input CMOS output. CMOS General purpose I/O. Capacitive sensing input analog output. Capacitive sensing input analog output. Capacitive sensing input analog output. CMOS output. CMOS General purpose I/O. CMOS output. CMOS General purpose I/O. CMOS output.
Legend: Analog input output CMOS CMOS compatible input output Open Drain compatible input Schmitt Trigger input with CMOS levels I2C= Schmitt Trigger input with High Voltage XTAL Crystal levels Note function selectable APFCON register. PIC16F193X devices only. devices only. PORTD available devices only. RE<2:0> available devices only
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 1-1: PIC16F193X/LF193X PINOUT DESCRIPTION (CONTINUED)
Function CPS14 SEG19 RD7(4)/CPS15/P1D/SEG20 CPS15 SEG20 RE0(5)/AN5/P3A(1)/CCP3(1)/ SEG21 CCP3 SEG21
Name RD6(4)/CPS14/P1C/SEG19
Input Type Power Power
Output Type CMOS General purpose I/O.
Description
Capacitive sensing input analog output. Capacitive sensing input analog output. Channel input.
CMOS output. CMOS General purpose I/O. CMOS output. CMOS General purpose I/O. CMOS output. CMOS Capture/Compare/PWM3. analog output. Channel input. analog output. Channel input. analog output. General purpose input. Master Clear with internal pull-up. Programming voltage. Positive supply. Ground reference. CMOS General purpose I/O. CMOS output. CMOS General purpose I/O. CMOS Capture/Compare/PWM5.
/AN6/P3B/SEG22
SEG22
/AN7/CCP5/SEG23
CCP5 SEG23
RE3/MCLR/VPP
MCLR
Legend: Analog input output CMOS CMOS compatible input output Open Drain compatible input Schmitt Trigger input with CMOS levels I2C= Schmitt Trigger input with High Voltage XTAL Crystal levels Note function selectable APFCON register. PIC16F193X devices only. devices only. PORTD available devices only. RE<2:0> available devices only
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
NOTES:
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
MEMORY ORGANIZATION
Program Memory Organization
enhanced mid-range core 15-bit program counter capable addressing program memory space. Table shows memory sizes implemented PIC16F193X/LF193X device family. Accessing location above these boundaries will cause wrap-around within implemented memory space. Reset vector 0000h interrupt vector 0004h (see Figures 2-1, 2-3).
TABLE 2-1:
DEVICE SIZES ADDRESSES
Device Program Memory Space (Words) 4,096 4,096 8,192 8,192 16,384 16,384 Last Program Memory Address 0FFFh 0FFFh 1FFFh 1FFFh 3FFFh 3FFFh
PIC16F1933/PIC16LF1933 PIC16F1934/PIC16LF1934 PIC16F1936/PIC16LF1936 PIC16F1937/PIC16LF1937 PIC16F1938/PIC16LF1938 PIC16F1939/PIC16LF1939
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
FIGURE 2-1: PROGRAM MEMORY STACK PIC16F1933/PIC16LF1933/ PIC16F1934/PIC16LF1934
PC<14:0> CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE
FIGURE 2-2:
PROGRAM MEMORY STACK PIC16F1936/PIC16LF1936/ PIC16F1937/PIC16LF1937
PC<14:0>
CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE
Stack Level Stack Level Stack Level Reset Vector 0000h
Stack Level Stack Level Stack Level Reset Vector 0000h
Interrupt Vector On-chip Program Memory Page
0004h 0005h 07FFh 0800h
Interrupt Vector Page
0004h 0005h 07FFh 0800h
Page Rollover Page 0FFFh 1000h On-chip Program Memory
Page 0FFFh 1000h Page 17FFh 1800h Page Rollover Page 1FFFh 2000h
Rollover Page
7FFFh
Rollover Page
7FFFh
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
FIGURE 2-3: PROGRAM MEMORY STACK PIC16F1938/PIC16LF1938/ PIC16F1939/PIC16LF1939
PC<14:0> CALL, CALLW RETURN, RETLW INTERRUPT, RETFIE Stack Level Stack Level Stack Level Reset Vector 0000h
2.1.1
READING PROGRAM MEMORY DATA
There methods accessing constants program memory. first method tables RETLW instructions. second method point program memory.
2.1.1.1
RETLW Instruction
RETLW instruction used provide access tables constants. recommended create such table shown Example 2-1.
EXAMPLE 2-1:
constants retlw retlw retlw retlw
RETLW INSTRUCTION
Interrupt Vector On-chip Program Memory Page
0004h 0005h 07FFh 0800h
DATA1 DATA2 DATA3 DATA4
Page 0FFFh 1000h Page 17FFh 1800h Page Page 1FFFh 2000h
my_function LOTS CODE. movlw DATA_INDEX call constants CONSTANT
instruction makes this type table very simple implement. your code must remain portable with previous generations microcontrollers, then instruction available older table read method must used.
2.1.1.2
Indirect Read with
Page Rollover Page
3FFFh 4000h
Rollover Page
program memory accessed data setting FSRxH register reading matching INDFx register. MOVIW instruction will place lower bits addressed word register. Writes program memory cannot performed INDF registers. Instructions that access program memory require extra instruction cycle complete. Example demonstrates accessing program memory FSR.
7FFFh
EXAMPLE 2-2:
ACCESSING PROGRAM MEMORY
FSR1H,7 moviw 0[INDF1] ;THE PROGRAM MEMORY
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
Data Memory Organization
data memory partitioned memory banks with bytes bank. Each bank consists core registers, Special Function Registers (SFR), common registers, bytes General Purpose Registers (GPR). active bank selected writing bank number into Bank Select Register (BSR). Unimplemented memory will read `0'. banks contain core SFRs common registers. Unimplemented SFRs GPRs will read `0'. data memory accessed either directly (via instructions that file registers) indirectly File Select Registers (FSR). Section "Indirect Addressing, INDF Registers" more information.
2.2.1
GENERAL PURPOSE REGISTER FILE
general purpose register file 8-bit memory your application. There bytes each data memory bank.
2.2.2
SPECIAL FUNCTION REGISTER
Special Function Registers registers used application control desired operation peripheral functions device. Special Function Registers classified into sets: core peripheral. Special Function Registers associated with "core" described following sections. registers associated with operation peripherals described appropriate peripheral chapter this data sheet.
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2009 Microchip Technology Inc.
TABLE 2-2:
BANK
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 T2CON CPSCON0 CPSCON1
PIC16F1933/1934 MEMORY MAP, BANKS
BANK
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 General Purpose Register Bytes 0EFh 0F0h Accesses 16Fh 170h Accesses 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 APFCON General Purpose Register Bytes 1EFh 1F0h
BANK
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON ANSELA ANSELB ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCTR 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON WPUB WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON CCPR4L CCPR4H CCP4CON CCPR5L CCPR5H CCP5CON 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON IOCBP IOCBN IOCBF
2009 Microchip Technology Inc.
06Fh 070h
General Purpose Register Bytes
Unimplemented Read 26Fh 270h Accesses 27Fh
Unimplemented Read 2EFh 2F0h Accesses 2FFh
Unimplemented Read 36Fh 370h Accesses 37Fh
Unimplemented Read 3EFh 3F0h Accesses 3FFh
Unimplemented Read
Accesses
07Fh Legend: Note
0FFh 17Fh Unimplemented data memory locations, read `0'.
available
TABLE 2-3:
BANK
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TMR4 T4CON TMR6 T6CON
PIC16F1933/1934 MEMORY MAP, BANKS 8-15
BANK
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
BANK
INDF0 780h INDF1 781h 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h 788h WREG 789h PCLATH 78Ah INTCON 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah Table 2-10 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
2009 Microchip Technology Inc.
Unimplemented Read 46Fh 470h Accesses 47Fh Legend: 4FFh 4EFh 4F0h
Unimplemented Read 56Fh 570h Accesses 57Fh
Unimplemented Read 5EFh 5F0h Accesses 5FFh
Unimplemented Read 66Fh 670h Accesses 67Fh
Unimplemented Read 6EFh 6F0h Accesses 6FFh
Unimplemented Read 76Fh 770h Accesses 77Fh
Unimplemented Read 7EFh 7F0h Accesses 7FFh Accesses
Unimplemented data memory locations, read `0'.
TABLE 2-4:
BANK
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 TxCON CPSCON0 CPSCON1
PIC16F1936/1937 MEMORY MAP, BANKS
BANK
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 General Purpose Register Bytes 0EFh 0F0h Accesses 16Fh 170h Accesses 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 APFCON General Purpose Register Bytes 1EFh 1F0h
BANK
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON ANSELA ANSELB ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON General Purpose Register Bytes 26Fh 270h Accesses 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON WPUB WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 General Purpose Register Bytes 2EFh 2F0h Accesses 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON CCPR4L CCPR4H CCP4CON CCPR5L CCPR5H CCP5CON 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON IOCBP IOCBN IOCBF
2009 Microchip Technology Inc.
31Fh 39Fh 320h General Purpose 3A0h Register Bytes 32Fh 330h 36Fh 370h Unimplemented Read 3EFh 3F0h Accesses 37Fh 3FFh
06Fh 070h
General Purpose Register Bytes
Unimplemented Read
Accesses
Accesses
07Fh Legend: Note
0FFh 17Fh Unimplemented data memory locations, read `0'.
available
TABLE 2-5:
BANK
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TMR4 T4CON TMR6 T6CON
PIC16F1936/1937 MEMORY MAP, BANKS 8-15
BANK
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 600h 601h 602h 603h 604h 605h 606h 607h 608h 609h 60Ah 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
BANK
INDF0 780h INDF1 781h 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h 788h WREG 789h PCLATH 78Ah INTCON 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah Table 2-10 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
2009 Microchip Technology Inc.
Unimplemented Read 46Fh 470h Accesses 47Fh Legend: 4FFh 4EFh 4F0h
Unimplemented Read 56Fh 570h Accesses 57Fh
Unimplemented Read 5EFh 5F0h Accesses 5FFh
Unimplemented Read 66Fh 670h Accesses 67Fh
Unimplemented Read 6EFh 6F0h Accesses 6FFh
Unimplemented Read 76Fh 770h Accesses 77Fh
Unimplemented Read 7EFh 7F0h Accesses 7FFh Accesses
Unimplemented data memory locations, read `0'.
TABLE 2-6:
BANK
000h 001h 002h 003h 004h 005h 006h 007h 008h 009h 00Ah 00Bh 00Ch 00Dh 00Eh 00Fh 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh 020h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON PORTA PORTB PORTC PORTD(1) PORTE PIR1 PIR2 PIR3 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 T2CON CPSCON0 CPSCON1
PIC16F1938/1939 MEMORY MAP, BANKS
BANK
080h 081h 082h 083h 084h 085h 086h 087h 088h 089h 08Ah 08Bh 08Ch 08Dh 08Eh 08Fh 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh 0A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TRISA TRISB TRISC TRISD(1) TRISE PIE1 PIE2 PIE3 OPTION PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1 General Purpose Register Bytes 0EFh 0F0h Accesses 16Fh 170h Accesses 17Fh 1FFh 100h 101h 102h 103h 104h 105h 106h 107h 108h 109h 10Ah 10Bh 10Ch 10Dh 10Eh 10Fh 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh 120h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON LATA LATB LATC LATD(1) LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 APFCON General Purpose Register Bytes 1EFh 1F0h
BANK
180h 181h 182h 183h 184h 185h 186h 187h 188h 189h 18Ah 18Bh 18Ch 18Dh 18Eh 18Fh 190h 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh 1A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON ANSELA ANSELB ANSELD(1) ANSELE(1) EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 RC1REG TX1REG SPBRGL1 SPBRGH1 RCSTA1 TXSTA1 BAUDCTL1 General Purpose Register Bytes 26Fh 270h Accesses 27Fh 200h 201h 202h 203h 204h 205h 206h 207h 208h 209h 20Ah 20Bh 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh 220h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON WPUB WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3 General Purpose Register Bytes 2EFh 2F0h Accesses 2FFh 280h 281h 282h 283h 284h 285h 286h 287h 288h 289h 28Ah 28Bh 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh 2A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1 General Purpose Register Bytes 300h 301h 302h 303h 304h 305h 306h 307h 308h 309h 30Ah 30Bh 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh 320h 32Fh 330h 36Fh 370h Accesses 37Fh
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON CCPR4L CCPR4H CCP4CON CCPR5L CCPR5H CCP5CON General Purpose Register Bytes 3EFh 3F0h Accesses 3FFh 380h 381h 382h 383h 384h 385h 386h 387h 388h 389h 38Ah 38Bh 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh 3A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON IOCBP IOCBN IOCBF General Purpose Register Bytes
2009 Microchip Technology Inc.
06Fh 070h
General Purpose Register Bytes
Accesses
07Fh Legend: Note
0FFh
Unimplemented data memory locations, read `0'. available
TABLE 2-7:
BANK
400h 401h 402h 403h 404h 405h 406h 407h 408h 409h 40Ah 40Bh 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh 420h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON TMR4 T4CON TMR6 T6CON General Purpose Register Bytes 46Fh 470h Accesses 47Fh Legend:
PIC16F1938/1939 MEMORY MAP, BANKS 8-15
BANK
480h 481h 482h 483h 484h 485h 486h 487h 488h 489h 48Ah 48Bh 48Ch 48Dh 48Eh 48Fh 490h 491h 492h 493h 494h 495h 496h 497h 498h 499h 49Ah 49Bh 49Ch 49Dh 49Eh 49Fh 4A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON General Purpose Register Bytes 4EFh 4F0h Accesses 4FFh 57Fh 56Fh 570h Accesses 5FFh 500h 501h 502h 503h 504h 505h 506h 507h 508h 509h 50Ah 50Bh 50Ch 50Dh 50Eh 50Fh 510h 511h 512h 513h 514h 515h 516h 517h 518h 519h 51Ah 51Bh 51Ch 51Dh 51Eh 51Fh 520h
DS41364B-page
PIC16F193X/LF193X
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON General Purpose Register Bytes 5EFh 5F0h 580h 581h 582h 583h 584h 585h 586h 587h 588h 589h 58Ah 58Bh 58Ch 58Dh 58Eh 58Fh 590h 591h 592h 593h 594h 595h 596h 597h 598h 599h 59Ah 59Bh 59Ch 59Dh 59Eh 59Fh 5A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON General Purpose Register Bytes
BANK
INDF0 600h INDF1 601h 602h STATUS 603h FSR0L 604h FSR0H 605h FSR1L 606h FSR1H 607h 608h WREG 609h PCLATH 60Ah INTCON 60Bh 60Ch 60Dh 60Eh 60Fh 610h 611h 612h 613h 614h 615h 616h 617h 618h 619h 61Ah 61Bh 61Ch 61Dh 61Eh 61Fh 620h General Purpose Register Bytes Unimplemented Read 66Fh 670h 6EFh 6F0h Accesses 67Fh 6FFh 680h 681h 682h 683h 684h 685h 686h 687h 688h 689h 68Ah 68Bh 68Ch 68Dh 68Eh 68Fh 690h 691h 692h 693h 694h 695h 696h 697h 698h 699h 69Ah 69Bh 69Ch 69Dh 69Eh 69Fh 6A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 700h 701h 702h 703h 704h 705h 706h 707h 708h 709h 70Ah 70Bh 70Ch 70Dh 70Eh 70Fh 710h 711h 712h 713h 714h 715h 716h 717h 718h 719h 71Ah 71Bh 71Ch 71Dh 71Eh 71Fh 720h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
BANK
INDF0 780h INDF1 781h 782h STATUS 783h FSR0L 784h FSR0H 785h FSR1L 786h FSR1H 787h 788h WREG 789h PCLATH 78Ah INTCON 78Bh 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah Table 2-10 79Bh Table 2-11 79Ch 79Dh 79Eh 79Fh 7A0h
2009 Microchip Technology Inc.
Unimplemented Read 76Fh 770h Accesses 77Fh
Unimplemented Read 7EFh 7F0h Accesses 7FFh Accesses
Accesses
Unimplemented data memory locations, read `0'.
TABLE 2-8:
BANK
800h 801h 802h 803h 804h 805h 806h 807h 808h 809h 80Ah 80Bh 80Ch 80Dh 80Eh 80Fh 810h 811h 812h 813h 814h 815h 816h 817h 818h 819h 81Ah 81Bh 81Ch 81Dh 81Eh 81Fh 820h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
PIC16F193X/LF193X MEMORY MAP, BANKS 16-23
BANK
880h 881h 882h 883h 884h 885h 886h 887h 888h 889h 88Ah 88Bh 88Ch 88Dh 88Eh 88Fh 890h 891h 892h 893h 894h 895h 896h 897h 898h 899h 89Ah 89Bh 89Ch 89Dh 89Eh 89Fh 8A0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 900h 901h 902h 903h 904h 905h 906h 907h 908h 909h 90Ah 90Bh 90Ch 90Dh 90Eh 90Fh 910h 911h 912h 913h 914h 915h 916h 917h 918h 919h 91Ah 91Bh 91Ch 91Dh 91Eh 91Fh 920h
2009 Microchip Technology Inc.
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON 980h 981h 982h 983h 984h 985h 986h 987h 988h 989h 98Ah 98Bh 98Ch 98Dh 98Eh 98Fh 990h 991h 992h 993h 994h 995h 996h 997h 998h 999h 99Ah 99Bh 99Ch 99Dh 99Eh 99Fh 9A0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON A00h A01h A02h A03h A04h A05h A06h A07h A08h A09h A0Ah A0Bh A0Ch A0Dh A0Eh A0Fh A10h A11h A12h A13h A14h A15h A16h A17h A18h A19h A1Ah A1Bh A1Ch A1Dh A1Eh A1Fh A20h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON A80h A81h A82h A83h A84h A85h A86h A87h A88h A89h A8Ah A8Bh A8Ch A8Dh A8Eh A8Fh A90h A91h A92h A93h A94h A95h A96h A97h A98h A99h A9Ah A9Bh A9Ch A9Dh A9Eh A9Fh AA0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON B00h B01h B02h B03h B04h B05h B06h B07h B08h B09h B0Ah B0Bh B0Ch B0Dh B0Eh B0Fh B10h B11h B12h B13h B14h B15h B16h B17h B18h B19h B1Ah B1Bh B1Ch B1Dh B1Eh B1Fh B20h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON B80h B81h B82h B83h B84h B85h B86h B87h B88h B89h B8Ah B8Bh B8Ch B8Dh B8Eh B8Fh B90h B91h B92h B93h B94h B95h B96h B97h B98h B99h B9Ah B9Bh B9Ch B9Dh B9Eh B9Fh BA0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
DS41364B-page
PIC16F193X/LF193X
Unimplemented Read 86Fh 870h Accesses 87Fh Legend: 8FFh 8EFh 8F0h
Unimplemented Read 96Fh 970h Accesses 97Fh
Unimplemented Read 9EFh 9F0h Accesses 9FFh
Unimplemented Read A6Fh A70h Accesses A7Fh
Unimplemented Read AEFh AF0h Accesses AFFh
Unimplemented Read B6Fh B70h Accesses B7Fh
Unimplemented Read BEFh BF0h Accesses BFFh
Unimplemented Read
Accesses
Unimplemented data memory locations, read `0'.
TABLE 2-9:
C00h C01h C02h C03h C04h C05h C06h C07h C08h C09h C0Ah C0Bh C0Ch C0Dh C0Eh C0Fh C10h C11h C12h C13h C14h C15h C16h C17h C18h C19h C1Ah C1Bh C1Ch C1Dh C1Eh C1Fh C20h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
PIC16F193X/LF193X MEMORY MAP, BANKS 24-31
BANK
C80h C81h C82h C83h C84h C85h C86h C87h C88h C89h C8Ah C8Bh C8Ch C8Dh C8Eh C8Fh C90h C91h C92h C93h C94h C95h C96h C97h C98h C99h C9Ah C9Bh C9Ch C9Dh C9Eh C9Fh CA0h INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON D00h D01h D02h D03h D04h D05h D06h D07h D08h D09h D0Ah D0Bh D0Ch D0Dh D0Eh D0Fh D10h D11h D12h D13h D14h D15h D16h D17h D18h D19h D1Ah D1Bh D1Ch D1Dh D1Eh D1Fh D20h
DS41364B-page
PIC16F193X/LF193X
BANK
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON D80h D81h D82h D83h D84h D85h D86h D87h D88h D89h D8Ah D8Bh D8Ch D8Dh D8Eh D8Fh D90h D91h D92h D93h D94h D95h D96h D97h D98h D99h D9Ah D9Bh D9Ch D9Dh D9Eh D9Fh DA0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON E00h E01h E02h E03h E04h E05h E06h E07h E08h E09h E0Ah E0Bh E0Ch E0Dh E0Eh E0Fh E10h E11h E12h E13h E14h E15h E16h E17h E18h E19h E1Ah E1Bh E1Ch E1Dh E1Eh E1Fh E20h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON E80h E81h E82h E83h E84h E85h E86h E87h E88h E89h E8Ah E8Bh E8Ch E8Dh E8Eh E8Fh E90h E91h E92h E93h E94h E95h E96h E97h E98h E99h E9Ah E9Bh E9Ch E9Dh E9Eh E9Fh EA0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON F00h F01h F02h F03h F04h F05h F06h F07h F08h F09h F0Ah F0Bh F0Ch F0Dh F0Eh F0Fh F10h F11h F12h F13h F14h F15h F16h F17h F18h F19h F1Ah F1Bh F1Ch F1Dh F1Eh F1Fh F20h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON F80h F81h F82h F83h F84h F85h F86h F87h F88h F89h F8Ah F8Bh F8Ch F8Dh F8Eh F8Fh F90h F91h F92h F93h F94h F95h F96h F97h F98h F99h F9Ah F9Bh F9Ch F9Dh F9Eh F9Fh FA0h
BANK
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG PCLATH INTCON
2009 Microchip Technology Inc.
Table 2-12
Unimplemented Read C6Fh C70h Accesses CFFh Legend: CFFh CEFh CF0h
Unimplemented Read D6Fh D70h Accesses D7Fh
Unimplemented Read DEFh DF0h Accesses DFFh
Unimplemented Read E6Fh E70h Accesses E7Fh
Unimplemented Read EEFh EF0h Accesses EFFh
Unimplemented Read F6Fh F70h Accesses F7Fh
Unimplemented Read FEFh FF0h Accesses FFFh Accesses
Unimplemented data memory locations, read `0'.
PIC16F193X/LF193X
TABLE 2-10: PIC16F1933/1936/1938 MEMORY MAP, BANK
Bank
791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h LCDCON LCDPS LCDREF LCDCST LCDRL LCDSE0 LCDSE1 LCDDATA0 LCDDATA1 LCDDATA3 LCDDATA4 LCDDATA6 LCDDATA7 LCDDATA9 LCDDATA10 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7ADh 7AEh 7AFh 7B0h 7B1h 7B2h 7B3h 7B4h 7B5h 7B6h 7B7h 7B8h
TABLE 2-11:
PIC16F1934/1937/1939 MEMORY MAP, BANK
Bank
LCDCON LCDPS LCDREF LCDCST LCDRL LCDSE0 LCDSE1 LCDSE2 LCDDATA0 LCDDATA1 LCDDATA2 LCDDATA3 LCDDATA4 LCDDATA5 LCDDATA6 LCDDATA7 LCDDATA8 LCDDATA9 LCDDATA10 LCDDATA11
Unimplemented Read 7EFh 7EFh Legend: Unimplemented data memory locations, read `0'. Legend:
Unimplemented Read
Unimplemented data memory locations, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-12: PIC16F193X/LF193X MEMORY MAP, BANK
Bank
F8Ch Unimplemented Read FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend:
STATUS_SHAD WREG_SHAD BSR_SHAD PCLATH_SHAD FSR0L_SHAD FSR0H_SHAD FSR1L_SHAD FSR1H_SHAD STKPTR TOSL TOSH Unimplemented data memory locations, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 000h(2) 001h(2) 002h(2) 003h(2) 004h(2) 005h(2) 006h(2) 007h(2) 008h(2) 009h(2) 00Bh(2) 00Ch 00Dh 00Eh 00Fh(3) 010h 011h 012h 013h 014h 015h 016h 017h 018h 019h 01Ah 01Bh 01Ch 01Dh 01Eh 01Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu RE2(3) CCP1IF LCDIF RE1(3) TMR2IF TMR4IF RE0(3) TMR1IF CCP2IF xxxx uuuu 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0- Name
SPECIAL FUNCTION REGISTER SUMMARY
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
00Ah(1, PCLATH INTCON PORTA PORTB PORTC PORTD PORTE PIR1 PIR2 PIR3 PIR4 TMR0 TMR1L TMR1H T1CON T1GCON TMR2 T2CON CPSCON0 CPSCON1
PORTA Data Latch when written: PORTA pins when read PORTB Data Latch when written: PORTB pins when read PORTC Data Latch when written: PORTC pins when read PORTD Data Latch when written: PORTD pins when read TMR1GIF OSFIF ADIF C2IF CCP5IF RCIF C1IF CCP4IF TXIF EEIF CCP3IF SSPIF BCLIF TMR6IF
Unimplemented Timer0 Module Register Holding Register Least Significant Byte 16-bit TMR1 Register Holding Register Most Significant Byte 16-bit TMR1 Register TMR1CS1 TMR1CS0 TMR1GE T1GPOL T1CKPS1 T1GT1CKPS0 T1GSPM T1OSCEN T1GGO/ DONE T1SYNC T1GVAL T1GSS1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu TMR1ON 0000 00-0 uuuu uu-u T1GSS0 0000 0x00 uuuu uxuu 0000 0000 0000 0000 1111 1111 1111 1111 TMR2ON T2CKPS1 T2CKPS0 -000 0000 -000 0000
Timer Module Register Timer Period Register T2OUTPS3 T2OUTPS2 T2OUTPS1 T2OUTPS0
Unimplemented CPSON CPSRNG1 CPSRNG0 CPSOUT CPSCH3 CPSCH2 CPSCH1 T0XCS
0000 0000
CPSCH0 0000 0000
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 080h(2) 081h(2) 082h(2) 083h(2) 084h(2) 085h(2) 086h(2) 087h(2) 088h(2) 089h(2) 08Bh(2) 08Ch 08Dh 08Eh 08Fh(3) 090h 091h 092h 093h 094h 095h 096h 097h 098h 099h 09Ah 09Bh 09Ch 09Dh 09Eh 09Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 1111 TXIE EEIE CCP3IE TRISE3 SSPIE BCLIE TMR6IE TRISE2(3) TRISE1(3) TRISE0(3) 1111 1111 CCP1IE LCDIE TMR2IE TMR4IE TMR1IE CCP2IE 0000 0000 0000 0000 0000 00-0 0000 00-0 -000 0-0- -000 0-0- T0CS WDTPS4 TUN5 IRCF2 OSTS T0SE WDTPS3 TUN4 IRCF1 HFIOFR RMCLR WDTPS2 TUN3 IRCF0 HFIOFL WDTPS1 TUN2 MFIOFR Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
08Ah(1, PCLATH INTCON TRISA TRISB TRISC TRISD TRISE PIE1 PIE2 PIE3 OPTION_REG PCON WDTCON OSCTUNE OSCCON OSCSTAT ADRESL ADRESH ADCON0 ADCON1
PORTA Data Direction Register PORTB Data Direction Register PORTC Data Direction Register PORTD Data Direction Register TMR1GIE OSFIE ADIE C2IE CCP5IE RCIE C1IE CCP4IE
Unimplemented WPUEN STKOVF SPLLEN T1OSCR INTEDG STKUNF IRCF3 PLLR
1111 1111 1111 1111 11qq qquu
WDTPS0 SWDTEN 0110 0110 TUN1 SCS1 LFIOFR TUN0 SCS0 HFIOFR 0000 0000 0011 1-00 0011 1-00 00q0 0q0- qqqq qq0xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Result Register Result Register High ADFM CHS4 ADCS2 CHS3 ADCS1 CHS2 ADCS0 CHS1 CHS0 ADNREF GO/DONE ADON
-000 0000 -000 0000
ADPREF1 ADPREF0 0000 -000 0000 -000
Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 100h(2) 101h(2) 102h(2) 103h(2) 104h(2) 105h(2) 106h(2) 107h(2) 108h(2) 109h(2) 10Bh(2) 10Ch 10Dh 10Eh 10Fh(3) 110h 111h 112h 113h 114h 115h 116h 117h 118h 119h 11Ah 11Bh 11Ch 11Dh 11Eh 11Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu C1OE C1PCH1 C2OE C2PCH1 TSEN DACOE -SRCLK1 SRSC2E C1POL C1PCH0 C2POL C2PCH0 TSRNG -DACR4 SRCLK0 SRSC1E LATE3 CDAFVR1 DACPSS1 DACR3 SRQEN SRRPE LATE2(3) C1SP C2SP LATE1(3) C1HYS C1NCH1 C2HYS C2NCH1 LATE0(3) -xxx -uuu C1SYNC 0000 -100 0000 -100 C1NCH0 0000 0000 C2SYNC 0000 -100 0000 -100 C2NCH0 0000 0000 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
10Ah(1, PCLATH INTCON LATA LATB LATC LATD LATE CM1CON0 CM1CON1 CM2CON0 CM2CON1 CMOUT BORCON FVRCON DACCON0 DACCON1 SRCON0 SRCON1 APFCON
PORTA Data Latch PORTB Data Latch PORTC Data Latch PORTD Data Latch C1ON C1INTP C2ON C2INTP SBOREN FVREN DACEN -SRLEN SRSPE C1OUT C1INTN C2OUT C2INTN FVRRDY DACLPS -SRCLK2 SRSCKE
MC2OUT MC1OUT BORRDY ADFVR0 0q00 0000 0q00 0000 DACNSS 000- 00-0 000- 00-0 DACR0 SRPR 0000 0000 0000 0000 0000 0000
CDAFVR0 ADFVR1 DACPSS0 DACR2 SRNQEN SRRCKE -DACR1 SRPS SRRC2E
SRRC1E 0000 0000 0000 0000
Unimplemented CCP3SEL T1GSEL P2BSEL SRNQSEL C2OUTSEL SSSEL
CCP2SEL -000 0000 -000 0000
Unimplemented Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 180h(2) 181h(2) 182h(2) 183h(2) 184h(2) 185h(2) 186h(2) 187h(2) 188h(2) 189h(2) 18Bh(2) 18Ch 18Dh 18Eh 18Fh(3) 190h(3) 191h 192h 193h 194h 195h 196h 197h 198h 199h 19Ah 19Bh 19Ch 19Dh 19Eh 19Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF ANSA1 ANSB1 IOCIF ANSA0 ANSB0 0000 000x 0000 000u 1111 1111 1111 1111 ANSD5 ANSD4 ANSD3 ANSD2 ANSE2 ANSD1 ANSE1 ANSD0 ANSE0 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Unimplemented ANSD7 ANSD6 Write Buffer upper bits Program Counter PEIE TMR0IE ANSA5 ANSB5 INTE ANSA4 ANSB4 IOCIE ANSA3 ANSB3 TMR0IF ANSA2 ANSB2
18Ah(1, PCLATH INTCON ANSELA ANSELB ANSELD ANSELE EEADRL EEADRH EEDATL EEDATH EECON1 EECON2 RCREG TXREG SPBRGL SPBRGH RCSTA TXSTA BAUDCON
1111 1111 1111 1111 -111 -111 0000 0000 0000 0000 -000 0000 -000 0000 xxxx xxxx uuuu uuuu xxxx uuuu
EEPROM Program Memory Address Register Byte EEPROM Program Memory Address Register High Byte
EEPROM Program Memory Read Data Register Byte EEPGD CFGS EEPROM Program Memory Read Data Register High Byte LWLO FREE WRERR WREN
0000 x000 0000 q000 0000 0000 0000 0000
EEPROM control register Unimplemented Unimplemented USART Receive Data Register USART Transmit Data Register BRG7 BRG15 SPEN CSRC ABDOVF BRG6 BRG14 RCIDL BRG5 BRG13 SREN TXEN BRG4 BRG12 CREN SYNC SCKP BRG3 BRG11 ADDEN SENDB BRG16 BRG2 BRG10 FERR BRGH BRG1 BRG9 OERR TRMT BRG0 BRG8 RX9D TX9D ABDEN
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 000x 0000 000x 0000 0010 0000 0010 01-0 0-00 01-0 0-00
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 200h(2) 201h(2) 202h(2) 203h(2) 204h(2) 205h(2) 206h(2) 207h(2) 208h(2) 209h(2) 20Bh(2) 20Ch 20Dh 20Eh 20Fh 210h 211h 212h 213h 214h 215h 216h 217h 218h 219h 21Ah 21Bh 21Ch 21Dh 21Eh 21Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u WPUB5 WPUB4 WPUB3 WPUB2 WPUB1 WPUB0 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
20Ah(1, PCLATH INTCON WPUB WPUE SSPBUF SSPADD SSPMSK SSPSTAT SSPCON1 SSPCON2 SSPCON3
Unimplemented WPUB7 WPUB6
1111 1111 1111 1111
Unimplemented Unimplemented WPUE3
1-xxxx xxxx uuuu uuuu
Synchronous Serial Port Receive Buffer/Transmit Register ADD7 MSK7 WCOL GCEN ACKTIM ADD6 MSK6 SSPOV ACKSTAT PCIE ADD5 MSK5 SSPEN ACKDT SCIE ADD4 MSK4 ACKEN BOEN ADD3 MSK3 SSPM3 RCEN SDAHT ADD2 MSK2 SSPM2 SBCDE ADD1 MSK1 SSPM1 RSEN AHEN ADD0 MSK0 SSPM0 DHEN
0000 0000 0000 0000 1111 1111 1111 1111 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 280h(2) 281h(2) 282h(2) 283h(2) 284h(2) 285h(2) 286h(2) 287h(2) 288h(2) 289h(2) 28Bh(2) 28Ch 28Dh 28Eh 28Fh 290h 291h 292h 293h 294h 295h 296h 297h 298h 299h 29Ah 29Bh 29Ch 29Dh 29Eh 29Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
28Ah(1, PCLATH INTCON CCPR1L CCPR1H CCP1CON PWM1CON CCP1AS PSTR1CON CCPR2L CCPR2H CCP2CON PWM2CON CCP2AS PSTR2CON CCPTMRS0 CCPTMRS1
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) P1M1 P1RSEN P1M0 P1DC6 DC1B1 P1DC5 CCP1AS1 DC1B0 P1DC4 CCP1AS0 STR1SYNC CCP1M3 P1DC3 PSS1AC1 STR1D CCP1M2 P1DC2 CCP1M1 P1DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP1M0 0000 0000 0000 0000 P1DC0 0000 0000 0000 0000
CCP1ASE CCP1AS2 Unimplemented
PSS1AC0 PSS1BD1 PSS1BD0 0000 0000 0000 0000 STR1C STR1B STR1A 0001 0001
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) P2M1 P2RSEN P2M0 P2DC6 DC2B1 P2DC5 CCP2AS1 C3TSEL1 DC2B0 P2DC4 CCP2AS0 STR2SYNC C3TSEL0 CCP2M3 P2DC3 PSS2AC1 STR2D C2TSEL1 CCP2M2 P2DC2 CCP2M1 P2DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP2M0 0000 0000 0000 0000 P2DC0 0000 0000 0000 0000
CCP2ASE CCP2AS2 C4TSEL1 C4TSEL0
PSS2AC0 PSS2BD1 PSS2BD0 0000 0000 0000 0000 STR2C STR2B STR2A 0001 0001
C2TSEL0 C1TSEL1 C1TSEL0 0000 0000 0000 0000 C5TSEL1 C5TSEL0
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 300h(2) 301h(2) 302h(2) 303h(2) 304h(2) 305h(2) 306h(2) 307h(2) 308h(2) 309h(2) 30Bh(2) 30Ch 30Dh 30Eh 30Fh 310h 311h 312h 313h 314h 315h 316h 317h 318h 319h 31Ah 31Bh 31Ch 31Dh 31Eh 31Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
30Ah(1, PCLATH INTCON CCPR3L CCPR3H CCP3CON PWM3CON CCP3AS PSTR3CON CCPR4L CCPR4H CCP4CON CCPR5L CCPR5H CCP5CON
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) P3M1 P3RSEN P3M0 P3DC6 DC3B1 P3DC5 CCP3AS1 DC3B0 P3DC4 CCP3AS0 STR3SYNC CCP3M3 P3DC3 PSS3AC1 STR3D CCP3M2 P3DC2 CCP3M1 P3DC1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP3M0 0000 0000 0000 0000 P3DC0 0000 0000 0000 0000
CCP3ASE CCP3AS2 Unimplemented
PSS3AC0 PSS3BD1 PSS3BD0 0000 0000 0000 0000 STR3C STR3B STR3A 0001 0001
Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) Unimplemented Capture/Compare/PWM Register (LSB) Capture/Compare/PWM Register (MSB) Unimplemented DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP4M0 0000 0000
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu CCP5M0 0000 0000
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 380h(2) 381h(2) 382h(2) 383h(2) 384h(2) 385h(2) 386h(2) 387h(2) 388h(2) 389h(2) 38Bh(2) 38Ch 38Dh 38Eh 38Fh 390h 391h 392h 393h 394h 395h 396h 397h 398h 399h 39Ah 39Bh 39Ch 39Dh 39Eh 39Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u IOCBP5 IOCBN5 IOCBF5 IOCBP4 IOCBN4 IOCBF4 IOCBP3 IOCBN3 IOCBF3 IOCBP2 IOCBN2 IOCBF2 IOCBP1 IOCBN1 IOCBF1 IOCBP0 IOCBN0 IOCBF0 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
38Ah(1, PCLATH INTCON IOCBP IOCBN IOCBF
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented IOCBP7 IOCBN7 IOCBF7 IOCBP6 IOCBN6 IOCBF6
0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 400h(2) 401h(2) 402h(2) 403h(2) 404h(2) 405h(2) 406h(2) 407h(2) 408h(2) 409h(2) 40Bh(2) 40Ch 40Dh 40Eh 40Fh 410h 411h 412h 413h 414h 415h 416h 417h 418h 419h 41Ah 41Bh 41Ch 41Dh 41Eh 41Fh Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
40Ah(1, PCLATH INTCON TMR4 T4CON TMR6 T6CON
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented Timer Module Register Timer Period Register
T4OUTPS3 T4OUTPS2 T4OUTPS1 T4OUTPS0
0000 0000 0000 0000 1111 1111 1111 1111 TMR4ON T4CKPS1 T4CKPS0 -000 0000 -000 0000
Unimplemented Unimplemented Unimplemented Unimplemented Timer Module Register Timer Period Register
T6OUTPS3 T6OUTPS2 T6OUTPS1 T6OUTPS0
0000 0000 0000 0000 1111 1111 1111 1111 TMR6ON T6CKPS1 T6CKPS0 -000 0000 -000 0000
Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Banks 9-14 x00h/ x80h(2) x00h/ x81h(2) x02h/ x82h(2) x03h/ x83h(2) x04h/ x84h(2) x05h/ x85h(2) x06h/ x86h(2) x07h/ x87h(2) x08h/ x88h(2) x09h/ x89h(2) INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
x0Ah/ PCLATH x8Ah(1),(2) x0Bh/ x8Bh(2) x0Ch/ x8Ch x1Fh/ x9Fh Legend: Note INTCON
Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Bank 780h(2) 781h(2) 782h(2) 783h(2) 784h(2) 785h(2) 786h(2) 787h(2) 788h(2) 789h(2) 78Bh(2) 78Ch 78Dh 78Eh 78Fh 790h 791h 792h 793h 794h 795h 796h 797h 798h 799h 79Ah 79Bh 79Ch 79Dh 79Eh 79Fh 7A0h 7A1h 7A2h 7A3h 7A4h 7A5h Legend: Note INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u WERR LCDA LCDIRI LRLBP1 LRLBP0 VLCD3PE LMUX1 LMUX0 Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
78Ah(1, PCLATH INTCON LCDCON LCDPS LCDREF LCDCST LCDRL LCDSE0 LCDSE1 LCDSE2(3) LCDDATA0 LCDDATA1 LCDDATA2(3) LCDDATA3 LCDDATA4 LCDDATA5(3)
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented LCDEN LCDIRE LRLAP1 SLPEN BIASMD LCDIRS LRLAP0
000- 0011 000- 0011 0000 0000 0000 0000 000- 000- 000- 000-
VLCD2PE VLCD1PE
LCDCST2 LCDCST1 LCDCST0 -000 -000 LRLAT2 LRLAT1 LRLAT0 0000 -000 0000 -000
Unimplemented Unimplemented SE15 SE23 SE14 SE22 SE13 SE21 SE12 SE20 SE11 SE19 SE10 SE18 SE17 SE16
0000 0000 uuuu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu
Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented SEG7 COM0 SEG15 COM0 SEG23 COM0 SEG7 COM1 SEG15 COM1 SEG23 COM1 SEG6 COM0 SEG14 COM0 SEG22 COM0 SEG6 COM1 SEG14 COM1 SEG22 COM1 SEG5 COM0 SEG13 COM0 SEG21 COM0 SEG5 COM1 SEG13 COM1 SEG21 COM1 SEG4 COM0 SEG12 COM0 SEG20 COM0 SEG4 COM1 SEG12 COM1 SEG20 COM1 SEG3 COM0 SEG11 COM0 SEG19 COM0 SEG3 COM1 SEG11 COM1 SEG19 COM1 SEG2 COM0 SEG10 COM0 SEG18 COM0 SEG2 COM1 SEG10 COM1 SEG18 COM1 SEG1 COM0 SEG9 COM0 SEG17 COM0 SEG1 COM1 SEG9 COM1 SEG17 COM1 SEG0 COM0 SEG8 COM0 SEG16 COM0 SEG0 COM1 SEG8 COM1 SEG16 COM1
xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X
TABLE 2-13:
Address Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Bank (Continued) 7A6h 7A7h 7A8h 7A9h 7AAh 7ABh 7ACh 7EFh Legend: Note LCDDATA6 LCDDATA7 LCDDATA8(3) LCDDATA9 LCDDATA10 LCDDATA11(3) SEG7 COM2 SEG15 COM2 SEG23 COM2 SEG7 COM3 SEG15 COM3 SEG23 COM3 SEG6 COM2 SEG14 COM2 SEG22 COM2 SEG6 COM3 SEG14 COM3 SEG22 COM3 SEG5 COM2 SEG13 COM2 SEG21 COM2 SEG5 COM3 SEG13 COM3 SEG21 COM3 SEG4 COM2 SEG12 COM2 SEG20 COM2 SEG4 COM3 SEG12 COM3 SEG20 COM3 SEG3 COM2 SEG11 COM2 SEG19 COM2 SEG3 COM3 SEG11 COM3 SEG19 COM3 SEG2 COM2 SEG10 COM2 SEG18 COM2 SEG2 COM3 SEG10 COM3 SEG18 COM3 SEG1 COM2 SEG9 COM2 SEG17 COM2 SEG1 COM3 SEG9 COM3 SEG17 COM3 SEG0 COM2 SEG8 COM2 SEG16 COM2 SEG0 COM3 SEG8 COM3 SEG16 COM3 xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu xxxx xxxx uuuu uuuu
Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
DS41364B-page
2009 Microchip Technology Inc.
PIC16F193X/LF193X
TABLE 2-13:
Address Banks 16-30 x00h/ x80h(2) x00h/ x81h(2) x02h/ x82h(2) x03h/ x83h(2) x04h/ x84h(2) x05h/ x85h(2) x06h/ x86h(2) x07h/ x87h(2) x08h/ x88h(2) x09h/ x89h(2) INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000 BSR3 BSR2 BSR1 BSR0 0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000 INTF IOCIF 0000 000x 0000 000u Name
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF
x0Ah/ PCLATH x8Ah(1),(2) x0Bh/ x8Bh(2) x0Ch/ x8Ch x1Fh/ x9Fh Legend: Note INTCON
Unimplemented
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
2009 Microchip Technology Inc.
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PIC16F193X/LF193X
TABLE 2-13:
Address Bank F80h(2) F81h(2) F82h(2) F83h(2) F84h(2) F85h(2) F86h(2) F87h(2) F88h(2) F89h(2)
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Value POR, Value other Resets
Name
INDF0 INDF1 STATUS FSR0L FSR0H FSR1L FSR1H WREG
Addressing this location uses contents FSR0H/FSR0L address data memory (not physical register) Addressing this location uses contents FSR1H/FSR1L address data memory (not physical register) Program Counter (PC) Least Significant Byte
xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx 0000 0000 0000 0000 1000 quuu 0000 0000 uuuu uuuu 0000 0000 0000 0000 0000 0000 uuuu uuuu 0000 0000 0000 0000
Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer Indirect Data Memory Address Pointer Indirect Data Memory Address High Pointer BSR4 BSR3 BSR2 BSR1 BSR0
0000 0000 0000 0000 uuuu uuuu -000 0000 -000 0000
Working Register Write Buffer upper bits Program Counter PEIE TMR0IE INTE IOCIE TMR0IF INTF IOCIF
F8Ah(1),(2 PCLATH F8Bh(2) F8Ch FE3h FE4h FE5h FE6h FE7h FE8h FE9h FEAh FEBh FECh FEDh FEEh FEFh Legend: Note STKPTR TOSL TOSH INTCON
0000 000x 0000 000u
Unimplemented
STATUS_ SHAD WREG_ SHAD BSR_ SHAD PCLATH_ SHAD FSR0L_ SHAD FSR0H_ SHAD FSR1L_ SHAD FSR1H_ SHAD Unimplemented Current Stack pointer Working Register Normal (Non-ICD) Shadow
-xxx -uuu
xxxx xxxx uuuu uuuu
Bank Select Register Normal (Non-ICD) Shadow Program Counter Latch High Register Normal (Non-ICD) Shadow Indirect Data Memory Address Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address High Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address Pointer Normal (Non-ICD) Shadow Indirect Data Memory Address High Pointer Normal (Non-ICD) Shadow
xxxx uuuu
-xxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
xxxx xxxx uuuu uuuu
1111 1111 xxxx xxxx uuuu uuuu -xxx xxxx -uuu uuuu
Stack byte Stack High byte
unknown, unchanged, value depends condition, unimplemented, read `0', reserved. Shaded locations unimplemented, read `0'. upper byte program counter directly accessible. PCLATH holding register PC<14:8>, whose contents transferred upper byte program counter. These registers addressed from bank. These registers/bits implemented devices, read `0'.
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2009 Microchip Technology Inc.
PIC16F193X/LF193X
2.2.3 CORE REGISTERS
core registers contain registers that directly affect basic operation PIC16F193X/LF193X. These registers listed below: INDF0 INDF1 STATUS FSR0 FSR0 High FSR1 FSR1 High WREG PCLATH INTCON Note: core registers first addresses every data memory bank.
2009 Microchip Technology Inc.
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PIC16F193X/LF193X
2.2.3.1 STATUS Register
STATUS register, shown Register 2-1, contains: arithmetic status Reset status bank select bits data memory (SRAM) STATUS register destination instruction, like other register. STATUS register destination instruction that affects bits, then write these three bits disabled. These bits cleared according device logic. Furthermore, bits writable. Therefore, result instruction with STATUS register destination different than intended. example, CLRF STATUS will clear upper three bits bit. This leaves STATUS register `000u u1uu' (where unchanged). recommended, therefore, that only BCF, BSF, SWAPF MOVWF instructions used alter STATUS register, because these instructions affect Status bits. other instructions affecting Status bits (Refer Section 26.0 "Instruction Summary"). Note bits operate Borrow Digit Borrow bits, respectively, subtraction.
REGISTER 2-1:
Legend: Readable unchanged
STATUS: STATUS REGISTER
R-1/q R-1/q R/W-x/x R/W-x/x DC(1) R/W-x/x C(1)
Writable unknown cleared
Unimplemented bit, read -n/n Value BOR/Value other Resets Value depends condition
Unimplemented: Read Time-out After power-up, CLRWDT instruction SLEEP instruction time-out occurred Power-down After power-up CLRWDT instruction execution SLEEP instruction Zero result arithmetic logic operation zero result arithmetic logic operation zero Digit Carry/Digit Borrow (ADDWF, ADDLW,SUBLW,SUBWF instructions)(1) carry-out from low-order result occurred carry-out from low-order result Carry/Borrow bit(1) (ADDWF, ADDLW, SUBLW, SUBWF instructions)(1) carry-out from Most Significant result occurred carry-out from Most Significant result occurred Borrow, polarity reversed. subtraction executed adding two's complement second operand. rotate (RRF, RLF) instructions, this loaded with either high-order low-order source register.
Note
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PIC16F193X/LF193X
2.2.3.2 OPTION register
OPTION register, shown Register 2-2, readable writable register, which contains various control bits configure: External interrupt Timer0 Weak pull-ups
REGISTER 2-2:
R/W-1/1 WPUEN Legend: Readable unchanged
OPTION_REG: OPTION REGISTER
R/W-1/1 INTEDG R/W-1/1 T0CS R/W-1/1 T0SE R/W-1/1 R/W-1/1 R/W-1/1 R/W-1/1
Writable unknown cleared
Unimplemented bit, read -n/n Value BOR/Value other Resets
WPUEN: Weak Pull-up Enable weak pull-ups disabled (except MCLR, enabled) Weak pull-ups enabled individual WPUx latch values INTEDG: Interrupt Edge Select Interrupt rising edge RB0/INT Interrupt falling edge RB0/INT T0CS: Timer0 Clock Source Select Transition RA4/T0CKI Internal instruction cycle clock (FOSC/4) T0SE: Timer0 Source Edge Select Increment high-to-low transition RA4/T0CKI Increment low-to-high transition RA4/T0CKI PSA: Prescaler Assignment Prescaler inactive effect Timer0 interrupt rate Prescaler active affects Timer0 interrupt rate PS<2:0>: Prescaler Rate Select bits
Value Timer0 Rate
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PIC16F193X/LF193X
PCLATH
2.3.3 COMPUTED FUNCTION CALLS
Program Counter (PC) bits wide. byte comes from register, which readable writable register. high byte (PC<14:8>) directly readable writable comes from PCLATH. Reset, cleared. Figure shows five situations loading computed function CALL allows programs maintain tables functions provide another execute state machines look-up tables. When performing table read using computed function CALL, care should exercised table location crosses memory boundary (each 256-byte block). using CALL instruction, PCH<2:0> registers loaded with operand CALL instruction. PCH<6:3> loaded with PCLATH<6:3>. CALLW instruction enables computed calls combining PCLATH form destination address. computed CALLW accomplished loading register with desired address executing CALLW. register loaded with value loaded with PCLATH.
FIGURE 2-4:
PCLATH PCLATH PCLATH
LOADING DIFFERENT SITUATIONS
Instruction with Destination
Result
GOTO, CALL
2.3.4
BRANCHING
OPCODE <10:0>
CALLW
branching instructions offset This allows relocatable code code that crosses page boundaries. There forms branching, BRA. will have incremented fetch next instruction both cases. When using either branching instruction, memory boundary crossed. using BRW, load register with desired unsigned address execute BRW. entire will loaded with address using BRA, entire will loaded with signed value operand instruction.
Stack
OPCODE <8:0>
2.3.1
MODIFYING
Executing instruction with register destination simultaneously causes Program Counter PC<14:8> bits (PCH) replaced contents PCLATH register. This allows entire contents program counter changed writing desired upper bits PCLATH register. When lower bits written register, bits program counter will change values contained PCLATH register those being written register.
devices have 16-level 15-bit wide hardware stack (refer Figures 2-3). stack space part either program data space. PUSHed onto stack when CALL CALLW instructions executed interrupt causes branch. stack POPed event RETURN, RETLW RETFIE instruction execution. PCLATH affected PUSH operation. stack operates circular buffer, STVREN (Configuration Word This means that after stack been PUSHed sixteen times, seventeenth PUSH overwrites value that stored from first PUSH. eighteenth PUSH overwrites second PUSH (and on). Note There instructions/mnemonics called PUSH POP. These actions that occur from execution CALL, CALLW, RETURN, RETLW RETFIE instructions vectoring interrupt address.
2.3.2
COMPUTED GOTO
computed GOTO accomplished adding offset program counter (ADDWF PCL). When performing table read using computed GOTO method, care should exercised table location crosses memory boundary (each 256-byte block). Refer Application Note AN556, "Implementing Table Read" (DS00556).
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PIC16F193X/LF193X
2.4.1 ACCESSING STACK
stack available through TOSH, TOSL STKPTR registers. STKPTR current value Stack Pointer. TOSH:TOSL register pair points stack. Both registers read/writable. split into TOSH TOSL 15-bit size access stack, adjust value STKPTR, which will position TOSH:TOSL, then read/write TOSH:TOSL. STKPTR bits allow detection overflow underflow. During normal program operation, CALL, CALLW Interrupts will increment STKPTR while RETURN RETFIE will decrement STKPTR. time STKPTR inspected much stack left. STKPTR always points currently used place stack. Therefore, CALL CALLW will write then increment STKPTR, return will decrement then unload
Indirect Addressing, INDF Registers
INDFn registers physical registers. instruction that accesses INDFn register actually accesses register address specified File Select Registers (FSR). FSRn address specifies INDFn registers, read will return write will occur (though Status bits affected). FSRn register value created pair FSRnH FSRnL. registers form 16-bit address that allows addressing space with 65536 locations. These locations divided into three memory regions: Traditional Data Memory Linear Data Memory Program Flash Memory
2.4.2
OVERFLOW/UNDERFLOW RESET
STVREN Configuration Word programmed, device will reset stack PUSHed beyond sixteenth level POPed beyond first level, setting appropriate bits (STKOVF STKUNF, respectively) PCON register.
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FIGURE 2-5: INDIRECT ADDRESSING
0x0000
0x0000 Traditional Data Memory
0x0FFF 0x1000 0x1FFF 0x2000
0x0FFF Reserved
Linear Data Memory
0x29AF 0x29B0 Address Range 0x7FFF 0x8000 Reserved 0x0000
Program Flash Memory
0xFFFF
0x7FFF
Note:
memory regions completely implemented. Consult device memory tables memory limits.
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PIC16F193X/LF193X
2.5.1 TRADITIONAL DATA MEMORY
traditional data memory region from address 0x000 address 0xFFF. addresses correspond absolute addresses SFR, common registers.
FIGURE 2-6:
TRADITIONAL DATA MEMORY
Direct Addressing Indirect Addressing FSRxH Bank Select 1111 Location Select FSRxL
From Opcode
Bank Select
Location Select 0000 0x00 0001 0010
0x7F Bank Bank Bank Bank
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PIC16F193X/LF193X
2.5.2 LINEAR DATA MEMORY 2.5.3 PROGRAM FLASH MEMORY
linear data memory region from address 0x2000 address 0x29AF. This region virtual region that points back 80-byte blocks memory banks. Unimplemented memory reads 0x00. linear data memory region allows buffers larger than bytes because incrementing beyond bank will directly memory next bank. bytes common memory included linear data memory region. make constant data access easier, entire program Flash memory mapped upper half address space. When FSRnH set, lower bits address program memory which will accessed through INDF. Only lower bits each memory location accessible INDF. Writing program Flash memory cannot accomplished FSR/INDF interface. instructions that access program Flash memory FSR/INDF interface will require additional instruction cycle complete.
FIGURE 2-7:
LINEAR DATA MEMORY
FSRnL
FIGURE 2-8:
PROGRAM FLASH MEMORY
FSRnL
FSRnH
FSRnH
Location Select Location Select 0x2000 0x020 Bank 0x06F 0x0A0 Bank 0x0EF 0x120 Bank 0x16F
0x8000
0x0000
Program Flash Memory (low bits)
0xF20 Bank 0x29AF 0xF6F 0xFFFF 0x7FFF
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PIC16F193X/LF193X
RESETS
differentiates between PIC16F193X/LF193X various kinds Reset: Most registers affected wake-up since this viewed resumption normal operation. bits cleared differently different Reset situations, indicated Table 3-6. These bits used software determine nature Reset. simplified block diagram On-Chip Reset Circuit shown Figure 3-1. MCLR Reset path noise filter detect ignore small pulses. Section 28.0 "Electrical Specifications" pulse width specifications.
Power-on Reset (POR) Reset during normal operation MCLR Reset Brown-out Reset (BOR) RESET instruction Stack Overflow Stack Underflow
Some registers affected Reset condition; their status unknown unchanged other Reset. Most other registers reset "Reset state" Power-on Reset (POR) MCLR Reset Reset Brown-out Reset (BOR)
FIGURE 3-1:
RESET Instruction Stack Pointer
SIMPLIFIED BLOCK DIAGRAM ON-CHIP RESET CIRCUIT
Stack Full/Underflow Reset
External Reset MCLR Sleep Time-out Rise Detect Brown-out Reset Enable OST/PWRT OST(2) OSC1 1024 Cycles 10-bit Ripple Counter Chip_Reset Pulse MCLRE
PWRT(2) LFINTOSC 11-bit Ripple Counter
Enable PWRT Enable OST(1) Note Table time-out situations. PWRT counters reset BOR.
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TABLE 3-1: STATUS BITS THEIR SIGNIFICANCE
RMCLR Condition Power-on Reset Reset Illegal, Illegal, Brown-out Reset Reset Wake-up from Sleep Interrupt Wake-up from Sleep MCLR Reset during normal operation MCLR Reset during Sleep RESET Instruction Executed Stack Overflow Reset (STVREN Stack Underflow Reset (STVREN STKOVF STKUNF
TABLE 3-2:
RESET CONDITION SPECIAL REGISTERS(2)
Condition Program Counter 0000h 0000h 0000h 0000h 0000h
STATUS Register 1000 uuuu 0uuu uuuu 0uuu 1uuu 0uuu uuuu uuuu uuuu
PCON Register 110x 0uuu 0uuu uuuu uuuu 11u0 uuuu u0uu uuuu uuuu
Power-on Reset MCLR Reset during normal operation MCLR Reset during Sleep Reset Wake-up from Sleep Brown-out Reset Interrupt Wake-up from Sleep RESET Instruction Executed Stack Overflow Reset (STVREN Stack Underflow Reset (STVREN
0000h 0000h 0000h
Legend: unchanged, unknown, unimplemented bit, reads `0'. Note When wake-up interrupt Global Enable (GIE) set, return address pushed stack loaded with interrupt vector (0004h) after execution Status implemented, that will read `0'.
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PIC16F193X/LF193X
MCLR
PIC16F193X/LF193X noise filter MCLR Reset path. filter will detect ignore small pulses. should noted that Reset does drive MCLR low. Voltages applied that exceed specification result both MCLR Resets excessive current beyond device specification during event. this reason, Microchip recommends that MCLR longer tied directly VDD. network, shown Figure 3-2, suggested. internal MCLR option enabled clearing MCLRE Configuration Word register. When MCLRE Reset signal chip generated internally. When MCLRE RE3/MCLR becomes external Reset input. this mode, RE3/MCLR weak pull-up VDD. In-Circuit Serial Programming affected selecting internal MCLR option. Low-voltage programming (LVP) mode will override MCLRE. additional information, refer Application Note AN607, "Power-up Trouble Shooting" (DS00607).
Power-up Timer (PWRT)
Power-up Timer provides fixed (nominal) time-out power-up only, from Brown-out Reset. Power-up Timer operates from oscillator. more information, Section "Internal Clock Modes". chip kept Reset long PWRT active. PWRT delay allows rise acceptable level. Configuration bit, PWRTE, disable set) enable cleared programmed) Power-up Timer. Power-up Timer should enabled when Brown-out Reset enabled, although required. Power-up Timer delay will vary from chip-to-chip vary variation Temperature variation Process variation parameters details "Electrical Specifications"). Note: (Section 28.0
Power-up Timer enabled PWRTE Configuration Word.
FIGURE 3-2:
RECOMMENDED MCLR CIRCUIT
PIC®
Watchdog Timer (WDT)
following features: Independent prescaler from Timer0 Time-out period from 1.024 seconds, typical Enabled Configuration bits WDTE<1:0> disabled during Sleep Controlled WDTCON register cleared under certain conditions described Table 3-3.
MCLR
3.4.1
OSCILLATOR
Power-on Reset (POR)
on-chip circuit holds chip Reset until reached high enough level proper operation. maximum rise time required. Section 28.0 "Electrical Specifications" details. enabled, maximum rise time specification does apply. circuitry will keep device Reset until reaches VBOR (see Section "Brown-Out Reset (BOR)"). When device starts normal operation (exits Reset condition), device operating parameters (i.e., voltage, frequency, temperature, etc.) must ensure operation. these conditions met, device must held Reset until operating conditions met.
derives time base from internal oscillator. Note: When Oscillator Start-up Timer (OST) invoked, held Reset. When count expired, will begin counting enabled).
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3.4.2 CONTROL
WDTE<1:0> bits located Configuration Word Register When `11', runs continuously. When entering Sleep always cleared. When `10', enabled while running, disabled during Sleep. When `01' under control SWDTEN bit, when `00' always disabled. WDTCON register contains SWDTEN WDTPS<4:0> bits. When WDTE<1:0> bits Configuration Word register anything `01', SWDTEN effect. When WDTE SWDTEN used enable disable WDT. Setting will enable clearing will disable WDT. WDTPS<4:0> bits control prescaler. Register 3-1. Reset value WDTCON gives nominal interval ~2s. Upon Reset, SWDTEN value will leave disabled WDTE<1:0> `01' Configuration Word. prescaler will always cleared Reset.
FIGURE 3-3:
WATCHDOG TIMER BLOCK DIAGRAM
WDTE<1:0> WDTE<1:0> SWDTEN WDTE<1:0> WDTE<1:0> Sleep
LFINTOSC
23-bit Programmable Prescaler
Time-out
WDTPS<4:0>
TABLE 3-3:
STATUS
Conditions Cleared
WDTE<1:0> WDTE<1:0> SWDTEN WDTE<1:0> enter Sleep CLRWDT Command Oscillator Fail Detected Exit Sleep System Clock T1OSC, EXTRC, INTOSC, EXTCLK Exit Sleep System Clock Change INTOSC divider (IRCF bits)
Cleared until Unaffected
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REGISTER 3-1:
Legend: Readable unchanged Writable unknown cleared Unimplemented: Read WDTPS<4:0>: Watchdog Timer Period Select bits Value Prescale Rate 00000 1:32 (Interval typ) 00001 1:64 (Interval typ) 00010 1:128 (Interval typ) 00011 1:256 (Interval typ) 00100 1:512 (Interval typ) 00101 1:1024 (Interval typ) 00110 1:2048 (Interval typ) 00111 1:4096 (Interval typ) 01000 1:8192 (Interval typ) 01001 1:16384 (Interval typ) 01010 1:32768 (Interval typ) 01011 1:65536 (Interval typ) (Reset value) 01100 01101 01110 01111 10000 10001 10010 1:131072 (217) (Interval typ) 1:262144 (218) (Interval typ) 1:524288 (219) (Interval typ) 1:1048576 (220) (Interval typ) 1:2097152 (221) (Interval typ) 1:4194304 (222) (Interval 128s typ) 1:8388608 (223) (Interval 256s typ) Unimplemented bit, read -n/n Value BOR/Value other Resets
WDTCON: WATCHDOG TIMER CONTROL REGISTER
R/W-0/0 WDTPS4 R/W-1/1 WDTPS3 R/W-0/0 WDTPS2 R/W-1/1 WDTPS1 R/W-1/1 WDTPS0 R/W-0/0 SWDTEN
10011 Reserved. Results minimum interval (1:32) 11111 Reserved. Results minimum interval (1:32) SWDTEN: Software Enable/Disable Watchdog Timer WDTE<1:0> This ignored. WDTE<1:0> turned turned WDTE<1:0> This ignored.
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PIC16F193X/LF193X
Brown-Out Reset (BOR)
Brown-out Reset enabled programming BOREN<1:0> bits Configuration register. brown-out trip point selectable from trip points BORV Configuration register. Between BOR, complete voltage range coverage execution protection implemented. bits used enable BOR. When BOREN always enabled. When BOREN enabled, disabled during Sleep. When BOREN controlled SBOREN BORCON register. When BOREN disabled. falls below VBOR greater than parameter (TBOR) (see Section 28.0 "Electrical Specifications"), Brown-out situation will reset device. This will occur regardless slew rate. Reset ensured occur falls below VBOR more than parameter (TBOR). drops below VBOR while Power-up Timer running, chip will back into Brown-out Reset Power-up Timer will re-initialized. Once rises above VBOR, Power-up Timer will execute Reset.
TABLE 3-4:
OPERATING MODES
Device Device Operation upon Operation upon wake- from release Sleep Waits ready(1) Waits ready
BOREN Config bits BOR_ON (11) BOR_NSLEEP (10) BOR_NSLEEP (10) BOR_SBOREN (01) BOR_SBOREN (01) BOR_OFF (00)
SBOREN
Device Mode
Mode
Awake Sleep
Active Active Disabled Active Disabled Disabled
Begins immediately Begins immediately Begins immediately
Note Even though this case specifically waits BOR, already operating, there delay startup.
FIGURE 3-4:
BROWN-OUT SITUATIONS
VBOR
Internal Reset
ms(1)
VBOR
Internal Reset
ms(1)
VBOR
Internal Reset Note delay only PWRTE programmed `0'.
ms(1)
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2009 Microchip Technology Inc.
PIC16F193X/LF193X
REGISTER 3-2:
R/W-1/u SBOREN Legend: Readable unchanged Writable unknown cleared Unimplemented bit, read -n/n Value BOR/Value other Resets Value depends condition
BORCON: BROWN-OUT RESET CONTROL REGISTER
R/W-q/u BORRDY
SBOREN: Software Brown-out Reset Enable BOREN SBOREN read/write, effect BOR. BOREN Enabled Disabled Unimplemented: Read BORRDY: Brown-out Reset Circuit Ready Status Brown-out Reset circuit active armed Brown-out Reset circuit disabled warming
2009 Microchip Technology Inc.
DS41364B-page
PIC16F193X/LF193X<b
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