2008 APPLICATION NOTE 4267 Proven Implementations Salaz

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2008 APPLICATION NOTE 4267 Proven Implementations Salaz

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Maxim Notes Digital Potentiometers Keywords: MAXQ2000,
2008
APPLICATION NOTE 4267
Proven Implementations
Salazar, Applications Engineering Manager
Abstract: This application note briefly reviews history bus. then presents configurations proven ensure easy communication between master slaves bus. Examples include schematics code. Appendix contains helpful definitions terms used this article.
Introduction
Inter developed Philips Semiconductor early 1980s simplify electronic products reducing number parallel data lines. Version specification, released Philips® 1992, defined simple, 2-wire, bidirectional communication between ICs. 1998, become facto standard low-speed IC-to-IC communications. that time more than licensed companies were using standard, interface included more than 1000 different ICs. configurations presented this article have been proven ensure easy communication with slave devices bus. Each implementation includes examples form schematics code. reader should familiar with following documents:
Specification, Version 2.1, January 2000. Philips Semiconductor document #9398 40011. April 1995. Philips Semiconductor document #98-8080-575-01. System Management (SMBusTM) Specification, Version 2.0, August 2000.
Background Discussion
operate Standard mode, Fast mode, High-Speed (Hs) mode, with maximum data rates 100kbps (Standard mode), 400kbps (Fast mode), Mbps mode with 400pF), 3.4Mbps mode with 100pF). original Standard mode incorporated 7-bit addressing, which allowed slave addresses. systems demanded more slave devices, 10-bit addressing introduced allocate more slave addresses. Fast mode added useful features slave devices. maximum data rate quadrupled 400kbps. Fast-mode also dropped support similar buses often linked with bus, i.e., buses that were longer compatible with higher data rate. suppress noise spikes, Fast-mode devices were given Schmitt-triggered inputs. addition, lines slave device were required exhibit high impedance when power removed. mode created mainly increase data rate-up times faster than Standard mode. buses operating mode, most significant change affects low-to-high transitions line. Because pullup resistors used Standard Fast mode cannot produce rise times fast enough meet Hs-mode specification, most Hs-mode systems must include active pullups line. Other changes include Hs-mode compatibility request, issued Hs-mode master Standard Fast mode using 8-bit master code. Not-Acknowledge name within frame) remains high immediately following master code, then communications remain mode until stop occurs. waveforms Figure illustrate master code entering mode.
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Figure These waveforms represent transfer from Standard- Fast-mode mode.
Proven Implementations On-Chip Peripherals
PIC18F442 microcontroller (µC) includes peripheral that supports Standard- Fast-mode Figure shows application circuit using that peripheral collect samples from 16-bit serial-output (MAX1169). When data received PIC®, immediately transmitted 115kBaud firmware UART. RS-232 transceiver (MAX3232E) then allows data captured personal computer's standard serial port. assembly source files needed implement Fastmode PIC's on-chip peripheral contained file I2C_on_chip_asm.zip. tool called MPLAB Version 6.10.00 used develop assembly code Figure circuit.
Figure peripheral internal this PIC18F442 connects 16-bit (MAX1169).
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Proven Implementations Bit-Banging
MAXQ2000 low-power 16-bit RISC capable bit-banging Standard-mode, Fast-mode, even 1.7MHz Hs-mode signals. Figure shows general-purpose schematic MAXQ2000 operating master three modes. active pullup included MAXQ2000 support 1.7MHz mode. file I2C_bit_bang_asm.zip contains assembly source files needed bit-bang Standard- Fast-mode systems using µC's GPIO lines.
Figure This schematic (based MAXQ2000 low-power depicts master capable operating Standard, Fast, mode. default clock speed MAXQ2000's firmware 100kHz, µC's 16MHz system clock allows bit-banged interface fast 400kHz. following code example shows capture interrupt events handle them simple interrupt-service routine. development tool used MAX-IDE Version (build date: 2004), which downloaded free from Maxim website. file I2C_bit_bang_c.zip contains C-source files required bit-bang Standard- Fast-mode link using MAXQ2000's GPIO lines. This example Figure based maxqi2c library consisting files, maxqi2c.h maxqi2c.c. When added your project, these files allow 100kHz 400kHz operation GPIO pin. code produce specified speed, however, Figure must 20MHz crystal instead 16MHz crystal.
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Embedded Workbench® MAXQ2000 Version 1.12B (FAE edition) development tool used this case. register download free copy Embedded Workbench MAXQ2000 Kickstart Edition) website. file HSI2C_bit_bang_asm_c.zip contains assembly source files required bit-bang 1.7MHz Hs-mode link using MAXQ2000 GPIO lines. mixing assembly code, source code this example takes full advantage strength each code type. Assembly optimizes speed, accomplishes many things just lines code. timing-critical Hs-mode receive function (hsi2cRecv) defined assembly source file hsi2c.asm. main source file initializes MAXQ2000's UART 115.2kBaud. source code produce 1.7MHz Hs-mode link, Figure must 20MHz crystal. main source file calls hsi2cRecv function when needed, printf function transfers data from on-chip UART, which 8-N-1 data format. Rowley CrossWorks Version (Build licensed copy) development tool used this example. obtain CrossWorks IDE, contact Rowley Associates Limited visit their website.
Proven Implementations Core Peripherals
core called DI2CM Digital Core Design) used many CPLD FPGA devices. DI2CM core converts parallel interface interface, implements true Hs-mode master capable clock speeds high 3.4MHz. application circuit Figure Altera® EPM3256AQC208-10 CPLD includes DI2CM core. This circuit requires 40MHz crystal oscillator (U3) achieve compatibility with both 1.7MHz 3.4MHz Hs-mode 3-state logic buffer with output enable allows DI2CM core produce active pullup line, required Hs-mode Logic inverters provided support both active-high active-low memory-mapped parallel interface.
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More detailed image (PDF, 841KB) Figure Configured shown, DI2CM core this Altera EPM3256AQC208-10 CPLD implements Hs-mode master. file HSI2C_IP_core_asm.zip contains assembly source files needed implement Hs-mode master, obtained interfacing 68HC16's memory-mapped parallel interface Altera EPM3256 CPLD programmed with DI2CM core. development tool used this example Motorola® 68HC Macro Assembler Version 4.1.
Conclusion
Because currently industry's most widely used serial bus, behooves system designer have handful proven implementations readily available. method that choose-on-chip, bit-banged, IP-core implementation- depends principally system processor. Nonetheless, nothing easier than using approach that proven already works. This article includes working reference each three methods.
Appendix Definition Terms
CPLD: Complex programmable logic device DI2CM: Hs-mode core from Digital Core Design FPGA: Field-programmable gate array GPIO: General-purpose input outputs hsi2cRecv: Hs-mode receive function, written assembly language
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Hs-mode: High-speed mode Integrated circuit IDE: Integrated development environment Intellectual property Inter-IC MAXQ2000: low-power 16-bit RISC microcontroller RS-232: Recommended standard #232 SCL: Hardware serial-clock line SDA: Hardware serial data line UART: Universal asynchronous receiver-transmitter Microcontroller 8-N-1: bits, parity, stop
References Philips Semiconductor Staff, "The Specification," Version 2.1, January 2000. Philips Semiconductor document #9398 40011. Philips Semiconductor Staff, "The it," April 1995. Philips Semiconductor document #98-8080575-01. Implementers Forum, "System Management (SMBus) Specification," Version 2.0, August 2000. Salazar, Maxim application note 2394, "Interfacing MAX1169 Microcontroller." Salazar, Maxim application note 3568, "Using MAXQ2000 with MAX4397 Create Inexpensive Audio/ Video Source Selector." Maxim application note 3588, "Software Driver MAXQ2000 Microcontroller." Maxim application note 3561, "Getting Started with MAX-IDE." Digital Core Design Staff, "DI2CM Controller Master, Core Specification," Version 2.25.ma. similar article published Embedded.com website, August 2007. Altera registered trademark Altera Corporation. Embedded Workbench registered trademark Systems Motorola registered trademark Motorola, Inc. Philips registered trademark Philips Corp. registered trademark Microchip Technology, Inc. SMBus trademark Intel Corp.
Application note 4267: www.maxim-ic.com/an4267 More Information technical support: www.maxim-ic.com/support samples: www.maxim-ic.com/samples Other questions comments: www.maxim-ic.com/contact
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Related Parts MAX1169: QuickView Full (PDF) Data Sheet Free Samples MAXQ2000: QuickView Full (PDF) Data Sheet Free Samples
AN4267, 4267, APP4267, Appnote4267, Appnote 4267 Copyright Maxim Integrated Products Additional legal notices: www.maxim-ic.com/legal
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2008 APPLICATION NOTE 4267 Proven Implementations Salaz

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