Application Note 381: 2001 Novel Storage Idea Supports Ultra-Fast

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Application Note 381: 2001 Novel Storage Idea Supports Ultra-Fast

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CONVERSION/SAMPLING CIRCUITS HIGH-SPEED SIGNAL PROCESSING
Application Note 381: 2001
Novel Storage Idea Supports Ultra-Fast Data Acquisition following article describes slow down store high-speed data typical flash data converter such MAX101A. This note also provides helpful guidance layout, timing information simple test circuit evaluate performance ADC, while same time testing functionality FIFO memory design.
Fast data-acquisition systems other high-speed applications convert analog signals digital word streams prerequisite extraction demodulation information. properly apply converter these applications, should understand dynamic parameters, circuit layout, available methods storing high-speed digital data. This article describes MAX101A converter evaluation along with interface PC-layout considerations necessary high-frequency operation. particular, presents memory-storage concept valuable high-speed data-acquisition systems. special technique been tested proven with digitized data from high-speed ADC. MAX101A: Data-Acquisition Workhorse MAX101A flash resides special package that includes track/hold amplifier (T/H) with 1.2GHz input bandwidth, quantizer proprietary design that achieves excellent dynamic performance available current 8-bit, 500Msps converters. Careful design vital achieving this performance. amplifier resides separate chip fabricated with Maxim's junction-isolated process, laser-trimmed differential inputs accept full-scale amplitudes ±125mV differential ±250mV single-ended. When sampling clock high, input amplifier buffers drives hold capacitor. With sampling clock transitioning low, sampling bridge closes (within interval known "aperture delay") allows resulting analog value held presented quantizer. circuit also buffers applied differential clock signal feeds quantizer. converter sports effective number bits (ENOB) 250MHz Nyquist frequency, excellent value made possible T/H's wide -3dB bandwidth (greater than 1.2GHz). Even when undersampling 600MHz input tone 500Msps, this unique circuit achieves ENOB greater than 6.8. MAX101A's time-interleaved quantizers, each consisting voltage-interleaved 7bit flash stages, manufactured with Maxim's 27GHz GST-2 bipolar process. Each stage independent reference-resistor string driven external, user-supplied reference buffer. Interleaved 7-bit stages give MAX101A very rate metastable error (less than
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error 1018 conversions), which turn provides superior linearity. bias lets user optimize performance adjusting relative sample times interleaved converters. MAX101A's 8-bit, single-ended output ports have been made ECL-compatible accommodate high-speed data streams, however most memories used with MAX101A TTL-compatible. ECL-to-TTL-level shifters must therefore introduced adjust signal levels before they applied chips. Proper packaging essential performance high-speed ADCs. MAX101A package 84-lead, multilayer, nonhermetic, ceramic type whose stripline architecture closely controls impedance from from each external package pins. junction-to-ambient thermal resistance approximately 12°C/W with proper cooling (200ft/min), which achieved with combination heatsink (ideally) external fan. simple cooling computer power supplies does when mounted heatsink attached bottom chip. PC-Layout Power-Supply Considerations MAX101AEVKIT addition dynamic parameters, factors importance high-speed users include cost, power dissipation, input-signal conditioning, proper layout. excellent example high-quality layout MAX101A evaluation board (Figure
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Larger Image Figure MAX101A core design evaluation board
evaluation kit's multilayer board exhibits special attention layout. Containing high-speed analog digital circuitry evaluating flash converter's initial performance, data outputs (two 8-bit words) data-clock output. conjunction with MAX101A, specifies data rates 500Msps. board accommodates external clock source connector accepts analog inputs (AIN+ AIN-) other connectors. Each analog input connects directly with terminations internal MAX101A. separate termination board with pulldown resistors included with kit. Connected main board with 3x32-pin EURO-card connector, provides proper termination along with access converter's output data. termination board also features data-clock outputs square headers, each providing eight data outputs. high-speed logic analyzer (e.g. HP16500C) lets observe either AData BData. MAX101A main evaluation board comes fully assembled tested with MAX101A installed requires standard power supplies -5.2V. This power supplied through 3x32 EURO-card connector through pads edge board. Nominal power dissipation main termination board combined 17W. simplify layout circuit design, integrate MAX101AEVKIT into your system modular subsystem.
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Because digital circuits excellent generators electromagnetic interference, multilayer board recommended high-speed components like MAX101A. Clock signals other high-frequency square waves rich harmonics that invade entire application, higher harmonic frequencies even excite resonance between cable traces. MAX101A evaluation board consists layers circuitry (ground, power, analog, digital) separated five layers epoxy (Table Table Layer-Thickness Profile MAX101AEVKIT Layer Type Dielectric Material Epoxy Thickness 280µm Dielectric Constant Copper Copper Foil 35.5µm -Layer Level 1-2, 2-3, 3-4, 4-5, Microstrip Signals Plane Plane
VCC/VTT Power Plane VEE/VAA Power Plane Signal
microstrip return. minimize effects interference, digital analog grounds should tied single "star connection" close power-supply source. example, MAX101AEVKIT's digital ground ties analog ground ferrite-bead suppressor. Another ferrite bead between digital power (VEE) -5.2V analog power (VAA) helps decouple power rails. best approach preventing interference keeping layout traces short avoiding extra resonance loops. Short traces minimize conductor impedance shorten signalpropagation delays, which measure about 5.7ps/mm (145ps/inch). Because prop delay important consideration operating high-speed MAX101A, Maxim recommends that trace lengths exceed inches (12mm). Though limits maximum delay 70ps each trace, this condition cannot always achieved. some cases it's more important corresponding lines equal length terminated correctly. Controlled-impedance transmission-line connections recommended analog inputs, clock signals, fast digital outputs. MAX101AEVKIT, instance, employs microstrip lines with various values characteristic impedance. ADC's data outputs drive differential line drivers through microstrip lines occupying layers microstrip lines, which occupy layers Table features profile nominal thicknesses required each layer foil dielectric material. achieve full speed, noise, high-quality operation multilayer-interconnect design, trace widths should 500µm microstrip lines 250µm microstrip lines.
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Interfacing MAX101A External Memory When clocked 500MHz, MAX101A produces 250MHz each interleaved ports This digitized data synchronized DCLK signal (port falling edge port rising edge). DCLK also clock D-type flip-flop storing data. major difficulty this design storing data conventional memory. following section provides practical fully tested solution that problem. Figure shows simplified version technique storing MAX101A data external FIFO registers. Each MAX101A port connected single 8-bit D-type storage register whose outputs valid nearly 4ns. Buffer registers port port drive highspeed buses that terminated with resistor networks matching line impedance.
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Figure Data storage concept MAX101A-RAM combination
Each input register drives four other D-type registers parallel. rather insignificant time delay introduced these registers issue, because their clock signal derived from edge opposite edge driving input-register clock. circuitry associated with port port identical, timing clock data signals will remain correct corresponding traces similar length geometry. Gate delays Figure have following relationship: tSHIFT REGISTER tSETUP DELAY tINPUT REGISTER tSETUP DATA D-FLIP-FLOPS control four data registers high-speed bus, 250MHz synchronization signals first divided four then applied 6-bit shift register. clock signals also slowed gate delay each compensate divider
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delay shift register's setup time. Good results achieved using gate each these delays. Division four produces 62.5MHz clock signal that shifts through dedicated register, producing identical-waveform outputs that emerge intervals. These signals have proper sequence clocking incoming data proper data registers. match data registers' ECL-compatible outputs with high-capacity FIFOs' TTL-compatible inputs, ECL-to-TTL converter's delay must compensated without violating FIFOs' setup time. Thanks delay ECL-to-TTL converters, each shift-register output connects FIFO bit-intervals later than does corresponding data-register output. This arrangement, which each output period 16ns long (equivalent four bit-intervals shift register), meets timing requirements Figure
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Figure Timing selection
FIFOs' Write_Enable signals allows scanning continuously triggering burst data. FIFO configuration discussed this article allows memory depths 32kbytes more. data scans Mbyte range, however, this data-storage method must modified substituted another technique. Timing requirements FIFO memory similar those MAX101A outputs. When data valid FIFO input, positive Write_Clock edge takes into memory.
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high-speed interconnects four data registers. Operating 15.625MHz, they require data every 64ns. This relatively long interval enables conventional, high-capacity SRAM memory. After ECL-to-TTL conversion, data rate sufficiently that stateof-the-art programmable logic devices take from there. Instead FIFO memory, example, FPGA could provide interface external static devices. Though tested, this approach (using 512kx8 SRAM devices) would allow memory depths 16Mbytes. Determining Linearity Among tests performed Figure circuit test ADC's linearity. logic analyzer used preliminary divide-by-10 tests able keep with MAX101A full speed, high-speed data acquisition system final form used successfully test confirm ADC's excellent linearity. that experiment (Figure constant voltage from quality voltage source (GossenMetrawatt) through resistor MAX101A's input. Hewlett Packard precision multimeter (HP3438A) monitored signal voltage. MAX101A requires input voltage between -250mV +250mV. results show excellent linearity high-speed core application.
Figure Configuration MAX101A linearity test
MAX101A full-scale input range (FSR) apparent from diagram input voltage versus output code (Table Figure Representing MAX101A operating single-ended mode, this diagram shows output codes corresponding input voltage taken through entire FSR. binary zero output (00000000) occurs -250mV. midscale output (01111101) indicates slight error when compared with ideal binary output midscale (10000000). Full scale (+250mV) produces output code 11110101, again indicating slight deviation with respect ideal output (11111111). These deviations caused offset that compensated within application necessary.
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Table MAX101A Input Ranges Input Differential AIN+ (mV)* AIN- (mV)* Output Code +125 -125 +250 Single-Ended -250 -125 +125 11111111 10000000 00000000 11111111 10000000 00000000 Full Scale Midscale Zero Scale Full Scale Midscale Zero Scale
offset present input, specified MAX101A data sheet's Electrical Characteristics. This offset compensated adjusting reference voltages introducing offset voltage input terminals AIN+ AIN-.
Figure MAX101A linearity function (VIN OUTBIN)
Successful high-frequency applications require excellent dynamic performance, high-quality layout, proper attention signal conditioning power consumption. MAX101A with unique combination amplifier quantizer ensures these attributes, does successor, 8-bit, 1Gsps MAX104. MAX104's high sample rate 2.2GHz differential amplifier represents current state-of-the-art performance 8-bit converters. Integrated Analog-to-Digital Digital-to-Analog Converters. Plassche, Rudy. Philips Research Laboratories, Eindhoven, Netherlands, 1994. Electronics. Horowitz, Paul Hill, Winfield. Cambridge University Press,
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1989, Edition, York. MAX101/MAX101A Evaluation data sheet. Maxim Integrated Products Inc., USA, 1996. MAX101A data sheet. Maxim Integrated Products Inc., USA, 1996. similar version this article appeared June 1998 issue Microwaves
MORE INFORMATION MAX101A: QuickView Full (PDF) Data Sheet (128k)
MAX101AEVKit: QuickView Full (PDF) Data Sheet (208k)
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Application Note 381: 2001 Novel Storage Idea Supports Ultra-Fast

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