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About Analog Dialogue
Analog Dialogue free technical magazine Analog Devices, Inc., published continuously thirty-five years, starting 1967. discusses products, applications, technology, techniques analog, digital, mixed-signal processing.
Volume incorporates articles published during 2001 Worldwide editions more. recent issues, starting with Volume Number (1995) have been archived that website accessed freely. special anniversary issues archives contain useful articles extracted from earlier editions, going back Volume Number This issue revisits series that have proved popular recent quinquennium. Analog Dialogue's objectives have always been inform engineers, scientists, electronic technicians about products technologies help them understand competently apply these products. frequent editions have least three further objectives: provide digests that alert readers prereleased newly available products. provide links important rapidly proliferating sources information activity fermenting within website (www.analog.com). listen reader suggestions provide answers their questions. Thus, Analog Dialogue more than magazine; links tendrils parts external website make bookmark favorite "high-pass-filtered" point entry analog.com site-the virtual world Analog Devices. hope that readers will think publications "Great Stuff" will consider Analog Dialogue bookmark favorite alternative path answer question, "What's technology ADI?" Welcome! Read enjoy! encourage your feedback!
Sheingold dan.sheingold@analog.com Editor, Analog Dialogue
2001 2002 Analog Devices, Inc., rights reserved
THIS ISSUE
Analog Dialogue Volume 2001
This annual issue Analog Dialogue contains reprints articles published on-line editions during 2001. special bonus, celebration 35th year print, adding reprints collections that have proven popular during past five years: Dave Robertson's five-part 1996-1997 series, "Selecting Mixed-Signal Components Digital Communication Systems," installments "Ask Applications Engineer" series, published line (and print) since 30th anniversary collection 1996. (You find that publication Analog Dialogue on-line Archives.)
Page Editor's Notes: Authors, Fellows Accurate Gain/Phase Measurement Radio Frequencies (AD8302) High Performance Narrowband Receiver Design Simplified Digitizing Subsystem LQFP (AD9870) Mixed-Signal Front (MxFE) Broadband Digital Set-Top Boxes (AD9873) Design Direct 6-GHz Local Oscillator with Wideband Integer-N Synthesizer (ADF4106) Winning Battle Against Latch-up CMOS Analog Switches Avoiding Instability Problems Single-Supply Applications Improved Data Acquisition Using Monolithic Dual-ADC Front (AD7719) Challenge-Met AD7873 Resistive-Touch-Screen Controller Versatile Programmable Amplifiers Digital Potentiometers with Nonvolatile Memory Advanced Driver Lowers Cost High Performance Data Projectors (AD8380) Sensing, Analyzing, Acting First Moments Earthquake Useful Role ADXL202 Dual-Axis Accelerometer Speedometer-Independent Car-Navigation Systems 35TH ANNIVERSARY BONUS MATERIAL Applications Engineer Resistance Amps Driving Capacitive Loads Switches Multiplexers Signal Corruption Industrial Measurement Logarithmic Amplifiers Explained Accelerometers-Fantasy Reality Selecting Mixed-Signal Components Digital Communication Systems Introduction Digital Modulation Schemes III: Sharing Channel Receiver Architecture Considerations Aliases, Images, Spurs
Cover: cover illustration designed executed Kristine Chmiel-Lafleur, Communications Services, Analog Devices, Inc.
Editor's Notes
close 2001, celebrate completion Analog Dialogue's 35th year print-and third year electronic version.This season also marks beginning undersigned's 34th year Analog Devices Editor this journal-and 53rd year advocating analog technology. early days, Philbrick, this featured Analog Computor (sic) building blocks. they would soon overshadowed fame cannibalized fortune smaller, still undifferentiated, analog building block that lurked within, dreaming identity. materialized 1952 Philbrick's versatile ubiquitous K2-W plug-in Differential Operational Amplifier, which celebrates jubilee birth 2002. K2-W, with 12AX7 tubes plugged top, harbinger compact precision cost modular measurement, control, much else. plugging into octal tube socket same tube (and same that later plugged into transistor-type sockets), this "smart tube" could also considered forerunner integrated circuit. heart circuits modules that perform analog computing, could even said that amps resulted transformation analog computers into components-in same that microprocessors would later turn digital computers into components. Enough analogy! Let's with Analog.
DiPilato (pages 13), product-line manager communication-specific integrated products within ADI's High-Speed Converter (HSC) group. Since joining 1987, been involved with industrial, instrumentation, communication-focused products- last eight years, standard- communication-specific products, including TxDAC® MxFEbrands. authored numerous articles. BSEE from Worcester Polytechnic Institute (1982) from Anna Maria College (1984). active church, enjoys swimming quality beach time with wife Lisa Nicholas. Zoltan Frasch (page principal applications engineer ADI's Display-Drive Electronics group. earned BSEE from University Toronto, Canada, 1976 joined 1999.
AUTHORS
John Cowles (page works Northwest Labs Beaverton, Oregon, designing RF-IF products communications market. received from University Michigan 1994. Before joining 1998, worked TRW, Redondo Beach, high-speed GaAs technologies. ADI, designed AD8302, which nominated Product Year both Electronic Products magazines. over technical publications high-speed devices circuits. Mike (page applications manager products Ireland. Mike graduated from University Limerick with Electronic Engineering. worked ious local companies before joining Analog Devices 1983 Applications Engineer. provided technical support wide variety Limerick-developed products, including high-speed ADCs, sigma-delta ADCs, DACs, activity interrupted two-year assignment field applications engineer U.S. spare time, listens music enjoys game snooker indoor football.
Barrie Gilbert (page first Fellow, "spent lifetime pursuit analog elegance." joined Analog Devices 1972, appointed Fellow 1979, manages Northwest Labs Beaverton, Oregon. Barrie born Bournemouth, England, 1937. Before joining ADI, worked with first-generation transistors SRDE 1954, Mullard, Ltd.; later Tektronix Plessey Research Labs. Barrie IEEE Fellow (1984) received numerous awards. some issued patents, authored about papers, co-author several books, reviewer several journals. awarded Honorary Doctorate Engineering from Oregon State University 1997. Paul Hendriks (page senior applications engineer ADI's Standard Linear Products Division (Wilmington, MA). been working High-Speed Converter product group past years, focusing high-speed conver ters communication applications. Since joining 1989, authored numerous articles, design ideas, product data sheets. Paul received BSEE 1986 from McGill University. Paul Kearney (page design engineer ADI's Precision-Converter product line, Limerick, Ireland. graduated with Electrical Engineering from University College Cork, Ireland, joined immediately thereafter, 1990. Before present assignment, 1998, worked product engineer.
ISSN 0161-3626
Analog Dialogue Volume ©Analog Devices, Inc. 2001
Martin Kessler (page first encountered 1990, coop student Munich, Germany. 1994, joined company fulltime, providing application support product lines. Subsequently, Martin moved Wilmington, where focuses efforts digital communication-specific mixed-signal front ends. Hobbies include skiing, hiking, backpacking, playing guitar. Charles ("Chuck") Kitchin (page hardware applications engineer Wilmington, main responsibilities include writing technical publications developing applications circuits. published over technical articles, three books, large number application notes. Chuck graduated with ASET from Wentwor Institute, Boston, then continued studying electrical engineering University Lowell. avocations include astronomy, amateur radio, painting. Alan (page applications engineer General-Purpose Converter Reference product line Precision Converter Division. BSEE from Florida International University currently pursuing graduate degree Jose State University. also worked National Semiconductor Fairchild Semiconductor, focusing powerelectronics applications. leisure, activities include playing soccer listening music. Iuri Mehr (page design engineer communications-specific products ADI's High-Speed Converter Group, Wilmington, received MSEE degree from Washington State University 1994. After two-year stint Design Engineer Crystal Semiconductor, joined 1996, Standard Products group. 1997, joined High-Speed Converter group. serves Associate Editor IEEE Transactions Circuits Systems Albert O'Grady (page staff applications engineer ADI's facility Limer ick, Ireland, providing applications support generalpurpose digital-to-analog converters (DACs) high-resolution, lowbandwidth, sigma-delta analog-todigital converters (ADCs). Albert holds BEng from University Limerick. spare time, Albert enjoys reading plays badminton tennis.
Giuseppe Olivadoti (page technical marketing specialist Development Tools product line. holds Electrical Engineering with concentration Computer ineer from Northeastern University.
Catherine Redmond (page applications engineer ADI's facility Limerick, Ireland, providing applications support generalpurpose converters Switch/ Multiplexer products. Catherine holds BEng from Cork Institute Technology joined 1997. interests include listening music, reading, travelling. Richard Schreier (page design engineer ADI's High-Speed Converters group, Wilmington, received degree from University Toronto 1991. Before joining ADI, Assistant Professor Oregon State University Corvallis, Oregon, from 1991 1997. Richard coedi-tor 1997 IEEE Press book deltasigma converters; also authored freeware Matlab toolbox high-level design simulation delta-sigma modulators. Peter Shih (page applications engineer with Central Applications group Wilmington, working closely with product-line applications engineers provide customer support linear products. joined 2000, after graduating from Tufts University with BSEE. interests include playing volleyball, traveling, eating! Spence (page product manager ADI's display-dr electronics strategy, based Wilmington, received BSEE from University Lowell, joined 1989.
Harvey Weinberg (page applications engineer ADI's Micromachined Products division Cambridge, BEng Electrical Engineering from Concordia University, Montreal, Canada. nine years, prior working applications engineer, designed analog- microcontroller-based instrumentation process-control industry.
Analog Dialogue Volume (2001)
FELLOWS
pleased note introduction four Fellows 2001 General Technical Conference. Fellow, Analog Devices (ADI), represents highest level achievement that technical contributor attain, with Vice President. criteria promotion Fellow very demanding. Fellows will have earned universal respect recognition from technical community unusual talent identifiable innovation state art. Their creative technical contributions product process technology, software, will have commercial success with major impact company's revenues earnings. Attributes include roles mentor, consultant, entrepreneur, organizational bridge, teacher, ambassador. Fellows must also effective leaders members teams-and perceiving customer needs. year 2001, unprecedented number four outstanding individuals-Denis Doyle, Paul Ferguson, Josh Kablotsky, Larry Singer-were identified having rare combination technical abilities, accomplishments, personal qualities qualify them enhance existing roster Fellows: Adams (1999), Woody Beckford (1997), Derek Bowers (1991), Paul Brokaw (1979), Counts (1983), Barrie Gilbert (1979), Gosser (1998), Bill Hunt (1998), Jody Lapham (1988), Chris Mangelsdorf (1998), Jack Memishian (1980), Doug Mercer (1995), Frank Murden (1999), Mohammad Nasser (1993), Palmer (1991), Carl Roberts (1992), Paul Ruggerio (1994), Brad Scharf (1993), David Smart (2000), Jake Steigerwald (1999), Mike Timko (1982), Tsang (1988), Mike Tuthill (1988), Wilson (1993), Scott Wurcer (1996).
Besides contributions inventor designer, also excels teacher, mentor, team builder, developed strong relationships with universities, delivered many technical papers lectures, served role recruiting promising graduates. from Dartmouth College from MIT-and pursuit from Oregon State University. holds patents currently player mixed-signal development ADI's wireless systems, including SoftFoneand Othellochipsets. Paul lives North Andover, with wife, Amy, their three children.
JOSH KABLOTSKY
Joining Development Tools group 1990, Josh contributed heavily created numerous software development methodologies tools that daily throughout company. developed software successful products diverse communications computer segments-and focused DSP-based video image processing. been responsible remote-access voice-over networks businesses, consulted processor architectures, been ADI's primary contact organizations such ITU-T TIA. contributed development many product areas, including answering-machine software, voice compression tone detection, acoustic echo cancellation, modem development, state-machine design, remote data gathering. Through application others development methodologies, also contributed indirectly much wider universe, including digital still cameras, color laser printers, wireless infrastructure, wireless terminals, IADs. BSEE from Cornell University, currently lives Sharon, with wife, Deborah.
DENIS DOYLE
Denis major contributor process development operations ADI's Limerick (Ireland) wafer fab. principal contributions have been evolution BiCMOS processes from 1-µm 0.35-µm feature size. also worked other projects, ranging from EPROMs process transfers between foundries. Denis Doyle received (Elect) from University College, Cork, Ireland, 1985, followed MEngSc PhD-for work small-geometry bipolar devices National Microelectronics Research Centre (NMRC), Cork, Ireland. 1991, joined Process Development group ADI, Limerick, where since worked process developments. Denis's current project development 0.6-µm, 30-V CMOS/BiCMOS process.
LARRY SINGER
Larry most recently lead converter designer High-Speed Converter Standard Products group Wilmington, graduate MIT, with (1985) (1987) degrees joined upon graduation, after being recruited Fellow-to-be Paul Ferguson. Since then developed many ADI's converters that join high speed high resolution, including both successive-approximation high-speed pipelined types. Early career, solved challenging problems design practical 14-bit ADCs bipolar-CMOS (BiCMOS), that used laser-trimmed thin-film-on-chip resistors. then moved moderate resolution bits) video (20-MSPS) converters, designing pipelined converters high-speed FLAMOS, advanced bipolar-CMOS process-with laser-trimmed resistors. Since then major contributions have been innovative CMOS designs, pushing boundaries capacitor matching segmentation, showing that performance bits could realized without calibration. With efforts, CMOS devices closing speed dynamic-performance with bipolar BiCMOS devices. Larry married, children, enjoys drumming playing volleyball.
PAUL FERGUSON
Paul inventive circuit designer contributed heavily field switched-capacitor circuits higher-order sigma-delta ADCs DACs. instrumental development inventions technologies that emergence leader business audio segment. Among these ideas offset calibration, which reduction "speaker pop" phenomena, once common throughout audio applications. also pioneer standard-cell layout novel higherorder sigma-delta loop architectures ADI.
Analog Dialogue Volume (2001)
Accurate Gain/Phase Measurement Radio Frequencies
John Cowles (john.cowles@analog.com) Barrie Gilbert (barrie.gilbert@analog.com)
INTRODUCTION Measuring Signals
Electronic circuits fall into broad categories-those that process transform signals those that measure signals. Their functions often combined, section receiver- which processes signal amplification demodulation), also delivers indication received signal-strength (the RSSI function), slowly-varying voltage that displayed and/or used automatic control variables such gain frequency (AGC AFC). Circuits that measure signal strength, whose fundamental metric power, generally called detectors, only thermopile (bolometer) measures this quantity directly. Integrated-circuit detectors invariably operate voltage sample signal measured. Circuits this class classified type signal transformation they provide. 1976, Analog Devices supplied first monolithic "true-rms" detectors moderate frequencies. this product line includes devices, such AD8361, that have extended this capability microwave domain. accurate determination signal power, independent waveshape (stated otherwise, probability density function) important modern communications systems such CDMA. Unlike thermal detectors, these true-rms detectors analog computation directly implement relevant equations-at gigahertz frequencies. Another valuable type detector (also using computation) demodulating logarithmic amplifier. name suggests, amplifies signal, which allows devices this class measure small signals, demodulates alternating waveform slowly-varying "quasi-dc" output. However, unlike detectors, whose output proportional root-mean-squared value input voltage, logarithmic detectors deliver output proportional decibel value signal level, referenced fixed voltage, VINT (defined below). output, usually voltage, interpreted terms either voltage power, simply using different value scaling parameter called "slope." amps, necessary voltage metrics signal scaling parameters. define input level, will (here meaning decibels relative rms) rather than refer "power," (decibels relative mW). This unambiguous, independent choice impedance input interface, appropriate detector. example, corresponds sine wave 2.83-V amplitude; similarly, refers 2.83-mV sine wave. operation these logarithmic detectors conforms function like this:
VOUT VSLP log(VSIG/VINT)
base-10 logarithms chosen [log10(10) decade], with decibels mind, slope voltage, VSLP, viewed terms "volts-per-decade" scaling voltage ratio. Since there decibels decade, corresponding "volts/dB" just one-twentieth this voltage. Thus, VSLP mV/decade, slope also expressed mV/dB. second scaling parameter, called "intercept," VINT, input voltage which argument unity. this voltage, independent choice base, output would zero, since log(1) practice, finite available gain amp, presence noise, other practical limitations result value VINT that extrapolated value, typically only microvolts, fixed design. question then arises precise interpretation what VINT represents. this quantity "volts dc," perhaps "volts rms"? some other metric, such simple average value, peak value? measurements ratios from level another, value VINT unimportant. However, where required determine absolute level VSIG, measurement accuracy depends directly value VINT just same reference voltage say, DVM. close study logarithmic amplifiers, which technique1 known "progressive compression," shows another effect encountered classical practice, namely, that effective value VINT strongly depends waveform input signal. that reason, choose define VINT sinusoidal input, then provide conversion factors various other waveforms. practice, control VINT untrimmed production cannot accurate often needed precision metrication. Laser trimming, first used AD640/641, more recently products such AD8306, provide very accurate calibration, using sine-wave input during calibration. However, while appropriate conversion factor known waveform maintain good accuracy, there remains basic problem waveformdependence. This poses problem contemporary systems where waveform both unknown vary rapidly.
Measurement Signal Ratios
This problem been addressed, AD8302, identical amps integrated monolithic form, shown Figure Each channel capable measuring signals over 60-dB range, from very frequencies GHz. defining function amplitude ("gain") output VMAG VSLP (VA/VB where independent signals, applied identical input ports AD8302, center-point, defined value output, VMAG, level difference (VSLP design choices, made with ease-of-use mind; both traceable band-gap reference).
CHANNEL DETECTOR PHASE (10mV/
CHANNEL
DETECTOR
GAIN (20mV/dB)
Figure AD8302 comprises pair accurately matched amps high-frequency phase detector.
Analog Dialogue 35-5 (2001)
customary fixed intercept Equation eliminated AD8302 taking difference outputs separate amps. This step computes ratio (VA/VB) (VINTB/VINTA); and, since amps identical, second term very accurately unity, independently temperature, supply voltage, numerous production variances. This elegant elimination fixed intercept results highly accurate measurement signal level, many applications. primary limitation accuracy argument matching co-integrated channels. This novel structure2 opens many measurement possibilities that would otherwise require distinct amps, with their inherent differences slope intercept calibration. AD8302 first permit direct measurement signal ratios. This unique capability measuring gain/loss relative phase (see below) between signal ports, over very wide range frequencies, will value many other applications. Figure illustrates output voltage variation function signal ratio (which, example, correspond gain loss channel being monitored) frequencies ranging from GHz. signal level presented Channel fixed while that Channel varied from relative Channel output, VMAG, demonstrates precise slope, VSLP, mV/dB center-point, VCP, very small deviation from ideal logarithmic (Figure demonstrates value using co-integrated amps.
CHANNEL LEVEL: -25dBm
Measurement Relative Phase
AD8302 also measure phase difference between signals, from frequencies GHz. Each individual amps generates "hard-limited" output final stage. These signals applied inputs novel multiplier-style phase detector having exact symmetry with regard inputs 180o range. phase output, VPHS, given
VPHS 90°)
where scaling voltage phase output phase difference between inputs. choice sign depends which quadrants constitute 180o phase interval. With inclusion this feature, AD8302 becomes "network analyzer chip." Figure illustrates phase measurement MHz, GHz, GHz. Here, phase difference generated "slip," slightly offsetting input frequencies allowing angle accumulate. slope VPHS output mV/°C, centered alternating sign slope apparent phase slips through 180o intervals. Figure shows measurement error. rapid increase error near 180o mainly dead-zones caused finite rise fall times hard-limited signals. unique ability AD8302 accurately measure phase these frequencies result excellent balance tightly-integrated amps.
18.0 10mV/DEGREES
VMAG
900MHz
VPHS
0.90 2.2GHz
2.2GHz
GAIN MEASUREMENT
900MHz PHASE Degrees
CHANNEL LEVEL: -25dBm
CHANNEL LEVEL: -25dBm
ERROR Degrees
ERROR
2.2GHz 1.9GHz
2.2GHz
900MHz
900MHz
GAIN MEASUREMENT
PHASE Degrees
Figure Measurements signal-level ratios exhibit errors less than high frequencies.
Figure phase measurement exhibits errors over wide angular ranges high frequencies.
Analog Dialogue 35-5 (2001)
Using AD8302
These capabilities measuring gain/loss relative phase between signal ports will value many applications. functionality, versatility, compact form-factor this "network analyzer chip" ideally suited in-situ diagnostics monitoring system parameters feedback feed-forward linearization control subsystems. These applications AD8302. measurement absolute signal level possible using known reference. shown Figure reference signal applied Channel creates effective intercept value When signals have similar waveforms, measurement very accurate. Even error uncertainty slope voltage minimized (eliminated, principle) ensure that inputs close-to-equal amplitude. This will often simple matter arrange, using attenuator larger signal position ratio VA/VB close unity. Centering techniques valuable when highest accuracy needed where very large dynamic ranges must handled.
AD8302
CHANNEL VSIGN_IN
COMM INPA OFSA VPOS OFSB INPB COMM
0.9V
20dB GAIN 100mV
VMAG
100MHz
300MHz FREQUENCY
1.3GHz
SOURCE 20dB ZLOAD 20dB
CMFLT
MFLT VMAG MSET VREF PSET VPHS PFLT CPFLT PHASE (10mV/Deg) VREF (1.80V) GAIN (30mV/dB)
INCIDENT REFLECTED DIRECTIONAL COUPLERS: 20dB
CHANNEL VSIGN_REF
AD8302
Figure Absolute measurements signal level using reference Channel intercept Channel most useful application AD8302 monitoring reporting gain loss functional block subsystem. example shown Figure samples input output signals 500-MHz amplifier with nominal gain monitored. using attenuators couplers, signals conditioned same general magnitude. gain response shows mid-scale frequency value, which corresponds 20-dB level difference amplifier bandwidth approximately MHz. functional block this example could have been frequency-translation device, such mixer. that case, inputs would different frequencies, measured quantity would conversion gain. Since waveforms remain similar, that source error again eliminated. However, when input frequencies differ greatly, systematic offset occur inequalities impedance match frequency dependence scaling amps gigahertz region. many communication systems, there unpredictable load presented external interface port. Variations this load
COMM INPA HPFA VPOS HPFB INPB COMM
FLMG VMAG MGFB VREF PHFB VPHS FLPH PHASE GAIN
Figure AD8302 monitoring frequency response amplifier under test reporting gain. lead changes system performance, even catastrophic failure extreme cases. great value provide means monitoring load impedance-or reflection coefficient terms-without perturbing Figure AD8302 configured measure reflection coefficient arbitrary load which, this case, PIN-diode whose bias swept change impedance. notch response curve represents near-match characteristic line impedance, where reflected signal almost zero.
detailed description theory operation amps found AD640 data sheet. Patent pending.
Analog Dialogue 35-5 (2001)
VOUT CHANNEL
AD8302
CMFLT
COMM INPA OFSA VPOS OFSB INPB COMM
MFLT VMAG MSET VREF
THRESHOLD VREF PHASE THRESHOLD PHASE
VMAG
CHANNEL
PSET VPHS PFLT
MATCH
CPFLT
"OPEN" DIODE BIAS
SOURCE INCIDENT WAVE 20dB
"SHORT"
Figure AD8302, configured gain- phase-comparator with controllable thresholds. controller mode, shown Figure VMAG VPHS pins drive gain/phase-adjusters that included signal chain being monitored servo overall gain phase system toward desired set-points presented MSET PSET pins.
REFLECTED WAVE
ZLOAD
INCIDENT REFLECTED DIRECTIONAL COUPLERS: 20dB
VOUT CHANNEL
AD8302
CMFLT CONTROL
COMM INPA OFSA VPOS OFSB INPB COMM
MFLT VMAG MSET VREF PSET VPHS
GAIN
THRESHOLD VREF PHASE THRESHOLD
PHASE CHANNEL
AD8302
COMM INPA HPFA VPOS HPFB INPB COMM
FLMG VMAG MGFB VREF PHFB VPHS FLPH
PFLT CPFLT
PHASE CONTROL
Figure AD8302 control loop that drives gain phase towards prescribed set-points. AD8302 broad frequency range inputs, ranging from arbitrarily frequencies (even audio!) GHz. wide dynamic range amps accommodates only large changes relative signal level also variations absolute levels. output quantities representing amplitude phase difference have maximum small-signal envelope bandwidth MHz; this optionally reduced adding external filter capacitors. AD8302 provides this powerful computational function first time monolithic form using advanced bipolar process. excellent log-amp matching, high-frequency capability, precise scaling gain phase measurement, small footprint, open opportunities in-situ monitoring controlling systems noninvasive fashion. Operation from 2.7-V 5.5-V supply voltages provided current only product available 14-pin TSSOP package.
Figure AD8302 monitors reflection coefficient load-a diode whose impedance manipulated bias.
Versatility Ease
AD8302 offers several other modes operation, result careful planning fundamentally versatile nature this unusual structure. previous examples have demonstrated AD8302 typical measurement mode, where VMAG VPHS outputs report signal level phase difference between inputs. However, built-in scaling center-points transfer functions adjusted using external resistors 1.80-V internal reference provided VREF pin. disconnecting output pins from feedback pins, MSET PSET, gain- phase-comparator realized, shown Figure Here, VMAG VPHS outputs toggle between maximum output voltage depending whether signal level phase difference greater than less than thresholds presented MSET PSET pins.
ACKNOWLEDGMENTS
authors would like recognize tireless efforts Kelly Shirine Eslamdoust product engineering, Simonson Rick Cory applications development.
Analog Dialogue 35-5 (2001)
High Performance Narrowband Receiver Design Simplified Digitizing Subsystem LQFP
Paul Hendriks, Richard Schreier, DiPilato
(paul.hendricks@analog.com; richard.schreier@analog.com; joe.dipilato@analog.com)
with host processor. AD9870 intended both base stations subscriber units, combining dynamic range required base stations with power consumption needed portable radios.
problem receivers dynamic range
dynamic range receiver determines ability recover low-level signals presence larger signals, known blockers interferers. Figure shows various sources that reduce effective dynamic range radio receiver. Assume moment that only signal present spectrum "small target signal." minimum detectable signal sensitivity will determined signal bandwidth (B), receiver's detection threshold (SNRMIN), receiver's noise figure (NF), inherent thermal noise limitations (kTB). temperature sensitivity estimated with following equation: Sensitivity SNRMIN log(B) (-174 dBm/Hz) Following some potential noise sources: Low-frequency noise becomes issue insufficient gain applied target signal prior down-conversion frequencies below corner process technology. components caused offsets second order distortion also problematic. Large interferers have their energy spread over broad range frequencies phase noise receiver's through process known "reciprocal mixing." larger interferer closer target signal, more likely target signal will corrupted noise transfer mechanism. Also, this interferer large enough induce nonlinearities receiver's front-end circuitry, possible spurious component back into target signal's passband. "half-IF" problem specific case afflicting receivers with poor second-order linearity-in which interferer falling halfway between target signal generates second order component that mixes with LO's second harmonic generate spur falling target signal. IIP2 specification receiver allows receiver designer quantify "halfIF" spur. difference, between interferer level, PIN, resulting second-order spur IIP2 PIN. With IIP2 dBm, AD9870 mostly immune this "half-IF" problem.
INTERFERERS "HALF INTERFERER LO)/2
INTRODUCTION
Mobile radios used public safety emergency services- police, fire ambulances-as well private services such fleet management. Increasingly, order provide enhanced services, along with improved spectral efficiency coverage, design these radios moved from traditional analogbased modulation schemes, such digital modulation approaches. Receivers these radios must capable accurately digitizing low-level, high-frequency signal presence large interfering signals. radios using some narrowband land mobile standards, interfering signals greater than desired channel, with frequency offsets little kHz. Since these systems usually cellular, geographical coverage range mobile radios also important feature-they must possess excellent sensitivity recover low-level signals originating from subscribers fringe coverage range. further complication, these radios often portable with high rates usage; they demand power consumption using smaller, longer-lived batteries. equipment designers, Analog Devices made available AD9870 Digitizing Subsystem, designed meet demanding requirements land mobile radio, similar narrowband radio applications, with superheterodyne architectures employing analog and/or digital modulation schemes. AD9870 integrates entire strip with minimal external components. accept signal frequencies high MHz, with bandwidths kHz, provides serial data output containing 16-bit data, which then demodulated
INTERFERER WITH "PHASE NOISE"
70dB MORE
SMALL TARGET SIGNAL
THERMAL NOISE
FREQUENCY
Figure "Big Problem" receivers dynamic range.
Analog Dialogue 35-3 (2001)
large interferers equally spaced frequency offsets (i.e., from target signal will result spurious component falling target signal through process intemodulation. linearity receiver this scenario captured IIP3 specification with higher numbers representing higher tolerance third-order intermodulation. difference, between equal interferers, PIN, resulting thirdorder intermodulation component (IIP3 PIN). AD9870 respectable IIP3 performance dBm, thus tolerating interferers high before degrading receivers sensitivity.
Superheterodyne Architecture
cope with large interferers that would otherwise degrade receiver's ability recover target low-level signal, superheterodyne architecture used translate signal down more intermediate (IF) frequencies where filtering adjacent interferer signals well amplification gain control target signal more practical. superheterodyne scheme been employed since World this most popular radio receiver architectures. generic version employing this architecture, common among narrowband digital receivers, shown signal-chain Figure
CHANNEL SELECT FILTER(S)
Prior RF-to-IF down-conversion, band-select filter (duplexer) and/or image reject filter selects entire band within which target signal operates. low-noise amplifier (LNA), which provides amplification intended band prior downconversion, critical determining receiver's sensitivity. down-converted spectrum following mixer often contains array signals varying strengths addition target signal. Channel selection amplification occurs target signal selected from among other signals more crystal SAW-type passive filters. After filtering, target signal undergoes further amplification, with signal strength stabilized preset level loop optimize quadrature demodulation process. many digital receivers, analog quadrature modulator separates signal into quadrature baseband components, which then digitized dual ADC. such cases, modulation accuracy demodulated signal quite sensitive analog offsets, quadrature mismatch, gain mismatch quadrature modulator dual ADC.
AD9870 Architecture
AD9870 digitizing subsystem reduces complexity typical superheterodyne receiver integrating most baseband, some digital post processing functional blocks shown Figure
QUAD DEMOD
BAND SELECT FILTER IMAGE REJECT FILTER
RF/IF SYNTHESIZER
SYNTHESIZER
Figure Typical superheterodyne architecture digital receiver.
PORT DATA
AD9870
PLL/VCO OSC.
SERIAL DATA
Figure AD9870 simplifies digital receiver while enhancing performance.
2.5MHz
(10MHz-300MHz) AAF/
fCLK 18MHz
10kHz-150kHz fCLK/8 DEMOD. DEC'N FILTER
FORMAT BASEBAND PROCESSOR
SUPPORT CIRCUITRY SYNTHESIZER SYNTHESIZER CONTROL BANDGAP REFERENCE
Figure Functional block diagram AD9870 shows level integration.
Analog Dialogue 35-3 (2001)
AD9870 differs from typical superheterodyne architecture employing wide-dynamic-range bandpass sigma-delta sample second-IF signal, along with neighboring interferers. demodulation target signal performed with digital accuracy stability, while intrusive nearby interferers suppressed digital filtering. Figure shows functional block diagram AD9870. Functioning similarly portion superheterodyne architecture, mixer used amplify downconvert target signal centered first-IF frequency lower second-IF frequency suitable digitization bandpass ADC. mixer provide approximately 10.5 gain, while preserving system dynamic range with input noise figure third-order intercept dBm.The high input impedance (360 simplifies interfacing crystal filters. on-chip synthesizer used conjunction with external loop filter generate tunable frequency. second-IF signal centered exactly 1/8th bandpass sample rate (i.e., fCLK/8) allow simple fS/8 digital quadrature demodulation scheme. Upon downconversion second-IF, signal processed tunable (and programmable) active third-order anti-alias filter (AAF) suppress signals which could appear within alias bands sampling (i.e., CLK/8 CLK/8. tuning circuitry support sample rates between MHz, with cut-off frequency typically tuned slightly beyond second-IF (i.e., f-3dB fCLK/3.2). Embedded variable-gain amplifier (VGA) that provides gain range (Figure gain, which extends dynamic range AD9870, either programmed directly controlled automatic gain-control (AGC) loop. loop typically invoked under strong signal conditions prevent "overloading" clipping converter maintaining programmable fixed-signal level input. AD9870 implements function with highly effective hybrid approach, shown Figure analog digital domains work together signal estimation control.
fCLK
IF2P IF2N
situations where strong target signal interferer falls within bandwidth first-stage decimate-by-20 digital filter, signal estimated digitally compared programmed reference level (AGCR). difference between levels digital integrator, which updates control adjust analog voltage VGA. Since strong interferer falling outside passband first-stage digital filter accurately estimated, analog loop based simple differential comparator monitors input assumes control loop during overrange condition, reduce gain. external capacitor used "smooth" transitions DAC, with time constant established capacitance internal source resistance DAC. cutoff frequency typically well outside control system's loop bandwidth ensure continual digital control loop dynamics. control loop bandwidth digitally programmable with attack decay times variable over wide range ability react overload condition. instantaneous dynamic range narrowband receiver signal chain containing dependent particular gain setting VGA, since noise contributed each stage signal path "overall" input-referred noise decreases gain preceding stage increases. This implies that input noise described noise figure, typically dominated first stages (i.e., mixer); noise sources signal chain (i.e., ADC) have minimal effect upon system's provided that there sufficient gain between these blocks.
MEAN VALUE CLIPS -24dBm
NOISE FIGURE
NOISE FIGURE
-100
VGA/
ej(2 fCLK/8)t
DEC1
-150 SIGNAL AMPLITUDE
CLIP POINT ABS(I[N]) ABS(Q[N])
Figure Dynamic range AD9870 depends setting. case AD9870, VGA's gain nominally adjustable over range. Figure shows AD9870's noise figure impacted gain setting target signal's interferer's) input power increased from dBm. Under small-signal conditions, gain; AD9870's noise figure LNA/Mixer well VGA's input noise. However, signal power increased, point reached (depending reference level) which VGA's gain begins decrease prevent clipping. this
(1-z
CONTROL
AGCR LEVEL
CDAC
fCLK/20
Figure "hybrid" control loop extends dynamic range AD9870.
Analog Dialogue 35-3 (2001)
MEAN VALUE
FIRST RESONATOR SECOND RESONATOR 0dBFS OUTPUT
9-LEVEL QUANTIZER dBFS/NBW ELEMENT SELECTION LOGIC
3.3kHz
-100
FREQUENCY
Figure Multibit fourth-order bandpass results deep notch fCLK/8.
DEC1 DATA FROM SIGMA-DELTA MODULATOR SINC4 FILTER DEC2 SINC4 FILTER DEC3 FILTER COMPLEX DATA PORT
Figure Digital quadrature demodulation, followed programmable decimation filters, provides baseband data. point, gain reduced signal power further increased. Also, this region, input signal level remains constant noise begins dominate such that system's degrades also rate. signal power continues increase, point reached (i.e., dBm) which gain absolute minimum further increases signal level seen input until clipping occurs (i.e., dBm). bandpass sigma-delta (Figure "heart" AD9870 that makes second-IF digitization approach feasible practical intended radio systems requiring high dynamic range with minimal power consumption. This ADC, together with back-end digital decimation filters, achieves nearly 14.5-ENOB performance within 10-kHz bandwidth, while sampling signal centered frequencies high 2.25 MHz. achieves these specifications while drawing mere from power supply. sigma-delta based fourth-order switchedcapacitor, multi-bit modulator consisting cascaded resonators that provide complex pairs zeros noise transfer function (NTF) falling near fCLK/8. location these complex zeros second-IF frequency, along with multibit feedback path, help ensure noise floor narrow region 73.3% fCLK/8) around second-IF frequency. digital output data from into digital signal processing section AD9870 (Figure This section consists fCLK/8 complex quadrature) demodulator followed three linear-phase filters. complex demodulator separates target second-IF signal centered CLK/8 into components prior filtering. output spectrum complex demodulator consists target signal, centered "dc," along with undesirable interferers and/or noise sufficiently filtered analog domain. series decimation filters used remove these undesirable components, while simultaneously reducing data rate accordance target channel's bandwidth. Depending modulation scheme, complex data rate (hence decimation factor) least factor greater than channel bandwidth allow further post-processing. Both DEC1 DEC2 cascaded fourth-order comb filter topology; DEC2's decimation factor user programmable accommodate different channel bandwidths. DEC3 decimateby-3 filter; sets close-in transition-band characteristics composite filter. 16-bit I-and-Q output DEC3 into synchronous serial-interface (SSI) function, which formats data into serial stream embeds other optional information AGC, signal strength, synchronization-into stream.
AVAILABILITY
AD9870 released production winter 2001. available 48-lead LQFP package $16.96 volume.* AD9870 datasheet available Analog Device's website (www.analog.com). evaluation board associated software also available.
*Recommended resale price USD. Prices subject change without notice. specific price quotations, touch with sales offices distributors.
Analog Dialogue 35-3 (2001)
AD9873 Mixed-Signal Front (MxFE) Broadband Digital Set-Top Boxes
Iuri Mehr, DiPilato, Martin Kessler
Widespread deployment cable extensive research providing better quality increased variety programming cable-modem functionality. This effort resulted development digital set-top boxes from several established vendors, including Scientific Atlanta Motorola (General Instrument). Instead analog vestigial-sideband modulated (VSB) channels, digital set-top boxes receive programming exchange information with head-end station using quadrature amplitude modulation (QAM). Transmitting analog information digital bits only more robust also makes available bandwidth more efficiently. Figure shows digital set-top connected head-end various devices inside residence office).
WALL CABLE
PHONE LINE
CABLE
ANALOG
DIGITAL
COMBINER
OUT-OF-BAND (OOB) CONTROL CHANNEL
TUNER (50MHZ -800MHz)
CABLE DRIVER (AD832x)
CHANNEL MODULATOR
PHONE LINE INTERFACE
MIXED-SIGNAL FRONT-END (AD9873)
MEMORY
COMPUTER INTERFACE
COMPUTER
(DOCSIS)
MPEG NTSC DECODER
MPEG NTSC ECODER
SYSTEM
Figure Inside typical digital set-top box.
Mixed-Signal Front
definition mixed-signal front set-top must take into account amount functionality required from transmit receive data paths. cost vital importance, selecting proper technology successful design. addition, time market equally important both vendor OEM. ASICs that include significant digital analog content often difficult schedule time needed handle inherent design challenges frequent need customer feedback. designers Analog Devices AD9873 took advantage both their experience set-top-box technology their inventory high-performance topological block core designs kind that would needed integrate essential high-performance analog mixed-signal functions single chip.
AD9873
SYNC INTERPOLATOR FILTER SERIAL PROFILE CONTROL FUNCTIONS SINC
HEAD-END
SET-TOP
COMPUTER
PHONE
Figure Cable set-top gateway configuration. Several services unified this fashion, including Internet access, cable even phone services. High data rates allow streaming-in MPEG movies well high-quality telephony (voice-packet) service. digital set-top box, like that shown Figure comprises several major subsystems implement such functions tuner, baseband transceivers, channel modulator (for compatibility with analog sets), MPEG NTSC decoders encoders, physical layer (PHY), media access control (MAC) cable modems. Since Internet access implies upstream channel, cable driver included; implemented using member AD832x family. also include out-of-band (OOB) control channel phone line interface. multiplicity complexity these blocks impose significant challenges designers both component board levels. large amount digital processing required, combined with high-quality reception requirements highdefinition digital pose numerous challenges digital set-top architects. addition, compatibility with analog calls clean analog signal processing from wall cable outlet set. Therefore, selecting proper partition integrated functions becomes requirement combining high-quality reception high data rates cable modem cost. mixed-signal front end, which implemented using AD9873, central set-top (Figure
SDELTA0 SDELTA1
SYNC
IF10 IF12 VIDEO
Figure AD9873 functional block diagram. Figure block diagram AD9873 Analog Front Converter Set-Top Boxes Cable Modems. receive data path contains several analog-to-digital converters (ADCs) accommodate various set-top functions described earlier. pair 8-bit ADCs used convert quadrature inputs from demodulated channel. They designed modest
Analog Dialogue 35-1 (2001)
performance-better than effective number bits (ENOB) when sampling less than MHz-since data utilizes lowcomplexity modulation (QPSK) narrow-band channel MHz). tighter specification required from 10-bit ADC, major role digitizing cable modem data. This type data broadcast using higher-order modulation, which requires higher signal-to-noise ratio. Hence, converter needs exhibit better than ENOB when sampling input signal MSPS. fourth ADC, 12-bit converter, sampling providing better than 10.5 ENOB inputs Nyquist rate, digitize high-definition signals. single-ended video signals multiplexed same input, programmable black-level clamp provided. outputs these converters multiplexed reduce number package pins. transmit data path contains demultiplexed interface, which receives baseband data, typically sampled about MHz). Since interpolation powerful tool reducing output filter requirements (used successfully AD9772 AD9856), three interpolation filters used. interpolation factor programmed bringing data rate MHz. overall interpolator frequency response determined half-band filters cascaded integrator comb filter (CIC). Following interpolator, quadrature modulator implemented using direct digital synthesis (DDS) generate sine cosine waveforms. Before being into DAC, signal compensated sin(x)/x roll-off, which results from conversion process. This operation optional, since roll-off becomes noticeable only toward synthesized carrier frequency range. produce low-spurious-content complex carrier frequencies approximately one-third sampling rate, that MHz. ADCs clocked directly from low-frequency crystal; frequency stepped on-board programmable phaselocked-loop (PLL) provide high-speed clock required DAC. This approach reduces undesirable clock jitter when sampling ADCs eliminates problems expense off-chip high-frequency oscillator. programmable also provides system clock other blocks within set-top box. Auxiliary digital sigma-delta outputs facilitate automatic gain control timing recovery functions. Many device parameters programmable through 4-pin serial interface. order seamlessly interface with member AD832x cable driver family, separate 3-wire interface included, several profile registers (which loaded through serial interface) designed speed changes transmit gain data carrier frequency. This achieved using dedicated external pins that address particular profile register bank. Figure shows AD9873 would used complete digital settop application. Designers broadband modems require combination small form factors, high performance levels, cost. Because cost area impact heat management within box, they cannot afford dissipate watts power transmit receive path. build large-scale digital integrated circuits that meet these requirements broadband modem designs, state art, low-voltage lithographies needed. However, they
suitable high-performance analog mixed-signal circuitry. Products like AD9873 provide solution this problem offering possibility using small highly integrated chips- digital ASIC mixed-signal "everything else"-that appropriately partition large scale digital from highperformance mixed-signal component.
CABLE MODEM DIGITAL ASIC
ENCODER
MAPPING FILTER BURST GEN.
CTRL
INTERPOLATOR
DIPLEXER COAX CABLE
ENCODER
AD8323
OUT-OF-BAND QPSK-DEMOD
DEMOD
AD9873
RISC CTRL
NTSC/PAL DECODER MPEG2 DECODER VIDEO ENCODER AUDIO/VIDEO CODEC
VIDEO CLAMP
USB/ ETHERNET
AD18xx ADV71xx
VIDEO CAMERA COMPUTER SYSTEM DISPLAY SPEAKERS
Figure Intelligent system partitioning helps solve challenge optimizing price, performance, size, power broadband modem designs. Figure demonstrates this approach leads trend broadband communication applications away from single-chip solutions that unsuccessfully attempt integrate large scale digital processing with high-performance mixed-signal devices. Emerging broadband modems require both more powerful digital processing (>MIPS) higher performance mixed-signal dynamic range bandwidth) devices. large scale integrated digital devices used these applications need utmost state-of-the-art (fine geometry), voltage, CMOS processes, while mixed-signal devices depend higher voltage CMOS processes that optimized handling mixed signals with high performance. first device family broadband MxFEs, AD9873 will allow designers take advantage "smart partitioning."
CHANGING SYSTEM PARTITIONING
TRADITIONAL PARTITIONING DIGITAL CHIP INCLUDING MIXED SIGNAL ADC/DAC: PARTITIONING TREND DIGITAL CUSTOMER ASIC, SEPARATE ADC/DAC (AD9873):
0.35 PROCESS
DIGITAL
ANALOG
0.25 PROCESS
DIGITAL
AD987x PROCESS
0.35
SOON
0.25 PROCESS
SOON
DIGITAL ANALOG
0.12 PROCESS
DIGITAL
ANALOG
0.25 PROCESS
+TURNKEY DIFFERENTIATION -TRADE-OFF REQUIRED BETWEEN COST FINE GEOMETRY AVAILABLE DIGITAL SECTION LARGER GEOMETRY REQUIRED HIGH-PERFORMANCE ANALOG
+MORE COST EFFECTIVE +OPTIMIZED PERFORMANCE +CUSTOMER DIFFERENTIATION -REQUIRES CUSTOMER'S
Figure Smart partitioning model.
Analog Dialogue 35-1 (2001)
Here's works: Deep submicron geometry processes readily support voltage levels required high-performance converters, coupling digital noise into analog signal chain will corrupt signal fidelity. There times when trying everything single chip results higherprice and/or lower-performance solution. Trying high-speed wide dynamic range mixed-signal devices with very large scale digital processing perfect case point. will always require compromises either digital area (cost), power consumption, mixed-signal performance. AD9873 broadband Mixed-Signal Front End, other MxFE products that will follow wake, gives designers benefit high integration, cost, power consumption, without compromising performance. AD9873 applies this optimized mixed-signal technology "smart" partitioning provide excellent dynamic performance variety modulation formats-FSK, QPSK, 16/32/64/256 QAM, OFDM, spread spectrum, etc. digital ASIC, which includes modulation encoding, implemented most cost effective finest geometry possible. With this costeffective approach, system designers keep more "value added" their digital ASIC, making best their system expertise, proprietary algorithms, intellectual property. AD9873's mixed-signal partitioning resolves cost performance tradeoff issues related integrating mixed-signal circuits within VLSI digital ASICs getting them chip.
AD9873 Features Performance
Quadrature Digital Upconverter: Output Bandwidth 12-Bit Direct Converter Direct Digital Synthesis Interpolation Sin(X)/X Filters 12-Bit MSPS Direct 10-Bit MSPS Direct Dual 8-Bit 16.5 MSPS ADCs Dual 12-Bit Sigma-Delta Control DACs Video Input with Clamp Circuitry Direct Interface AD8321/AD8313 Cable Driver Programmable Clock Multiplier Single Supply Operation Power-Down Modes 100-Lead MQFP
Performance AD9873 characterized with respect commercial temperature range; however, safely used from -40°C +75°C. Figure shows spectral plot 12-bit performance with 10-MHz input.
MAGNITUDE
Other Applications AD9873 Mixed-Signal Front
Besides cable set-top boxes, AD9873 well suited variety other standard proprietary broadband communications applications, depicted Figure Here list other applications where AD9873 used: Cable Modem Digital Communications Data Video Modems Power Line Modem Satellite Systems Multimedia Broadband Wireless Communication Home Networking
-105
-125 FREQUENCY
Figure AD9873's 12-bit performance plot with 10-MHz input. Figure shows spectral plot producing 42-MHz 16-QAM signal. Figure shows constellation diagram 64-QAM signal generated AD9873.
DIGITAL ASIC
CTRL
INTERPOLATOR
AD832x
MAGNITUDE
FRONT
DIGITAL PHYSICAL LAYER
AD9873
VIDEO CLAMP
Figure Broadband modems over cable, power line, wireless, using AD9873.
FREQUENCY
Figure AD9873 performance plot.
Analog Dialogue 35-1 (2001)
POWER SUPPLY DIOFIFO INTERFACE
AD9873
VIDEO INTERFACE 12-BIT ANALOG INTERFACE 10-BIT ANALOG INTERFACE 8-BIT ANALOG INTERFACE QAM-, NTSCOR SINGLETONE GENERATOR
FIFO CARD CARD
REGISTER CONTROL SOFTWARE
PARALLEL PORT INTERFACE
CLOCK GENERATOR
DIGITAL WAVEFORM GENERATOR
INTERFACE
FILTER
AD8323
SPECTRUMOR VECTORANALYZER
EVALUATION BOARD
Figure AD9873 64-QAM constellation plot.
Figure AD9873 evaluation setup.
Figure AD9873 evaluation board software interface.
Evaluation Board Software
AD9873 Evaluation board software allow users easily program quickly evaluate AD9873 specific modem application.
AVAILABILITY
AD9873 released production summer 2000. available 100-lead MQFP package, priced $16.58 (1000s), sells less then high volume.
Analog Dialogue 35-1 (2001)
Design Direct 6-GHz Local Oscillator with Wideband Integer-N Synthesizer
Mike Curtin (mike.curtin@analog.com)
INTRODUCTION
Establishing benchmark speed phase-noise performance, ADF4106 Phase-Locked-Loop Synthesizer fully specified operate frequencies GHz.This allows designs 5.4-GHz 5.8-GHz upper band greatly simplified. Fabricated advanced 0.35-µm BiCMOS process, displaces pin- software-compatible 4-GHz ADF4113 fastest available integer-N synthesizer-and achieve 3-dB lower phase noise boot! requires only 3.3-V supply, specified compatibility with tuning voltage levels often required modular VCOs used base stations. ADF4106 frequency synthesizer (Figure used implement local oscillators (LOs) down-conversion sections wireless receivers transmitters. consists lownoise digital phase frequency detector (PFD), precision charge pump, programmable reference divider, programmable counters, dual-modulus prescaler (P/P bit) bit) counters, conjunction with dual-modulus prescaler (P/P implement N-divider
AVDD DVDD
addition, 14-bit reference counter allows selectable REFIN frequencies input. complete phase-locked loop (PLL) implemented synthesizer used with external loop filter voltage-controlled oscillator (VCO). very high bandwidth means that frequency doublers eliminated many high-frequency systems, simplifying system architecture lowering cost.
Wide bandwidth allows function 6-GHz local oscillator
standard system architecture used ADF4106 predecessor, ADF4113, shown Figure Since maximum operating frequency ADF4113 about GHz, higher frequencies require frequency doubler-which usually calls extra amplifier produce adequate level doubler. ADF4106 eliminates frequency doubler associated circuitry, achieving much simpler more power-efficient example, design shown Figure generates output frequencies with 1-MHz channel separation from GHz. phase noise measured upper dBc/Hz.
fREF REFERENCE DIVIDER PHASE DETECTOR LOWPASS FILTER fOUT fREF
COUNTER
fOUT fOUT (fREF/R) fOUT (fREF) (N/R)
Figure Standard architecture. Because input impedance ADF4106 this high operating frequency very close terminating resistor input needed maximum power transfer efficiency. When operating lower frequencies, s-parameters data sheet give impedance values needed matching.
CPGND REFERENCE RSET
REFIN
14-BIT COUNTER COUNTER LATCH
PHASE FREQUENCY DETECTOR
CHARGE PUMP
DATA
24-BIT INPUT REGISTER
FUNCTION LATCH
LOCK DETECT
CURRENT SETTING
CURRENT SETTING
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 COUNTER LATCH
FROM FUNCTION LATCH
13-BIT COUNTER LOAD AVDD SDOUT
HIGH
MUXOUT
RFINA RFINB
PRESCALER LOAD 6-BIT COUNTER
ADF4106
DGND
AGND
Figure Functional block diagram ADF4106.
Analog Dialogue 35-6 (2001)
phase noise allows work low-noise, fast-settling 1.5-GHz local oscillator
ADF4106, conjunction with wide bandwidth divider, improve phase noise lock time standard local oscillator circuit frequencies below GHz. typical wireless system might generating frequencies 200-kHz increments from 1450 1500 MHz. Using integer-N architecture this, phase/frequency detector reference frequency needed, value would vary from 7250 (1450 MHz) 7500 (1500 MHz). Using ADF4106 best performance would give phase noise figure dBc/Hz. Typical reference spurs such system would kHz. Implementing loop bandwidth kHz, typical lock time degrees phase error would However, wideband operation possible with ADF4106 allows alternative architecture considered, shown Figure this configuration, core operated multiple final desired output frequency. example given above, final desired frequency range 1450 1500 MHz. multiple within device's frequency range 5800 6000 (four times desired output band). proposed scheme, shown Figure fPFD operates kHz, fVCO band 5800 6000 MHz, final system output obtained dividing fVCO four. fOUT (fPFD N)/X Some consequences using this architecture follow.
Phase-noise reduction (see page
synthesizer phase noise logfPFD relationship. This means that every doubling frequency, there will 3-dB degradation synthesizer phase noise. However, output from will divided down, phase noise obeys logX rule. every doubling there will gain phase noise performance. frequency quadrupled above, fVCO divided four with correct fOUT. Thus will lost quadrupling fPFD gained division four. This results overall gain phase-noise performance, using Figure compared standard architecture. this example, resulting phase noise would dBc/Hz.
Reference spur reduction
integer-N PLL, spurious frequencies occur integer multiples frequency output. Figure using fVCO, these spurs will fPFD, 2fPFD, 3fPFD, etc. However, fOUT, fundamental frequency divided spurious frequencies still exist integer multiples frequency. Note, however, that they reduced amplitude logX log4 dB). Figure using architecture Figure with generating fOUT 1450 1500 with 200-kHz spacing, frequency spurs will exist integer multiples kHz, frequency levels below dBc. Note that although step frequency kHz, lowest frequency spur kHz.
RFOUT 100pF
6.2k 20pF
FREFIN
AVDD 1000pF 1000pF REFIN 100pF
100pF V940ME03
4.3k 1.5nF
ADF4106
COMPATIBLE SERIAL
DATA RSET
MUXOUT
LOCK DETECT 100pF
RFINA RFINB
CPGND
AGND
5.1k
DGND
100pF
NOTE DECOUPLING CAPACITORS (0.1 F/10pF) AVDD, DVDD, ADF4106 V940ME03 HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure ADF4106 used implement 6.0-GHz local oscillator.
fREF fPFD
TCXO REFERENCE
DIVIDER
CHARGE PUMP
LOOP FILTER
DIVIDER fVCO
LOCAL OSCILLATOR OUTPUT MIXER
fOUT SYNTHESIZER I.C. DIVIDER
Figure Architecture improved lock time, phase noise, reference spurs.
Analog Dialogue 35-6 (2001)
fVCO
fOUT fVCO
DIVIDER INPUT
DIVIDER OUTPUT
Log10X (dB)
fPFD
fPFD
Figure Comparing output spectrum fVCO fOUT Figure
(3V) 6.2k 20pF (5V)
(5V)
FREFIN
AVDD 1000pF 1000pF REFIN 100pF
RFOUT
100pF
100pF
HMC362S8G
100pF RFOUT
4.3k 1.5nF
V940ME03
ADF4106
100pF
COMPATIBLE SERIAL
DATA RSET
CPGND AGND
MUXOUT
LOCK DETECT 100pF
RFINA RFINB
5.1k
DGND
100pF NOTE DECOUPLING CAPACITORS (0.1 F/10pF) AVDD, DVDD, ADF4106 V940ME03 HAVE BEEN OMITTED FROM DIAGRAM CLARITY.
Figure Using ADF4106 with output divider generate 1.5-GHz local oscillator.
Shorter lock time
Since Figure operating higher frequency, phase comparisons occurring higher rate; this will cause loop lock faster. addition, because higher frequency, wider loop bandwidth possible, this helps improving lock time. this example, lock time about within degrees phase error loop bandwidth kHz. actual implementation Figure shown Figure summarize, circuit Figure provides following performance: Phase Noise Reference Spurs dBc/Hz 1-kHz offset <-100 (system noise floor) 200-kHz, 400-kHz, 600-kHz offsets 800-kHz offset Lock Time within degrees phase error price this improved performance extra cost output divider extra power consumption system whole (the typically adds ADF4106's 13-mA current requirement). Thus improved performance must critical requirement selecting this architecture.The extra board space needed implementation minimal since comes 8-lead SOIC package.
BANDWIDTH
0.35-µm BiCMOS fabrication process careful application design techniques permit prescaler section ADF4106 operate with input level (referred guaranteed over industrial temperature range (-40 +85°C). Figure shows typical sensitivity plot ADF4106 TSSOP package -40°C, +25°C, +85°C. clearly seen that performance well within limits device with signals below dBm.
INPUT POWER
INPUT FREQUENCY
Figure ADF4106 sensitivity frequency.
Analog Dialogue 35-6 (2001)
PHASE NOISE
Phase noise, measure purity local oscillator signal, single most critical specification local oscillator section radios-with direct bearing receiver sensitivity. ratio output carrier power noise power 1-Hz bandwidth given offset from carrier. Expressed ratio, units phase noise dBc/Hz. Phase noise typically measured with spectrum analyzer.
ERROR DETECTOR CHARGE PUMP e(s) LOOP FILTER
With this phase-noise figure merit, engineer work total phase noise given frequency output frequency. example, consider generation local oscillator signal with frequencies from 1700 1800 channel spacing kHz. Using equation (2), close-in phase noise using ADF4106 synthesizer
PNTOTAL -219 log(9000) log(200
(-219 dBc/Hz
Z(s) fOUT
fPFD
dBc/Hz Figure shows that ADF4106 obeys logfPFD "rule" (PFD phase noise substantially linear with frequency) fairly consistently MHz. Some integer-N devices begin degrade rapidly once frequency goes above MHz. Note that -219 dBc/Hz figure merit obtained extrapolating Figure back graph used quickly identify performance possible given setup once value known. example, graph corresponds phase noise -166 dBc/Hz. Adding logN dBc) gives phase noise dBc/Hz.
FEEDBACK DIVIDER
Figure Basic phase-locked loop model. circuit Figure used circuit model discussion phase noise. Total phase noise phase-locked loop (dB) expressed follows: PNTOTAL SYNTH where PNTOTAL total phase noise PNSYNTH phase noise synthesizer circuit itself logN increase phase noise frequency magnification associated with feedback ratio, 1/N. logfPFD increase noise associated with incoming frequency. graph Figure shows ADF4106's phase noise characteristics function frequency, fPFD. With given measured total noise, synthesizer noise inferred SYNTH PNTOTAL
ACKNOWLEDGEMENTS
note thanks Bill Hunt valuable editorial comments, Brendan Daly, verified circuits used. author would also like acknowledge customers have provided valuable feedback this device.
References
[1]. Mini-Circuits Corporation, Designer's Handbook, 1996. [2]. L.W. Couch, Digital Analog Communications Systems. Macmillan Publishing Company, York, 1990. [3]. Vizmuller, Design Guide, Artech House, 1995. [4]. R.L. Best, Phase Locked Loops: Design, Simulation Applications, Edition, McGraw Hill, 1997. [5]. Bannerjee, Dean, "PLL Performance, Simulation Design," National Semiconductor website. [6]. Analog Devices, Inc., ADF4106 Data Sheet. Online www.analog.com. [7]. Hittite Microwave Corporation, HMC362S8G Data Sheet. Curtin, Mike, "Phase-Locked Loops," Analog Dialogue, Volume 1999. Three-part series Analog Dialogue 33-3, 33-5, 33-7 (1999) online www.analog.com/ Goldberg, Bar-Giora, Digital Frequency Synthesis Demystified, (LLH, 1999). [10] Egan, William Frequency Synthesis Phase Lock: Edition, John Wiley Sons (1999).
This provides figure merit Synthesizer circuit itself, irrespective noise contributed value frequency, since these would same similar circuit being compared. ADF4106, this figure -219 dBc/Hz, 3-dB improvement ADF4113, which been best available integer-N synthesizer terms phase noise.
-120
-130 PHASE NOISE dBc/Hz
-140
-150 ADF4113 -160 ADF4106 -170
-180
100k
FREQUENCY
100M
Figure ADF4106 phase noise frequency.
Analog Dialogue 35-6 (2001)
Winning Battle Against Latch-up CMOS Analog Switches
Catherine Redmond (catherine.redmond@analog.com)
INTRODUCTION
This article will briefly describe causes, mechanisms, consequences latch-up discuss available prevention methods. Although give understanding latch-up occurs CMOS switches, similar principles apply many other CMOS devices. Latch-up defined creation lowimpedance path between power supply rails result triggering parasitic device. this condition, excessive current flow possible, potentially destructive situation exists. After even very short period time this condition, device which occurs destroyed weakened; potential damage occur other components system. Latch-up caused number triggering factors, discussed below-including overvoltage spikes transients, exceeding maximum ratings, incorrect power sequencing.
When thus latched, longer dependent trigger source applied gate (G), continual low-impedance path exists between anode cathode. Since triggering source need constant, could simply spike glitch; removing will turn SCR. long current through sufficiently large, will remain latched state. however, current reduced point where falls below holdingcurrent value, switches off. Figure shows current-to-voltage transfer function SCR. order bring device conductive state, either voltage applied across must reduced value where each transistor turns off, current through must reduced below holding current. CMOS switch channel effectively consists PMOS NMOS devices connected parallel; control signals turn applied drivers. Since these devices located close together die, possible that with appropriate excitation, parasitic devices conduct-a form behavior possible with CMOS circuit. Figure illustrates simplified cross section showing CMOS structures, PMOS NMOS; these could connected together inverter switch channel. parasitic transistors responsible latch-up behavior, (vertical PNP) (lateral NPN) also shown.
SUBSTRATE N-WELL
Cause
understanding latch-up, desirable briefly review basics understand participating components. already stated, latch-up occurs result triggering parasitic device- effect (silicon controlled rectifier), four-layer pnpn device formed least least transistor connected shown Figure
LATCHED STATE
Figure Cross-section PMOS NMOS devices, showing parasitic transistors substrate used devices from ADG7xx family switches multiplexers, while devices from ADG4xx ADG5xx families substrate. From Figure seen that reinterpretation silicon configuration shows that inherent parasitic bipolar transistors, produce parasitic structure discussed above (Figure
FORWARD BLOCKING REGION
Figure Transistor equivalent SCR. Current voltage characteristic SCR. normally device "blocking state," which negligible current flows. behavior similar that forwardbiased diode, conducts from anode, cathode, only control signal applied gate, normally state, presents high impedance path between supplies. When triggered into conducting state result excitation applied gate, said "latched." enters this state result current from gate injected into base which causes current flow base-emitter junction turns causing further current injected into base This positive feedback condition ensures that both transistors saturate; current flowing through each transistor ensures that other remains saturation.
GND/VSS
Figure Rearrangement view parasitic bipolars Figure shows structure.
Triggering mechanisms
Having described architecture that makes latch-up possible, discuss events that trigger such behavior. latch-up occur through following mechanisms. Supply voltages exceeding absolute maximum ratings. These ratings data sheet indication maximum voltage that safely applied switch. Anything excess result breakdown internal junction hence damage device. addition, operation switch under conditions close maximum ratings degrade long term reliability. important note that these ratings apply
Analog Dialogue 35-05 (2001)
times, including when switch being powered off. triggering mode could result from transients supply rails. Input/output voltage exceeding either supply rail more than diode drop. This could occur result fault channel input-if part system powered prior supplies being present switch similar CMOS components system). powered part circuit would sending signals other devices design which able handle voltage levels presented. resulting voltage levels could exceed maximum rating device possibly result latch-up. Again, this could occur result spikes glitches input output channels. Poorly managed multiple power supplies. Switches that have multiple power supplies tend more susceptible latch-up resulting from improper power supply sequencing. Such switches usually have analog supplies, VSS, digital supply, some cases, when digital supply applied prior other supplies, possible maximum ratings exceeded device enter latch-up state. general, those devices that require external digital supply, recommend that when power being applied removed from device, care should taken ensure maximum ratings exceeded. When triggering mechanisms described above occur, parasitic structure Figure begin conduct, producing impedance state between power supply rails. there current limit mechanism supplies, excessive current will flow through this structure through switch. This could destroy switch other components allowed persist. With high current levels, device would have remain latch-up state very long; even very brief latch-up result permanent damage current limited.
hence latch-up. While Figure shows case where digital input exceeding supply switch, diode also protects against overvoltages applied switch's analog signal path. Now, consider switch with multiple supplies, where example, digital supply, applied device prior other supplies, exceeding maximum ratings exposing circuit potential latch-up. Internal diodes turned simple addition Schottky diode, connected between (Figure will adequately prevent conduction subsequent latch-up. This works very well; ensures that when applied switch, always within diode drop (0.3 Schottky) maximum ratings exceeded.
CMOS DEVICE
Figure Addition Schottky diode from ensures maximum ratings exceeded. Where addition extra component viable option, cost limited board space, switches available that have been manufactured with process that ensures that they latchup proof. process uses insulating oxide layer (trench) between NMOS PMOS devices each switch. This oxide layer both horizontal vertical produces complete isolation between devices, shown Figure
Protection prevention
such fate inevitable CMOS circuitry. simplest preventing latch-up occurring adhere absolute maximum ratings. this always possible, there other methods designing latch-up-proof system.
1N914 POWERED IC#1 ROUT OUTPUT INPUT POWERED DOWN IC#2 RSUB
P-CHANNEL
N-CHANNEL
BURIED OXIDE LAYER SUBSTRATE (BACKGATE)
Figure Cross section switch manufactured with trench processing. This eliminates parasitic bipolar devices between transistors, resulting latch-up-proof switch. "Latch-up-proof" means that matter what power sequenced device, latchup cannot occur. Table lists Analog Devices switches, multiplexers, channel protectors that have such processing. Although devices listed latch-up-proof, designed handle overvoltages outside supply rails, table indicates. addition these latch-up proof switches, there other devices that tolerate underand overvoltages, with power applied, V/-25 excess supplies V/-40 with power applied device.These devices specifically designed ensure that they handle faults event power-on -off conditions. They also employ insulating oxide layer protect against latch-up. They available either multiplexers channel protectors.
DGND
RP-WELL
COMMON GROUND
DGND IDGND
Figure Addition diode series with prevents triggering. Here some options protecting against preventing latchup: Where possible digital analog inputs exceed supply-either while power being applied during operation-the addition diode connected series with prevents base current from flowing, thus avoiding triggering
Analog Dialogue 35-5 (2001)
multiplexers structure having n-channel, p-channel, n-channel MOSFETs series (Figure provide both device- signal-source protection event overvoltage power loss. multiplexer withstand continuous overvoltage inputs from When analog inputs outputs exceeds power supplies, MOSFETs will switch off, multiplexer input output) appears open circuit, output clamped within supply rail, thereby preventing overvoltage from damaging circuitry following multiplexer. This protects multiplexer, circuitry drives, sensors signal sources which drive multiplexer. Figure shows what happens channel ADG438F event positive overvoltage. Because fault protection works regardless presence supplies, muxes also ideal applications where power sequencing cannot always guaranteed protect analog inputs (e.g., hotinsertion rack systems).
+55V OVERVOLTAGE n-CHANNEL MOSFET
three extra components channel, plus board space accommodate them. channel protector would equally effective simpler solution single small package.
ADG465
VOUT VOUT
OUTPUT CLAMPED 1.5V
Figure Channel protector clamps overvoltages within power supply rail voltage protects sensitive components. example, channel protector could used conjunction with ADC, switch, multiplexer, other device ensure that channels protected, both event over- undervoltage, fault when system unpowered. These devices withstand continuous voltage inputs from Because channel protection works regardless presence supplies, channel protectors also ideal applications where power sequencing cannot always guaranteed protect analog inputs. familiar example hot-insertion rack systems.)
Figure overvoltage applied input channel ADG438F/ADG439F multiplexer state. Similarly, channel protectors used protect sensitive components from voltage transients signal path whether power supplies present. They built like fault-protected muxes described above. When powered, channel always condition, event fault, clamps output within supply rails, shown Figure Channel protectors generally placed series with signal path ahead standard CMOS processed devices ensure that potential faults tolerated without damage components system. common protecting channel from potential faults, either powered nonpowered condition, connect diodes current limiting resistors between channel supplies. While effective solution, requires
CONCLUSION
Inasmuch application tolerate latch-up, necessary aware possibility, understand protect against take measures prevent from happening. Given some thought available methods components, indeed possible assemble latch-up-proof system. While discrete solutions-such diodes-could used, devices like latch-upproof switches, fault protected multiplexers, channel protectors provide simpler, more compact, more generally suitable solution, resulting robust system likely give fewer problems field.
Table Latch-up proof Analog Devices switches, multiplexers, channel protectors.
Part Number ADG431A ADG432A ADG433A ADG441 ADG442 ADG444 ADG511A ADG512A ADG513A ADG438F ADG508F ADG439F ADG509F ADG465 ADG466 ADG467
Function Quad SPST (NC) Quad SPST (NO) Quad SPST Quad SPST (NC) Quad SPST (NO) Quad SPST Quad SPST Quad SPST Quad SPST Octal Channel Multiplexer Octal Channel Multiplexer Differential Channel Differential Channel Single Channel Protector Triple Channel Protector Octal Channel Protector
Latch-up Proof
Over/Under-Voltage Capability
Package1 R-16 R-16 R-16 R-16, N-16 R-16, N-16 R-16, N-16 R-16 R-16 R-16 R-16, N-16 RN-16, RW-16, N-16 R-16, N-16 RN-16, RW-16, N-16 RT-6, RM-8 RM-8, R-8, RS-20, R-18
DIP, R/RN 0.15" SOIC, 0.3" SOIC, SSOP, µSOIC, SOT-23
Normally Closed; Normally Open
Analog Dialogue 35-5 (2001)
Avoiding Instability Problems Single-Supply Applications
Charles Kitchin
SINGLE DUAL SUPPLY?
Although advantageous implement circuits with balanced dual supplies, there many practical applications where, energy conservation other reasons, single-supply operation necessary desirable. example, battery power, automotive marine equipment, provides only single polarity. Even linepowered equipment, such computers, have only singlepolarity built-in supply, furnishing system. processing analog signals, common feature single-supply operation need additional components each stage appropriate signal biasing. this carefully thought through executed, instability other problems encountered.
100k RLOAD SIGNALS, VOUT (R2/R1)) WHERE 100k
(1/2RA)
COUT VOUT RLOAD
*STAR GROUND
Figure potentially unstable single-supply circuit. This simple circuit additional potentially serious limitations. First, amp's inherent ability reject supply-voltage variations avail, change supply voltage will directly change VS/2 biasing voltage resistor divider. While this does present problem common-mode noise appearing power-supply terminals will amplified, along with input signal (except lowest frequencies). With gain 100, millivolts ripple will amplified level output. Even worse, instability occur circuits where must supply large output currents into load. Unless power supply well regulated (and well bypassed), significant signal voltages will appear supply line. With amp's noninverting input referenced directly supply line, these signals will directly back into amp, often phase relationship that will produce "motor boating" other forms oscillation. While extremely careful layout, multicapacitor power supply bypassing, star grounds, printed circuit board "power plane," help reduce noise maintain circuit stability, better employ circuit design changes that will improve power supply rejection. suggested here.
Common Problems with Resistor Biasing
Single-supply applications have inherent problems that usually encountered dual-supply circuits. fundamental issue signal swing both positive negative with respect "common," this zero-signal reference voltage must fixed level between supply rails. principal advantage dual supplies that their common connection provides stable, low-impedance zero reference. supply voltages usually equal opposite (and often tracking), that absolute necessity. With single supply, such node must created artificially, introducing additional circuitry provide some form biasing, maintain signal common appropriate midsupply voltage. Since usually desirable large output values limit symmetrically, bias usually established midpoint rated amplifier output range convenience, one-half supply voltage. most effective achieve this with regulator, Figure however, popular method involves tapping supply voltage with pair resistors. Though apparently simple, there problems with this. Illustrating problem, circuit Figure which several design weaknesses, ac-coupled noninverting amplifier. signal capacitively coupled out. average level ac-coupled input biased VS/2 RA-RB divider pair, in-band gain R2/R1. "noise gain" reduced unity capacitively coupling feedback with zero established that level output equal bias voltage. This avoids distortion excessive amplification amplifier's input offset voltage. amplifier's closed-loop gain rolls from R2/R1) high frequency unity with break frequencies 1/[2 1/[2 C1], introducing phase shifts that those associated with input- output-coupling circuits.
Decoupling Biasing Network from Supply
step toward solution bypass bias-voltage divider, provide separate input return resistor, modifying circuit shown Figure point voltage divider bypassed signals capacitor restore powersupply rejection. Resistor RIN, which replaces RA/2 circuit's input impedance signals, also provides return path input.
(1/2RA) RLOAD *STAR GROUND 100k 100k 100k
VS/2 VS/2 150k
COUT VOUT RLOAD
1/10TH BW2, BW3, SIGNALS, VOUT (R2/R1)) WHERE <<R1 MINIMIZE INPUT BIAS CURRENT ERRORS, SHOULD EQUAL (1/2
Figure decoupled single-supply biasing circuit.
Analog Dialogue 35-2 (2001)
values should, course, feasible; values chosen here intended conserve supply current, might wish battery-powered application. bypass capacitor value should also carefully chosen. With k/100 voltage divider similar capacitance value bandwidth this network's impedance, parallel combination equal 1/[2 (RA/2) Although this improvement Figure common-mode rejection drops below allowing substantial feedback through power supply signal frequencies. This requires larger capacitor avoid "motorboating" other manifestations instability. practical approach increase value capacitor large enough effectively bypass voltage divider frequencies within circuit's passband. good rule thumb this pole one-tenth input bandwidth, RINCIN R1C1. amplifier's gain still unity. Even amp's input bias currents need considered. RIN, series with RA/RB voltage divider, adds considerable resistance series with amp's positive input terminal. Maintaining amp's output close midsupply, using common voltage-feedback amps that have symmetrical balanced inputs, achieved balancing this resistance choice Depending supply voltage, typical values that provide reasonable compromise between increased supply current increased sensitivity amplifier bias current, range from single supplies, down supply Amplifiers designed high-frequency applications (especially current-feedback types) need input feedback resistances order maintain bandwidth presence stray capacitance. such AD811, which designed video speed applications, will typically have optimum performance using resistor Therefore, these types applications need much smaller resistor values RA/RB voltage divider (and higher bypass capacitances) minimize input bias current avoid low-frequency instability. Because their bias current, need balancing input resistors great applications with modern FET-input amps, unless circuit required operate over very wide temperature range. that case, balancing resistance amp's input terminals still wise precaution.
(1/2RA) RLOAD <<XC1 SIGNALS, VOUT (R2/R1) WHERE <<R1 MINIMIZE INPUT BIAS CURRENT ERRORS, SHOULD EQUAL *STAR GROUND 100k 100k
Figure shows biasing bypassing might applied case inverting amplifier. resistor divider biasing technique cost keeps amp's output voltage VS/2, amp's commonmode rejection still depends time constant formed capacitor Using value that provides least times time constant input coupling network (R1/C1 RIN/CIN) will help ensure reasonable common-mode rejection ratio. With resistors practical values kept fairly small long circuit bandwidth low.
Zener Diode Biasing
more effective provide necessary VS/2 biasing single-supply operation Zener-diode regulator, such that shown Figure Here current supplied Zener diode through resistor Capacitor helps reduce Zenergenerated noise from appearing input.
SELECT PROVIDE DESIRED ZENER OPERATING CURRENT, TEXT. VZENER RLOAD *STAR GROUND 100k 100k COUT VOUT RLOAD
SIGNALS, VOUT (R2/R1)) WHERE <<R1 MINIMIZE INPUT BIAS CURRENT ERRORS, SHOULD EQUAL RIN.
Figure noninverting single-supply amplifier using Zener diode biasing. Zener with operating voltage close VS/2 should chosen. Resistor needs selected provide high enough current operate Zener stable rated voltage keep Zener output noise low.Yet, also important minimize power consumption (and heating) avoid damage Zener. input draws little current from reference, good idea choose low-power diode. mW-rated device best, more common types also acceptable. ideal Zener current varies with each manufacturer, practical levels between (250 device) (500 device) usually good compromise this application. Within operating limits Zener, circuit Figure basically provides reference-level impedance, which restores amp's power supply rejection. benefits substantial, there price: more power consumed, amp's output fixed Zener voltage, rather than VS/2. power supply voltage drops substantially, asymmetrical clipping occur large signals. Also, input bias currents still need considered. Resistors should close same value prevent input bias currents from creating substantial offset voltage error. Figure inverting amplifier circuit using same Zener biasing method.
VS/2 VS/2
COUT VOUT RLOAD
Figure decoupled single-supply inverting amplifier circuit.
Analog Dialogue 35-2 (2001)
SELECT PROVIDE DESIRED ZENER OPERATING CURRENT, TEXT. VZENER RLOAD ZENER 100k
DC-Coupled Single-Supply Circuits
far, only ac-coupled circuits have been discussed. Although with suitable large input output coupling capacitors, ac-coupled circuit operate frequencies well below some applications require true input output coupling. Circuits that provide constant voltage impedance, such Zener diodes regulators discussed above, used provide "ground-level" voltages. Alternatively, VS/2 biasing resistors Figures through buffered provide low-impedance "phantom ground" circuit shown Figure low-voltage battery, supply source, should "rail rail" device that able operate effectively over full supply-voltage range. also needs able supply positive negative output current large enough satisfy main circuit's load requirement. Capacitor bypasses voltage divider attenuate resistor noise. This circuit does need provide power supply rejection, because will always drive common terminal ("ground") one-half supply voltage
110k
COUT VOUT RLOAD 100k
SIGNALS, VOUT (R2/R1) WHERE <<R1
*STAR GROUND
MINIMIZE INPUT BIAS CURRENT ERRORS, SHOULD EQUAL RIN.
Figure inverting single-supply amplifier using Zener-diode biasing. Table shows some common Zener diode types that chosen provide halfway supply bias various supply voltage levels. convenience, practical values provided furnish device currents Circuits lower circuit noise, optimum Zener current selected referring manufacturer's data sheet.
Table Suggested Zener-diode part numbers (Motorola types) values Figures
Supply Voltage Reference Voltage Diode Type 1N4100 1N4693 1N4627 1N4691 1N4623 1N4687 1N4617 1N4682 Zener Current Value
220k 220k
VS/2
1.5k 11.5k 1.15k 9.31k 5.23k
*STAR GROUND
Figure Using provide "phantom ground" battery-powered direct-coupled applications.
Biasing Using Linear Voltage Regulator
circuits operating from standard, 1.65 biasing voltage needed. Zener diodes commonly available only down although 1.225 AD589 AD1580 bandgap shunt regulators used like Zener diodes provide fixed-though centered-voltage impedance. easiest provide arbitrary values biasing voltage impedance (for example, VS/2) linear voltage regulator, such ADM663A ADM666A, shown Figure output adjusted from will provide lowimpedance biasing single-supply voltages from 16.5
SENSE
Circuit Turn-On Time Issues
final issue that needs considered circuit turn-on time. approximate turn-on time will depend time constant lowest-bandwidth filter being used. circuits with passive biasing shown here should require RB-C2 voltage-divider network have longer time constant than that input output circuit. This simplify circuit design (since three different poles input bandwidth). This long-time constant also helps keep biasing network from "turning before amp's input output networks, thus allowing amp's output gradually climb from zero volts VS/2 without being driven positive supply rail. required corner frequency 1/10th that R1/C1 RLOAD/COUT. example: Figure circuit gain value provides With 50,000 capacitor provides time constant 0.15 seconds. amp's output will take about seconds seconds settle reasonably close VS/2. Meanwhile, input output networks, will charge times faster. applications where circuit's turn-on time become excessively long, Zener active biasing method better choice.
ADM663A VOUT ADM666A
VSET
VS/2 VS/2
COUT VOUT RLOAD
1.3V ADJUSTABLE OUTPUT
*STAR GROUND
Figure single-supply biasing circuit using linear voltage regulator.
Analog Dialogue 35-2 (2001)
Improved Data Acquisition Using Monolithic Dual-ADC Front
Albert O'Grady
Designers measurement systems such temperaturecompensated weigh scales instrumentation, perform their task more effectively with single-chip converter/ analog front end. AD7719 features high resolution inherent sigma-delta converters; augmented throughput, contains ADCs (24- 16-bit resolution), permitting simultaneous parallel conversions input variables without latency inherent analog multiplexing schemes. employs signalchopping approach that provides signal conditioning with stable gain minimal offset, coupled with built-in calibration, eliminate need calibration field. conveniently includes matched pair current sources, simplify transducer excitation improve measurement accuracy when using resistive transducers. Other useful features include circuitry that switched low-side switches that used conserve power when converters transducer power being used, plus digital port monitoring control external devices. AD7719, complete analog front low-frequency measurement applications, newest addition Analog Devices family high-resolution, low-bandwidth, sigma-delta converters. builds experience gained from employing previous generations sigma-delta converters applications ranging from weigh scales portable instrumentation, pressure, temperature transducer measurement, smart transmitters, liquid/gas chromatography, industrial process control. enhanced features mentioned above (see Figure address many issues that commonly recur design such high-performance data acquisition systems. AD7719 contains independent, high-resolution, sigmadelta ADCs. Each analog-to-digital conversion accomplished second-order sigma-delta modulator with programmable sinc3 filter. addition, makes available switchable matched excitation current sources, low-side power switches, digital port, temperature sensor. 24-bit main channel, with programmable-gain amplifier (PGA) that gains from 128, accepts fully differential, unipolar, bipolar input signals with ranges 1.024 REFIN1 volts. reference input differential provide ratiometric conversion. main analog input channel internally buffered provide very high input impedance; this allows input signals applied directly from transducer without need external signal conditioning. 16-bit auxiliary channel unbuffered offers input signal range REFIN2 one-half REFIN2. device operates from 32,768 (32K) crystal, with onboard generating required internal operating frequencies. output data rate from AD7719 software
DVDD
DGND
REFIN(+) REFIN(-)
XTAL1 XTAL2
AVDD IEXC1 IOUT1 REFERENCE DETECT IEXC2
OSC.
IOUT2 AIN1 AIN2 AIN3 AIN4
AVDD
MAIN CHANNEL 24-BIT SERIAL INTERFACE CONTROL LOGIC DOUT SCLK RESET
AGND AIN5 AIN6 AUXILIARY CHANNEL 16-BIT AVDD TEMP SENSOR PORT
AD7719
AVDD
AGND
REFIN2
PWRGND P1/SW1 P2/SW2
Figure AD7719 functional block diagram. programmable. This allows digital filter notches placed user-defined frequencies. example, with programmed update rate 19.8 rejection notches achieved simultaneously. peak-to-peak resolution depends programmed gain output data rate. device operates from single supply. When operating from supply, power dissipation with both ADCs continuously use. Dissipation reduced disabling both ADCs when appropriate. AD7719 available housed space-saving 28-lead SOIC TSSOP packages.
Signal-Processing Chain
ADCs employ sigma-delta conversion realize bits no-missing-codes performance.The sigma-delta modulator converts sampled input signal into digital pulse train whose duty cycle contains digital information. sinc3 programmable low-pass filter then decimates modulator output data stream give valid data conversion result programmable output rates from 5.35 (186.77 period) 105.03 (9.52 ms). chopping scheme employed minimize channel offset, gain, drift errors. block diagram main input channel shown Figure signal chain auxiliary similar that Figure omits buffer blocks. sampling frequency modulator loop many times higher than bandwidth input signal (oversampled). integrator modulator shapes quantization noise (which results from analog-to-digital conversion) that noise concentrated near one-half modulator frequency. output sigma-delta modulator feeds directly into digital filter, which band-limits response frequency significantly lower than one-half modulator frequency. this manner, 1-bit output comparator translated into band-limited, noise output from ADC. filter's cutoff frequency decimated output data rate programmable sinc-filter (SF) control word loaded filter register. alternating digital output values that result from input chopping summed final summing stage average offsets low-frequency noise. Each output word from filter summed averaged with previous filter output produce
Analog Dialogue 35-2 (2001)
fCHOP
fMOD
fCHOP
fADC
ANALOG INPUT
MOD0
DIGITAL OUTPUT
SINC FILTER
Figure Main signal chain. valid output result written data register. resulting very offset offset- gain-drift specifications quite beneficial applications where drift, noise rejection, optimum rejection important. Besides reduction quantization noise, digital filter also provides normal-mode rejection respective filter control-word settings applications requiring substantial rejection both filter's response default programmed setting (data-update rate 19.8 notches close both frequencies, with >100 rejection shown Figure
ATTENUATION
AD7719 overcomes this problem incorporating independent channels, converting parallel. primary variable secondary variable converted simultaneously, output data from both measurements available parallel, thus avoiding latency associated with multiplexed data acquisition systems. addition, on-chip current sources used excite temperature sensors, such thermistors RTDs temperature monitoring. second commonly encountered issue low-power, batteryoperated weighing systems unnecessary consumption power front-end transducer when standby mode. AD7719's on-chip low-side power switches address this issue removing power transducer when low-power mode, thus offering substantial power savings. Another issue with weigh-scale applications concerns calibration: when often should take place? Because AD7719 factory-calibrated, signal chain uses chopping scheme implementation, gain offset drift reduced minimum, thereby eliminating need calibration field. This performance advantage when AD7719 used weigh-scale applications (Figure circuit Figure main channel monitors bridge transducer, secondary channel monitors temperature means thermistor. bridge transducer's differential output terminals (OUT+ OUT-), connected differential input terminals, AIN1 AIN2. typical bridge with sensitivity mV/V will produce rated full-scale output when excited with excitation source. excitation voltage bridge used directly provide reference suitable resistor divider, which will allow full dynamic range input utilized. Because this implementation fully ratiometric, variations excitation voltage introduce errors system. choice resistance values, shown diagram, gives 1.875 reference voltage AD7719 when excitation voltage With main channel programmed gain 128, full-scale input span corresponds full output span from transducer. requirement weigh-scale applications reject power-mains frequency components much possible. Simultaneous rejection obtained programming AD7719 output data rate 19.8 13-bit peak-to-peak resolution will achieved with AD7719 configured gain with 19.8 update rate. peak- to-peak resolution increased reducing update rate performing extra digital filtering controller. Temperature measured using thermistor AD7719's secondary channel. Thermistors, high-temperature-coefficient
-100 -120 -140 -160 FREQUENCY
Figure Filter profile showing simultaneous rejection nulls with sinc3 filter control word
Typical Applications
AD7719 provides complete analog front implementing frequency measurements using temperature-, pressure-, other transducers. weigh-scale applications, example, secondary variable-such temperature-may need monitored addition primary variable from bridge transducer order compensate variations bridge properties with temperature. Traditionally, sigma-delta ADCs have used single converter with integrated multiplexer front measure multiple input variables. This means that user switch channels front measure secondary variable; consequence, measurement speed suffers from settling time latency associated with digital filter when switching input sources. systems where sigma-delta uses second-order modulator third-order digital filter, output settling time step input three times data rate order fully flush digital filter data pertaining previous channel.This greatly reduce system throughput achievable these applications.
Analog Dialogue 35-2 (2001)
electrical circuit elements formed with semiconductor material, available with negative positive temperature coefficients (NTC PTC). thermistor acts like resistor with temperature coefficient typically -3%/°C -5%/°C. Thermistors offer benefits high stability, precision, small size, compatibility competitive price many applications. They have fast response among highest-sensitivity temperature transducers available. operating temperature range circuit Figure determined choice thermistor. Using 1K7A1 thermistor from Betatherm, with nominal resistance 25°C, employing excitation-current source, operating temperature range -26°C +70°C.
EXCITATION VOLTAGE
with temperature changes. configuring secondary channel AD7719 19.8 update rate, 16-bit peak-to-peak performance obtained. Another application that makes good matched current sources AD7719 where 3-wire used precision temperature measurement, manner shown Figure 3-wire configurations, lead resistances would cause errors single current source were used, excitation current, flowing through RL3, will develop voltage drop across RL1, which adds voltage causes error between AIN1 AIN2.
AVDD IOUT1 XTAL1
OUT- OUT+
AVDD AIN1 AIN2 REFIN REFIN AIN5 IOUT1 XTAL2 XTAL1 32kHz
REFIN(+) 12.5k REFIN(-) AIN1 AGND
DRDY SCLK DOUT DGND AGND PWRGND CONTROLLER
XTAL2
AIN2 IOUT2
DRDY SCLK DOUT CONTROLLER
1K7A1
THERMISTOR AIN6
AD7719
AD7719
DGND
REFIN2 RREF
Figure 3-wire measurement using AD7719. scheme shown Figure however, second current source used null this error furnishing equal opposite compensating current, IOUT2, through RL2, which produces equal voltage drop opposite direction. This current adds IOUT1 flows harmlessly ground through common-mode resistance, producing common-mode voltage, which rejected differential inputs. This analysis assumes that equal, since leads would normally same material equal length, that common-mode voltage developed currents within common-mode range ADC. current from IOUT1 also used develop reference voltage AD7719, across 12.5 resistor, shown, applied differential reference inputs AD7719. This scheme ensures that analog input voltage span remains ratiometric reference voltage. errors analog input voltage, temperature drift RTD's current source, compensated variation reference voltage. current sources typically matched better than voltage compliance either current source AVDD
Figure Weigh-scale application takes advantage many features AD7719. this application, same current source that excites thermistor also generates reference voltage AD7719. result, variations excitation current affect performance, configuration provides fully ratiometric conversion. most common wiring arrangement these applications 4-wire force/sense configuration order reduce effects lead resistances system performance. Although lead resistance drive wires shifts common-mode voltage, does degrade performance circuit. Lead resistance sense wires immaterial, current flows these wires high input impedance AD7719 analog inputs. However, reference-setting resistor must have temperature coefficient avoid errors reference voltage
*See article, "Transducer/Sensor Excitation Measurement Techniques," Analog Dialogue 34-05 (2000).
Analog Dialogue 35-2 (2001)
Challenge- AD7873 Resistive-Touch-Screen Controller
Paul Kearney (paul.kearney@analog.com)
INTRODUCTION
Today, handheld personal digital assistants (PDAs) popping just about everywhere. They finding favor, only with busy executives, also with mainstream consumers-and even classroom! Their ease portability have been keys their rapidly growing success. most popular examples* include Palm Pilot series, Handspring Visor, Sony Clie. estimated that this year alone some million units will sold worldwide, with annual sales expected grow million units 2004. common feature these units their method entering data stylus resistive touch screen. With user easily enter dates his/ diary, send email, keep shorthand minutes meetings, etc. touch screen itself typically 4-wire resistive element. (There also 5-wire resistive screens capacitor screens market, they typically more expensive.) touch screen interfaces with host microprocessor converter (ADC), such AD7873 AD7843, which have special features tailored application. This article will discuss common application issues faced designers when interfacing resistive touch screen, they solved with AD7873.
STYLUS NODE FLOATS MINUS PLANE
(STYLUS) PRESSURE FORCES PLANE SHORT PLANE LOCATION SENSED COORDINATE PLUS
XPLUS
PLANE
XMINUS
SUPPLY
SWITCHES INTERNAL TOUCH-SCREEN CONTROLLER WHICH POWER SCREEN
VOLTAGE SENSED POSITION SPACER DOTS SEPARATE LAYERS GROUND
Figure Stylus interfacing with 4-wire resistive touch screen. X-coordinate measurement depicted. During measurement given coordinate, resistive planes powered along axis through switches controller chip, other plane used sense location coordinate powered plane. coordinate measurement, plane powered. plane used sense where located powered plane follows: location where depresses touch screen, planes shorted. voltage `picked sensed plane proportional location touch powered plane. This voltage then converted using controller's ADC. Y-coordinate measurement, power applied plane, plane used sense position, voltage digitized. digital code corresponding coordinates then operated host microprocessor, command, information, instruction intended stylus location registered.
Theory Operation Details Application
touch screen usually consists layers transparent resistive material-usually indium oxide (ITO) some other form resistive polyester material, with silver electrodes. total resistance each layer varies from vendor vendor, typical screens range. layers stacked insulating layer glass, separated tiny spacer dots. They interfaced electrically controller converter. Figures show, simplified form, controller might interface with 4-wire resistive screen.
APPLIES PRESSURE TOUCH SCREEN
Basic AD7873 touch-screen interface
Figure illustrates simplified block diagram AD7873. addition serving coordinate-measurement transducer, provides number peripheral functions important PDA's function, including measurements temperature battery condition, touch detection, pressure measurement-plus on-chip 2.5-V voltage reference. Figure illustrates typical application diagram AD7873 interfacing with 4-wire resistive touch screen. First let's discuss basic functionality-stylus coordinate measurement. touch-screen switches left Figure drive resistive screen so-called tablet pins, tablet pins also serve sensors position voltage from screen when active, applying method interfacing described briefly above. number things were considered implementation design. First, switches must able source sink current to/from impedance screen. Say, example, supply screen impedance p-MOS switches positive supply pins) must able source when screen powered coordinate measurement. Similarly n-MOS switches ground (these
*All brand product names mentioned trademarks registered trademarks their respective holders.
PROTECTIVE HARD COAT
Y-PLANE RESISTIVE FILM X-PLANE RESISTIVE FILM PROTECTIVE HARD BACKING
HOST MICROPROCESSOR
TOUCH SCREEN CONTROLLER POWERS SCREENS SENSES POSITION FROM THEM.
Figure touch screen uses multilayer sandwich resistive films protective coatings.
Analog Dialogue 35-4 (2001)
TEMPERATURE SENSOR XPLUS TEMPIN YPLUS XMINUS YMINUS TOUCH-SCREEN SWITCHES INPUT VDAC VCOM XPLUS VBAT BATTERY MONITOR YPLUS DUAL INT/EXT VREF BUFF BANDGAP XMINUS YMINUS COMP SPORT DCLK BUSY DOUT INTERRUPT PENIRQ
AUXIN BATIN
Figure AD7873 block diagram. pins) must capable sinking this switches' drain source connections must carefully designed layout stage avoid electromigration problems (due large current density these nodes).The conservatively designed AD7873 switches capable supplying screen, using supply.
AD7873
REF+ REF- taken from pins, respectively. conversion will ratiometric; i.e., result conversion will equal ratio touchscreen resistance measuring point total touch-screen resistance, irrespective voltage drop AD7873's switches. This best ensuring accuracy coordinate measurements.
SUPPLY REFERENCE EFFECTIVELY POTENTIAL ACROSS SCREEN REF+ REF-
TOUCH SCREEN BATTERY
DCLK SERIAL/CONVERSION CLOCK CHIP SELECT SERIAL DATA BUSY CONVERTER STATUS DOUT SERIAL DATA PENIRQ INTERRUPT -100k PULL-UP VBAT VREF
TOUCH SCREEN MODELLED RESISTOR MESH
VOLTAGE REGULATOR DECOUPLING SUPPLY DECOUPLING
SCREEN GROUND
VSCREEN
Figure Typical application circuit using AD7873. on-resistance switches, about also posed challenge. example, when used with screen impedances minimum supply voltage voltage drop across switches appreciable greatly reduces dynamic range signals applied converter input. avoid corresponding reduction conversion accuracy effective resolution, because resistance switches track resistance screen over temperature supply, converter must able operate ratiometric mode. Figures illustrate respectively AD7873 configured both ratiometric single-ended modes operation coordinate measurements. Using ratiometric mode, actual reference taken from drain nodes switches powering screen. example, coordinate being measured, theY plane
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