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About Analog Dialogue

Dan Sheingold dan.sheingold@analog.com Editor, Analog Dialogue

About Analog Dialogue
Analog Dialogue is the free technical magazine of Analog Devices, Inc., published continuously for thirty-five years, starting in 1967. It discusses products, applications, technology, and techniques for analog, digital, and mixed-signal processing.
Dan Sheingold dan.sheingold@analog.com Editor, Analog Dialogue
IN THIS ISSUE
Analog Dialogue Volume 35, 2001
Cover: The cover illustration was designed and executed by Kristine Chmiel-Lafleur, of Communications Services, Analog Devices, Inc.
AUTHORS
John Cowles (page 5) works at ADI Northwest Labs in Beaverton, Oregon, designing RF-IF products for the communications market. He received a PhD in EE from the University of Michigan in 1994. Before joining ADI in 1998, he worked at TRW, in Redondo Beach, CA, on high-speed GaAs and InP technologies. At ADI, he designed the AD8302, which was nominated for Product of the Year by both Electronic Products and EDN magazines. He has over 50 technical publications on high-speed devices and circuits. Mike Cur tin (page 17) is the applications manager for RF products in Ireland. Mike graduated from the University of Limerick with a BSc in Electronic Engineering. He worked in var ious local companies before joining Analog Devices in 1983 as an Applications Engineer. He has provided technical support for a wide variety of Limerick-developed products, including high-speed ADCs, sigma-delta ADCs, and DACs, an activity interrupted by a two-year assignment as a field applications engineer in the U.S. In his spare time, he listens to music and enjoys a game of snooker or indoor football.
ISSN 0161-3626
Giuseppe Olivadoti (page 41) is the technical marketing specialist for the DSP Development Tools product line. He holds a BS in Electrical Engineering with a concentration in Computer Eng ineer ing from Northeastern University.
Analog Dialogue Volume 35 (2001)
NEW FELLOWS
JOSH KABLOTSKY
DENIS DOYLE
LARRY SINGER
PAUL FERGUSON
Paul is an inventive circuit designer who has contributed heavily in the field of switched-capacitor circuits and higher-order sigma-delta ADCs and DACs. He was instrumental in the development of new inventions and technologies that led to the emergence of ADI as the leader in the PC business audio segment. Among these are new ideas for offset calibration, which led to a reduction in "speaker pop" phenomena, once common throughout audio applications. He was also a pioneer in standard-cell layout and novel higherorder sigma-delta loop architectures at ADI.
Analog Dialogue Volume 35 (2001)
Accurate Gain / Phase Measurement at Radio Frequencies up to 2.5 GHz
by John Cowles (john.cowles@analog.com) and Barrie Gilbert (barrie.gilbert@analog.com)
INTRODUCTION Measuring Signals
Measurement of Signal Ratios to 2.5 GHz
CHANNEL A LOG AMP DETECTOR PHASE (10mV / )
CHANNEL B
LOG AMP DETECTOR
GAIN (20mV / dB)
Figure 1. The AD8302 comprises a pair of accurately matched log amps and a high-frequency phase detector.
Analog Dialogue 35-5 (2001)
The customary fixed intercept of Equation 1, is eliminated in the AD8302 by taking the difference of the outputs of the two separate log amps. This key step computes the log of the ratio (VA / VB) (VINTB / VINTA) and, since the log amps are identical, the second term is very accurately unity, independently of temperature, supply voltage, and numerous production variances. This elegant elimination of a fixed intercept results in a highly accurate measurement of signal level, in many applications. The primary limitation to the accuracy of the log argument is now the matching of the two co-integrated channels. This novel "C" structure2 opens up many measurement possibilities that would otherwise require the use of two distinct log amps, with their inherent differences in slope and intercept calibration. The AD8302 is the first IC to permit the direct measurement of ac signal ratios. This unique capability for measuring gain / loss and the relative phase (see below) between two signal ports, over a very wide range of frequencies, will be of value in many other applications. Figure 2 illustrates the output voltage variation as a function of signal ratio (which, for example, may correspond to the gain or loss of a channel being monitored) at frequencies ranging from 900 MHz to 2.2 GHz. The signal level presented to Channel B is fixed while that at Channel A is varied from -30 dB to +30 dB relative to Channel B. The output, VMAG, demonstrates the precise slope, VSLP, of 20 mV / dB and a center-point, VCP, of 900 mV. The very small deviation from an ideal logarithmic law (Figure 2b) demonstrates the value of using co-integrated log amps.
2.5 CHANNEL A LEVEL: -25dBm
Measurement of Relative Phase to 2.5 GHz
The AD8302 can also measure the phase difference between two signals, from low frequencies up to 2.5 GHz. Each of the individual log amps generates a "hard-limited" output at its final stage. These signals are applied to the two inputs of a novel multiplier-style phase detector having exact symmetry with regard to its two inputs and a 180o range. The phase output, VPHS, is given by,
where V is the scaling voltage for the phase output and is the phase difference between the two inputs. The choice of sign depends on which two quadrants constitute the 180o phase interval. With the inclusion of this feature, the AD8302 becomes a "network analyzer on a chip." Figure 3 illustrates phase measurement at 900 MHz, 1.9 GHz, and 2.2 GHz. Here, the phase difference was generated as a "slip, " by slightly offsetting the two input frequencies and allowing the angle to accumulate. The slope of the VPHS output is 10 mV / °C, centered at a VCP of 900 mV. The alternating sign of the slope is apparent as the phase slips through 180o intervals. Figure 3b shows the measurement error. The rapid increase in error near 0o and 180o is due mainly to dead-zones caused by the finite rise and fall times of the hard-limited signals. The unique ability of the AD8302 to accurately measure phase at these frequencies is a result of the excellent balance of its two tightly-integrated log amps.
18.0 10mV / DEGREES
900MHz
0.90 2.2GHz
1.0 2.2GHz 0.2
15 -5 5 -15 GAIN MEASUREMENT - dB
900MHz 0 90 180 270 0 PHASE - Degrees 90 180
4 CHANNEL A LEVEL: -25dBm 3 30 40
CHANNEL A LEVEL: -25dBm
ERROR - Degrees
ERROR - dB
20 2.2GHz 10 1.9GHz
2.2GHz 1
0 900MHz -10
-1 900MHz -2 40
5 20 15 10 0 -5 -10 -15 -20 -25 GAIN MEASUREMENT - dB
250 150 200 PHASE - Degrees
(b) Figure 2. Measurements of signal-level ratios (a) exhibit errors (b) of less than 0.2 dB up to high frequencies.
(b) Figure 3. The phase measurement (a) exhibits low errors (b) over wide angular ranges and up to high frequencies.
Analog Dialogue 35-5 (2001)
Using the AD8302
These new capabilities for measuring gain / loss and the relative phase between two signal ports will be of value in many RF and IF applications. The functionality, versatility, and compact form-factor of this "network analyzer on a chip" are ideally suited for in-situ diagnostics and monitoring of system parameters and for feedback and feed-forward linearization and control of subsystems. These are a few applications of the AD8302. The measurement of absolute signal level is now possible using a known ac reference. As shown in Figure 4, the reference signal applied to Channel B creates an effective intercept of value VB. When the two signals have similar waveforms, the measurement can be very accurate. Even the error due to uncertainty in the slope voltage can be minimized (eliminated, in principle) if one can ensure that the two inputs are close-to-equal in amplitude. This will often be a simple matter to arrange, using an attenuator pad on the larger signal to position the ratio VA / VB close to unity. Centering techniques are valuable when the highest accuracy is needed or where very large dynamic ranges must be handled.
AD8302
1 COMM 2 INPA 3 OFSA 4 VPOS 5 OFSB 6 INPB 7 COMM
20dB GAIN 100mV
100MHz
300MHz FREQUENCY
1.3GHz
SOURCE 20dB ZLOAD 0dB 20dB
CMFLT
MFLT 14 VMAG 13 MSET 12 VREF 11 PSET 10 VPHS 9 PFLT 8 CPFLT PHASE (10mV / Deg) VREF (1.80V) GAIN (30mV / dB)
INCIDENT AND REFLECTED DIRECTIONAL COUPLERS: 20dB R2 C5 C3 C6 C4 R1
AD8302
Figure 4. Absolute measurements of signal level using an AC reference on Channel B as the intercept for Channel A. The most useful application of the AD8302 is in monitoring and reporting the gain or loss of a functional block or subsystem. In the example shown in Figure 5, samples of the input and output signals of a 500-MHz IF amplifier with a nominal gain of 20 dB are monitored. By using attenuators and couplers, the two signals are conditioned to be of the same general magnitude. The gain response shows the mid-scale low frequency value, which corresponds to a 20-dB level difference at the amplifier and a 3dB bandwidth of approximately 500 MHz. The functional block in this example could have been a frequency-translation device, such as a mixer. In that case, the two inputs would be at different frequencies, and the measured quantity would be the conversion gain. Since the waveforms remain similar, that source of error is again eliminated. However, when the input frequencies differ greatly, a systematic offset may occur due to inequalities in the impedance match and the frequency dependence of the scaling of the two log amps in the gigahertz region. In many communication systems, there is an unpredictable load presented to an external interface port. Variations in this load can
COMM INPA HPFA VPOS HPFB INPB COMM
FLMG 14 VMAG 13 R5 MGFB 12 VREF 11 PHFB 10 VPHS 9 R6 FLPH 8 C8 PHASE GAIN
Figure 5. The AD8302 monitoring the frequency response of an amplifier under test and reporting the gain. lead to changes in system performance, or even to catastrophic failure in extreme cases. It is of great value to provide the means of monitoring the load impedance-or reflection coefficient in RF terms-without perturbing it. In Figure 6, the AD8302 is configured to measure the reflection coefficient of an arbitrary load which, in this case, is a PIN-diode whose bias is swept to change its impedance. The notch in the response curve represents a near-match to the 50- characteristic line impedance, where the reflected signal is almost zero.
A detailed description of the theory of operation of log amps can be found in the AD640 data sheet. 2 Patent pending.
Analog Dialogue 35-5 (2001)
VOUT CHANNEL A
AD8302
CMFLT
COMM INPA OFSA VPOS OFSB INPB COMM
MFLT 14 VMAG 13 MSET 12 VREF
MAG OUT MAG THRESHOLD VREF PHASE THRESHOLD PHASE OUT
DUT CHANNEL B
PSET 10 VPHS 9 PFLT 8
MATCH
CPFLT
"OPEN" DIODE BIAS
SOURCE INCIDENT WAVE 20dB 1dB
"SHORT"
Figure 7. The AD8302, configured as a gain- and phase-comparator with controllable thresholds. In the controller mode, shown in Figure 8, the VMAG and VPHS pins drive gain / phase-adjusters that are included in the signal chain being monitored so as to servo the overall gain and phase of the system toward the desired set-points presented to the MSET and PSET pins.
REFLECTED WAVE
ZLOAD
INCIDENT AND REFLECTED DIRECTIONAL COUPLERS: 20dB R2 R1
VOUT CHANNEL A
AD8302
CMFLT MAG CONTROL
COMM INPA OFSA VPOS OFSB INPB COMM
MFLT 14 VMAG 13 MSET 12 VREF 11 PSET 10 VPHS
MAG THRESHOLD VREF PHASE THRESHOLD
DUT PHASE CHANNEL B
AD8302
1 COMM 2 INPA 3 HPFA 4 VPOS 5 HPFB 6 INPB 7 COMM
FLMG 14 VMAG 13 R5 MGFB 12 VREF 11 PHFB 10 VPHS 9 R6 FLPH 8 C8
PFLT 8 CPFLT
PHASE CONTROL
Figure 6. The AD8302 monitors the reflection coefficient of a load-a PIN diode whose impedance is manipulated by its bias.
Versatility and Ease of Use
The AD8302 offers several other modes of operation, the result of careful planning and the fundamentally versatile nature of this unusual structure. The previous examples have demonstrated the AD8302 in its typical measurement mode, where the VMAG and VPHS outputs report the signal level and phase difference between its inputs. However, the built-in scaling and center-points of the transfer functions can be adjusted using external resistors and the 1.80-V internal reference provided at the VREF pin. By disconnecting the output pins from the feedback pins, MSET and PSET, a gain- and phase-comparator is realized, as shown in Figure 7. Here, the VMAG and VPHS outputs toggle between 0 V and the maximum output voltage of 1.8 V, depending on whether the signal level and phase difference are greater than or less than the thresholds presented to the MSET and PSET pins.
ACKNOWLEDGMENTS
The authors would like to recognize the tireless efforts of Tom Kelly and Shirine Eslamdoust in product engineering, and Ron Simonson and Rick Cory for applications development. b
Analog Dialogue 35-5 (2001)
High Performance Narrowband Receiver Design Simplified by IF Digitizing Subsystem in LQFP
By Paul Hendriks, Richard Schreier, and Joe DiPilato
(paul.hendricks@analog.com richard.schreier@analog.com joe.dipilato@analog.com)
with a host processor. The AD9870 is intended for both base stations and subscriber units, combining the dynamic range required by base stations with the low power consumption needed by portable radios.
The big problem in all receivers is dynamic range
TWO INTERFERERS "HALF IF" INTERFERER @ (f0 + LO) / 2
INTRODUCTION
Mobile radios are used for public safety and emergency services- police, fire and ambulances-as well as for private services such as fleet management. Increasingly, in order to provide enhanced services, along with improved spectral efficiency and coverage, the design of these radios has moved from traditional analogbased modulation schemes, such as FM and PM, to digital modulation approaches. Receivers for these radios must be capable of accurately digitizing a low-level, high-frequency signal in the presence of large interfering signals. In radios using some narrowband land mobile standards, interfering signals can be 70 dB greater than the desired channel, with frequency offsets as little as 25 kHz. Since these systems usually are not cellular, the geographical coverage range of mobile radios is also an important feature-they must possess excellent sensitivity to recover low-level signals originating from subscribers at the fringe of the coverage range. As a further complication, these radios are often portable with high rates of usage they demand low power consumption using smaller, longer-lived batteries. As an aid to equipment designers, Analog Devices has made available the AD9870 IF Digitizing Subsystem, an IC designed to meet the demanding requirements of land mobile radio, and similar narrowband radio applications, with superheterodyne architectures employing analog and / or digital modulation schemes. The AD9870 integrates the entire IF strip with minimal external components. It can accept an IF signal at frequencies as high as 300 MHz, with bandwidths up to 150 kHz, and provides a serial data output containing 16-bit I and Q data, which can then be demodulated
INTERFERER WITH "PHASE NOISE"
70dB OR MORE
SMALL TARGET SIGNAL
THERMAL NOISE
FREQUENCY
Figure 1. The "Big Problem" in all receivers is dynamic range.
Analog Dialogue 35-3 (2001)
Two large interferers at equally spaced frequency offsets (i.e., f0 + and f0 + 2) from the target signal will result in a spurious component falling on top of the target signal through a process of intemodulation. The linearity of a receiver in this scenario is captured in its IIP3 specification with higher numbers representing a higher tolerance to third-order intermodulation. The difference, or , between the two equal interferers, PIN, and the resulting thirdorder intermodulation component is 2 (IIP3 - PIN). The AD9870 has a respectable IIP3 performance of -1 dBm, thus tolerating interferers as high as -45 dBm before degrading the receivers sensitivity.
Superheterodyne Architecture
CHANNEL SELECT FILTER(S)
AD9870 Architecture
The AD9870 IF digitizing subsystem reduces the complexity of a typical superheterodyne receiver by integrating most of the IF, baseband, and some digital post processing functional blocks as shown in Figure 3.
QUAD DEMOD
ADC RF LNA BAND SELECT FILTER IMAGE REJECT FILTER VGA 90
RF LO AGC ADC Q
RF / IF SYNTHESIZER
IF LO CLK SYNTHESIZER
Figure 2. Typical superheterodyne architecture for a digital receiver.
RF LNA IF SPI PORT DATA
AD9870
RF LO RF PLL / VCO IF VCO REF OSC.
I / Q SERIAL DATA
Figure 3. The AD9870 simplifies the digital receiver while enhancing performance.
IF IN (10MHz-300MHz) LNA AAF / VGA
FORMAT SSI TO BASEBAND PROCESSOR
SUPPORT CIRCUITRY LO SYNTHESIZER CLK SYNTHESIZER SPI AND CONTROL BANDGAP REFERENCE
Figure 4. Functional block diagram of the AD9870 shows the level of integration.
Analog Dialogue 35-3 (2001)
20 IF2P IF2N I Q
45 42 39 36 MEAN AGC VALUE 50 ADC CLIPS AT -24dBm 150
NOISE FIGURE - dB
33 30 27 24 21 18 15 12 NOISE FIGURE
VGA / AAF
ej(2 fCLK / 8)t
DEC1 20
9 -150 -85 -80 -75 -70 -65 -60 -55 -50 -45 -40 -35 -30 -25 -20 SIGNAL AMPLITUDE - dBm
ADC CLIP POINT ABS(IN) + ABS(QN) OLW VGA DAC
GCN GCP
1 (1-z -1)
AGC CONTROL
AGCR REF LEVEL
fCLK / 20
Figure 5. A "hybrid" AGC control loop extends the dynamic range of the AD9870.
Analog Dialogue 35-3 (2001)
MEAN AGC VALUE
0 FIRST RESONATOR -g SECOND RESONATOR -g 0dBFS OUTPUT
9-LEVEL QUANTIZER dBFS / NBW ELEMENT SELECTION LOGIC z z-1
5 4 6 FREQUENCY - MHz
Figure 7. Multibit fourth-order bandpass - ADC results in deep notch at fCLK / 8.
COS DEC1 DATA FROM SIGMA-DELTA MODULATOR SIN SINC4 FILTER 20 M I DEC2 SINC4 FILTER M+1 DEC3 FIR FILTER 3 COMPLEX DATA TO Q SSI PORT
AVAILABILITY
Recommended resale price USD. Prices are subject to change without notice. For specific price quotations, get in touch with our sales offices or distributors.
Analog Dialogue 35-3 (2001)
AD9873 Mixed-Signal Front End (MxFE) for Broadband Digital Set-Top Boxes
By Iuri Mehr, Joe DiPilato, and Martin Kessler
Widespread deployment of TV cable has led to extensive research in providing better quality and increased variety in TV programming and cable-modem functionality. This effort resulted in the development of digital set-top boxes from several established vendors, including Scientific Atlanta and Motorola (General Instrument). Instead of analog vestigial-sideband modulated (VSB) channels, digital set-top boxes receive TV programming and exchange information with the head-end station using quadrature amplitude modulation (QAM). Transmitting analog information in digital bits is not only more robust but also makes use of available bandwidth more efficiently. Figure 1 shows a digital set-top box connected to the head-end and to various devices inside the residence (or office).
WALL TV SET TV CABLE
PHONE LINE
TV CABLE
ANALOG TV SET
DIGITAL TV SET
COMBINER
OUT-OF-BAND (OOB) CONTROL CHANNEL
TUNER (50MHZ -800MHz)
CABLE DRIVER (AD832x)
CHANNEL 3 / 4 MODULATOR
PHONE LINE INTERFACE
MIXED-SIGNAL FRONT-END (AD9873)
MEMORY
COMPUTER INTERFACE
COMPUTER
PHY AND MAC (DOCSIS)
MPEG AND NTSC DECODER
MPEG AND NTSC ECODER
SYSTEM BUS
Figure 2. Inside a typical digital set-top box.
Mixed-Signal Front End
The definition of a mixed-signal front end for a set-top box must take into account the amount of functionality required from the transmit and receive data paths. Low cost is of vital importance, so selecting a proper technology is key to a successful design. In addition, time to market is equally important for both the IC vendor and the OEM. ASICs that include significant digital and analog content are often difficult to schedule due to the time needed to handle the inherent design challenges and the frequent need for customer feedback. The designers of the Analog Devices AD9873 took advantage of both their experience in set-top-box technology and their inventory of high-performance topological block core designs of the kind that would be needed to integrate the essential high-performance analog and mixed-signal functions on a single chip.
AD9873
COS Tx IQ TX Tx SYNC INTERPOLATOR FILTER SIN 3 PLL SERIAL ITF PROFILE 4 2 CONTROL FUNCTIONS DDS 12 12 CA INV SINC 12 DAC Tx
HEAD-END
SET-TOP BOX
COMPUTER
PHONE
Figure 1. Cable set-top box gateway configuration. Several services can be unified in this fashion, including Internet access, cable TV and even phone services. High data rates allow streaming-in MPEG movies as well as high-quality telephony (voice-packet) service. A digital set-top box, like that shown in Figure 2, comprises several major subsystems to implement such functions as a TV tuner, baseband transceivers, a channel 3 / 4 modulator (for compatibility with analog TV sets), MPEG and NTSC decoders and encoders, physical layer (PHY), and media access control (MAC) for cable modems. Since Internet access implies an upstream channel, a cable driver is included it can be implemented using a member of the AD832x family. The box can also include an out-of-band (OOB) control channel and a phone line interface. The multiplicity and complexity of all these blocks impose significant challenges on designers at both the component and board levels. The large amount of digital processing required, combined with the high-quality reception requirements of highdefinition digital TV, pose numerous challenges to digital set-top box architects. In addition, compatibility with analog TV calls for clean analog signal processing from the wall TV cable outlet to the TV set. Therefore, selecting a proper partition for integrated functions becomes a key requirement for combining high-quality TV reception and high data rates in a cable modem at low cost. The mixed-signal front end, which can be implemented using the AD9873, is central to the set-top box (Figure 2).
SDELTA0 SDELTA1 REF CLK
ADC ADC ADC
IIN QIN IF10 IF12 VIDEO
Figure 3. AD9873 functional block diagram. Figure 3 is a block diagram of the AD9873 Analog Front End Converter for Set-Top Boxes and Cable Modems. The receive data path contains several analog-to-digital converters (ADCs) to accommodate the various set-top box functions described earlier. A pair of 8-bit ADCs is used to convert quadrature inputs from the demodulated OOB channel. They are designed for modest
Analog Dialogue 35-1 (2001)
suitable for high-performance analog and mixed-signal circuitry. Products like the AD9873 provide a solution to this problem by offering the possibility of using two small highly integrated chips- a digital ASIC and a mixed-signal "everything else"-that appropriately partition the large scale digital IC from the highperformance mixed-signal component.
CABLE MODEM DIGITAL ASIC
FEC ENCODER
MAPPING Tx FILTER BURST GEN.
INTERPOLATOR IQ MOD
DIPLEXER COAX CABLE
FEC ENCODER
AD8323
ADC ADC
OUT-OF-BAND QPSK-DEMOD
QAM DEMOD
AD9873
RISC CTRL
NTSC / PAL DECODER MPEG2 DECODER VIDEO ENCODER AUDIO / VIDEO CODEC
ADC VIDEO CLAMP
USB / ETHERNET
AD18xx ADV71xx
VIDEO CAMERA COMPUTER SYSTEM TV DISPLAY AND SPEAKERS
CHANGING THE SYSTEM PARTITIONING
TRADITIONAL PARTITIONING DIGITAL CHIP INCLUDING MIXED SIGNAL ADC / DAC: NEW PARTITIONING TREND DIGITAL CUSTOMER ASIC, SEPARATE ADC / DAC (AD9873):
0.35 m PROCESS
DIGITAL
ANALOG
0.25 m PROCESS
DIGITAL
AD987x PROCESS
0.35 m
0.25 m PROCESS
DIGITAL ANALOG
0.12 m PROCESS
DIGITAL
ANALOG
0.25 m PROCESS
+TURNKEY -NO DIFFERENTIATION -TRADE-OFF REQUIRED BETWEEN LOW COST OF FINE GEOMETRY AVAILABLE FOR DIGITAL SECTION AND LARGER GEOMETRY REQUIRED FOR HIGH-PERFORMANCE ANALOG
Figure 5. Smart partitioning model.
Analog Dialogue 35-1 (2001)
AD9873 Key Features and Performance
232 MHz Quadrature Digital Upconverter: - DC to 70 MHz Output Bandwidth - 12-Bit Direct IF D / A Converter - Direct Digital Synthesis - Interpolation and Sin(X) / X Filters 12-Bit 33 MSPS Direct IF ADC 10-Bit 33 MSPS Direct IF ADC Dual 8-Bit 16.5 MSPS I&Q ADCs Dual 12-Bit Sigma-Delta Control DACs Video Input with Clamp Circuitry Direct Interface to AD8321 / AD8313 PGA Cable Driver Programmable PLL Clock Multiplier Single 3.3 V Supply Operation Power-Down Modes 100-Lead MQFP
Performance of the AD9873 was characterized with respect to the commercial temperature range however, it can be safely used from -40°C to +75°C. Figure 7 shows a spectral plot of the 12-bit ADC performance with a 10-MHz input.
MAGNITUDE - dB
Other Applications for the AD9873 Mixed-Signal Front End
Besides cable set-top boxes, the AD9873 is well suited for a variety of other standard and proprietary broadband communications applications, as depicted in Figure 6. Here is a list of other applications where the AD9873 can be used: - Cable Modem - Digital Communications - Data and Video Modems - Power Line Modem - Satellite Systems - PC Multimedia - Broadband Wireless Communication - Home Networking
-125 0 2 4 6 8 FREQUENCY - MHz 10 12
DIGITAL ASIC
INTERPOLATOR IQ MOD
AD832x
MAGNITUDE - dB
RF FRONT END
DIGITAL PHYSICAL LAYER
AD9873
ADC VIDEO CLAMP
Figure 6. Broadband modems over cable, power line, or wireless, using the AD9873.
FREQUENCY - MHz
Figure 8. AD9873 DAC performance plot.
Analog Dialogue 35-1 (2001)
POWER SUPPLY DIOFIFO INTERFACE
AD9873
VIDEO INTERFACE 12-BIT ANALOG INTERFACE 10-BIT ANALOG INTERFACE 8-BIT ANALOG INTERFACE QAM-, NTSCOR SINGLETONE GENERATOR
FIFO CARD DIO CARD
REGISTER CONTROL SOFTWARE
SPI TO PARALLEL PORT INTERFACE
TTL CLOCK GENERATOR
DIGITAL WAVEFORM GENERATOR
Tx AWG INTERFACE
FILTER
AD8323
SPECTRUMOR VECTORANALYZER
EVALUATION BOARD
Figure 9. AD9873 64-QAM constellation plot.
Figure 10. AD9873 evaluation setup.
Figure 11. AD9873 evaluation board and software interface.
Evaluation Board and Software
The AD9873 Evaluation board and software allow users to easily program and quickly evaluate the AD9873 for a specific modem application.
AVAILABILITY
Analog Dialogue 35-1 (2001)
Design a Direct 6-GHz Local Oscillator with a Wideband Integer-N PLL Synthesizer
By Mike Curtin (mike.curtin@analog.com)
INTRODUCTION
AVDD DVDD
addition, the 14-bit reference (R) counter allows selectable REFIN frequencies at the PFD input. A complete phase-locked loop (PLL) can be implemented if the synthesizer is used with an external loop filter and voltage-controlled oscillator (VCO). Its very high bandwidth means that frequency doublers can be eliminated in many high-frequency systems, simplifying system architecture and lowering cost.
Wide bandwidth allows it to function as a 6-GHz local oscillator
The standard PLL system architecture used by the ADF4106 and its predecessor, the ADF4113, is shown in Figure 2. Since the maximum operating frequency of the ADF4113 is about 4 GHz, higher frequencies require the use of a frequency doubler-which usually calls for an extra RF amplifier to produce an adequate level for the doubler. Use of the ADF4106 eliminates the frequency doubler and its associated circuitry, achieving a much simpler and more power-efficient LO. For example, the design shown in Figure 3 generates RF output frequencies with 1-MHz channel separation from 5.4 GHz up to 6.0 GHz. The phase noise measured at the upper end is -83 dBc / Hz.
N COUNTER
Figure 2. Standard PLL architecture. Because the input impedance of the ADF4106 at this high operating frequency is very close to 50 , a 50- terminating resistor at the RF input is not needed for maximum power transfer efficiency. When operating at lower frequencies, the s-parameters in the data sheet give the impedance values needed for matching.
VP CPGND REFERENCE RSET
REFIN
14-BIT R COUNTER 14 R COUNTER LATCH
PHASE FREQUENCY DETECTOR
CHARGE PUMP
CLK DATA LE
24-BIT INPUT REGISTER
FUNCTION LATCH
LOCK DETECT
CURRENT SETTING 1
CURRENT SETTING 2
CPI3 CPI2 CPI1 CPI6 CPI5 CPI4 A, B COUNTER LATCH
FROM FUNCTION LATCH
19 13 13-BIT B COUNTER LOAD AVDD MUX SDOUT
HIGH Z
MUXOUT
RFINA RFINB
PRESCALER P / P + 1 LOAD 6-BIT A COUNTER M3 M2 M1
ADF4106
Figure 1. Functional block diagram of the ADF4106.
Analog Dialogue 35-6 (2001)
Low phase noise allows it to work as a low-noise, fast-settling 1.5-GHz local oscillator
VDD VP
Phase-noise reduction (see page 4)
The synthesizer phase noise has a 10 logfPFD relationship. This means that for every doubling of the PFD frequency, there will be 3-dB degradation in the synthesizer phase noise. However, the output from the VCO will be divided down, and its phase noise obeys a 20 logX rule. So, for every doubling of X, there will be a gain of 6 dB in phase noise performance. If the PFD frequency is quadrupled as above, fVCO is divided by four to end up with the correct fOUT. Thus 6 dB will be lost due to the quadrupling of fPFD and 12 dB is gained due to the division by four. This results in an overall gain of 6 dB in phase-noise performance, using Figure 4a, compared to the use of the standard architecture. In this example, the resulting phase noise would be -94 dBc / Hz.
Reference spur reduction
RFOUT 100pF
16 6.2k 2 20pF VT
FREFIN
AVDD DV VP DD 2 1000pF 1000pF CP 8 REFIN 51 100pF
14 100pF 18 10 VCC RF OUT V940ME03
4.3k 1.5nF
ADF4106
GND 1, 3, 4, 5, 7, 8, 9, 11, 12, 13
SPI COMPATIBLE SERIAL BUS
CE CLK DATA LE RSET
MUXOUT
LOCK DETECT 100pF
RFINA 6 RFINB 5
CPGND
100pF
NOTE DECOUPLING CAPACITORS (0.1 F / 10pF) ON AVDD, DVDD, VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 3. The ADF4106 used to implement a 6.0-GHz local oscillator.
fREF fPFD
TCXO REFERENCE
R DIVIDER R
CHARGE PUMP
LOOP FILTER
X DIVIDER X fVCO
LOCAL OSCILLATOR OUTPUT TO MIXER
fOUT PLL SYNTHESIZER I.C. N DIVIDER N
Figure 4a. Architecture for improved lock time, phase noise, and reference spurs.
Analog Dialogue 35-6 (2001)
DIVIDER INPUT
DIVIDER OUTPUT
20 Log10X (dB)
Figure 4b. Comparing the output spectrum at fVCO and fOUT of Figure 4a.
VDD (3V) 7 15 16 6.2k 2 20pF VT VP (5V)
VCC (5V)
FREFIN
AVDD DV VP DD 2 1000pF 1000pF CP 8 REFIN 51 100pF
14 VCC
RFOUT
100pF 18
100pF
4, 6 VCC IN HMC362S8G 4 GND 8
100pF RFOUT
4.3k 1.5nF
V940ME03 GND 1, 3, 4, 5, 7, 8, 9, 11, 12, 13
ADF4106
100pF
SPI COMPATIBLE SERIAL BUS
CE CLK DATA LE RSET
CPGND AGND
MUXOUT
LOCK DETECT 100pF
RFINA 6 RFINB 5
100pF NOTE DECOUPLING CAPACITORS (0.1 F / 10pF) ON AVDD, DVDD, VP OF THE ADF4106 AND ON VCC OF THE V940ME03 HAVE BEEN OMITTED FROM THE DIAGRAM TO AID CLARITY.
Figure 5. Using the ADF4106 with an output divider to generate a 1.5-GHz local oscillator.
Shorter lock time
BANDWIDTH
The 0.35-µm BiCMOS fabrication process and careful application of RF design techniques permit the prescaler section of the ADF4106 to operate at up to 6.0 GHz with an input level of -10 dBm (referred to 50 ), guaranteed over the industrial temperature range (-40 to +85°C). Figure 6 shows a typical sensitivity plot for the ADF4106 in a TSSOP package at -40°C, +25°C, and +85°C. It can clearly be seen that performance to 6 GHz is well within the limits of the device with signals below -15 dBm.
RF INPUT POWER - dBm
Figure 6. ADF4106 sensitivity vs. frequency.
Analog Dialogue 35-6 (2001)
PHASE NOISE
Phase noise, a measure of the purity of the local oscillator signal, is the single most critical specification in the local oscillator section of radios-with a direct bearing on receiver sensitivity. It is the ratio to output carrier power of the noise power in a 1-Hz bandwidth at a given offset from the carrier. Expressed as a log ratio, the units of phase noise are dBc / Hz. Phase noise is typically measured with a spectrum analyzer.
ERROR DETECTOR CHARGE PUMP e(s) + Kd PFD - LOOP FILTER VCO
With this phase-noise figure of merit, an engineer can work out the total PLL phase noise for any given PFD frequency and RF output frequency. For example, consider generation of a local oscillator signal with frequencies from 1700 MHz to 1800 MHz and channel spacing of 200 kHz. Using equation (2), the close-in phase noise using the ADF4106 as the PLL synthesizer is
Z(s) Kv s fOUT
N FEEDBACK DIVIDER
ACKNOWLEDGEMENTS
A note of thanks to Bill Hunt for valuable editorial comments, and to Brendan Daly, who verified the circuits used. The author would also like to acknowledge all the ADI customers who have provided valuable feedback on this device.
References
This provides a figure of merit for the PLL Synthesizer circuit itself, irrespective of the noise contributed by PLL N value and PFD frequency, since these would be the same for any similar circuit being compared. For the ADF4106, this figure is -219 dBc / Hz, a 3-dB improvement on the ADF4113, which had been the best available integer-N synthesizer in terms of phase noise.
-130 PHASE NOISE - dBc / Hz
-150 ADF4113 -160 ADF4106 -170
-180 10k
1M FREQUENCY - Hz
Figure 8. ADF4106 phase noise vs. PFD frequency.
Analog Dialogue 35-6 (2001)
Winning the Battle Against Latch-up in CMOS Analog Switches
by Catherine Redmond (catherine.redmond@analog.com)
INTRODUCTION
This article will briefly describe the causes, mechanisms, and consequences of latch-up and discuss available prevention methods. Although our aim is to give an understanding of latch-up as it occurs in CMOS switches, similar principles apply to many other CMOS devices. Latch-up may be defined as the creation of a lowimpedance path between power supply rails as a result of triggering a parasitic device. In this condition, excessive current flow is possible, and a potentially destructive situation exists. After even a very short period of time in this condition, the device in which it occurs can be destroyed or weakened and potential damage can occur to other components in the system. Latch-up may be caused by a number of triggering factors, to be discussed below-including overvoltage spikes or transients, exceeding maximum ratings, and incorrect power sequencing.
When thus latched, and no longer dependent on the trigger source applied to the gate (G), a continual low-impedance path exists between anode and cathode. Since the triggering source need not be constant, it could simply be a spike or a glitch removing it will not turn off the SCR. As long as the current through the SCR is sufficiently large, it will remain in its latched state. If, however, the current can be reduced to a point where it falls below a holdingcurrent value, IH, the SCR switches off. Figure 1b shows the current-to-voltage transfer function for an SCR. In order to bring the device out of its conductive state, either the voltage applied across the SCR must be reduced to a value where each transistor turns off, or the current through the SCR must be reduced below its holding current. A CMOS switch channel effectively consists of PMOS and NMOS devices connected in parallel control signals to turn it off and on are applied via drivers. Since all these MOS devices are located close together on the die, it is possible that with appropriate excitation, parasitic SCR devices may conduct-a form of behavior possible with any CMOS circuit. Figure 2 illustrates a simplified cross section showing two CMOS structures, one PMOS and one NMOS these could be connected together as an inverter or as the switch channel. The parasitic transistors responsible for latch-up behavior, Q1 (vertical PNP) and Q2 (lateral NPN) are also shown.
P+ N+ Q2 RS P- SUBSTRATE N+ P+ Q1 P+ RW N-WELL N+
Cause
For an understanding of latch-up, it is desirable to briefly review the basics and understand the participating components. As already stated, latch-up occurs as a result of triggering a parasitic device- in effect an SCR (silicon controlled rectifier), a four-layer pnpn device formed by at least one pnp and at least one npn transistor connected as shown in Figure 1.
I A A P N G P N G Q1 NPN Q2 PNP LATCHED STATE
Figure 2. Cross-section of PMOS and NMOS devices, showing parasitic transistors Q1 and Q2. P- substrate is used in devices from the ADG7xx family of switches and multiplexers, while devices from ADG4xx and ADG5xx families use N+ substrate. From Figure 2, it can be seen that a reinterpretation of the silicon configuration shows that the inherent parasitic bipolar transistors, Q1 & Q2, produce the parasitic SCR structure discussed above (Figure 3).
VS FORWARD BLOCKING REGION
Figure 1. a) Transistor equivalent of an SCR. b) Current voltage characteristic of an SCR. An SCR is a normally off device in a "blocking state, " in which negligible current flows. Its behavior is similar to that of a forwardbiased diode, but conducts from anode, A, to cathode, K, only if a control signal is applied to the gate, G. In its normally off state, the SCR presents a high impedance path between supplies. When triggered into its conducting state as a result of excitation applied to the gate, the SCR is said to be "latched." It enters this state as a result of current from the gate injected into the base of Q2, which causes current flow in the base-emitter junction of Q1. Q1 turns on causing further current to be injected into base of Q2. This positive feedback condition ensures that both transistors saturate and the current flowing through each transistor ensures that the other remains in saturation.
GND / VSS
Figure 3. Rearrangement of the way we view the parasitic bipolars of Figure 2 shows an SCR structure.
Triggering mechanisms
Having described the architecture that makes latch-up possible, we now discuss the events that can trigger such behavior. SCR latch-up can occur through one of the following mechanisms. · Supply voltages exceeding the absolute maximum ratings. These ratings in the data sheet are an indication of the maximum voltage that can safely be applied to the switch. Anything in excess may result in breakdown of an internal junction and hence damage to the device. In addition, operation of the switch under conditions close to the maximum ratings may degrade long term reliability. It is important to note that these ratings apply at all
Analog Dialogue 35-05 (2001)
times, including when the switch is being powered on and off. The triggering mode could result from transients on supply rails. · Input / output pin voltage exceeding either supply rail by more than a diode drop. This could occur as a result of a fault on a channel or input-if a part of the system is powered on prior to the supplies being present at the switch (or similar CMOS components in the system). The powered part of the circuit would be sending signals to other devices in the design which may not be able to handle the voltage levels presented. The resulting voltage levels could exceed the maximum rating of the device and possibly result in latch-up. Again, this could occur as a result of spikes or glitches on input or output channels. · Poorly managed multiple power supplies. Switches that have multiple power supplies tend to be more susceptible to latch-up resulting from improper power supply sequencing. Such switches usually have two analog supplies, VDD and VSS, and a digital supply, VL. In some cases, when the digital supply is applied prior to the other supplies, it may be possible for maximum ratings to be exceeded and the device to enter a latch-up state. In general, for those devices that require an external digital supply, VL, we recommend that when power is being applied to and removed from the device, care should be taken to ensure the maximum ratings are not exceeded. When any of the triggering mechanisms described above occur, the parasitic SCR structure of Figure 1a may begin to conduct, producing a low impedance state between power supply rails. If there is no current limit mechanism on the supplies, excessive current will flow through this SCR structure and through the switch. This could destroy the switch and other components if allowed to persist. With high current levels, a device would not have to remain in a latch-up state for very long even very brief latch-up can result in permanent damage if current is not limited.
VL D VC VDD VDD
CMOS DEVICE
Figure 5. Addition of a Schottky diode from VL to VDD ensures maximum ratings are not exceeded. Where the addition of an extra component is not a viable option, due to cost or limited board space, switches are available that have been manufactured with a process that ensures that they are latchup proof. The process uses an insulating oxide layer (trench) between the NMOS and PMOS devices of each switch. This oxide layer is both horizontal and vertical and produces complete isolation between MOS devices, as shown in Figure 6.
Protection and prevention
But such a fate is not inevitable in CMOS circuitry. The simplest way of preventing latch-up occurring is to adhere to the absolute maximum ratings. If this is not always possible, there are other methods of designing a latch-up-proof system.
+5V 0V 1N914 VDD IC POWERED UP IC#1 ROUT OUTPUT IIN ~ 0 INPUT IB ~ 0 IC ~ 0 IC POWERED DOWN IDD ~ 0 IC#2 RSUB T R E N C H
P-CHANNEL
N-CHANNEL
BURIED OXIDE LAYER SUBSTRATE (BACKGATE)
Figure 6. Cross section of switch manufactured with trench processing. This eliminates the parasitic bipolar devices between transistors, resulting in a latch-up-proof switch. "Latch-up-proof" means that no matter what way the power is sequenced to the device, latchup cannot occur. Table 1 lists Analog Devices switches, multiplexers, and channel protectors that have such processing. Although all the devices listed are latch-up-proof, not all are designed to handle overvoltages outside the supply rails, as the table indicates. In addition to these latch-up proof switches, there are other devices that can tolerate underand overvoltages, with power applied, of +40 V / -25 V in excess of supplies and +55 V / -40 V with power not applied to the device.These devices are specifically designed to ensure that they can handle faults in the event of power-on or -off conditions. They also employ the insulating oxide layer to protect against latch-up. They are available for use either as multiplexers or as channel protectors.
RP-WELL
COMMON GROUND
DGND IDGND ~ 0
Figure 4. Addition of a diode in series with VDD prevents SCR triggering. Here are some options for protecting against and preventing latchup: Where it is possible for digital or analog inputs to exceed the V DD supply-either while power is being applied or during operation-the addition of a diode connected in series with VDD prevents base current from flowing, thus avoiding SCR triggering
Analog Dialogue 35-5 (2001)
The multiplexers use a structure having n-channel, p-channel, and n-channel MOSFETs in series (Figure 7) to provide both device- and signal-source protection in the event of an overvoltage or power loss. The multiplexer can withstand continuous overvoltage inputs from -40 V to +55 V. When one of the analog inputs or outputs exceeds the power supplies, one of its MOSFETs will switch off, the multiplexer input (or output) appears as an open circuit, and the output is clamped to within the supply rail, thereby preventing the overvoltage from damaging any circuitry following the multiplexer. This protects the multiplexer, the circuitry it drives, and the sensors or signal sources which drive the multiplexer. Figure 7 shows what happens on one channel of the ADG438F in the event of a positive overvoltage. Because the fault protection works regardless of the presence of supplies, the muxes are also ideal for use in applications where power sequencing cannot always be guaranteed to protect analog inputs (e.g., hotinsertion rack systems).
+55V OVERVOLTAGE n-CHANNEL MOSFET IS OFF VDD VSS Q1 Q2 Q3
three extra components per channel, plus the board space to accommodate them. A channel protector would be an equally effective but simpler solution in a single small package.
VDD VSS VD1 ADG465 VS1
VIN VIN VDD
VOUT VOUT
OUTPUT CLAMPED @ VDD - 1.5V
Figure 8. Channel protector clamps overvoltages to within power supply rail voltage and protects sensitive components. For example, a channel protector could be used in conjunction with an ADC, switch, multiplexer, or other device to ensure that all the channels are protected, both in the event of an over- or undervoltage, and a fault when the system is unpowered. These devices can withstand continuous voltage inputs from -40 V to +40 V. Because the channel protection works regardless of the presence of supplies, channel protectors are also ideal for use in applications where power sequencing cannot always be guaranteed to protect analog inputs. (A familiar example is hot-insertion rack systems.)
Figure 7. +55 V overvoltage applied to the input channel of ADG438F / ADG439F multiplexer in ON state. Similarly, channel protectors are used to protect sensitive components from voltage transients in the signal path whether or not the power supplies are present. They are built like the fault-protected muxes described above. When powered, the channel is always in the ON condition, but in the event of a fault, it clamps the output to within the supply rails, as shown in Figure 8. Channel protectors are generally placed in series with the signal path ahead of standard CMOS processed devices to ensure that potential faults can be tolerated without damage to components in the system. A common way of protecting a channel from potential faults, in either a powered or nonpowered condition, is to connect diodes and current limiting resistors between the channel and the supplies. While it is an effective solution, it requires
CONCLUSION
Inasmuch as no application can tolerate latch-up, it is necessary to be aware of its possibility, understand it, protect against it, and take measures to prevent it from happening. Given some thought and the use of available methods and components, it is indeed possible to assemble a latch-up-proof system. While discrete solutions-such as diodes-could be used, devices like latch-upproof switches, fault protected multiplexers, and channel protectors may provide a simpler, more compact, and more generally suitable solution, resulting in a robust system likely to give fewer problems in the field. b
Table 1. Latch-up proof Analog Devices switches, multiplexers, and channel protectors.
Part Number ADG431A ADG432A ADG433A ADG441 ADG442 ADG444 ADG511A ADG512A ADG513A ADG438F ADG508F ADG439F ADG509F ADG465 ADG466 ADG467
Latch-up Proof Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes Yes
Over / Under-Voltage Capability No No No No No No No No No Yes Yes Yes Yes Yes Yes Yes
Package1 R-16 R-16 R-16 R-16, N-16 R-16, N-16 R-16, N-16 R-16 R-16 R-16 R-16, N-16 RN-16, RW-16, N-16 R-16, N-16 RN-16, RW-16, N-16 RT-6, RM-8 RM-8, R-8, N-8 RS-20, R-18
Analog Dialogue 35-5 (2001)
Avoiding Op Amp Instability Problems In Single-Supply Applications
by Charles Kitchin
Although it is advantageous to implement op amp circuits with balanced dual supplies, there are many practical applications where, for energy conservation or other reasons, single-supply operation is necessary or desirable. For example, battery power, in automotive and marine equipment, provides only a single polarity. Even linepowered equipment, such as computers, may have only a singlepolarity built-in supply, furnishing 5 V dc or 12 V dc for the system. In processing analog signals, a common feature of single-supply operation is the need for additional components in each stage for appropriate signal biasing. If this is not carefully thought through and executed, instability and other problems may be encountered.
COUT VOUT RLOAD R2
STAR GROUND
Common Problems with Resistor Biasing
Decoupling the Biasing Network from the Supply
COUT VOUT RLOAD
Figure 2. A decoupled single-supply op amp biasing circuit.
Analog Dialogue 35-2 (2001)