FlexRay Controller MB88121B DESCRIPTION MB88121B FlexRay* co

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FlexRay Controller MB88121B DESCRIPTION MB88121B FlexRay* co

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DS04-22117-1E
FlexRay Controller MB88121B
DESCRIPTION
MB88121B FlexRay* controller developed vehicles that built-in FlexRay interface. FlexRay controller complies with version FlexRay consortium protocol specification able controlled from parallel interface serial interface with host. MB88121B contains PLL, connects crystal oscillation circuit (4/5/8/10 MHz), generates FlexRay operation clock Also, possible input FlexRay operation clock externaly. FlexRay registered trademark Daimler Chrysler
FEATURES
FlexRay specifications Supports version FlexRay protocol specifications Provides maximum message buffers Kbytes message When data section bytes, Maximum message buffers When data section bytes, Maximum message buffers Provides variable length message buffers Each message buffer configured receive buffer, transmit buffer, part receive FIFO Host access message buffers input buffer output buffer Input buffer: Stores message transferred message Output buffer: Stores message that been read from message Filtering slot counter, cycle counter, channel Each channel maximum bitrate Mbps Maskable interrupts MHz/5 MHz/8 MHz/10 external oscillator circuit input Supports external clock input interface 16-bit non-multiplexed parallel interface mode 16-bit multiplexed parallel interface mode interface mode transfer request signal output Single power supply Single power supply
Copyright©2008 FUJITSU MICROELECTRONICS LIMITED rights reserved 2008.6
MB88121B
BLOCK DIAGRAM
RXDA TXDA, TXENA RXDB TXDB, TXENB
FlexRay Channel Protocol Controller (PRT) FlexRay Channel Protocol Controller (PRT)
Transient Buffer
(TBF)
Transient Buffer
(TBF)
Global Time Unit (GTU) System Universal Control (SUC)
BCLK DMA_REQ INT4 INT0 MDE2 MDE0 E-RAY
Interface (CIF)
Input Buffer
(IBF)
Frame Symbol Processing (FSP)
Network Management (NEM)
Message Handler
Output Buffer
(OBF)
Message
Interrupt Control (INT)
Oscillator Circuit
Selector
SCLK
MB88121B
DS04-22117-1E
MB88121B
FUNCTION
Table functions each mode 16-bit Multiplexed Parallel Interface Mode DMA_REQ (Continued) MDE2 MDE1 MDE0 ALE/AS INT2 RXDB TXENB TXDB BCLK 16-bit Non-multiplexed Parallel Interface Mode CYCS0 STPWT INT0 TXDA TXENA RXDA CYCS Interface Mode
DS04-22117-1E
MB88121B
(Continued) AD10 INT2 INT3 INT4 MBSU_TX1 MBSU_RX1 MBSU_TX2 MBSU_RX2 MDS2 MDS1 MDS0 INT2 INT3 INT4 16-bit Multiplexed Parallel Interface Mode 16-bit Non-multiplexed Parallel Interface Mode INT1 MBSU_TX1 MBSU_RX1 MBSU_TX2 MBSU_RX2 Interface Mode
DS04-22117-1E
MB88121B
FUNCTIONAL DESCRIPTION EACH BLOCK
Interface (CIF Interface) interface connects host FlexRay controller (E-Ray). Input Buffer (IBF Input Buffer) Used write message buffers message RAM. host write header section data section from input buffer specific message buffer. message handler transfers data from input buffer selected message buffer message RAM. Output Buffer (OBF Output Buffer) Used read from message buffers message RAM. message handler transfers data from selected message buffer output buffer. Once data transfer complete, host read header section data section message buffer that transferred from output buffer. Message Handler (MHD Message Handler) message handler controls data transfers between following components. Input/output buffer message transient storage buffer FlexRay protocol controllers message Message (MRAM Message RAM) message composed single-port that able hold configuration data built-in FlexRay message buffers (max. 128). Transient Buffer (TBF Transient Buffer RAM) Stores data sections messages. FlexRay Channel Protocol Controller (PRT FlexRay Channel Protocol Controller) FlexRay channel protocol controller composed shift register FlexRay protocol FSM. protocol controller provides following functions. Checking controlling timings Receiving transmitting FlexRay frames symbols Checking header Generating checking frame Connecting driver addition, protocol controller block connected following blocks. Physical layer (bus driver) Transient storage buffer Message handler Global time unit System universal control Frame symbol processing Network management Interrupt control DS04-22117-1E
MB88121B
Global Time Unit (GTU Global Time Unit) global time unit provides following functions. Generating microticks Generating macroticks Fault tolerant clock synchronization using Falgorithm Rate correction Offset correction Cycle counter Dynamic segment (microslot) timing control Support external clock correction System Universal Control (SUC System Universal Control) system universal control controls following functions. Configuration Wakeup Startup Normal operation Passive operation Monitor mode Frame Symbol Processing (FSP Frame Symbol Processing) Frame symbol processing controls following function. Checking that timing frames symbols correct Testing syntactic semantic validity received frames Setting slot status flag Network Management (NEM Network Management) Sets handling network management vector Interrupt Control (INT Interrupt Control) following functions available controlling interrupts. Provision error interrupt flags Controlling enabling/disabling interrupt sources Controlling allocation interrupt sources interrupt lines module Enabling/disabling interrupt lines module Managing interrupt timers Halting capturing watch times
DS04-22117-1E
MB88121B
ASSIGNMENT
host interface mode selected setting operation mode selection (MD2-0) extension mode selection (MDE2-0) MB88121B. Interface mode ways, 16-bit non-multiplexed parallel mode, 16-bit multiplexed parallel mode, interface mode. assignments each mode shown below. 16-bit Non-multiplexed Parallel Interface Mode (TOP VIEW)
INT1
DMA_REQ MDE0 MDE1 MDE2 TXDB TXENB RXDB INT2
DS04-22117-1E
CYCS0 STPWT INT0 TXDA TXENA RXDA CYCS BCLK
(FPT-64P-M03)
MB88121B
16-bit Multiplexed Parallel Interface Mode (TOP VIEW)
MBSU_RX2 MBSU_TX2
MBSU_RX1 MBSU_TX1 INT4 INT3 INT2 INT1
AD10
DMA_REQ MDE0 MDE1 MDE2 TXDB TXENB RXDB ALE/AS
CYCS0 STPWT INT0 TXDA TXENA RXDA CYCS BCLK
(FPT-64P-M03)
DS04-22117-1E
MB88121B
Interface Mode (TOP VIEW)
MBSU_RX2 MBSU_TX2
MBSU_RX1 MBSU_TX1
INT1
MDS2 MDS1 MDS0
INT2 INT3 INT4
MDE0 MDE1 MDE2 TXDB TXENB RXDB
CYCS0 STPWT INT0 TXDA TXENA RXDA CYCS
(FPT-64P-M03)
DS04-22117-1E
MB88121B
DESCRIPTIONS
1,17, 16,32,48 name pins power supply pins. Connect power supply pins same potential. Power supply stabilization capacitor pin. Connect ceramic capacitor with capacitance more. Oscillator Oscillator pin. Also used external clock input pin. Operation mode selection inputs Mode 16-bit parallel Serial Description
Refer MODE SETTING" details. Note Operation guaranteed settings other than those listed above used. External reset input. device initialized when this "L". Note Always this when power supply connected, maintain until oscillation stabilization wait time elapsed. Indicates start dynamic segment. dynamic segment started pulse output when SDSE Debug Support Register (DBGS) "1". This fixed when SDSE Debug Support Register "0". Indicates start cycle Cycle started pulse output when CYCS0E Debug Support Register (DBGS) "1". This fixed when CYCS0E Debug Support Register "0". Note Cycle does output pulse release from reset. Stop watch trigger input. Functions stop watch trigger specified setting Stop Watch Register (STPW1). Interrupt output. This changes indicate occurrence interrupt. This interrupt enabled disabled using EINT0 Interrupt Line Enable Register (ILE). Data output ch.A. Operation enable output ch.A. Transmit data output enabled when this "L". This reset. Data input ch.A. Indicates start cycle. cycle started pulse output when CYCSE Debug Support Register (DBGS) "1". This fixed when CYCSE Debug Support Register "0". clock input. interface mode, this high impedance state. device with this left open fixed "L". (Continued)
CYCS0
STPWT
INT0 TXDA TXENA RXDA CYCS BCLK
DS04-22117-1E
MB88121B
name
Description Chip select input. chip selected when this "L". Read enable input. register value output pins when this "L". when "L". interface mode, this high impedance state. device with this left open, fixed "L". Write enable input. data pins written register when this "L". when "L". interface mode, this high impedance state. device with this left open, fixed "L". 16-bit non-multiplexed parallel interface mode, this interrupt output Timer Timer This changes indicate occurrence Interrupt Interrupt Timer Timer interrupt occurs when TINTE0 TINTE1 Interrupt Register (INT) "1". Note output state this undefined when power turned FR460 mode 16-bit multiplexed parallel interface mode, this address strobe input. This signal active low. Note output state this undefined when power turned 16FX mode 16-bit multiplexed parallel interface mode, this address latch enable input. This active high. Note output state this undefined when power turned interface mode, this high impedance state. device with this left open, fixed "L". Note output state this undefined when power turned Indicates start macrotick. macrotick started pulse output when Debug Support Register (DBGS) "1". This fixed when Debug Support Register "0". Data input ch.B. Operation enable output ch.B. Transmit data output enabled when this "L". This reset. Data output ch.B. Ready output. device ready state when this "H". interface mode, this high impedance state. device with this left open, fixed "L". Extended mode selection inputs. transfer request output. high impedance state reset. This output enabled DMAOE Support Register (DMAS). interface mode, this high impedance state. device with this left open, fixed "L". Interrupt output. This changes indicate occurrence interrupt. This interrupt enabled disabled using EINT1 Interrupt Line Enable Register (ILE). (Continued)
INT2
RXDB TXENB TXDB MDE2 MDE0 DMA_REQ
INT1
DS04-22117-1E
MB88121B
name
Description 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this Interrupt output. This changes indicate occurrence interrupt. TINTE0 Interrupt Register (INT) "1", output when Timer interrupt occurs. TINTE0 Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned interface mode, this high impedance state. device with this left open, fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this Interrupt output. This changes indicate occurrence interrupt. TINTE1 Interrupt Register (INT) "1", output when Timer interrupt occurs. TINTE1 Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned interface mode, this high impedance state. device with this left open, fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this low-voltage detection interrupt output. This changes indicate occurrence interrupt. LVD5E LVD18E Interrupt Register (INT) "1", this changes when LVD5 LVD18 Interrupt Register (INT) changes "1". LVD5E LVD18E bits Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned interface mode, this high impedance state. device with this left open, fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned
INT2
INT3
INT4
16-bit multiplexed parallel interface mode interface mode, this indicates changes message buffer status ch.A transmit buffer. MBSUE Debug MBSU_TX1 Support Register (DBGS) "1", this changes when message buffer updated. MBSUE Debug Support Register (DBGS) "0", this fixed "L". Note output state this undefined when power turned (Continued)
DS04-22117-1E
MB88121B
name
Description 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned
16-bit multiplexed parallel interface mode interface mode, this indicates changes message buffer status ch.A reception buffer. MBSUE Debug Support Register (DBGS) "1", this changes MBSU_RX1 when message buffer updated. MBSUE Debug Support Register (DBGS) "0", this fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, this address input. 16-bit multiplexed parallel interface mode, this high impedance state. device with this left open, fixed "L". interface mode, this serial clock input. operation mode determined MDS1 MDS0 settings. 16-bit non-multiplexed parallel interface mode, this address input. 16-bit multiplexed parallel interface mode, this high impedance state. device with this left open, fixed "L". interface mode, this serial data input. Input serial data this synchronously with serial clock according operation mode. 16-bit non-multiplexed parallel interface mode, this address input. 16-bit multiplexed parallel interface mode, this high impedance state. device with this left open, fixed "L". interface mode, this serial data output. When "L", serial data output synchronously with serial clock according operation mode. When "H", this high impedance state. 16-bit non-multiplexed parallel interface mode, this address input. 16-bit multiplexed parallel interface mode interface mode, this high impedance state. device with this left open, fixed "L". 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned
16-bit multiplexed parallel interface mode interface mode, this indicates changes message buffer status ch.B transmit buffer. MBSUE Debug Support Register (DBGS) "1", this changes MBSU_TX2 when message buffer updated. MBSUE Debug Support Register (DBGS) "0", this fixed "L". Note output state this undefined when power turned (Continued)
DS04-22117-1E
MB88121B
name
Description 16-bit non-multiplexed parallel interface mode, this address input. Note output state this undefined when power turned
16-bit multiplexed parallel interface mode interface mode, this indicates changes message buffer status ch.B reception buffer. MBSUE Debug Support Register (DBGS) "1", this changes MBSU_RX2 when message buffer updated. MBSUE Debug Support Register (DBGS) "0", this fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, these pins data pins. D15, 16-bit multiplexed parallel interface mode, these pins data pins. This data effect operation during address cycle. interface mode, these pins high impedance state. device with this left open, fixed "L". 16-bit non-multiplexed parallel interface mode, these pins data pins. 16-bit multiplexed parallel interface mode, these pins data pins. This data effect operation during address cycle. interface mode, these pins high impedance state. device with these pins left open, fixed "L". 16-bit non-multiplexed parallel interface mode, these pins data pins. 16-bit multiplexed parallel interface mode, these pins address/data pins. interface mode, these pins determine operation mode. 16-bit non-multiplexed parallel interface mode, these pins data pins. 16-bit multiplexed parallel interface mode, these pins address/data pins. interface mode, these pins high impedance state. device with these pins left open, fixed "L". 16-bit non-multiplexed parallel interface mode, this data pin. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this address/data pin. Note output state this undefined when power turned interface mode, this Interrupt output. This changes indicate occurrence interrupt. TINTE0 Interrupt Register (INT) "1", output when timer interrupt occurs. TINTE0 Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned (Continued)
46,47
AD10 MDS2 MDS0 AD7, INT2
DS04-22117-1E
MB88121B
(Continued) name INT3
Description 16-bit non-multiplexed parallel interface mode, this data pin. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this address/data pin. Note output state this undefined when power turned interface mode, this Interrupt output. This changes indicate occurrence interrupt. TINTE1 Interrupt Register (INT) "1", output when timer interrupt occurs. TINTE1 Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, this data pin. Note output state this undefined when power turned 16-bit multiplexed parallel interface mode, this address/data pin. Note output state this undefined when power turned interface mode, this low-voltage detection interrupt output. This changes indicate occurrence interrupt. LVD5E LVD18E Interrupt Register (INT) LVD5 LVD18 Interrupt Register (INT) "1", this changes "H". LVD5E LVD18E Interrupt Register (INT) "0", this output fixed "L". Note output state this undefined when power turned 16-bit non-multiplexed parallel interface mode, these pins data pins. Note output state this undefined when power turned
INT4
16-bit multiplexed parallel interface mode, these pins address/data pins. Note output state this undefined when power turned interface mode, these pins high impedance state. device with these pins left open, fixed "L".
DS04-22117-1E
MB88121B
HANDLING DEVICES
When turning power supply Always assert settings initialization reset using immediately after power turned Furthermore, order ensure oscillation stabilization wait time oscillator circuit immediately after power turned keep level input connected stabilization wait time required oscillator circuit. Undefined outputs power-on When power turned state input/output pins remain undefined until power supply voltage reaches recommended operating range. External clock input when power turned When power turned always keep external clock input connected until oscillation stabilization wait time released. Preventing latch-up Latch-up phenomenon that occur voltage excess maximum rated value applied between pins input pins, output pins, pins. When latch-up occurs, power supply current increases dramatically components burned out. Therefore, ensure that operating voltages exceed absolute maximum rated values when device being used. Power supply pins This device multiple pins multiple pins. Ensure that these pins connected power supply ground. Furthermore, impedance connections between power supply source pins pins device ensure that voltage differences occur. Handling unused pins unused input pins left unconnected, malfunctions occur device permanently damaged latch-up. Handle unused input input/output pins connecting them pull-up pull-down resistance more. Leave unused output pins unconnected. Mode pins (MD0, MD1, MD2, MDE0, MDE1, MDE2) Connect mode pins directly pins prevent device from entering wrong mode noise these pins. addition, keep length pattern printed circuit board between mode pins pins short possible. Notes using external clock When external clock used, supply with inverted clock.
DS04-22117-1E
MB88121B
FlexRay controller
Notes when clock selected clock input stops while clock selected, microcontroller continue operate using self-oscillations. However, microcontroller guaranteed operate under these conditions.
DS04-22117-1E
MB88121B
NOISE PREVENTION
Power supply pins addition capacitor that serves stabilize power supply, recommended that capacitors less fitted near device (approximately each power supply pins measure reduce unwanted radiation noise. Furthermore, recommended that pattern beneath device made into solid ground plane, that area ground plane increased much possible, that ground wire traces made thick possible, these effective means reducing unwanted radiation.
Approx.
FlexRay controller
stabilization
noise prevention
there inductance between power supply device, attach capacitors directly next power supply pins device. Furthermore, recommended that inductance placed near device (approximately mm).
Approx.
FlexRay controller
DS04-22117-1E
MB88121B
ELECTRICAL CHARACTERISTICS
Absolute Maximum Ratings
Parameter Power supply voltage*1 Input voltage*1 Output voltage*
Symbol IOLAV IOLAV IOHAV IOHAV TSTG
Rating
Unit
Remark
level maximum output current level average output current level maximum total output current level average total output current level maximum output current level average output current level maximum total output current level average total output current Power consumption Storage temperature parameter based must exceed
maximum output current defined peak value single pin. average output current specifies mean value current flowing through corresponding pins over period average total output current specifies mean value currents flowing through corresponding pins over period
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
DS04-22117-1E
MB88121B
Recommended Operating Conditions
Parameter Power supply voltage Symbol Condition operating operating ceramic capacitor capacitor with similar frequency characteristics. capacitors with larger capacitance than smoothing capacitors pins. Value unit
Smoothing capacitor
(within tolerance 50%)
Operating temperature
WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their representatives beforehand.
DS04-22117-1E
MB88121B
Characteristics
(VCC (VCC Parameter Symbol Pins other than level input voltage level output voltage level output voltage Power supply current Pins other than Condition Value Under operating conditions Unit Remark
level input voltage
With hysteresis
DS04-22117-1E
MB88121B
Characteristics
Clock Timing (VCC (VCC Parameter Symbol Condition Value Input clock cycle width PWH, Input clock rise time fall time Clock Timing
Unit
Remark Oscillator circuit external clock) When using external clock, duty ratio guide. When using external clock
Clock frequency Clock cycle time
tCR,
Clock Input Connection Circuit Using crystal oscillator ceramic oscillator
FlexRey controller
DS04-22117-1E
MB88121B
16-bit Non-multiplexed Parallel Interface Mode (VCC (VCC Parameter clock cycle BCLK BCLK pulse width BCLK pulse width System clock cycle SCLK SCLK pulse width SCLK pulse width setup time hold time Address setup time Address hold time setup time hold time Data output delay time Data output hold time* setup time hold time Data setup time Data hold time output delay time output maintain time Valid time Symbol tBCYC tBCLCH tBCHCL tSCYC tSCLCH tSCHCL tCLCS tCLCO tCLAS tCLAH tCLRL tCLRH tRLDV tRHDX tCHDX tCLWL tCLWH tCHDV tCLDV tRDYS tRDYH tRSTL Condition Value 31.25 18.0 13.0 14.0 14.0 18.0 200.0 19.0 30.0 18.5 18.5 15.4 25.4 Unit
timing with which signal faster than which signal "H", value tCHDX applied data output hold time, otherwise value tRHDX applied. Reset
tRSTL
System Clock
tSCYC SCLK tSCHCL tSCLCH
DS04-22117-1E
MB88121B
FR360 Interface Mode
tBCYC BCLK tBCHCL tBCLCH tCLCS tCLCO
tCLRL
tCLAS
tCLAH
tCLRH tRLDV tRHDX
tCHDX
tCLWL
tCLWH tCLDV
tCHDV tRDYH tRDYS
FR460 Interface Mode
tBCYC BCLK tBCHCL tBCLCH tCLCS tCLAS tCLRL tRLDV tRHDX tCLWL tCLDV tCHDV tRDYH tRDYS tCLAH tCLCO
tCLRH
tCHDX
tCLWH
DS04-22117-1E
MB88121B
16-bit Multiplexed Parallel Interface Mode (VCC (VCC Parameter clock cycle BCYC BCYC pulse width BCYC pulse width System clock cycle SCYC SCYC pulse width SCYC pulse width setup time hold time Address setup time Address hold time Address strobe latch setup time Address strobe latch width setup time hold time Data output delay time Data output hold time* setup time hold time Data setup time Data hold time output delay time output maintain time Symbol tBCYC tBCLCH tBCHCL tSCYC tSCLCH tSCHCL tCLCS tCLCO tAHAS tAHAH tCLAS tAHAL tCLRL tCLRH tRLDV tRHDX tCHDX tCLWL tCLWH tCHDV tCLDV tRDYS tRDYH Condition Value 31.25 18.0 19.0 30.0 18.5 18.5 15.4 25.4 Unit
timing with which signal faster than which signal "H", value tCHDX applied data output hold time, otherwise value tRHDX applied.
DS04-22117-1E
MB88121B
FR460 Interface Mode
tBCYC BCLK tBCHCL tBCLCH tCLCS tAHAL tCLAS tCLRL tAHAS D11, AD10 tCLWL tAHAS D11, AD10 tCHDV tRDYH tRDYS tAHAH tCLDV tCLWH tAHAH tRLDV tCLCO
tCLRH tRHDX
tCHDX
DS04-22117-1E
MB88121B
16FX Interface Mode
tBCYC BCLK tBCHCL tBCLCH tCLCS tCLCO
tCLAS tAHAL tCLRL tRLDV tAHAS tCLWL tCLWH tAHAH tAHAS D11, AD10 tCHDV tRDYH tRDYS tCLDV tAHAH tCLRH
tCHDX tRHDX
DS04-22117-1E
MB88121B
Interface Mode interface mode (MDS1 MDS0 (VCC (VCC Parameter clock cycle pulse width pulse width settle delay settle delay setup time hold time setup time hold time high impedance delay recovery time Symbol tSKCYC tSKHSL tSKLSH tCLSV tSLSV tSHSS tSHSH tSHCSS tSLCSH tCHSZ tCSHSH Condition Value 6trp* Unit
clock cycle FlexRay RAM.
tCLSV tSHCSS tSKCYC tSKHSL tSKLSH tSLSV tCHSZ tSLCSH
tCSHSH
tSHSS tSHSH
DS04-22117-1E
MB88121B
interface mode (MDS1 MDS0 (VCC (VCC Parameter cycle pulse width pulse width settle delay setup time hold time setup time hold time high impedance delay recovery time Symbol tSKCYC tSKHSL tSKLSH tSHSV tSLSS tSLSH tSHCSS tSLCSH tCHSZ tCSHSH Condition Value 6trp* Unit
clock cycle FlexRay RAM.
tSHCSS tSKCYC tSKHSL tSKLSH tCHSZ tSHSV tCSHSH tSLCSH
tSLSS tSLSH
DS04-22117-1E
MB88121B
interface mode (MDS1 MDS0 (VCC (VCC Parameter cycle pulse width pulse width settle delay settle delay setup time hold time setup time hold time high impedance delay recovery time Symbol tSKCYC tSKHSL tSKLSH tCLSV tSHSV tSLSS tSLSH tSLCSS tSHCSH tCHSZ tCSHSH Condition Value 6trp* Unit
clock cycle FlexRay RAM.
tCLSV tSLCSS tCSHSH tSKCYC tSKHSL tSKLSH tSHSV tCHSZ tSHCSH
tSLSS tSLSH
DS04-22117-1E
MB88121B
interface mode (MDS1 MDS0 (VCC (VCC Parameter cycle pulse width pulse width settle delay setup time hold time setup time hold time high impedance delay recovery time clock cycle FlexRay RAM. Symbol tSKCYC tSKHSL tSKLSH tSLSV tSHSS tSHSH tSLCSS tSHCSH tCHSZ tCSHSH Condition Value 6trp* Unit
tSLCSS tSKCYC tSKLSH tSKHSL tCHSZ tSLSV tCSHSH tSHCSH
tSHSS tSHSH
DS04-22117-1E
MB88121B
SYSTEM DESCRIPTION
Address Symbol Name Initial Value Access Customer registers 0000H 0004H 0008H 000CH Special registers 0010H 0014H 0018H 001CH 0020H 0024H 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 007CH 0080H 0084H 0088H 008CH 0090H 0094H EILS SILS EIES EIER SIES SIER STPW1 STPW2 Reserved (Write-prohibited) Reserved (Write-prohibited) Reserved Lock Register Error Interrupt Register Status Interrupt Register Error Interrupt Line Select Register Status Interrupt Line Select Register Error Interrupt Enable Register (set) Error Interrupt Enable Register (reset) Status Interrupt Enable Register (set) Status Interrupt Enable Register (reset) Interrupt Line Enable Register Timer Configuration Register Timer Configuration Register Stop Watch Register Stop Watch Register Reserved 00000300H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 0303FFFFH 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00020000H 00000000H 00000000H 00000000H CCNT DBGS DMAS Version Information Register Clock Control Register Debug Support Register Support Register Interrupt Register 043079FFH 00000000H 00000000H 00000000H
Interrupt-related registers
Communication controller (CC) control registers SUCC1 SUCC2 SUCC3 NEMC PRTC1 PRTC2 Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register 0C401000H 01000504H 00000011H 00000000H 084C0633H 0F2D0A0EH (Continued) DS04-22117-1E
MB88121B
Address 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H 00C8H 00CCH 00FCH 0100H 0104H 0108H 010CH 0110H 0114H 0118H 011CH 0120H 0124H 0128H 012CH 0130H 0168H 016CH 0170H 01A8H
Symbol MHDC GTUC1 GTUC2 GTUC3 GTUC4 GTUC5 GTUC6 GTUC7 GTUC8 GTUC9 GTUC10 GTUC11
Name Configuration Register Reserved Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Configuration Register Reserved
Initial Value 00000000H 00000000H 00000280H 0002000AH 02020000H 00080007H 0E000000H 00020000H 00020004H 00000002H 00000101H 00020005H 00000000H 00000000H
Access
Communication controller (CC) status registers CCSV CCEV MTCCV SWNIT ESIDn OSIDn Status Vector Register Error Vector Register Reserved Slot Counter Value Register Macrotick Cycle Counter Value Register Rate Correction Value Register Offset Correction Value Register Sync Frame Status Register Symbol Window Status Register Aggregated Channel Status Register Reserved Even Cycle Sync Frame Register Reserved Cycle Sync Frame Register 00104000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H (Continued) DS04-22117-1E
MB88121B
Address 01ACH 01B0H 01B8H 01BCH 02FCH 0300H 0304H 0308H 030CH 0310H 0314H 0318H 031CH 0320H 0324H 0328H 032CH 0330H 0334H 0338H 033CH 0340H 0344H 0348H 034CH 0350H 03ECH 03F0H 03F4H 03F8H 03FCH
Symbol NMVn Reserved
Name
Initial Value 00000000H 00000000H
Access
Network Management Registers
Reserved
00000000H
Message buffer control registers FRFM MHDS LDTS MHDF TXRQ1 TXRQ2 TXRQ3 TXRQ4 NDAT1 NDAT2 NDAT3 NDAT4 MBSC1 MBSC2 MBSC3 MBSC4 Message Configuration Register FIFO Rejection Filter Register FIFO Rejection Filter Mask Register FIFO Critical Level Register Message Handler Status Register Last Dynamic Transmit Slot Register FIFO Status Register Message Handler Constraints Flags Register Transmission Request Register Transmission Request Register Transmission Request Register Transmission Request Register Data Register Data Register Data Register Data Register Message Buffer Status Changed Register Message Buffer Status Changed Register Message Buffer Status Changed Register Message Buffer Status Changed Register Reserved 01800000H 01800000H 00000000H 00000080H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H
Message buffer status registers
Identification registers CREL ENDN Core Release Register Endian Register Reserved 07260412H 87654321H 00000000H (Continued) DS04-22117-1E
MB88121B
(Continued) Address Input buffers 0400H 04FCH 0500H 0504H 0508H 050CH 0510H 0514H 0518H 05FCH Output buffers 0600H 06FCH 0700H 0704H 0708H 070CH 0710H 0714H 0718H 07FCH RDDSn RDHS1 RDHS2 RDHS3 OBCM OBCR Read Data Section Registers Read Header Section Register Read Header Section Register Read Header Section Register Message Buffer Status Register Output Buffer Command Mask Register Output Buffer Command Request Register Reserved 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H WRDSn WRHS1 WRHS2 WRHS3 IBCM IBCR Write Data Section Registers Write Header Section Register Write Header Section Register Write Header Section Register Reserved Input Buffer Command Mask Register Input Buffer Command Request Register Reserved 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H 00000000H Symbol Name Initial Value Access
DS04-22117-1E
MB88121B
Host Interface
16-bit non-multiplexed parallel interface mode
Host
A[10:0]
MB88121B
A[10:0]
D[15:0]
D[15:0]
BCLK DMA_REQ INT0 INT2
BCLK DMA_REQ INT0 INT2 MD[2:0] MDE[2:0]
FlexRay Physical LayerA/Bch
MD[2:0] MDE[2:0]
square wave input Reset
DS04-22117-1E
MB88121B
16-bit multiplexed parallel interface mode
Host
AD[10:0]
MB88121B
AD[10:0]
D[15:11] BCLK ALE/AS DMA_REQ INT0 INT4
D[15:11] BCLK ALE/AS DMA_REQ INT0 INT4 MD[2:0] MDE[2:0] MD[2:0] MDE[2:0]
FlexRay Physical LayerA/Bch
square wave input Reset
DS04-22117-1E
MB88121B
interface mode
Host
MB88121B
MD[2:0] MDE[2:0] MDS[2:0]
FlexRay
Physical LayerA/Bch
MD[2:0] MDE[2:0] interface mode setting
INT0 INT4
INT0 INT4
square wave input Reset
DS04-22117-1E
MB88121B
MODE SETTING
setting bits selects host interface sets mode.
Host Interface Mode Selection
Interface mode 16-bit non-multiplexed parallel interface 16-bit multiplexed parallel interface Serial interface MDE2 MDE1 MDE0 Mode setting FR460 FR360 FR460 16FX
Refer Serial interface frequency selection", Serial interface type selection", interface mode settings".
Serial Interface Frequency Selection
these accordance with external input frequency when serial interface operating. MDE2 MDE1 Frequency
Serial Interface Type Selection
MDE0 Note MD[2:0] Type interface mode Reserved
Interface Mode Setting
MDS2 MDS1 MDS0 Setting MDS2 Serial data transfer direction Transferred from least significant Transferred from most significant MDS1 clock polarity Active clock selection Active clock selection MDS0 clock phase Data sampling even clock edges Data sampling clock edges
Note MD[2:0] 110, MDE0 DS04-22117-1E
MB88121B
TEST MODE OUTPUT SIGNAL
Debug Support Signal
FlexRay timing signal outputs HIGH corresponding pins duration clock cycle when output enabled using Debug Support Register (DBGS). CYCS (Cycle start) signal Outputs start timing signal communication cycles 63). (Macrotick start) signal Macrotick start timing signal (Start Dynamic Segment) signal Dynamic segment start timing signal CYCS0 (Cycle Start signal Cycle Start signal part CYCS signal. Whereas CYCS signal indicates start cycles (cycle 63), CYCS0 indicates CYCS cycle timing therefore same.
Message Buffer Update Signal
FlexRay message buffer status update signal output HIGH corresponding duration clock cycle when output enabled using Debug Support Register (DBGS). This only valid 16-bit multiplexed parallel interface mode interface mode. MBSU_TX1 (Message Buffer Status update Transmission Channel Transmission signal channel MBSU_RX1 (Message Buffer Status update Reception Channel Reception signal channel MBSU_TX2 (Message Buffer Status update Transmission Channel Transmission signal channel MBSU_RX2 (Message Buffer Status update Reception Channel Reception signal channel
DS04-22117-1E
MB88121B
CUSTOMER REGISTERS
Version Information Register (VER: Version Information)
version information register indicates each revision number this LSI.
Address
VID[7:0] INV[7:0]
CIV[7:0]
ECR[7:0]
Initial Value
0000H
043079FFH
bit7 bit0 ECR[7:0] 0xFF FlexRay revision MB88121B
bit15 bit8 CIV[7:0] 0x79 bit23 bit16 INV[7:0] 0x30 identification number MB88121B Revision number MB88121B
Read only
bit31 bit24 VID[7:0] 0x04
JEDEC MB88121B
bit31 bit24
name JEDEC code Revision
Function Specifies Fujitsu JEDEC code. MB88121B, reading these bits returns 0x04. Writing these bits effect operation. Represents revision number LSI. MB88121B, reading these bits returns 0x30. Writing these bits effect operation.
bit23 bit16
bit15 bit8
Represents identification number LSI. This lowest digits number hexadecimal notation. identification number MB88121B, reading these bits returns 0x79. Writing these bits effect operation. FlexRay identification Represents FlexRay identification number. MB88121B, reading these bits returns 0xFF. these bits return 0xFF, information stored CREL register. Refer CREL register revision number. Writing these bits effect operation.
bit7 bit0
DS04-22117-1E
MB88121B
Clock Control Register (CCNT: Clock Control)
clock control register (CCNT) configures clock supplied FlexRay controller.
Address
0004H SDIV[1:0] STOP RCLK PMUL[1:0] SSEL
Initial Value
00000000H
bit0 bit1 SSEL bit3, bit2 [PMUL[1:0] bit4 RCLK bit5 STOP
oscillator enabled oscillator stopped oscillator enabled System clock selection Clock from X0/X1 Clock from multiplication X0/X1 MHz) times X0/X1 MHz) times X0/X1 MHz) times X0/X1 MHz) times clock selection Selects system clock Selects system clock divided Clock stop Supplies clock FlexRay controller. Stops clock FlexRay controller.
bit6 Reserved Always write this bit. When read, this always returns "0". bit8, bit7 SDIV[1:0] System clock division System clock System clock divided System clock divided System clock divided bit31 bit9 Reserved Always write this bit. When read, this always returns "0".
Readable/writable DS04-22117-1E
MB88121B
bit31 bit9
name RSV: Reserved
Function These bits reserved. These bits always return when read. Always write these bits. Configures frequency divider system clock (sclk). clock divided according these bits used FlexRay operating clock (f_sclk). SDIV[1] SDIV[0] System clock System clock divided System clock divided System clock divided Function
bit8, bit7
SDIV[1:0]: System clock division
Note Changing these bits prohibited while FlexRay controller available transmit receive. bit6 RSV: Reserved This reserved. This always returns when read. Always write this bit. Stops system clock (sclk). When this "1", system clock stops being supplied FlexRay controller. oscillator circuit continues operate even when this "1". following procedures this "1". When using Prohibit FlexRay controller from transmitting receiving. SSEL STOP When using Prohibit FlexRay controller from transmitting receiving. STOP following procedures this "0". When using STOP After lock-up time (600 elapsed, SSEL Enable FlexRay controller transmit receive. When using STOP Note Changing this prohibited while FlexRay controller available transmit receive. RCLK: clock selection This selects whether system clock (sclk) divided used clock (f_bclk) used directly clock. Note Changing this prohibited while FlexRay controller available transmit receive. (Continued)
bit5
STOP: Stop
bit4
DS04-22117-1E
MB88121B
(Continued)
Name
Function Determines multiplication factor. these bits such that clock becomes MHz. interface mode, configuration values MDE1 MDE0 pins loaded into these bits upon release from reset.
bit3, bit2
PMUL[1:0]: multiplication
PMUL[1]
PMUL[0]
Function Multiply X0/X1 MHz) Multiply X0/X1 MHz) Multiply X0/X1 MHz) Multiply X0/X1 MHz)
Note Change these bits before setting "1". This selects between X0/X1 clock clock output from PLL. "0": Selects clock from X0/X1. "1": Selects clock output from PLL. Notes When changing this from "1", first then ensure lock-up time (600 before changing this bit. stop oscillator, first this before setting "0". This enables oscillator. interface mode, this upon release from reset. Disables oscillator. Enables oscillator. Note Change this when SSEL "0". Note Clock Control Register only updated when CCSV:POCS5 POCS0 bits DEFAULT_CONFIG state CONFIG state. Clock system diagram When MD[2:0]=100 (16-bit interface)
clock f_bclk
bit1
SSEL: System clock (sclk) selection
bit0
PON: oscillator enabled
System clock
SSEL bit1 bit0 bit3,bit2 PMUL[1:0] STOP bit5 sclk bit4 RCLK
FlexRay operating clock f_sclk
bit8,bit7 SDIV[1:0]
DS04-22117-1E
MB88121B
Debug Support Register (DBGS: Debug Support)
Always access this register together with Support Register 32-bit value.
Address
0008H Initial Value
MBSUE
CYCSE
SDSE
CYCS0E
Support register (DMAS) 00000000H
Readable/writable
bit26 bit16 Reserved Always write these bits. When read, these bits always return "0". bit27 CYCS0E CYCS0 output enabled Output disabled Output enabled bit28 SDSE output enabled Output disabled Output enabled bit29 output enabled Output disabled Output enabled bit30 CYCSE CYCS output enabled Output disabled Output enabled bit31 MBSUE MBSU output enabled Output disabled Output enabled
Name
Function This enables internal MBSU_TX1, MBSU_RX1, MBSU_TX2, MBSU_RX2 signals output MBSU_TX1, MBSU_RX1, MBSU_TX2, MBSU_RX2 pins. When this "1", internal signals output, when "0", pins fixed "L". Note: This setting only active interface mode multiplexed parallel interface mode. This enables internal CYCS signal (cycle start) output CYCS pin. When this "1", internal CYCS signal output, when "0", CYCS fixed "L". (Continued)
MBSUE: MBSU output enable
CYCSE: CYCS output enable
DS04-22117-1E
MB88121B
(Continued)
Name MTE: output enable
Function This enables internal signal (macrotick) output pin. When this "1", internal signal output, when "0", fixed "L".
This enables internal signal (dynamic segment start) SDSE: output pin. When this "1", internal signal output enable output, when "0", fixed "L". CYCS0E: This enables internal CYCS0 signal (cycle start) output CYCS0 output enable CYCS0 pin. When this "1", internal CYCS0 signal output, when "0", CYCS0 fixed "L". RSV: Reserved bits These bits reserved. These bits always return when read. Always write these bits.
DS04-22117-1E
MB88121B
Support Register (DMAS: Support)
Support Register controls output signal DMAC.
Address
0008H DMAINV DMARE DMAOE
Debug support register (DBGS)
Initial Value
00000000H
bit0 DMAOE bit1 DMARE bit2 DMAINV transfer request output enable transfer request (DMA_REQ) high impedance state. transfer request (DMA_REQ) output. transfer request enable transfer requests disabled. transfer requests enabled. transfer request inversion transfer requests made using level transfer requests made using level
bit15 bit3 Reserved Always write these bits. When read, these bits always return "0". Readable/writable
bit15 bit3
name
Function
Reserved These bits reserved. These bits always return when read. Always write these bits. DMAINV: transfer request inversion This inverts transfer request signal. "0": transfers requested level. "1": transfers requested level. Note This setting valid when DMAOE "1". (Continued)
bit2
DS04-22117-1E
MB88121B
(Continued)
name DMARE: transfer request enable
Function This enables transfer requests. "0": transfer requests disabled. "1": transfer requests enabled. Note This setting valid when DMAOE "1". This enables outputs transfer request (DMA_REQ). transfer request (DMA_REQ) high impedance state. transfer request (DMA_REQ) output.
bit1
bit0
Notes When this "0", transfer request (DMA_REQ) placed DMAOE: high impedance state. pins connected transfer transfer request pin, pull-up resistance output from another request output required. enable Simultaneously changing this from changing DMAINV create hazard signal transfer request (DMA_REQ). avoid this, change value DMAINV beforechanging this from "1".
Note interface mode, setting this register effect operation because there request (DMA_REQ).
DS04-22117-1E
MB88121B
Interrupt Register (INT: Interrupt)
Interrupt Register (INT) performs low-voltage detection control, flag display, timer interrupt output control.
Address 000CH
LVD18CL
LVD5CL
TINT1E
TINT0E
LVD18E
LVD5E
LVD18
LVD5
Initial Value
00000000H
Readable/writable DS04-22117-1E
bit0 LVD5 low-voltage detect voltage detected voltage detected bit1 LVD18 Core low-voltage detect voltage detected voltage detected bit2 LVD5E voltage detection enabled voltage detection disabled voltage detection enabled bit3 LVD18E Core voltage detection enabled Core voltage detection disabled Core voltage detection enabled bit4 TINT0E Timer interrupt output enabled output disabled output enabled bit5 TINT1E Timer interrupt output enabled output disabled output enabled bit6 LVD5CL LVD5 clear clear Clear bit7 LVD18CL LVD18 clear clear Clear bit31 bit8 Reserved Always write these bits. When read, these bits always return "0".
MB88121B
bit31 bit8
name RSV: Reserved LVD18CL: LVD18 clear
Function These bits reserved. These bits always return when read. Always write these bits. Clears core power supply (1.8 voltage detection flag. "0": flag changed. "1": flag cleared "0". Note This always returns when read.
bit7
bit6
Clears power supply voltage detection flag. "0": flag changed. LVD5CL: "1": flag cleared "0". LVD5CL clear Note This always returns when read. TINTE1: TINTE1 enable TINTE0: TINTE0 enable LVD18E: LVD18 interrupt enable This enables timer interrupt signal output pin. "0": Disables output interrupt signal pin. "1": Enables timer interrupt signal output pin. This enables timer interrupt signal output pin. "0": Disables output interrupt signal pin. "1": Enables timer interrupt signal output pin. This enables core power supply (1.8 voltage detection interrupt signal output pin. "0": Disables output interrupt signal pin. "1": Enables LVD18 voltage detection interrupt signal output pin. This enables power supply voltage detection interrupt signal output pin. "0": Disables output interrupt signal pin. "1": Enables LVD5 voltage detection interrupt signal output pin. Core power supply (1.8 voltage detection flag. "0": detected. "1": Voltage drop detected. Note This cleared writing LVD18CL bit. power supply voltage detection flag. "0": detected. "1": Voltage drop detected. Note This cleared writing LVD5CL bit.
bit5
bit4
bit3
bit2
LVD5E: LVD5 interrupt enable LVD18: voltage detection flag LVD5: voltage detection flag
bit1
bit0
Note 16-bit non-multiplexed parallel interface mode, LVD5, LVD18, TINT0, TINT1 interrupt signals output INT2. 16-bit multiplexed parallel interface mode interface mode, LVD5 LVD18 interrupt signals output INT4, TINT0 interrupt signal output INT2, TINT1 interrupt signal output INT3.
Other Registers
Refer MB88121B users manual details other registers.
DS04-22117-1E
MB88121B
PACKAGE DIMENSIONS
64-pin plastic LQFP Lead pitch Package width package length Lead shape Sealing method Mounting height Weight 0.50 10.0 10.0 Gullwing Plastic mold 1.70 0.32g
(FPT-64P-M03)
Code (Reference)
64-pin plastic LQFP (FPT-64P-M03)
Note These dimensions include resin protrusion. Note Pins width pins thickness include plating thickness. Note Pins width include cutting remainder.
12.00±0.20(.472±.008)SQ
10.00±0.10(.394±.004)SQ
0.145±0.055 (.006±.002)
Details part 0.08(.003) 1.50 -0.10 .059 -.004
+0.20 +.008
(Mounting height)
INDEX
0°~8° 0.50±0.20 (.020±.008) 0.60±0.15 (.024±.006)
0.10±0.10 (.004±.004) (Stand off)
0.25(.010)
LEAD
0.50(.020)
0.20±0.05 (.008±.002)
0.08(.003)
2003-2008 FUJITSU MICROELECTRONICS LIMITED F64009S-c-5-9
Dimensions (inches). Note: values parentheses reference values
Please confirm latest Package dimension following URL.
DS04-22117-1E
MB88121B
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ further information please contact: North South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 Arques Avenue, Sunnyvale, 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 Korea FUJITSU MICROELECTRONICS KOREA LTD. KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA LTD. Lorong Chuan, #05-08 Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw
Rights Reserved. contents this document subject change without notice. Customers advised consult with sales representatives before ordering. information, such descriptions function application circuit examples, this document presented solely purpose reference show examples operations uses FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does warrant proper operation device with respect based such information. When develop equipment incorporating device based such information, must assume responsibility arising such information. FUJITSU MICROELECTRONICS assumes liability damages whatsoever arising information. information this document, including descriptions function schematic diagrams, shall construed license exercise intellectual property right, such patent right copyright, other right FUJITSU MICROELECTRONICS third party does FUJITSU MICROELECTRONICS warrant non-infringement third-party's intellectual property right other right using such information. FUJITSU MICROELECTRONICS assumes liability infringement intellectual property rights other rights third parties which would result from information contained herein. products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated accompanying fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), requiring extremely high reliability (i.e., submersible repeater artificial satellite). Please note that FUJITSU MICROELECTRONICS will liable against and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. Exportation/release products described this document require necessary procedures accordance with regulations Foreign Exchange Foreign Trade Control Japan and/or export control laws. company names brand names herein trademarks registered trademarks their respective owners.
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FlexRay Controller MB88121B DESCRIPTION MB88121B FlexRay* co

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