ASSP Bi-CMOS Dual Serial Input Frequency Synthesizer MB15F63

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ASSP Bi-CMOS Dual Serial Input Frequency Synthesizer MB15F63

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DS04-21382-1Ea
ASSP
Bi-CMOS
Dual Serial Input Frequency Synthesizer MB15F63UL
DESCRIPTION
MB15F63UL 2000 frequency synthesizer with high-speed frequency switching function based Fractional-N (Phase Locked Loop), Integer-N frequency synthesizer which enables pulse swallow operation. Encased subminiature package (thin-BCC20), MB15F63UL successfully achieved small thin external form (BCC20 package dimensions: 3.50 3.50 0.60 mm). MB15F63UL suitable digital mobile communication devices such GSM.
FEATURES
High frequency operation 1800 2000 (IF) Fractional-N function Modulo 1048576 method) Fractional-N, enabling high-speed lock-up phase noise voltage operation Ultra power supply current (RF) +1.4 (IF) locking state Direct power saving function Power supply current power saving mode (controllable external pin) (Vcc (Vcc Internal automatic switch changeover circuit (changeover time selectable) function update changeover time Constant-current charge pump circuit capable switching control current value through serial data control internal changeover circuit steady-state operation: high-speed changeover: (Continued)
Copyright©2006-2008 FUJITSU MICROELECTRONICS LIMITED rights reserved 2006.10
MB15F63UL
(Continued) Open-drain NMOS switch that turned from internal changeover circuit Prescaler division ratio 2000 prescaler (16/17/20/21) /600 prescaler (8/9, 16/17) 29-bit shift register input control Serial input 14-bit programmable reference divider Binary 6-bit side) Binary 14-bit swallow counter 16383 side) Serial input programmable divider consisting Binary 4-bit swallow counter side) Binary 7-bit swallow counter side) Binary 7-bit programmable counter side) /Binary 11-bit swallow counter 2047 side) On-chip phase control phase comparator Built-in digital locking detector circuit detect locking unlocking Extended operating temperature
MB15F63UL
ASSIGNMENTS
(TOP VIEW)
finIF PSIF VPIF DoIF DoRF VPRF LD/fout XfinIF OSCin VccIF Data VccRF finRF
XfinRF PSRF
(LCC-20P-M06)
MB15F63UL
DESCRIPTIONS
name VPIF DoIF DoRF VPRF LD/fout Descriptions Charge pump power supply IF-PLL Charge pump output IF-PLL Ground Open-drain switch changing over high-speed mode filter Charge pump output RF-PLL Power supply RF-PLL charge pump Lock detect signal output (LD) /phase comparator monitoring output (fout) pin. output signal selected serial data. outputs fout signal/LDS outputs signal Power saving mode control RF-PLL section. This must when power supply started (Open prohibited. Normal mode/PS Power saving mode Ground Prescaler complimentary input RF-PLL section. This should grounded capacitor. Prescaler input RF-PLL. Connection external should coupling. Power supply RF-PLL Load enable signal input (with schmitt trigger circuit) When "H", data shift register transferred corresponding latch according control serial data. Serial data input (with schmitt trigger circuit) Data transferred corresponding latch (IF-ref. counter, IF-prog. counter, RF-ref. counter, RF-prog. counter) according control serial data. Clock input 29-bit shift register (with schmitt trigger circuit) data shifted into shift register rising edge clock. Power supply IF-PLL programmable reference divider input pin. TCXO should connected with coupling capacitor. Prescaler complimentary input IF-PLL section. This should grounded capacitor. Prescaler input IF-PLL. Connection external should coupling. Power saving mode control IF-PLL section. This must when power supply started (Open prohibited.) Normal mode/PS Power saving mode
PSRF XfinRF finRF VccRF
Data
VccIF OSCin XfinIF finIF
PSIF
MB15F63UL
BLOCK DIAGRAM
finIF XfinIF SWIF
Prescaler 8/9, 16/17
Programmable Counter latch Swallow Counter Phase Comparator SWIF
Lock Detect Charge Pump VPIF DoIF
VccIF PSIF
latch Reference Counter latch 26-bit Shift Register Data
PSIF
OSCin
LDIF
frIF fpIF fpRF frRF
Selector
LD/fout
finRF XfinRF
Prescaler 16/17/20/21
Programmable Counter latch Swallow Counter latch Reference Counter
LDRF
Lock Detect Charge Pump VPRF DoRF
Sigma Delta Fractional Modulation latch
Phase Comparator
PSRF FCRF latch Timer TMC,TM1-7
VccRF
latch
PSRF
PSRF
control ODSW
MB15F63UL
ABSOLUTE MAXIMUM RATINGS
Rating +125
Parameter Power supply voltage Input voltage Output voltage Storage temperature LD/fout
Symbol Tstg
Unit
WARNING: Semiconductor devices permanently damaged application stress (voltage, current, temperature, etc.) excess absolute maximum ratings. exceed these ratings.
RECOMMENDED OPERATING CONDITIONS
Rating
Parameter Power supply voltage Input voltage Operating temperature
Symbol
Unit
WARNING: recommended operating conditions required order ensure normal operation semiconductor device. device's electrical characteristics warranted when device operated within these ranges. Always semiconductor devices within their recommended operating condition ranges. Operation outside these ranges adversely affect reliability could result device failure. warranty made with respect uses, operating conditions, combinations represented data sheet. Users considering application outside listed conditions advised contact their representatives beforehand.
MB15F63UL
ELECTRICAL CHARACTERISTICS
(Vcc Parameter Power supply current Power saving current
Symbol IccIF*1
Condition IF-PLL section RF-PLL section IF-PLL section RF-PLL section IF-PLL section RF-PLL section (2.7 RF-PLL section (2.9 Reference counter setting value Reference counter setting value IF-PLL section termination RF-PLL section termination (fin 2000 MHz) RF-PLL section termination (fin MHz) RF-PLL section Schmitt trigger input Schmitt trigger input
Value 0.1*9 0.1*9 10.0 1800 2000
Unit
IpsIF*10 IpsRF*10 finIF
finRF*3 Operating frequency OSCin
finRF
fosc
finIF
PfinIF
Input sensitivity finRF PfinRF
-1.0 -1.0 +1.0 +1.0 Vp-p (Continued)
Input available OSCin voltage Operating frequency phase comparator level input voltage level input voltage level input voltage level input voltage level input current level input current level output voltage level output voltage Data,
VOSC fMAIN_PD IIH*4 IIL*4
PSIF, PSRF
Data,
LD/fout
MB15F63UL
(Vcc Parameter level output voltage level output voltage level output voltage level output voltage High impedance cutoff current level output current level output current level output current level output current level output current level output current level output current level output current level output current level output current Symbol VDOH DoIF VDOL VDOH DoRF VDOL DoIF DoRF IOFF IOH*4 LD/fout IDOH*4 IDOL DoIF IDOH*4 IDOL IDOH*4 IDOL DoRF IDOH*4 IDOL IDOL/IDOH IDOMT*5 Charge DoIF pump current rate
DOVD
Condition VccIF VPIF IDOH -0.5 VccIF VPIF IDOL VccRF VPRF IDOH -0.01 VccRF VPRF IDOL 0.01 VOFF Vcc-0.5 VccIF VPIF VDoIF VPIF/2 CSIF "L", VccIF VPIF VDoIF VPIF/2 CSIF "H", VccRF VPRF VDoRF VPRF/2 steady state (locking state) VccRF VPRF VDoRF VPRF/2 channels changeover Vp/2 0.5V Vcc/2 Vp/2 normal mode (OFF) high-speed mode (ON)
Value -2.2 +0.8 -8.2 +4.1 -160 -6.1 +2.4 -1.5 +1.5 -6.0 +6.0 -4.5 +4.5 -1.0 -0.8 +2.2 -4.1 +8.2 +160 -2.4 +6.1 15.0
Unit
IDOTA*7
DoRF IDOL/IDOH IDOMT*8 Open-drain output resistance ZSSH high-speed (SW)
finIF MHz, fosc 19.2 MHz, frIF kHz, VCCIF VPIF locking state. finRF 1600 MHz, fosc 19.2 MHz, frRF 19.2 MHz, VCCRF VPRF locking state. (Continued)
MB15F63UL
(Continued) coupling. 1000 capacitor connected under condition minimum operating frequency. symbol means direction current flow. (||I3| |I4||) (|I3| |I4|) 100% 3.0V, (IDOL, IDOH respectively) (||I2| |I1||) (|I1| |I2|) 100% 3.0V, (IDOL, IDOH respectively) (||IDO (85c) |IDO (-40c) (|IDO (85c) |IDO (-40C) 100% (||IDOL| |IDOH||) (|IDOL| |IDOH|) 100% Power supply current (Data, setting.) Power supply current fosc 19.2 MHz, (Data, GND, setting.)
IDOL
IDOH Vp/2
Charge pump output potential
MB15F63UL
FUNCTIONAL DESCRIPTION
Serial Data Input
Serial data processed using Data, Clock, pins. Serial data controls programmable reference divider programmable divider separately. Binary serial data entered through Data pin. data shifted into shift register rising edge Clock. When signal taken high, stored data latched according control data. following table shows shift register configuration combinations data transfer control bits. Destination serial data
Note Start data input with first.
Setting data
Fractional-N Synthesizer RF-PLL section each setting value Fractional-N Synthesizer counter, according following equations. fvcoRF NTOTAL fOSC NTOTAL numerator fractional division with fractional portion discarded. When value even-numbered result division calculation, added Integer-N Synthesizer IF-PLL section Integer-N Synthesizer counter set, according following equations. fvcoIF NTOTAL fOSC NTOTAL fvcoRF/fvcoIF NTOTAL fosc Output frequency externally connected Total number divisions from prescaler input phase comparator input Reference oscillation frequency (OSCin input frequency) side Setting value binary 6-bit reference counter side Setting value binary 14-bit reference counter 16383) side Division ratio prescaler (16) side Division ratio prescaler side Setting value binary 7-bit programmable counter 127) side Setting value binary 11-bit programmable counter 2047) side Setting value binary 4-bit swallow counter side Setting value binary 4-bit swallow counter 127, Numerator fractional division 1048575, Denominator fractional division (220 1048576)
MB15F63UL
Data description name F1RF F20RF A1RF A4RF N1RF N7RF R1RF R6RF A1IF A7IF N1IF N11IF R1IF R14IF
Description
Bits setting fractional numerator RF-PLL (Setting range: 1048575) (Refer Table Bits setting division ratio RF-side swallow counter (Setting range: (Refer Table Bits setting RF-side main counter (Setting range: 127) (Refer Table Bits setting division ratio RF-side reference counter (Setting range: (Refer Table Bits setting division ratio IF-side swallow counter (Setting range: 127) (Refer Table Bits setting IF-side main counter (Setting range: 2047) (Refer Table Bits setting division ratio IF-side reference counter (Setting range: 16383) (Refer Table Control setting Speedup Mode (Refer Table TMC_bit disabled TMC_bit enabled Bits setting speedup timer (Refer Table Power saving RF-PLL section Phase switching RF-side phase comparator (Refer Table Control open-drain switch ODSW "0"Dynamic ODSW "1"OFF Phase switching IF-side phase comparator (Refer Table Charge pump switching IF-PLL section CSIF ±1.5mA CSIF ±6.0mA Bits setting division ratio IF-side prescaler SWIF 16/17 SWIF Power saving IF-PLL section Control bits selecting monitor function (Refer Table switching order order order Dummy bit: Must fixed
PSRF FCRF ODSW FCIF CSIF
SWIF PSIF LDS,
MB15F63UL
Table Fractional counter numerator value Setting Setting value 1048574 1048575
Table Swallow counter setting Setting value
Table Main counter setting Setting value
Table Reference counter setting Setting value
Table Swallow counter setting Setting value
MB15F63UL
Table Main counter setting Setting value 2046 2047
Table Reference counter setting Setting value 16382 16383
Table Speedup timer update value setting Setting value case) fosc 19.2 420.0 423.3 unit:µs Charge pump current switching time 64/fosc
Table Charge pump output current setting Charge pump output current 0.094 fixed 0.094 switched
MB15F63UL
Table LD/fout output setting LD/fout output frIF fout frRF fpIF fpRF 2000 Maximum operating frequency [MHz]* 1800
maximum operating frequency varies depending output state LD/fout output fout output). Table Comparator polarity setting Polarity
Note accordance with pass filter polarity, when designing frequency synthesizer.
high
When When
output Frequency
high Input Voltage
MB15F63UL
Power Saving Mode (Intermittent Operation)
PSIF ExternalPIN SerialData IFPLL Power save Power save Power save Active PSRF ExternalPIN SerialData RFPLL Power save Power save Power save Active
intermittent operation allows internal circuits operate only when required stop otherwise. designed control power consumed entire circuit block. However, circuit starts operating directly from stop state, phase relation undefined, even when comparison frequency (fp) same reference frequency (fr) input phase comparator. result, phase comparator generates excessive error signals, causing problem unlocking PLL. solve this problem, intermittent operation control been implemented control fluctuations locked frequency performing forcible phase adjustment beginning operation. Operation mode channel crystal oscillator circuit operation performs normal operation. Power save mode This mode realizes current consumption stopping circuits which will cause problem even when stopped. this condition, standard consumption current channel with maximum this point, same levels when locked. enters high impedance state, voltage input voltage control oscillator (VCO) remains same voltage operation mode (i.e. locked state) with time constant pass filter. Therefore, output frequency maintained almost same level lock frequency. Notes When power (VCC) first applied, device must power saving mode (external undefined serial data) serial data input after power supply became stable, then power saving mode released after completed data input.
Data
(power saving mode) Power serial data later after power supply remains stable (VCC Release power saving mode
MB15F63UL
Serial Data Input Timing
Divide ratio performed through serial interface using Data pin, Clock pin, pin. Setting data read into shift register rise Clock signal, transferred latch rise signal. following diagram shows data input timing.
1st. data Control
Data
2nd. data Invalid data
should when data transferred into shift register.
MB15F63UL
PHASE COMPARATOR OUTPUT WAVEFORM
frRF
fpRF
"H")
DoRF
"L")
DoRF
Output Logic IF-PLL section Locking state/Power saving state Locking state/Power saving state Unlocking state Unlocking state
RF-PLL section Locking state/Power saving state Unlocking state Locking state/Power saving state Unlocking state
output
Notes Phase error detection range Pulses signal during locked state output prevent dead zone. RF-PLL section output becomes when phase more. output becomes when phase error less continues cycles more. depend input frequency. (fin ex.) 1629.9 9.82 (fin 19.63 IF-PLL section output becomes when phase more. output becomes when phase error less continues three cycles more. depend OSCin input frequency. fosc ex.) fosc 13.0 fosc
MB15F63UL
MEASURMENT CIRCUIT (for Measuring Input Sensitivity fin/OSCin)
VCCIF
Controller (setting divide ratio)
Data VCCRF
1000
1000 finRF XfinIF MB15F63UL Bump Chip Carrier-20 VCCIF PSIF XfinRF 1000
OSCin
1000
finIF
VCCRF
PSRF LD/fout
VPIF DoIF
DoRF
VPRF
Oscilloscope
MB15F63UL
TYPICAL CHARACTERISTICS
Input Sensitivity
input sensitivity Input frequency
input sensitivity (dBm)
1000 1500 2000 2500 3000 SPEC
Input frequency (MHz)
input sensitivity Input frequency
input sensitivity (dBm)
SPEC
1000 1500
Input frequency (MHz)
MB15F63UL
OSCin Input Sensitivity
OSCin input sensitivity Input frequency
OSCin input sensitivity (dBm)
SPEC
Input frequency (MHz)
MB15F63UL
output current
Charge pump output current (µA)
VCCRF VPRF
-200
Charge pump output voltage
Charge pump output current (mA)
VCCRF VPRF
-6.0
Charge pump output voltage
MB15F63UL
output current
Charge pump output current (mA)
VCCIF VPIF
-2.0
Charge pump output voltage
Charge pump output current (mA)
VCCIF VPIF
-7.0
Charge pump output voltage
MB15F63UL
input impedance
finIF input impedance
6.2119 -21.005 12.628 600.000 82.813 -246.07 22.242 -117.85 7.8457 -49.664
START 100.000
STOP 600.000
finRF input impedance
12.429 2.9873 237.72 000.000 32.969 -153.25 17.539 -65.531
18.783 -26.514
START 100.000
STOP 000.000
MB15F63UL
OSCin input impedance
195.13
-3.0835
2.5808 20.000 4.116 -10.916 -6.3023 195.13 -3.0835
START 5.000
STOP 20.000
MB15F63UL
REFERENCE INFORMATION
S.G. OSCin
fvco MHz/V Vvco fosc 13.0 "1", "0", ODSW "0", "1", MODE
2200 10000 0.62
Spectrum Analyzer
Phase Noise Spurious Noise Offset
ATTEN VAVG -88.56 dB/Hz 1.00 ATTEN
Offset
VAVG -116.8 dB/Hz 200.0
1.00 -88.56 dB/Hz
200.0 -116.8 dB/Hz
CENTER 800.00000
SPAN 10.00
CENTER 800.0000 SPAN 500.0 1.30
Ref. Leakage Offset
ATTEN VAVG -82.17 6.50
6.50 -82.17
CENTER 812.50
SPAN 15.00 50.0
MB15F63UL
Lock time
835.004000
835.000000
834.996000 0.00 500.0 100.0 µs/div 1.000
Lock time
800.004000
800.000000
799.996000 0.00 500.0 100.0 µs/div 1.000
MB15F63UL
APPLICATION EXAMPLE
LPFRF
Output VCCIF
VCO, RF-PLL
VCCRF
Controller (setting divide ratio)
Data
OSCin TCXO XfinIF
finRF
1000
MB15F63UL Bump Chip Carrier-20 XfinRF 1000 VCCRF PSIF PSRF VPIF DoIF VPRF LD/fout
1000
VCCIF
finIF
Output
Lock Det.
LPFIF
DoRF
VCO, IF-PLL
Note CLK, Data built-in schmitt trigger circuits (insert pull-down pull-up register prevent oscillation when open-circuit input)
MB15F63UL
PRECAUTIONS
Fractional-N used section based system following characteristics. Integer operation when When "0", circuit block stopped completely same operation normal Integer product performed. Therefore, most preferable noise characteristics achieved. Generation spurious signals 1.Spurious signals generated offset part which comparison frequency (equivalent reference leak integer type). Example: fosc when fvco band, Ntotal becomes becomes (Integer mode) Spurious signals generated MHz" offset. (Reference leak) (The waveform resembles that reference leakage shown Leakage "REFERENCE INFORMATION". filter used eliminate effects.) circuit operation, spurious signals generated where located. Example: fosc MHz; band: When fvco 806.2 MHz, Ntotal becomes 142.0307692. becomes 32263. Consequently, spurious signals generated kHz" offset.
Offset
ATTEN VAVG -82.50 200.0
200.0 -82.50
CENTER 806.2000
SPAN 500.0 1.30
Adjusting filter reduce these spurious signals. Furthermore, modifying change setting value avoid generate spurious signals. example, when fosc Ntotal becomes 125.0307692., where fvco 812.7 MHz. Therefore, becomes 32263. Spurious signals supposed generated kHz" offset. However, changed will become 572683 2.366 MHz" spurious signals will outer frequencies. Therefore, effects will foreseen.
MB15F63UL
Note that problem cannot avoided when setting value swallow counter odd-numbered (also applicable 806.2 environment, used above explanation). However, spurious signals reduced changing (reducing limit band. Note that this case, comparison frequency itself changes, resulting change loop band deterioration Therefore,each case should handled accordance with system used. Some example waveforms attached following.
MB15F63UL
(200 offset)
ATTEN VAVG -89.50 200.0 ATTEN
(200kHz offset)
VAVG -90.83 200.0
200.0 -89.50
200.0 -90.83
CENTER 812.7000
SPAN 500.0 1.30
CENTER 812.7000
SPAN 500.0 1.30
(loop band waveform)
ATTEN VAVG -3.00 12.00 ATTEN 10dB
(loop band waveform)
VAVG -3.00 10.08
12.00 -3.00
10.08 -3.00
CENTER 812.70000
SPAN 50.00 1.40
CENTER 812.70000
SPAN 50.00 1.40
(1kHz offset)
ATTEN 10dB VAVG -89.23 dB/Hz 1.00 ATTEN
(1kHz offset)
VAVG -82.57 dB/Hz 1.00
1.00 -89.23 dB/Hz
1.00 -82.57 dB/Hz
CENTER 812.70000
SPAN 10.00
CENTER 812.70000
SPAN 10.00
MB15F63UL
Excessive spurious signals generated when setting binary division such 1/2, 1/4, 1/8. difficult reduce excess level, value shifted acceptable range frequency differences reduce Example: Spurious noise generated entire floor when 524288 (F/Q 1/2). Spurious noise generated entire floor when 262144 (F/Q 1/4). following section shows examples spurious waveforms generated above cases well examples waveforms when added value
MB15F63UL
524288(F/Q 1/2)
ATTEN -8.83 809.2500 ATTEN 10dB
262144(F/Q 1/4)
-8.50 807.6250
809.2500 -8.83
807.6250 -8.50
CENTER 809.2500
SPAN 200.0
CENTER 807.6250
SPAN 200.0
524288
ATTEN -8.50 809.2500 ATTEN
262144
-8.67 807.6250
809.2500 -8.50
807.6250 -8.67
CENTER 809.2500
SPAN 200.0
CENTER 807.6250
SPAN 200.0
524288
ATTEN -9.17 809.2500 ATTEN
262144
-9.17 807.6250
809.2500 -9.17
807.6250 -9.17
CENTER 809.2500
SPAN 200.0
CENTER 807.6250
SPAN 200.0
MB15F63UL
Notes VCCRF VCCIF must equal voltage. Even either RF-PLL IF-PLL used, power must supplied VCCRF VCCIF keep them equal. recommended that non-use controlled power saving function. protect against damage electrostatic discharge, note following handling precautions Store transport devices conductive containers. properly grounded workstations, tools, equipment. Turn power before inserting device into removing device from socket. Protect leads with conductive sheet when transporting board-mounted device.
MB15F63UL
ORDERING INFORMATION
Part number MB15F63ULPVA1 Package 20-pin, Plastic (LCC-20P-M06) Remarks
MB15F63UL
PACKAGE DIMENSIONS
20-pin plastic Lead pitch Package width package length Sealing method Mounting height Weight 0.50 3.50 3.50 Plastic mold 0.60 0.01
(LCC-20P-M06)
20-pin plastic (LCC-20P-M06)
3.50±0.10 (.138±.004) 0.55±0.050 (.022±.0020) Mount height
3.00(.118)REF. 0.50±0.10 (.020±.004) 0.50(.020)
0.50(.020) TYP. INDEX AREA 3.50±0.10 (.138±.004)
2.90(.114) TYP.
2.90(.114) TYP. 1.00(.004) REF.
0.95 (.037)
1PIN INDEX 1.55(.061)
0.075±0.025 (.003±.001) (Stand off) Details part 0.14(.006)
Details part 0.40±0.06 (.016±.002) 0.40±0.06 (.016±.002) 0.20(.008) 0.30±0.06 (.012±.002)
0.05(.002) 0.30±0.06 (.012±.002)
0.20(.008) 1PIN INDEX
2004 FUJITSU LIMITED C20057S-c-1-1
Dimensions (inches). Note: values parentheses reference values.
FUJITSU MICROELECTRONICS LIMITED
Shinjuku Dai-Ichi Seimei Bldg. 7-1, Nishishinjuku 2-chome, Shinjuku-ku, Tokyo 163-0722, Japan Tel: +81-3-5322-3347 Fax: +81-3-5322-3387 http://jp.fujitsu.com/fml/en/ further information please contact: North South America FUJITSU MICROELECTRONICS AMERICA, INC. 1250 Arques Avenue, Sunnyvale, 94085-5401, U.S.A. Tel: +1-408-737-5600 Fax: +1-408-737-5999 http://www.fma.fujitsu.com/ Europe FUJITSU MICROELECTRONICS EUROPE GmbH Pittlerstrasse 63225 Langen, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122 Korea FUJITSU MICROELECTRONICS KOREA LTD. KOSMO TOWER, 1002 Daechi-Dong, Kangnam-Gu,Seoul 135-280 Korea Tel: +82-2-3484-7100 Fax: +82-2-3484-7111 http://www.fmk.fujitsu.com/ Asia Pacific FUJITSU MICROELECTRONICS ASIA LTD. Lorong Chuan, #05-08 Tech Park, Singapore 556741 Tel: +65-6281-0770 Fax: +65-6281-0220 FUJITSU MICROELECTRONICS SHANGHAI CO., LTD. Rm.3102, Bund Center, No.222 Road(E), Shanghai 200002, China Tel: +86-21-6335-1560 Fax: +86-21-6335-1605 http://cn.fujitsu.com/fmc/ FUJITSU MICROELECTRONICS PACIFIC ASIA LTD. 10/F., World Commerce Centre, Canton Road Tsimshatsui, Kowloon Hong Kong Tel: +852-2377-0226 Fax: +852-2376-3269 http://cn.fujitsu.com/fmc/tw
Rights Reserved. contents this document subject change without notice. Customers advised consult with sales representatives before ordering. information, such descriptions function application circuit examples, this document presented solely purpose reference show examples operations uses FUJITSU MICROELECTRONICS device; FUJITSU MICROELECTRONICS does warrant proper operation device with respect based such information. When develop equipment incorporating device based such information, must assume responsibility arising such information. FUJITSU MICROELECTRONICS assumes liability damages whatsoever arising information. information this document, including descriptions function schematic diagrams, shall construed license exercise intellectual property right, such patent right copyright, other right FUJITSU MICROELECTRONICS third party does FUJITSU MICROELECTRONICS warrant non-infringement third-party's intellectual property right other right using such information. FUJITSU MICROELECTRONICS assumes liability infringement intellectual property rights other rights third parties which would result from information contained herein. products described this document designed, developed manufactured contemplated general use, including without limitation, ordinary industrial use, general office use, personal use, household use, designed, developed manufactured contemplated accompanying fatal risks dangers that, unless extremely high safety secured, could have serious effect public, could lead directly death, personal injury, severe physical damage other loss (i.e., nuclear reaction control nuclear facility, aircraft flight control, traffic control, mass transport control, medical life support system, missile launch control weapon system), requiring extremely high reliability (i.e., submersible repeater artificial satellite). Please note that FUJITSU MICROELECTRONICS will liable against and/or third party claims damages arising connection with above-mentioned uses products. semiconductor devices have inherent chance failure. must protect against injury, damage loss from such failures incorporating safety design measures into your facility equipment such redundancy, fire protection, prevention over-current levels other abnormal operating conditions. Exportation/release products described this document require necessary procedures accordance with regulations Foreign Exchange Foreign Trade Control Japan and/or export control laws. company names brand names herein trademarks registered trademarks their respective owners.
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ASSP Bi-CMOS Dual Serial Input Frequency Synthesizer MB15F63

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