PowerPSoCIntelligent Driver Integrated Power Peripherals Four int
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PowerPSoCIntelligent Driver
Integrated Power Peripherals Four internal side N-Channel power FETs RDS(ON)- 1.0A devices configurable switching frequency Four hysteretic controllers Independently programmable upper lower thresholds Programmable minimum on/off timers Four side gate drivers with programmable drive strength Four precision high side current sense amplifiers Three 16-bit dimming modulators: PrISM, DMM, fast response (100 voltage comparators 8-bit reference DACs Built-in switching regulator eliminates external supply Multiple topologies including floating load buck, floating load buck-boost, boost Core Processor speeds Advanced Peripherals (PSoC® Blocks) Capacitive sensing application capability DMX512 interface DALI interface master slave Full-duplex UARTs Multiple masters slaves Integrated temperature sensor 12-bit ADCs 12-bit incremental ADCs 9-bit DACs Programmable gain amplifiers Programmable filters comparators 32-bit timers counters Complex peripherals combining blocks Configurable GPIO pins Programmable Configurations sink GPIO function pins Pull pull down, high strong, open drain drive modes GPIO function pins analog inputs GPIO analog outputs GPIO Configurable interrupt GPIO Flexible On-chip Memory Flash program storage 50,000 erase write cycles SRAM data storage In-System Serial Programming (ISSP) Partial Flash updates Flexible protection modes EEPROM emulation Flash Complete Development Tools Free development software: PSoC Designer Full featured, In-Circuit Emulator Programmer Full speed emulation Complex breakpoint structure kBytes trace memory Visual Embedded Design based express drivers Binning compensation Temperature feedback Applications Stage lighting Architectural lighting General purpose lighting Automotive emergency vehicle lighting Landscape lighting Display lighting Effects lighting Signage lighting Device Options CY8CLED04D0x Four internal FETs with 0.5A 1.0A options Four external gate drivers Built-in switching regulator CY8CLED03D0x Three internal FETs with 0.5A 1.0A options Three external gate drivers Built-in switching regulator CY8CLED04G01 Four external gate drivers Built-in switching regulator CY8CLED03G01 Three external gate drivers Built-in switching regulator 56-pin Package
Figure 1-1. PowerPSoC Architectural Block Diagram
Port Port Port Analog Drivers
Analog Global Digital Interconnect Global Analog Interconnect
Interupt
SYSTEM
Logic Core
PrISM/
Power System Analog
PSoC
SRAM bytes Interrupt Controller
CORE
Clock Signals
Supervisory Flash Nonvolatile Memory( SROM)
Decoder
Hysteretic
Chbond_bus
Controller Channels(
Gate Driver(LV)
Power FETs (HV)
GDRV
(M8C) Core
Sleep Watchdog System
Analog Block
Internal Main Oscillator( IMO)
Internal Speed Oscillator ILO)
Hysteretic
GDRV
DIGITAL SYSTEM
Digital PSoC Block Array
ANALOG SYSTEM
Analog PSoC Block Array Analog
Comparator Bank
Power System Digital
Multiple Clock Sources
Hysteretic
GDRV
AINX
DCB13
Bank
Digital Rows
Hysteretic
GDRV
2Analog Columns
Vref
Digital Clocks
MACs
Decimator Type2)
System Resets
Internal Analog Voltage Multiplexer Reference
Regulator
POWER PERIPHERALS
PSoC SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-46319 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised April 2009
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Logic Block Diagrams
Figure 2-1. CY8CLED04D0x Logic Block Diagram
CSA0
CSP0 CSN0
DAC0 DAC1
Hysteretic Mode Controller
Gate Drive
PGND0
External Gate Drive Gate Drive
CSA1
CSP1 CSN1
DAC2 DAC3
Hysteretic Mode Controller
External Gate Drive
PGND1
CSA2
CSP2 CSN2
Analog
DAC4 DAC5
Gate Drive Hysteretic Mode Controller External Gate Drive
PGND2
CSA3
CSP3 CSN3
DAC6 DAC7
Gate Drive Hysteretic Mode Controller External Gate Drive
PGND3
FN0{0,1,2,3}
Digital
Comp Comp Comp Comp Comp
Comp
Channel PWM/ PrISM/DMM
Analog
SREGHVIN
DAC10
DAC11
DAC12
DAC8
DAC9
DAC13
SREGSW
From Analog AINX
System
Auxiliary Power Regulator
SREGCSP SREGCSN SREGFB SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller SROM Flash Sleep Watchdog
Port
PORT2{2}
Core (M8C) Clock Sources (Includes ILO)
Port Port
PORT1{0,1,4,5,7}
PORT0{3,4,5,7}
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital Clocks
MACs
Decimator Type
System Resets
Internal Voltage Ref.
Analog Input Muxing
SYSTEM RESOURCES
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Figure 2-2. CY8CLED03D0x Logic Block Diagram
CSA0
CSP0 CSN0
DAC0 DAC1
Hysteretic Mode Controller
Gate Drive
PGND0
External Gate Drive Gate Drive
CSA1
CSP1 CSN1
DAC2 DAC3 Analog
Hysteretic Mode Controller
External Gate Drive
PGND1
CSA2
CSP2 CSN2
DAC4 DAC5
Gate Drive Hysteretic Mode Controller External Gate Drive
PGND2
FN0{0,1,2,3}
Digital
Comp Comp Comp Comp Comp
Comp
Channel PWM/ PrISM/DMM
Analog
SREGHVIN
DAC10
DAC11
DAC12
DAC8
DAC9
DAC13
SREGSW
From Analog AINX
System
Auxiliary Power Regulator
SREGCSP SREGCSN SREGFB SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller SROM Flash Sleep Watchdog
Port
PORT2{2}
Core (M8C) Clock Sources (Includes ILO)
Port Port
PORT1{0,1,4,5,7}
PORT0{3,4,5,7}
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital Clocks
MACs
Decimator Type
System Resets
Internal Voltage Ref.
Analog Input Muxing
SYSTEM RESOURCES
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Figure 2-3. CY8CLED04G01 Logic Block Diagram
CSA0
CSP0 CSN0
DAC0 DAC1
Hysteretic Mode Controller
External Gate Drive
CSA1
CSP1 CSN1
DAC2 DAC3
Hysteretic Mode Controller
External Gate Drive
CSA2
CSP2 CSN2
Analog
DAC4 DAC5
Hysteretic Mode Controller
External Gate Drive
CSA3
CSP3 CSN3
DAC6 DAC7
Hysteretic Mode Controller
External Gate Drive
FN0{0,1,2,3}
Digital
Comp Comp Comp Comp Comp
Comp
Channel PWM/ PrISM/DMM
Analog
SREGHVIN
DAC10
DAC11
DAC12
DAC8
DAC9
DAC13
SREGSW
From Analog AINX
System
Auxiliary Power Regulator
SREGCSP SREGCSN SREGFB SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller SROM Flash Sleep Watchdog
Port
PORT2{2}
Core (M8C) Clock Sources (Includes ILO)
Port Port
PORT1{0,1,4,5,7}
PORT0{3,4,5,7}
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital Clocks
MACs
Decimator Type
System Resets
Internal Voltage Ref.
Analog Input Muxing
SYSTEM RESOURCES
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Figure 2-4. CY8CLED03G01 Logic Block Diagram
CSA0
CSP0 CSN0
DAC0 DAC1
Hysteretic Mode Controller
External Gate Drive
CSA1
CSP1 CSN1
DAC2 DAC3 Analog
Hysteretic Mode Controller
External Gate Drive
CSA2
CSP2 CSN2
DAC4 DAC5
Hysteretic Mode Controller
External Gate Drive
FN0{0,1,2,3}
Digital
Comp Comp Comp Comp Comp
Comp
Channel PWM/ PrISM/DMM
Analog
SREGHVIN
DAC10
DAC11
DAC12
DAC8
DAC9
DAC13
SREGSW
From Analog AINX
System
Auxiliary Power Regulator
SREGCSP SREGCSN SREGFB SREGCOMP
Global Digital Interconnect
Global Analog Interconnect
PSoC CORE
SRAM Interrupt Controller SROM Flash Sleep Watchdog
Port
PORT2{2}
Core (M8C) Clock Sources (Includes ILO)
Port Port
PORT1{0,1,4,5,7}
PORT0{3,4,5,7}
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Ref.
Analog Block Array
Digital Clocks
MACs
Decimator Type
System Resets
Internal Voltage Ref.
Analog Input Muxing
SYSTEM RESOURCES
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PowerPSoCFunctional Overview
PowerPSoC family incorporates programmable system-on-chip technology with best class power electronics controllers switching devices create easy power-system-on-chip solutions lighting applications. PowerPSoC family devices designed replace traditional MCUs, system ICs, numerous discrete components that surround them. PowerPSoC devices feature high performance power electronics including power FETs, hysteretic controllers, current sense amplifiers, PrISM/PWM modulators create complete power electronics solution power management. Configurable power, analog, digital, interconnect circuitry enables high level integration host industrial, commercial, consumer lighting applications. This architecture integrates programmable analog digital blocks enable user create customized peripheral configurations that match requirements each individual application. Additionally, device includes fast CPU, Flash program memory, SRAM data memory, configurable range convenient pinouts packages. PowerPSoC architecture, illustrated block diagrams, comprises five main areas: PSoC core, digital system, analog system, system resources, power peripherals which include power FETs, hysteretic controllers, current sense amplifiers, PrISM/PWM modulators. Configurable global busing combines device resources into complete custom system. PowerPSoC family devices have 10-port I/Os that connect global digital analog interconnects, providing access eight digital blocks analog blocks.
Programmable minimum time Floating load buck, boost, floating load buck-boost topology controller
PowerPSoC contains four hysteretic controllers. There hysteretic controller each channel device. reference inputs hysteretic controller provided reference DACs illustrated level block diagram page (see Figure 2-1). hysteretic control function output generated comparing feedback value thresholds. Going below lower threshold turns switch exceeding upper threshold turns switch shown Figure output current waveforms shown Figure 4-2. Figure 4-1. Generating Hysteretic Control Function Output
Lower Limit Comparator REF_A FN0.x Upper Limit Comparator REF_B Timer Modulation Enable Trip Function Hyst Timer
Power Peripherals
CY8CLED04D0X first product PowerPSoC family integrate power peripherals further integration your power electronics applications.The PowerPSoC family intelligent power controller used lighting applications that need traditional MCUs discrete power electronics support. power peripherals CY8CLED04D0X include four power MOSFETs with current ratings each. also integrates gate drivers that enable applications drive external MOSFETs higher current voltage capabilities. controller programmable threshold hysteretic controller, with user-selectable feedback paths that uses current mode floating load buck, boost, floating load buck/boost configurations. Figure 4-2. Current Waveforms
REF_B
ILED
REF_A
Hysteretic Controllers
hysteretic controllers provide cycle cycle switch control with fast transient response which simplifies system design requiring external compensation. hysteretic controllers include following features:
Hyst
Four independent channels configurable thresholds Wide switching frequency range from minimum on-time off-time circuits PowerPSoC prevent oscillations very high frequencies, which very destructive output switches.
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Side N-Channel FETs
internal side N-Channel FETs designed enhance system integration. side N-Channel FETs include following features:
modulator consists 12-bit block 4-bit (Delta Sigma Modulator) block. width PWM, width DMM, clock defines output frequency. duty cycle output dithered using block which user selectable resolution bits. 4.4.3 Mode Configuration
Drive capability Switching times (rise fall times) ensure high efficiency (more than 90%) Drain source voltage rating RDS(ON) ensure high efficiency Switching frequency
High resolution operation bits User programmable period from 65535 clocks Dedicated module enables customers core PSoC digital blocks other Interrupt rising edge output terminal count Precise phase control manage system current edges Phase synchronization among four channels output aligned left, right, center
External Gate Drivers
These gate drivers enable external FETs with higher current capabilities lower RDS(ON). external gate drivers directly drive MOSFETS that used switching applications. gate driver provides multiple programmable drive strength steps enable improved management. external gate drivers include following features.
Programmable drive strength options (25%, 50%, 75%, 100%) management Rise fall times with load
features down counter pulse width register. comparator output asserted when count value less than equal value pulse width register.
Current Sense Amplifier
Four high side current sense amplifiers provide differential sense capability sense voltage across current sense resistors lighting systems. current sense amplifier includes following features:
Dimming Modulation Schemes
There three dimming modulation schemes available with PowerPSoC. configurable modulation schemes are:
Operation with high common mode voltage High common mode rejection ratio Programmable bandwidth optimize system noise immunity
Precise Intensity Signal Modulation (PrISM) Delta Sigma Modulation Mode (DMM) Pulse Width Modulation (PWM)
4.4.1 PrISM Mode Configuration
High resolution operation bits Dedicated PrISM module enables customers core PSoC digital blocks other needs Clocking Selectable output signal density Reduced
off-chip resistor Rsense used high side current measurement shown Figure page output current sense amplifier goes Power Peripherals Analog Multiplexer where user selects which hysteretic controller route Table illustrates example values Rsense different currents. Table 4-1. Rsense Values Different Currents Load Current (mA) 1000 Typical Rsense
PrISM mode compares output pseudo-random counter with signal density value. comparator output asserts when count value less than equal value signal density register. 4.4.2 Mode Configuration
High resolution operation bits Configurable output frequency delta sigma modulator width trade repeat rates versus resolution Dedicated module enables customers PSoC digital blocks other uses Clocking
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Figure 4-3. High Side Current Measurement
CSP0
Rsense0
Built-in Switching Regulator
switching regulator used power voltage portion PowerPSoC) from input line. This regulator based upon peak current control loop which support output current. current being consumed PowerPSoC used power additional system peripherals. features built-in switching regulator include:
CSN0
CSP3
Rsense3
Power Peripheral Analog
Ability self power device from input line Small filter component sizes Fast response transients
CSN3
Figure 4-4. Built-in Switching Regulator
Voltage Comparators
There comparators that provide high speed comparator operation over voltage, over current, various other system event detections. example, comparators used zero crossing detection input line monitoring total current. Programmable internal analog routing enables these comparators monitor various analog signals. These comparators include following features:
Error Amplifier
SREGHVIN VREGIN
Logic Gate Drive Comparator
SREGSW SREGCSP SREGCSN SREGCOMP Ccomp SREGFB Rsense Rfb1
VREGOUT
Current Sense
High speed comparator operation: response time Programmable interrupt generation input offset voltage input bias currents
Rfb2 Rcomp
precision voltage comparators available. differential positive negative inputs comparators routed from analog multiplexer output goes digital multiplexer. programmable inverter used select output polarity. User selectable hysteresis enabled disabled trade-off noise immunity versus comparator sensitivity.
Analog Multiplexer
analog multiplexer used multiplex signals between power peripheral blocks. configures Power Peripherals Analog Multiplexer connections using memory mapped registers. analog multiplexer includes following features:
Reference DACs
reference DACs used generate points various analog modules such Hysteretic controllers comparators. reference DACs include following features:
Connect signals ensure needed flexibility Ensure signal integrity minimum signal corruption Configurability through Cypress PSoC Designer
8-bit resolution Guaranteed monotonic operation gain errors settling time
4.10 Digital Multiplexer
digital multiplexer used multiplex signals between power peripheral blocks.The Power Peripherals Digital Multiplexer configurable switching matrix that connects power peripheral digital resources. This Power Peripheral Digital Multiplexer independent main PSoC digital buses global interconnect PSoC core. digital multiplexer includes following features:
These DACs available provide programmable references various analog comparator functions controlled memory mapped registers. DAC[0:7] embedded hysteretic controllers required upper lower thresholds channel [8:13] connected Power Peripherals Analog Multiplexer provide programmable references comparator bank. These used trip points which enable over voltage, over current, other system event detection.
Connect signals ensure needed flexibility Configurability through Cypress PSoC Designer
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4.11 Function Pins (FN0[0:3])
function pins dedicated control pins used perform system level functions with power peripheral blocks PowerPSoC. These pins dynamically configurable, enabling them perform multitude input output functions. These I/Os have direct access input output voltage comparators, input hysteretic controller, output digital blocks device. function pins register mapped. microcontroller control read state these pins interrupt function. Some system benefits function are:
Figure 4-6. PowerPSoC Master/Slave Configuration
PowerPSoC (Slave
FN0(x)
Hysteretic Controller
PowerPSoC (Slave
Enabling higher voltage current-sense amplifier shown Figure Synchronizing dimming multiple PowerPSoC controllers shown Figure Programmable fail-safe monitor dedicated shutdown hysteretic controller shown Figure
PowerPSoC (Master)
FN0(0)
FN0(x)
Hysteretic Controller
FN0(1)
FN0(2) FN0(3) FN0(x)
PowerPSoC (Slave
Along with above functionality, these I/Os also provide interrupt functionality enabling intelligent system responses power control lighting system status. Figure 4-5. External Application
External
Hysteretic Controller
PowerPSoC (Slave
HVDD
Rsense
FN0(x)
Hysteretic Controller
VLED
PPSoC
DAC0 FN0(0) DAC1
Figure 4-7. Event Detection
External Gate Drive
Hysteretic Mode Controller
External
Event Detect
FN0(0)
Trip
Hysteretic Mode Controller
FN0(1) FN0(2) FN0(3) DAC6
Hysteretic Mode Controller
DAC7
External Gate Drive
External Gate Drive
Event Detect
FN0(3)
Trip
Hysteretic Mode Controller
External Gate Drive
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PSoC Core
PSoC core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. uses interrupt controller with vectors simplify programming real time embedded events. program execution timed protected using included Sleep Watchdog Timers (WDT) time protect program execution. Memory encompasses Flash program storage, SRAM data storage, EEPROM emulated using Flash. Program Flash uses four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate percent over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. clocks, together with programmable clock dividers system resource), provide flexibility integrate almost timing requirement into PowerPSoC device. PowerPSoC GPIOs provide connection CPU, digital, analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
There four digital blocks each row. This allows optimum choice system resources your application. Figure 5-1. Digital System Block Diagram
Configuration Input
BB00 DBB01 DCB02
CB03
Output Configuration
BB00 Configuration
Input
Configuration
Output
DB12
Analog System
analog system contains configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PowerPSoC analog functions (most available user modules) listed below.
Digital System
digital system contains eight digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Digital peripheral configurations include those listed below.
Analog-to-digital converters with 12-bit resolution, selectable incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (two with drive PSoC core resource) 1.3V reference system resource) Modulators Correlators Peak detectors Many other topologies possible
DALI DMX512 Counters bit) Timers bit) UART 8-bit with selectable parity master slave slave multi-master Cyclical redundancy checker/generator bit) IrDA Pseudo random sequence generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller.
Analog blocks arranged column three, which includes (Continuous Time) (Switched Capacitor) blocks, shown Figure page
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Figure 5-2. Analog System Block Diagram
P0[7] P0[4]
Additional System Resources
System resources provide additional capability useful complete systems. Additional resources include multiplier, decimator, voltage detection, power reset. Brief statements describing merits each resource follow.
P0[5] P1[4] P0[3]
P1[7]
P1[0]
multiply accumulates (MACs) provide fast 8-bit multipliers with 32-bit accumulate, assist both general math digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (power reset) circuit eliminates need system supervisor. Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. designer generate additional clocks using digital PSoC blocks clock dividers. module provides communication over wires. Slave, master, multi-master applications supported. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. Versatile analog multiplexer system.
P1[5]
P1[1]
P2[2] Analog Right Array Input Configuration
ACI0[1:0] ACI1[1:0]
Analog Left
ACM0
ACol1Mux ACol0Mux
ACM1
BCol1Mux
SplitMux
Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21
Interface Digital System
AGND=VBG
Reference Generators
Bandgap
Microcontroller Interface (Address Bus, Data Bus, Etc.)
Analog Multiplexer System
Analog connects every GPIO ports Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. split into sections simultaneous dual-channel processing. additional analog input multiplexer provides second path bring Port pins analog array. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
Track pad, finger sensing Crosspoint connection between combinations
When designing capacitive sensing applications, refer latest signal-to-noise signal level requirements application notes, found http://www.cypress.com Design Resources Application Notes. general, unless otherwise noted relevant application notes, minimum signal-to-noise ratio (SNR) CapSense applications 5:1.
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Applications
following figures show examples applications which PowerPSoC family devices adds intelligent power control power applications. Figure 6-1. Lighting with RGGB Color Mixing Configured Floating Load Buck Converter
HVDD RSENSE HVDD RSENSE HVDD RSENSE HVDD RSENSE
Dual mode Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Oscillator Power
Master Slave
Configurable Analog
Flash, RAM,
Core
Configurable Digital Blocks
Auxiliary Power Regulator
Figure 6-2. Lighting with RGBA Color Mixing Driving External MOSFETS Floating Load Buck Converter
HVDD
SENSE
HVDD
SENSE
HVDD
SENSE
HVDD
SENSE
Dual mode Hysteretic
References DAC1 DAC2 PrISM
Gate Drive
Dual mode Hysteretic
References DAC1 DAC2 PrISM
Gate Drive
Dual mode Hysteretic
References DAC1 DAC2 PrISM
Gate Drive
Dual mode Hysteretic
References DAC1 DAC2 PrISM
Gate Drive
Oscillator Power
Master Slave
Configurable Analog
Flash
Core
Configurable Digital Blocks
Auxiliary Power Regulator
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
Figure 6-3. Lighting with Single Channel Boost Driving Three Floating Load Buck Channels
HVDD SENSE
SENSE
SENSE
SENSE
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Hysteretic
Hysteretic references DAC1 DAC2 PrISM
Oscillator Power
Master Slave
Configurable Analog
Flash, RAM,
Core
Configurable Digital Blocks
Auxiliary Power Regulator
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PowerPSoC Device Characteristics
There major groups devices PowerPSoC family. group 4-channel 56-pin other 3-channel 56-pin QFN. These summarized following table. Table 7-1. PowerPSoC Device Characteristics
Device Group CY8CLED04D01-56LTXI CY8CLED04D02-56LTXI CY8CLED04G01-56LTXI CY8CLED03D01-56LTXI CY8CLED03D02-56LTXI CY8CLED03G01-56LTXI Internal Power FETs 4X1.0A 4X0.5A 3X1.0A 3X0.5A External Gate Drivers Digital Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Flash Size
Getting Started
quickest understand PowerPSoC device read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PowerPSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming information, refer PowerPSoC Technical Reference Manual. up-to-date ordering, packaging, electrical specification information, latest PowerPSoC device data sheets www.cypress.com.
cannot find answer your question, call technical support 1-800-541-4763.
Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PowerPSoC family.
Application Notes
Application notes excellent introduction wide variety possible PowerPSoC designs. Layout Guidelines, Thermal Management Firmware Design Guidelines some topics covered. view PowerPSoC application notes, http://www.cypress.com.
PSoC Designer Software Subsystems
9.1.1 System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PowerPSoC Intelligent Drivers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PowerPSoC device. 9.1.2 Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PowerPSoC blocks. Examples user modules Current Sense Amplifiers, PrISM, PWM, DMM, Floating Load Buck, Boost. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application.
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PowerPSoC development. Cypress Online Store site http://www.cypress.com, click Online Store shopping cart icon, click PowerPSoC (Power Programmable System-on-Chip) view current list available items.
Training
Free PowerPSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PowerPSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Technical Support
PowerPSoC application engineers take pride fast accurate response. They reached with 24-hour guaranteed response
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. 9.1.3 Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools. 9.1.4 Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PowerPSoC family devices. products allow create complete programs PowerPSoC family devices. optimizing compilers provide features tailored PowerPSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. 9.1.5 Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PowerPSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. 9.1.6 Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Designing with User Modules
development process PowerPSoC device differs from that traditional fixed function microprocessor. configurable power, analog, digital hardware blocks give PowerPSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PowerPSoC Blocks, have ability implement wide variety user selectable functions. PowerPSOC development process summarized following four steps: Select Components Configure Components Organize Connect Generate, Verify Debug Select Components. chip-level view components called "user modules". User modules make selecting implementing peripheral devices simple come power, analog, digital, mixed signal varieties. standard user module library contains over common peripherals such Current Sense Amplifiers, PrISM, PWM, DMM, Floating Buck, Boost, ADCs, DACs, Timers, Counters, UARTs, other common peripherals such DTMF generators Bi-Quad analog filter sections. Configure Components. Each components selected establishes basic register settings that implement selected function. They also provide parameters allowing precise configuration your particular application. example, User Module configures more digital PSoC blocks, each bits resolution. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter other information needed successfully implement your design. Organize Connect. Signal chains built chip level interconnecting user modules each other pins. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources. Generate, Verify, Debug. When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides high level user module functions. chip-level designs generate software based your design. chip-level view provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. complete code development environment allows development customization your applications assembly language, both.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PowerPSoC devices.
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last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations, external signals.
Acronym ISSP IPOR MOSFET PPOR PowerPSoC PrISM PSoC RGBA RGGB SRAM UART Input/Output
Description In-System Serial Programming Imprecise Power Reset Light Emitting Diode Least-Significant Voltage Detect Microcontroller Metal-Oxide-Semiconductor Field Effect Transistor Most-Significant Chip Debugger Program Counter Power Reset Precision Power Reset Power Programmable System-on-ChipPrecise Intensity Signal Modulation Programmable System-on-ChipPulse Width Modulator Quad Flat leads Package Red, Green, Blue, Amber Red, Green, Green, Blue Switched Capacitor Serial Peripheral Interface Static Random Access Memory Technical Reference Manual Universal Asynchronous Receiver/Transmitter Universal Serial Watch Timer
Document Conventions
11.1 Acronyms Used
following table lists acronyms that used this document. Acronym DALI DTMF EEPROM GPIO Description Alternating Current Analog-to-Digital Converter Application Programming Interface Central Processing Unit Current Sense Amplifier Continuous Time Digital-to-Analog Converter Digital Addressable Lighting Interface Direct Current Delta Sigma Modulation Mode Digital Multiplexing Delta Sigma Modulator Dual-Tone Multi Frequency External Crystal Oscillator Electrically Erasable Programmable Read-Only Memory ElectroMagnetic Interference Frequently Asked Questions Field Effect Transistor Full Scale Range General Purpose Graphical User Interface Human Body Model Integrated Circuit In-Circuit Emulator Integrated Development Environment Internal Low-speed Oscillator Internal Main Oscillator
11.2 Units Measure
units measure table located Electrical Specifications section. Table 14-1 page lists abbreviations used measure PowerPSoC devices.
11.3 Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated decimal.
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
Information
12.1 CY8CLED04D0x 56-Pin Part Pinout (without OCD)
CY8CLED04D01 CY8CLED04D02 PowerPSoC devices available with following pinout information. Every port (labeled with "FN0") capable Digital I/O. Table 12-1. CY8CLED04D0x 56-Pin Part Pinout (QFN)
Digital
Rows
Type
Analog Power Columns Peripherals
Name P1[0]
Description
Figure 12-1. CY8CLED04D0x 56-Pin PowerPSoC Device
GPIO/I2C (secondary), ISSP primary P2[2] GPIO/Direct Switch connection P0[3] GPIO/Ainput(coI0) Aoutput (coI0) P0[5] GPIO/Ainput(coI0) Aoutput (coI1) Capsense P0[7] GPIO/Connects Analog Column Capsense P1[1] GPIO/I2C SCLK (secondary) ISSP primary P1[5] GPIO/I2C SDATA (Primary) P1[7] GPIO/ SCLK (Primary) Digital Ground Connect Connect Connect Connect XRES External Reset Digital Power Supply Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSA2 CSP2 Current Sense Positive Input Power Supply CSA2 CSP3 Current Sense Positive Input Power Supply CSA3 CSN3 Current Sense Negative Input SREGCOMP Voltage Regulator Error Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator SREGHVIN Switch Mode Regulator GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground PGND3 PGND2 PGND1 Power Ground External Side Gate Driver Power Switch Power Ground External Side Gate Driver Power Switch Power Switch External Side Gate Driver Power Ground Power Switch External Side Gate Driver Power FETGround Gate Driver Ground
View
P1[4] P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] XRES
Exposed
AVSS AVDD CSN2 CSP2 CSP3 CSN3 SREGCOMP SREGFB SREGCSN SREGCSP
Connect Exposed PGNDx
Digital
Type
Analog Power Rows Columns Peripherals
Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1
CSN1 P0[4] P1[4]
PGND0 GDVSS
Gate Driver Power Supply Function Function Function Function Current Sense Negative Input Current Sense Positive Input Power Supply CSA0 Current Sense Positive Input Power Supply CSA1 Current Sense Negative Input GPIO/Connects Analog Column (1), connects bandgap output Digital Power Supply Digital Ground GPIO External Clock Input
Document Number: 001-46319 Rev.
SREGSW SREGHVIN
PGND0 PGND1 PGND2 PGND3 GDVSS GDVDD
Description
Page
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
12.2 CY8CLED04G01 56-Pin Part Pinout (without OCD)
CY8CLED04G01 PowerPSoC device available with following pinout information. Every port (labeled with "FN0") capable Digital I/O. Table 12-2. CY8CLED04G01 56-Pin Part Pinout (QFN)
Digital
Rows
Type
Analog Power Columns Peripherals
Name P1[0]
Description
Figure 12-2. CY8CLED04G01 56-Pin PowerPSoC Device
GPIO/I2C (secondary), ISSP primary P2[2] GPIO/Direct Switch connection P0[3] GPIO/Ainput(coI0) Aoutput (coI0) P0[5] GPIO/Ainput(coI0) Aoutput (coI1) Capsense P0[7] GPIO/Connects Analog Column Capsense P1[1] GPIO/I2C SCLK (secondary) ISSP primary P1[5] GPIO/I2C SDATA (Primary) P1[7] GPIO/ SCLK (Primary) Digital Ground Connect Connect Connect Connect XRES External Reset Digital Power Supply Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSP2 Current Sense Positive Input Power Supply CSA2 CSP3 Current Sense Positive Input Power Supply CSA3 CSN3 Current Sense Negative Input SREGCOMP Voltage Regulator Error Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator SREGHVIN Switch Mode Regulator GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground Digital PGND3 DNC[1] PGND2 DNC[1] DNC[1] PGND1 DNC[1] Power Ground External Side Gate Driver Connect Power Ground External Side Gate Driver Connect Connect External Side Gate Driver Power Ground Connect External Side Gate Driver Power Ground Gate Driver Ground
View
P1[4] P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] XRES
Exposed
SREGCOMP SREGFB SREGCSN
Connect Exposed PGNDx
Type
Analog Power Rows Columns Peripherals
Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1
SREGHVIN
SREGCSP SREGSW
PGND0 PGND1 PGND2 PGND3 GDVSS GDVDD
Description Gate Driver Power Supply Function Function Function Function Current Sense Negative Input Current Sense Positive Input Power Supply CSA0 Current Sense Positive Input Power Supply CSA1 Current Sense Negative Input GPIO/Connects Analog Column (1), connects bandgap output Digital Power Supply Digital Ground GPIO External Clock Input
CSN1 P0[4] P1[4]
PGND0 GDVSS
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
12.3 CY8CLED04DOCD1 56-Pin Part Pinout (with OCD)
CY8CLED04DOCD1 PowerPSoC device available with following pinout information. Every port (labeled with "FN0") capable Digital I/O. Table 12-3. CY8CLED04DOCD1 56-Pin Part Pinout (QFN)
Digital Type
Analog Power Rows Columns Peripherals
Name P1[0]
Description
Figure 12-3. CY8CLED04DOCD1 56-Pin PowerPSoC Device
GPIO/I2C SDATA (secondary) ISSP primary P2[2] GPIO/Direct Switch connection P0[3] GPIO/Ainput (coIO) Aoutput (coIO) P0[5] GPIO/Ainput (coIO) Aoutput (coIO) Capsense P0[7] GPIO, connects Analog Column Capsense P1[1] GPIO/I2C SCLK (secondary) ISSP primary P1[5] GPIO/I2C SDATA (Primary) P1[7] GPIO/ SCLK (Primary) Digital Ground OCDE Chip Debugger Port OCDO Chip Debugger Port CCLK Chip Debugger Port HCLK Chip Debugger Port XRES External Reset Digital Power Supply Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSP2 Current Sense Positive Input Power Supply CSA2 CSP3 Current Sense Positive Input Power Supply CSA3 CSN3 Current Sense Negative Input SREGCOMP Voltage Regulator Error Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator SREGHVIN Switch Mode Regulator GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground Digital PGND3 PGND2 PGND1 PGND0 GDVSS Power Ground External Side Gate Driver Power Switch Power Ground External Side Gate Driver Power Switch Power Switch External Side Gate Driver Power Ground Power Switch External Side Gate Driver Power Ground Gate Driver Ground
View
CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS CSN1 CSP1 CSP0 P1[4] P0[4] P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] OCDE OCDO CCLK HCLK XRES
Exposed
AVSS AVDD CSN2 CSP2 CSP3
CSN3 SREGCOMP SREGFB
Connect Exposed PGNDx
Type
Analog Power Rows Columns Peripherals
Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1
CSN1 P0[4] P1[4]
Gate Driver Power Supply Function Function Function Function Current Sense Negative Input Current Sense Positive Input Power Supply CSA0 Current Sense Positive Input Power Supply CSA1 Current Sense Negative Input GPIO/Connects Analog Column (1), bandgap output Digital Power Supply Digital Ground GPIO External Clock Input
Document Number: 001-46319 Rev.
SREGSW SREGHVIN
SREGCSN SREGCSP
PGND0 PGND1 PGND2 PGND3 GDVSS GDVDD
Description
Page
Feedback
CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
12.4 CY8CLED03D0x 56-Pin Part Pinout (without OCD)
CY8CLED03D01 CY8CLED03D02 PowerPSoC devices available with following pinout information. Every port (labeled with "FN0") capable Digital I/O. Table 12-4. CY8CLED03D0x 56-Pin Part Pinout (QFN)
Type Digital Analog
Power Rows Columns Peripherals
Name P1[0]
Description
Figure 12-4. CY8CLED03D0x 56-Pin PowerPSoC Device
GPIO/ (secondary), ISSP primary P2[2] GPIO/Direct Switch connection P0[3] GPIO/Ainput(coI0) Aoutput (coI0) P0[5] GPIO/Ainput(coI0) Aoutput (coI1) Capsense P0[7] GPIO/Connects Analog Column Capsense P1[1] GPIO/I2C SCLK (secondary) ISSP primary P1[5] GPIO/I2C SDATA (Primary) P1[7] GPIO/ SCLK (Primary) Digital Ground Connect Connect Connect Connect XRES External Reset Digital Power Supply Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSA2 CSP2 Current Sense Positive Input Power Supply CSA2 DNC[1] Connect DNC[1] Connect SREGCOMP Voltage Regulator Error Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator SREGHVIN Switch Mode Regulator GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground Digital
Rows
View
P1[4] P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] XRES
Exposed
AVSS AVDD CSN2 CSP2 SREGCOMP SREGFB SREGCSN SREGCSP
Connect Exposed PGNDx
Type
Analog Power Columns Peripherals
Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1
SREGSW SREGHVIN
PGND0 PGND1 PGND2 PGND3 GDVSS GDVDD
Description Gate Driver Power Supply Function Function Function Function Current Sense Negative Input Current Sense Positive Input Power Supply CSA0 Current Sense Positive Input Power Supply CSA1 Current Sense Negative Input GPIO/Connects Analog Column (1), connects bandgap output Digital Power Supply Digital Ground GPIO External Clock Input
PGND3 DNC[1] DNC[1] PGND2 PGND1 PGND0 GDVSS
Power Ground Connect Connect Power Ground External Side Gate Driver Power Switch Power Switch External Side Gate Driver Power Ground Power Switch External Side Gate Driver Power FETGround Gate Driver Ground
CSN1 P0[4] P1[4]
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
12.5 CY8CLED03G01 56-Pin Part Pinout (without OCD)
CY8CLED03G01 PowerPSoC device available with following pinout information. Every port (labeled with "FN0") capable Digital I/O. Table 12-5. CY8CLED03G01 56-Pin Part Pinout (QFN)
Digital
Rows
Type
Analog Power Columns Peripherals
Name P1[0]
Description
Figure 12-5. CY8CLED03G01 56-Pin PowerPSoC Device
GPIO/I2C (secondary), ISSP primary P2[2] GPIO/Direct Switch connection P0[3] GPIO/Ainput(coI0) Aoutput (coI0) P0[5] GPIO/Ainput(coI0) Aoutput (coI1) Capsense P0[7] GPIO/Connects Analog Column Capsense P1[1] GPIO/I2C SCLK (secondary) ISSP primary P1[5] GPIO/I2C SDATA (Primary) P1[7] GPIO/ SCLK (Primary) Digital Ground Connect Connect Connect Connect XRES External Reset Digital Power Supply Digital Ground AVSS Analog Ground AVDD Analog Power Supply CSN2 Current Sense Negative Input CSP2 Current Sense Positive Input Power Supply CSA2 DNC[1] Connect DNC[1] Connect SREGCOMP Voltage Regulator Error Comp SREGFB Regulator Voltage Mode Feedback Node SREGCSN Current Mode Feedback Negative SREGCSP Current Mode Feedback Positive SREGSW Switch Mode Regulator SREGHVIN Switch Mode Regulator GDVDD Gate Driver Power Supply GDVSS Gate Driver Ground Digital PGND3 DNC[1] DNC[1] PGND2 DNC[1] DNC[1] PGND1 DNC[1] Power Ground Connect Connect Power Ground External Side Gate Driver Connect Connect External Side Gate Driver Power Ground Connect External Side Gate Driver Power Ground Gate Driver Ground
View
P1[4] P0[4] CSN1 CSP1 CSP0 CSN0 FN0[3] FN0[2] FN0[1] FN0[0] GDVDD GDVSS P1[0] P2[2] P0[3] P0[5] P0[7] P1[1] P1[5] P1[7] XRES
Exposed
AVSS AVDD CSN2 CSP2 SREGCOMP SREGFB SREGCSN SREGCSP
Connect Exposed PGNDx
Type
Analog Power Rows Columns Peripherals
Name GDVDD FN0[0] FN0[1] FN0[2] FN0[3] CSN0 CSP0 CSP1
CSN1 P0[4] P1[4]
PGND0 GDVSS
Gate Driver Power Supply Function Function Function Function Current Sense Negative Input Current Sense Positive Input Power Supply CSA0 Current Sense Positive Input Power Supply CSA1 Current Sense Negative Input GPIO/Connects Analog Column (1), connects bandgap output Digital Power Supply Digital Ground GPIO External Clock Input
Note Connect (DNC) pins must left unconnected, floating. Connecting these pins power ground cause improper operation failure device.
Document Number: 001-46319 Rev.
SREGSW SREGHVIN
PGND0 PGND1 PGND2 PGND3 GDVSS GDVDD
Description
Page
Feedback
CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
Register General Conventions
13.1 Abbreviations Used
register conventions specific this section listed Table 13-1. Table 13-1. Register Conventions Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
13.2 Register Naming Conventions
register naming convention specific PSoC core section PowerPSoC blocks their registers <Prefix>mn<Suffix> where index, column index Therefore, ASD13CR3 register analog PowerPSoC block column register naming convention specific power peripheral section PowerPSoC blocks their registers <Prefix>x<Suffix> where number channel Therefore, CSA0_CR register power peripheral PowerPSoC block Current Sense Amplifier, channel
13.3 Register Mapping Tables
PowerPSoC device total register address space bytes. register space also referred space broken into parts. Flag register (CPU_F) determines which bank user currently When set, user said "extended" address space "configuration" registers. More detailed description Registers found PowerPSoC TRM.
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13.4 Register Bank Table
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 FN0DR FN0IE FN0GS FN0DM2 Addr (0,Hex) Access Name DPWM0PCF DPWM0PDH DPWM0PDL DPWM0PWH DPWM0PWL DPWM0PCH DPWM0PCL DPWM0GCFG DPWM1PCF DPWM1PDH DPWM1PDL DPWM1PWH DPWM1PWL DPWM1PCH DPWM1PCL DPWM1GCFG DPWM2PCF DPWM2PDH DPWM2PDL DPWM2PWH DPWM2PWL DPWM2PCH DPWM2PCL DPWM2GCFG DPWM3PCF DPWM3PDH DPWM3PDL DPWM3PWH DPWM3PWL DPWM3PCH DPWM3PCL DPWM3GCFG AMX_IN AMUX_CFG ARF_CR CMP_CR0 ASY_CR CMP_CR1 PAMUX_S1 PAMUX_S2 PAMUX_S3 PAMUX_S4 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 DPWM0PCFG DPWM1PCFG DPWM2PCFG DPWM3PCFG DPWMINTFLG DPWMINTMSK DPWMSYNC Addr (0,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) Access Name VDAC0_CR VDAC0_DR0 VDAC0_DR1 VDAC1_CR VDAC1_DR0 VDAC1_DR1 VDAC2_CR VDAC2_DR0 VDAC2_DR1 VDAC3_CR VDAC3_DR0 VDAC3_DR1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) Access
ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3
PDMUX_S1 PDMUX_S2 PDMUX_S3 PDMUX_S4 PDMUX_S5 PDMUX_S6 CHBOND_CR DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0
VDAC6_CR VDAC6_DR0 VDAC6_DR1 VDAC4_CR VDAC4_DR0 VDAC4_DR1 VDAC5_CR VDAC5_DR0 VDAC5_DR1 MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
13.5 Register Bank Table: User Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 FN0DM0 FN0DM1 FN0IC0 FN0IC1 Addr (1,Hex) Access Name CSA0_CR Addr (1,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (1,Hex) Access Name CMPCH0_CR CMPCH2_CR CMPCH4_CR CMPCH6_CR CMPBNK8_CR CMPBNK9_CR CMPBNK10_CR CMPBNK11_CR CMPBNK12_CR CMPBNK13_CR Addr (1,Hex) Access
CSA1_CR
CSA2_CR
CSA3_CR
ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU HYSCTLR0CR HYSCTLR1CR HYSCTLR2CR HYSCTLR3CR MUX_CR0 MUX_CR1 MUX_CR2 SREG_TST OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN DBB10IN DBB10OU DBB11FN DBB01IN DBB01OU DCB12FN DCB12IN DCB12OU DCB13FN DCB13IN DCB13OU
CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2
DEC_CR2 IMO_TR ILO_TR BDG_TR
TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 GDRV0_CR GDRV1_CR GDRV2_CR GDRV3_CR
AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1
CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
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Electrical Specifications
This section presents electrical specifications CY8CLED04D0X, CY8CLED03D0X, CY8CLED04G01, CY8CLED03G01 PowerPSoC device family. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40°C 85°C 115°C, except where noted. Table 14-1 lists units measure that used this section. Table 14-1. Units Measure Symbol Unit Measure degrees Celsius decibels Hertz peak-to-peak sigma:one standard deviation volts ohms 1024 bytes parts million samples second watts amperes Symbol Kbit Vrms Unit Measure 1024 bits kilohertz kilohms megahertz megaohms microamperes microfarads microhenrys microseconds microvolts microvolts root-mean-square microwatts Symbol Unit Measure milliampere millisecond millivolts milliwatts nanoamperes nanoseconds nanovolts picoamperes picofarads picoseconds femtofarads
14.1 Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. user guidelines production tested. Symbol TSTG Description Storage Temperature +115 Units Notes Higher storage temperatures reduces data retention time. Recommended storage temperature 50°C. 115°C Relative VSS, AVSS, GDVSS respectively Applies only GPIO pins PGNDx connected GDVSS
VDD, AVDD, GDVDD VIO2 VFET
Ambient Temperature with Power Applied Supply Voltage VDD, AVDD, GDVDD Input Voltage
-0.5 -0.5 -1.0
+6.0
Voltage Applied Tri-state Maximum Voltage from Power Switch (SWx) Power Ground (PGNDx) VCSP,VCSN Maximum Voltage applied pins VSENSE Maximum Input Differential Voltage across input IMAIO Maximum Current into Port Configured Analog Driver IMIO Maximum Current into Port Function
Note Stresses beyond "Absolute Maximum Ratings" cause permanent damage device. system designer must ensure that Absolute Maximum Ratings NEVER exceeded. Functional operation implied under conditions beyond "Electrical Characteristics", listed page onwards. Extended exposure "Absolute Maximum Ratings" affect device reliability.
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Symbol tREGIN tHVDD
Description Latch current Electrostatic Discharge Voltage High Voltage Supply Ramp Time (SREGHVIN pin) High Voltage Supply Ramp Time (CSPx pins)
2000
Units
Notes JESD78A Conformal Human Body Model ESD.
Figure 14-1. High Voltage Supply Ramp Time (SREGHVIN pin)
VREGIN
14.2 Operating Temperature
Symbol Description Ambient Temperature Junction Temperature +115 Units Notes 115°C
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Electrical Characteristics
15.1 System Level
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. These design guidance only. Table 15-1. System Level Operating Specifications Symbol tD,MAX Description Circuit Switching Frequency Range Hysteretic Control Loop Maximum Delay Time from Input State Change Output Duty Cycle Hysteretic Controllers Power Converter Efficiency 0.02 Units Notes
HVDD 24V, 0.25 HVDD 24V,
15.2 Chip Level
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Note PowerPSoC Technical Reference Manual more information DPWMxPCF register Table 15-2. Chip Level Specifications Symbol VDD, AVDD, GDVDD HVDD IVDD Description Digital, Analog, Gate Driver Supply Voltage Range High Voltage Supply Voltage Range Supply Current (VDD pins), 4.75 5.25 Units Notes should powered from same source. Applies High Voltage pins CSPx SREGHVIN. pins need same voltage level. Conditions 25°C, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. Conditions 25°C, Internal Power External Gate Driver MHz, 25°C, Built-in Switching Regulator disabled, DPWMxPCF Power Peripherals disabled, analog power 115°C, Built-in Switching Regulator disabled, DPWMxPCF Power Peripherals disabled, analog power
IAVDD IGDVDD
Supply Current(AVDD pin) Supply Current Channel(GDVDD pins) Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.
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Table 15-3. Chip Level Specifications Symbol fIMO24 fCPU1 fBLK f32K1 Jitter32k Jitter24M1 Description Internal Main Oscillator Frequency Frequency Digital PSoC Block Frequency Internal Low-Speed Oscillator Frequency Period Jitter Period Jitter (IMO) Peak-to-Peak 23.04 0.093 24.96 24.96 49.92[3] Units Refer "PSoC Core Digital Block Specifications" page Notes
Figure 15-1. Period Jitter (IMO) Timing Diagram
15.3 Power Peripheral Side N-Channel
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-4. Side N-Channel Specifications Symbol VDS,INST IDMAX Description Operating Drain Source Voltage Instantaneous Drain Source Voltage Average Drain Current Maximum Instantaneous Repetitive Pulsed Current Units CY8CLED03/4D01 devices CY8CLED03/4D02 devices Less than duty cycle average current 0.1MHz. CY8CLED03/4D01 devices Less than duty cycle average current 0.5A, 0.1MHz. CY8CLED03/4D02 devices GDVDD 25°C CY8CLED03/4D01 devices 0.5A, GDVDD 25°C CY8CLED03/4D02 devices 25°C 115°C Notes
RDS(ON)
Drain Source resistance
6.25
IDSS ISFET
Switching Node PGND Leakage Supply Current Channel (Internal Gate Driver)
Note individual user module data sheets information maximum frequencies user modules.
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Table 15-5. Side N-Channel Specifications Symbol Rise Time Fall Time Description Units Notes
Figure 15-2. Side N-Channel Test Circuit IDSS,
INPUT
15.4 Power Peripheral External Power Driver
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. Typical parameters apply 25°C. These design guidance only. Table 15-6. Power Driver Specifications Symbol VOHN VOLN ISFETDRV Description 0.45 Units =100 =100 GDVDD Notes N-Channel Driver Output Voltage -Drive 0.45 High N-Channel Driver Output Voltage -Drive Supply Current Channel External Driver
Table 15-7. Power Driver Specifications Symbol tp(LH) tp(HL) Rise Time Fall Time Propagation Delay (Low-to-High) Propagation Delay (High-to-Low)) Description Units GDVDD Notes
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15.5 Power Peripheral Hysteretic Controller
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-8. Hysteretic Controller Specifications Symbol VICM ISHYST Description Comparator Input Offset Voltage Input Common Mode Voltage Range Hysteresis Voltage Supply Current Hysteretic Controller Units Comparator Internal Hysteresis VICM 1.5V 2.5V Includes Power Peripheral Comparators Reference DAC, Notes VICM VICM
Table 15-9. Hysteretic Controller Specifications Symbol Description MONOSHOT<1:0> MONOSHOT<1:0> MONOSHOT<1:0> MONOSHOT<1:0> Units Timers Disabled Notes tOFF Minimum ON/OFF timer
15.6 Power Peripheral Comparator
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-10. Comparator Specifications Symbol VHYS VOVDRV ISCOMP Description Input Voltage Range Comparator Input Offset Voltage Hysteresis Voltage Overdrive Voltage Supply Current Comparator Units VICM VICM 2.5V VICM 1.5V 1.5V VICM 2.5V Notes
VICM,COMP Comparator Input Common Mode Voltage Range
Table 15-11. Comparator Specifications Symbol Description Comparator Delay Time (FN0x FN0x pin) Units Notes VOVDRV 5mV, 10pF
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Figure 15-3. Comparator Timing Diagram
15.7 Power Peripheral Current Sense Amplifier
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. Typical parameters apply HVDD 25°C. These design guidance only. Table 15-12. Current Sense Amplifier Specifications Symbol VICM Description Input Common Mode Voltage Operating Range Units Notes Either terminal amplifier must exceed this range functionality Absolute Maximum Rating VSENSE should never exceeded. Absolute Maximum Ratings page VSENSE VSENSE Enabling causes incremental draw AVDD rail.
VICM(Tolerant) Functional Operating Range
VSENSE IS,CSA IBIASP IBIASN PSRHV VIOS CIN_CSP CIN_CSN
Input Differential Voltage Range Supply Current Input Bias Current Input Bias Current Power Supply Rejection (CSP pin) Gain Input Offset Input Capacitance Input Capacitance
19.7
20.3
Table 15-13. Current Sense Amplifier Specifications Symbol tSETTLE tPOWERUP Description Output Settling Time Final Value Power Time Final Value Units Notes
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Figure 15-4. Current Sense Amplifier Timing Diagram
VINPUT VINPUT VINPUT -150 VCSP SETTLE SETTLE tDELAY ACTIVATE
VCSP tPOWERUP K*25 Valid K*100
time
15.8 Power Peripheral PWM/PrISM/DMM Specification Table
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. Typical parameters apply 25°C. These design guidance only. PowerPSoC Technical Reference Manual more information PWM/PrISM/DMM. Table 15-14. PWM/PrISM/DMM Specifications Symbol IS,Modulation Description Supply Current PWM, PrISM, Units Notes
Table 15-15. PWM/PrISM/DMM Specifications Symbol Mode fRANGE16 fRANGE8 PrISM Mode fRANGE Mode fRANGE,Dimming Dimming Frequency Range 24,000,000/ (256*Max Period) 48,000,000/(Mi Period) Period: (Right Aligned), (Center Aligned), 4(Left Aligned) Period: (Right Aligned), 8190 (Center Aligned), (Left Aligned) PrISM Output Frequency Range 24,000,000/(256*(2M-1) 48,000,000/2 Min: 255, Maqx: Output Frequency Range 16-bit period Output Frequency Range 8-bit period 24,000,000/(256*216) 24,000,000/(256*28) 48,000,000/216 48,000,000/28 Period Value Min: 255, Max: Period Value Min: 255, Max: Description Units Notes
fRANGE,Dither
Dither Frequency Range
(1/16)*(Min fRANGE,Dimming)
(15/16)*(Max fRANGE,Dimming)
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15.9 Power Peripheral Reference Specification
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. Typical parameters apply 25°C. These design guidance only. Table 15-16. Reference Specifications Symbol ISDAC AERROR OSERROR VDACFS VDACMM Description Supply Current Reference Integral Linearity Differential Linearity Gain Error Offset Error Fullscale Voltage Reference Fullscale Voltage Mismatch (Pair Reference DACs Even Odd) -1.5 -0.5 Units Mode Mode Mode Mode1 Mode Mode Mode Mode1 Mode Mode Mode Mode Notes Mode Mode1
Table 15-17. Reference Specifications Symbol tSETTLE tSTARTUP Description Output settling time final value Startup time within final value 10.5 Units Notes Mode Mode1 Mode Mode1
15.10 Power Peripheral Built-in Switching Regulator
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115oC. Typical parameters apply 25°C. These design guidance only. Table 15-18. Built-in Switching Regulator Specifications Symbol VREGIN VREGOUT VRIPPLE VUVLO ILOAD IS,BSR ISB,HV IINRUSH LineREG LoadREG PSRR EBSR Description Input Supply Voltage Range Output Voltage Range Output Ripple Under Voltage Lockout Voltage Output Current -Active Mode Supply Current Built-in Switching Regulator Standby Current (High Voltage) Inrush Current Line Regulation Load Regulation Power Supply Rejection Ratio Built-in Switching Regulator Efficiency 0.01 Units ILOAD VREGIN VREGIN 24V, ILOAD VRIPPLE 0.2*VREGIN, fRIPPLE VREGIN ILOAD VREGIN VUVLO: Power Down Mode VREGIN VUVLO: Active Mode Notes Absolute Maximum Ratings page Does include VRIPPLE
RDS(ON),PFET PFET Drain Source resistance
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Table 15-19. Built-in Switching Regulator Specifications Symbol tRESP tREGIN tPD_ACT tACT_PD Description Switching Frequency 0.956 Response time within 0.5% final value Startup Time Power Down Time High Voltage Supply Ramp Time (SREGHVIN pin) Time from Power Down Active Mode Time from Active Mode Power Down Mode 1.04 Units Notes Absolute Maximum Ratings page
Table 15-20. Built-in Switching Regulator Recommended Components Component Name Rfb1 Rfb2 Ccomp Rcomp Rsense Value 0.698 2200 Unit Notes Tolerance better Tolerance better Tolerance better Tolerance better Tolerance better, Saturation current rating higher Tolerance better Ceramic, grade, Minimum Ceramic, grade
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Figure 15-5. Built-in Switching Regulator Timing Diagram
VREGIN VREGIN
VREGOUT
tHVDD
Powerdown MODE
tPD_ACT
Time
Figure 15-6. Built-in Switching Regulator
Error Amplifier
SREGHVIN VREGIN
Logic Gate Drive Comparator
SREGSW SREGCSP SREGCSN SREGCOMP Ccomp SREGFB Rsense Rfb1
VREGOUT
Current Sense
Rfb2 Rcomp
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15.11 General Purpose IO/Function
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-21. GPIO/FN0 Specifications Symbol COUT Description Pull Resistor Pull Down Resistor High Output Level Output Level Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output 0.75 Units Notes
maximum combined budget maximum combined budget
Gross tested 25°C. 25°C.
Table 15-22. GPIO/FN0 Specifications Symbol fGPIO tRiseF tFallF tRiseS tFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode
Figure 15-7. GPIO/Function Timing Diagram
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15.12 PSoC Core Operational Amplifier Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched Capacitor PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Table 15-23. Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 35.0 Units V/°C Gross tested 25°C. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA Input Leakage Current (Port analog pins) Input Capacitance (Port analog pins) Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias)
GOLOA
Open Loop Gain Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High
VOHIGHOA High Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High VOLOWOA Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High ISOA Supply Current (including associated Analog Output Buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
1200 2400 4600
1000 1600 3200 6400
(VDD 2.25) (VDD 1.25V) VDD.
PSRROA
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Table 15-24. Operational Amplifier Specifications Symbol Description tROA Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High tSOA Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High SRROA Rising Slew Rate (20% 80%) load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High SRFOA Falling Slew Rate (20% 80%) load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Gain Bandwidth Product BWOA Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High ENOA Noise (Power Medium, Opamp Bias High) Units Notes
0.72 0.62
0.92 0.72
0.15
0.01 0.75
nV/rt-Hz
15.13 PSoC Core Power Comparator
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-25. Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Units Notes
Table 15-26. Power Comparator Specifications Symbol tRLPC Description response time Units Notes overdrive comparator reference within VREFLPC.
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15.14 PSoC Core Analog Output Buffer
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-27. Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High VOHIGHOB High Output Voltage Swing (Load ohms VDD/2) Power Power High VOLOWOB Output Voltage Swing (Load ohms VDD/2) Power Power High ISOB PSRROB Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Units V/°C Notes
(0.5 1.3) VOUT (VDD 2.3).
Table 15-28. Analog Output Buffer Specifications Symbol tROB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High Units Notes
tSOB
SRROB
0.65 0.65
SRFOB
0.65 0.65
BWOBSS
BWOBLS
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15.15 PSoC Core Analog Reference
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Table 15-29. Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND VDD/2[4] AGND BandGap AGND BandGap[4] AGND BandGap[4] AGND Block Block Variation (AGND VDD/2)[4] RefHi VDD/2 BandGap RefHi BandGap RefHi BandGap RefLo VDD/2 BandGap RefLo BandGap
1.28 VDD/2 0.04 0.048 0.009 -0.034 VDD/2 0.10 0.06 0.112 VDD/2 0.04 0.06
1.30 VDD/2 0.01 0.030 0.008 0.000 VDD/2 VDD/2 0.024
1.32 VDD/2 0.007 0.024 0.016 0.034 VDD/2 0.10 0.06 0.076 VDD/2 0.04 0.06
Units
Notes
0.022 0.010 0.018
15.16 PSoC Core Analog Block
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-30. Analog Block Specifications Symbol Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switched Capacitor) 12.2 Units Notes
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15.17 PSoC Core
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Note bits PORLEV table below refer bits VLT_CR register. PowerPSoC Technical Reference Manual more information VLT_CR register. Table 15-31. Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.36 2.82 4.55 2.40 2.95 4.70 2.51[5] 2.99[6] 3.09 3.20 4.55 4.75 4.83 4.95 Units Notes must greater than equal 2.5V during startup reset from Watchdog
2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71
2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81
Notes AGND tolerance includes offsets local buffer PSoC block. Bandgap voltage 1.3V 0.02V. Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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15.18 PSoC Core Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-32. Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV Description Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify 50,000 1,800,000 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
FlashENPB Flash Endurance (per block) FlashENT FlashDR Flash Endurance (total)[7] Flash Data Retention[8]
Table 15-33. Programming Specifications Symbol tRSCLK tFSCLK tSSCLK tHSCLK fSCLK tERASEB tWRITE tDSCLK Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Units Notes
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles) full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information. Guaranteed -40°C 85°C
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15.19 PSoC Core Digital Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-34. Digital Block Specifications Function Timer Description Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits 50[9] 50[9] 50[9] 49.92 49.92 24.96 8.32 4.16 24.96 49.92 24.96 49.92 Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate over clocking.
49.92 24.96 49.92 24.96
Units
Notes
Note minimum input pulse width based input synchronizers running nominal period).
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15.20 PSoC Core Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V 115°C. Typical parameters apply 25°C. These design guidance only. Table 15-35. Characteristics Pins Symbol fSCLI2C tHDSTAI2C tLOWI2C tHIGHI2C tSUSTAI2C tHDDATI2C tSUDATI2C tSUSTOI2C tBUFI2C tSPI2C Description Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time Setup Time STOP Condition Free Time Between STOP START Condition Pulse Width Spikes Suppressed Input Filter. Standard Mode Fast Mode 100[10] Units Notes
Figure 15-8. Definition Timing Fast/Standard Mode
Note fast mode device used standard mode system, requirement tSUDATI2 must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSUDATI2 1000 1250 (according standard mode specification) before line released.
Document Number: 001-46319 Rev.
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
Ordering Information
16.1 Device Features
Table 16-1. Device Features Ordering Information PowerPSoC Part Number CY8CLED04D01-56LTXI CY8CLED04D02-56LTXI CY8CLED04G01-56LTXI CY8CLED04DOCD1-56LTXI CY8CLED03D01-56LTXI CY8CLED03D02-56LTXI CY8CLED03G01-56LTXI Pins Package Channels Voltage Internal FETs 1.0A 0.5A 1.0A 1.0A 0.5A Gate Drivers External Side N-FETs
Ordering Code Definitions
LED0x (xxxx) xxxx Package Type: LTX=QFN Pb-Free Thermal Rating: Industrial
Count OCD1 Chip Debugger Part Number Family Code: Channel, Channel Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
Document Number: 001-46319 Rev.
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01
Packaging Information
Packaging Dimensions
This section illustrates package specification CY8CLED04D0X, CY8CLED03D0X, CY8CLED04G01, CY8CLED03G01, along with thermal impedance package solder reflow peak temperatures. Important Note information preferred dimensions mounting packages, following Application Note Figure 18-1. 56-Pin (8x8
001-45705
18.1 Thermal Impedance
Package QFN[12] Typical [11] 16.6 oC/W
19.1.1 PSoC Designer 5.0At core PSoC development software suite PSoC Designer. Used thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge under Design Resources Software Drivers. 19.1.2 PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer 5.0. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge
18.2 Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Package Minimum Peak Temperature[13] 240oC Maximum Peak Temperature 260oC
Development Tools
19.1 Software
This section presents development tools available current PowerPSoC device families including CY8CLED04D0X, CY8CLED03D0X, CY8CLED04G01, CY8CLED03G01.
19.2 Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PowerPSoC device, AN2323, Debugging Build PSoC Emulator into Your Board.
Notes POWER achieve thermal impedance specified package, center thermal should soldered ground plane. Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste Refer solder manufacturer specifications.
Document Number: 001-46319 Rev.
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CY8CLED04D01, CY8CLED04D02 CY8CLED03D01, CY8CLED03D02 CY8CLED04G01, CY8CLED03G01 Document History Page
Document Title: CY8CLED04G01, CY8CLED03G01, CY8CLED03D01, CY8CLED03D02, CY8CLED04D01, CY8CLED04D02 PowerPSoCIntelligent Driver Document Number: 001-46319 Revision 2506500 2575708 Orig. Change ANWA/ ANWA/ AESA Submission Date 5/20/2008 10/01/08 data sheet. Updated Logic Block Diagram with AINX label SREGFB pin. Updated Current Sense Amplifier Specification Table. Updated External Gate Driver Specification Table. Updated Register Table. Extensive changes made content electrical specifications. Updated Notes electrical specifications. Updated sections pages Release external site Updated Figure 14-1, Figure 15-2, Figure 15-4. Description Change
2662774
2/19/2009 02/25/2009 03/10/2009 04/03/2009 04/27/2009
2665155 KJV/PYRS 2671254 KJV/PYRS 2683506 2698529 KJV/PYRS
Sales, Solutions, Legal Information
21.1 Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
21.2 Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
21.3 PSoC Solutions
General Power/Low Voltage Precision Analog Drive 2.0b psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
Cypress Semiconductor Corporation, 2008-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 001-46319 Rev.
Revised April 2009
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PowerPSoCTM, PSoC DesignerTM, Programmable System-on-ChipTM, PrISMare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations.
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