PSoC® Programmable System-on-Chip Powerful Harvard Architecture P
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PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 3.0V 5.25V Operating Voltage Operating Voltages Down 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC® Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UARTs Multiple SPIMasters Slaves Connectable GPIO Pins Complex Peripherals Combining Blocks Precision, Programmable Clocking Internal ±2.5% 24/48 Oscillator 24/48 with Optional 32.768 Crystal Optional External Oscillator, Internal Oscillator Watchdog Sleep Flexible On-Chip Memory Bytes Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink, Source GPIO Pull Pull down, High Strong, Open Drain Drive Modes GPIO standard analog inputs GPIO, plus additional analog inputs with restricted routing Four Analog Outputs GPIO Configurable Interrupt GPIO
Additional System Resources Slave, Master, Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Complex Events Compilers, Assembler, Linker
Logic Block Diagram
Port Port Port Port Port Port
PSoC CORE
System
Global Digital Interconnect SRAM Bytes Interrupt Controller
Analog Drivers
Global Analog Interconnect Flash Sleep Watchdog
SROM
CPUCore (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
Analog Input Muxing
Digital Clocks
Multiply Accum.
Decimator System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 38-12013 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2009
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PSoC Functional Overview
PSoC family consists many Programmable System-on-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with one, cost single-chip programmable device. PSoC devices include configurable blocks analog digital logic, well programmable interconnects. This architecture allows user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, illustrated left, comprised four main areas: PSoC Core, Digital System, Analog System, System Resources. Configurable global busing allows device resources combined into complete custom system. PSoC CY8C29x66 family have five ports that connect global digital analog interconnects, providing access digital blocks analog blocks.
Digital System
Digital System composed digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Figure 3-1. Digital System Block Diagram
Port Port Port Port Port Port
Digital Clocks FromCore
System
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. uses interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, bytes SRAM data storage, EEPROM emulated using Flash. Program Flash utilizes four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate 2.5% over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. crystal accuracy desired, (32.768 external crystal oscillator) available Real Time Clock (RTC) optionally generate crystal-accurate system clock using PLL. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. PSoC GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
Input Configuration
DBB10 DBB11 DCB12
DCB13
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include those listed below.
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity slave master slave multi-master available System Resource) Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown table titled "PSoC Device Characteristics" page
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Analog System
Analog System composed configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) listed below.
Figure 3-2. Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (four with drive Core Resource) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible
P2[3]
P2[4] P2[2] P2[0]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks, shown figure below.
Interface Digital System RefHi RefLo AGND
Analog Reference
Reference Generators AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
Additional System Resources
System Resources, some which have been previously listed, provide additional capability useful complete systems. Additional resources include multiplier, decimator, switch mode pump, voltage detection, power reset. Statements describing merits each system resource below. Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist general math digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. module provides communication over wires. Slave, master, multi-master modes supported.
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Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter.
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC® Programmable System-on-ChipTechnical Reference Manual CY8C28xxx PSoC devices. date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups.The PSoC device covered this data sheet highlighted below. Table 3-1. PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34 Flash Size
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
4[1] 4[1] 3[2]
Bytes Bytes Bytes Bytes Bytes Bytes
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
Notes Limited analog functionality. analog blocks CapSense.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built support third party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family. 5.1.4 Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. 5.1.5 Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. 5.1.6 Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
5.1.1 System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Programmable System-on-Chip Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. 5.1.2 Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. 5.1.3 Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user selectable functions. PSoC development process summarized following four steps: Select Components Configure Components Organize Connect Generate, Verify, Debug
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, programmable system-on-chip varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
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Document Conventions
Acronyms Used
This table lists acronyms used this data sheet. Table 7-1. Acronyms Acronym EEPROM GPIO ISSP IPOR PPOR PSoC® SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose in-circuit emulator integrated development environment input/output in-system serial programming imprecise power reset least-significant voltage detect most-significant program counter programmable gain amplifier power reset precision power reset Programmable System-on-Chippulse width modulator read only memory switched capacitor switch mode pump static random access memory
Units Measure
units measure table located section Electrical Specifications page Table 11-1 page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
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Pinouts
CY8C29x66 PSoC device available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital However, Vss, Vdd, SMP, XRES capable Digital
28-Pin Part Pinout
Table 8-1. 28-Pin Part Pinout (PDIP, SSOP, SOIC)
Type Digital Analog Power Power Input Power Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description Analog column input. Analog column input column output. Analog column input column output. Analog column input.
Figure 8-1. CY8C29466 28-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1]
Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection external components required. Serial Clock (SCL). Serial Data (SDA). Crystal (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
PDIP SSOP SOIC
P0[6], P0[4], P0[2], P0[0], P2[6],ExternalVREF P2[4],ExternalAGND P2[2], P2[0], XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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44-Pin Part Pinout
Table 8-2. 44-Pin Part Pinout (TQFP)
Type Digital Analog Power Power Input Power Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] Description Direct switched capacitor block input. Direct switched capacitor block input.
Figure 8-2. CY8C29566 44-Pin PSoC Device
P0[6], P0[4], P0[2], P0[0], P2[6],ExternalVREF P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2]
Switch Mode Pump (SMP) connection external components required.
Serial Clock (SCL). Serial Data (SDA). Crystal (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-ChipTechnical Reference Manual details.
Document Number: 38-12013 Rev.
P3[1] I2CSCL, P1[7] SDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P3[0]
P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3]
P2[7] P0[1], P0[3], P0[5], P0[7],
TQFP
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48-Pin Part Pinouts
Table 8-3. 48-Pin Part Pinout (SSOP)
Type Digital Analog Power Power Input Power Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description Analog column input. Analog column input column output. Analog column input column output. Analog column input.
Figure 8-3. CY8C29666 48-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2CSCL, P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin,P1[1]
Direct switched capacitor block input. Direct switched capacitor block input.
Switch Mode Pump (SMP) connection external components required.
SSOP
Serial Clock (SCL). Serial Data (SDA). Crystal (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
P0[6], P0[4], P0[2], P0[0], P2[6],External VREF P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2C
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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Table 8-4. 48-Pin Part Pinout (QFN)**
Power Input Power Type Digital Power Analog Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VREF). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Active high external reset with internal pull down. Optional External Clock Input (EXTCLK). Crystal (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal (XTALout), Serial Data (SDA), ISSP-SDATA*. Serial Clock (SCL). Serial Data (SDA). Switch Mode Pump (SMP) connection external components required. Description Direct switched capacitor block input. Direct switched capacitor block input.
Figure 8-4. CY8C29666 48-Pin PSoC Device
P0[6], P0[4], A,IO P0[2], A,IO P0[0], P2[6],ExternalVREF P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0]
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details. package center that must connected ground (Vss).
Document Number: 38-12013 Rev.
I2CSDA,P1[5] P1[3] I2CSCL,XTALin,P1[1] I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P5[0] P5[2]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3]
P5[1] I2CSCL,P1[7]
P2[5] P2[7] P0[1], P0[3], A,IO P0[5], A,IO P0[7],
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100-Pin Part Pinout
Table 8-5. 100-Pin Part Pinout (TQFP)
Type Digital Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0] P1[2] P1[4] P1[6] Description connection. connection. Analog column input. Type Digital Analog Name P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] Power P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] P0[7] P0[5] P0[3] Ground connection. connection. Description
Direct switched capacitor block input. Direct switched capacitor block input.
connection. connection. Switch Mode Pump (SMP) connection external components required. Ground connection.
Input
connection. connection. Active high external reset with internal pull down.
Power Power
Serial Clock (SCL). connection. connection. connection. Serial Data (SDA). Crystal (XTALin), Serial Clock (SCL), ISSP-SCLK*. connection. Supply voltage. connection. Ground connection. connection.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). connection. External Voltage Reference (VREF). connection. Analog column input. connection. connection. Analog column input column output. connection. Analog column input column output. connection. Analog column input. Supply voltage. Supply voltage. Ground connection. Ground connection.
Power Power Power Power
Power Power
Crystal (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). connection. connection. connection.
connection. Analog column input. connection. Analog column input column output. connection. Analog column input column output. connection.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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Figure 8-5. CY8C29866 100-Pin PSoC Device
P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6],External VREF P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0]
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SDA, P1[5] P1[3] XTALin,I2CSCL,P1[1] P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] XTALout,I2CSDA,P1[0] P1[2] EXTCLK,P1[4] P1[6]
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7]
P6[7] P6[6] P6[5] P6[4] P6[3] P6[2] P6[1] P6[0]
TQFP
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100-Pin Part Pinout (On-Chip Debug)
100-pin TQFP part CY8C29000 On-Chip Debug (OCD) PSoC device. Note parts only used in-circuit debugging. parts available production Table 8-6. 100-Pin Part Pinout (TQFP)
Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1]* P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] P1[0]* Description internal connection. internal connection. Analog column input. Analog Digital Digital Name P5[0] P5[2] P5[4] P5[6] P3[0] P3[2] P3[4] P3[6] HCLK CCLK XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P6[0] P6[1] P6[2] P6[3] P6[4] P6[5] P6[6] P6[7] P0[7] P0[5] P0[3] Description internal connection.
Direct switched capacitor block input. Direct switched capacitor block input.
Power Power
even data data output Switch Mode Pump (SMP) connection required external components. Ground connection.
Input Power
high speed clock output clock output Active high reset with internal pull down.
Ground connection.
Serial Clock (SCL) internal connection. internal connection. internal connection. Serial Data (SDA). IFMTEST Crystal (XTALin), Serial Clock (SCL), SCLK. internal connection. Supply voltage. internal connection. Ground connection. internal connection.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND) input. internal connection. External Voltage Reference (VREF) input. internal connection. Analog column input. internal connection. internal connection. Analog column input column output. internal connection. Analog column input column output, VREF. internal connection. Analog column input. Supply voltage. Supply voltage. Ground connection. Ground connection.
Power Power Power Power Power Crystal (XTALout), Serial Data (SDA), SDATA P1[2] VFMTEST P1[4] Optional External Clock Input (EXTCLK) P1[6] internal connection. internal connection. internal connection. LEGEND Analog, Input, Output, Connection, TC/TM: Test. ISSP which POR. Power
internal connection. Analog column input. internal connection. Analog column input column output. internal connection. Analog column input column output. internal connection.
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Figure 8-6. CY8C29000 (Not Production)
P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], P0[0], P2[6], External VREF P2[4], External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES CCLK HCLK P3[6] P3[4] P3[2] P3[0] P5[6] P5[4] P5[2] P5[0]
SDA, P1[5] P1[3] XTALin, SCL, P1[1]
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P7[7] P7[6] P7[5] P7[4] P7[3] P7[2] P7[1] P7[0] XTALout, SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6]
P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[7] P5[5] P5[3] P5[1] SCL, P1[7]
TQFP
P6[7] P6[6] P6[5] P6[4] P6[3] P6[2] P6[1] P6[0]
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This section lists registers CY8C29x66 PSoC device. detailed register information, reference PSoC Programmable System-on-Chip Technical Reference Manual.
Register Conventions
Abbreviations Used
register conventions specific this section listed following table. Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields reserved should accessed.
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Table 10-1. Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 PRT6DR PRT6IE PRT6GS PRT6DM2 PRT7DR PRT7IE PRT7GS PRT7DM2 DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 DBB10DR1 DBB10DR2 DBB10CR0 DBB11DR0 DBB11DR1 DBB11DR2 DBB11CR0 DCB12DR0 DCB12DR1 DCB12DR2 DCB12CR0 DCB13DR0 DCB13DR1 DCB13DR2 DCB13CR0 Addr (0,Hex) Access Name DBB20DR0 DBB20DR1 DBB20DR2 DBB20CR0 DBB21DR0 DBB21DR1 DBB21DR2 DBB21CR0 DCB22DR0 DCB22DR1 DCB22DR2 DCB22CR0 DCB23DR0 DCB23DR1 DCB23DR2 DCB23CR0 DBB30DR0 DBB30DR1 DBB30DR2 DBB30CR0 DBB31DR0 DBB31DR1 DBB31DR2 DBB31CR0 DCB32DR0 DCB32DR1 DCB32DR2 DCB32CR0 DCB33DR0 DCB33DR1 DCB33DR2 DCB33CR0 AMX_IN Addr (0,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Addr (0,Hex) Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 Addr (0,Hex) Access
ARF_CR CMP_CR0 ASY_CR CMP_CR1
MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1
TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 ACB03CR2
CPU_F
CPU_SCR1 CPU_SCR0
Blank fields Reserved should accessed.
Access specific.
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Table 10-2. Register Bank Table: Configuration Space
Addr (1,Hex) Access Name DBB20FN DBB20IN DBB20OU DBB21FN DBB21IN DBB21OU DCB22FN DCB22IN DCB22OU DCB23FN DCB23IN DCB23OU DBB30FN DBB30IN DBB30OU DBB31FN DBB31IN DBB31OU DCB32FN DCB32IN DCB32OU DCB33FN DCB33IN DCB33OU CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 DBB01FN DBB01IN DBB01OU AMD_CR1 ALT_CR0 DCB02FN ALT_CR1 DCB02IN CLK_CR2 DCB02OU DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 DBB10FN ACB00CR3 DBB10IN ACB00CR0 DBB10OU ACB00CR1 ACB00CR2 DBB11FN ACB01CR3 DBB11IN ACB01CR0 DBB11OU ACB01CR1 ACB01CR2 DCB12FN ACB02CR3 DCB12IN ACB02CR0 DCB12OU ACB02CR1 ACB02CR2 DCB13FN ACB03CR3 DCB13IN ACB03CR0 DCB13OU ACB03CR1 ACB03CR2 Blank fields Reserved should accessed. Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 PRT6DM0 PRT6DM1 PRT6IC0 PRT6IC1 PRT7DM0 PRT7DM1 PRT7IC0 PRT7IC1 DBB00FN DBB00IN DBB00OU Addr (1,Hex) Access Addr (1,Hex) RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access specific. Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI3RI RDI3SYN RDI3IS RDI3LT0 RDI3LT1 RDI3RO0 RDI3RO1 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Addr (1,Hex) Access
OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
DEC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR
CPU_F
FLS_PR1
CPU_SCR1 CPU_SCR0
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Electrical Specifications
This section presents electrical specifications CY8C29x66 PSoC device. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40°C 85°C 100°C, except where noted. Refer Table 11-17 electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure 11-1. Voltage versus Frequency Figure 11-2. Frequency Options
4.75 Voltage 3.00 4.75 Voltage
SLIMO Mode
5.25
5.25
following table lists units measure that used this chapter. Table 11-1. Units Measure Symbol
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
3.60 3.00
Symbol
Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
Kbit Vrms
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11.1 Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Table 11-2. Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100 Unit
Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65oC degrade reliability.
VIOZ IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch Current
-0.5 Vss- 2000
+6.0
Human Body Model ESD.
11.2 Operating Temperature
Table 11-3. Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Unit Notes temperature rise from ambient junction package specific. "Thermal Impedances" page user must limit power consumption comply with this requirement.
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11.3 Electrical Characteristics
11.3.1 Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-4. Chip-Level Specifications
Symbol IDD3 IDDP ISBH ISBXTL ISBXTLH VREF Supply Voltage Supply Current Supply Current Supply current when using SLIMO mode. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator, crystal oscillator active. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, crystal oscillator active. Reference Voltage (Bandgap) Description 3.00 1.28 5.25 1.32 Units Notes specifications, Table 3-15 page Conditions 5.0V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 0.366 kHz. Conditions 3.3V, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 0.366 kHz. Conditions 3.3V, 0.75 MHz, SYSCLK doubler disabled, 0.375 MHz, 23.44 kHz, 0.09 kHz. Conditions with internal slow speed oscillator, 3.3V, Conditions with internal slow speed oscillator, 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Trimmed appropriate Vdd.
11.3.2 General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-5. GPIO Specifications
Symbol Pull Resistor Pull down Resistor High Output Level Description Unit 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. Vdd-1.0V, limitations total current note 0.75V, limitations total current note 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC. Notes
Output Level
0.75
COUT
High Level Source Current Level Sink Current Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
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11.3.3 Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Typical parameters apply 25°C design guidance only. Table 11-6. Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 1200 2400 4600 35.0 1600 3200 6400 Unit V/oC (Vdd 2.25) (Vdd 1.25V) Vdd. Gross tested Package dependent. Temp Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHO
Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range. Cases, except highest. Power High, Opamp Bias High Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals)
VOLOWOA Output Voltage Swing (internal signals) ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
PSRROA
Table 11-7. 3.3V Operational Amplifier Specifications
Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Common Mode Rejection Ratio Open Loop Gain High Output Voltage Swing (internal signals) 1.65 1.32 1200 2400 35.0 1600 3200 Unit V/oC Gross tested Package dependent. Temp Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA CMRROA GOLOA VOHIGHO
VOLOWOA Output Voltage Swing (internal signals) ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
Allowed (Vdd 2.25) (Vdd 1.25V)
PSRROA
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11.3.4 Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table 11-8. Power Comparator Specifications
Symbol VREFLPC ISLPC VOSLPC supply current voltage offset Description power comparator (LPC) reference voltage range Unit
11.3.5 Analog Output Buffer Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-9. Analog Output Buffer Specifications
Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB PSRROB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Unit V/°C
Table 11-10. 3.3V Analog Output Buffer Specifications Symbol
VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB VOLOWOB ISOB PSRROB
Description
Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio
Units
V/°C
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11.3.6 Switch Mode Pump Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-11. Switch Mode Pump (SMP) Specifications
Symbol VPUMP VPUMP IPUMP VBAT5V VBAT3V VBATSTART VPUMP_Line VPUMP_Load Description 3.25 5.25 3.60 Unit Notes Configuration footnote.[3] Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.[3] Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.[3] trip voltage 3.25V. trip voltage 5.0V. Configuration footnote.[3] trip voltage 5.0V. Configuration footnote.[3] trip voltage 3.25V. Configuration footnote.[3] 100. 1.25V -40oC. Output Voltage from Pump 4.75 Output Voltage from Pump 3.00 Available Output Current VBAT 1.5V, VPUMP 3.25V VBAT 1.8V, VPUMP 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery Start Pump Line Regulation (over VBAT range) Load Regulation
Configuration footnote.[3] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table 3-15 page Configuration footnote.[3] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table 3-15 page Configuration footnote.[3] Load Configuration footnote.[3] Load trip voltage 3.25V.
VPUMP_Ripple Output Voltage Ripple (depends capacitor/load) FPUMP DCPUMP Efficiency Switching Frequency Switching Duty Cycle
Figure 11-3. Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Note inductor, capacitor, Schottky diode. Figure 11-3.
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11.3.7 Analog Reference Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Note Avoid using P2[4] digital signaling when using analog resource that depends Analog Reference. Some coupling digital signal appear AGND. Table 11-12. Analog Reference Specifications
Symbol VBG5 Description Bandgap Voltage Reference 1.28 AGND Vdd/2[4] Vdd/2 0.02 AGND BandGap[4] 2.52 AGND P2[4] (P2[4] Vdd/2)[4] P2[4] 0.013 AGND BandGap[4] 1.27 AGND BandGap[4] 2.03 AGND Block Block Variation (AGND Vdd/2)[4] -0.034 RefHi Vdd/2 BandGap Vdd/2 1.21 RefHi BandGap 3.75 RefHi BandGap P2[6] (P2[6] 1.3V) P2[6] 2.478 RefHi P2[4] BandGap (P2[4] Vdd/2) P2[4] 1.218 RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) P2[4] P2[6] 0.058 RefHi BandGap 2.50 RefHi BandGap 4.02 RefLo BandGap 0.082 RefLo BandGap P2[6] (P2[6] 1.3V) P2[6] 0.084 RefLo P2[4] BandGap P2[4] 0.056 (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) P2[4] P2[6] 0.057 1.30 Vdd/2 2.60 P2[4] 2.08 0.000 Vdd/2 P2[6] P2[4] P2[4] P2[6] 2.60 4.16 0.023 P2[6] 0.025 P2[4] 0.026 1.32 Vdd/2 0.02 2.72 P2[4] 0.013 1.34 2.13 0.034 Vdd/2 1.382 4.05 P2[6] 2.722 P2[4] 1.382 P2[4] P2[6] 0.058 2.70 4.29 0.129 P2[6] 0.134 P2[4] 0.107 Unit
P2[4] P2[6] 0.026
P2[4] P2[6] 0.110
Table 11-13. 3.3V Analog Reference Specifications
Symbol Description VBG33 Bandgap Voltage Reference 3.3V 1.28 1.30 1.32 Unit
AGND Vdd/2[4] AGND BandGap[4] AGND P2[4] (P2[4] Vdd/2) AGND BandGap[4] AGND BandGap[4] AGND Block Block Variation (AGND Vdd/2)[4]
Vdd/2 0.02 P2[4] 0.009 1.27 2.03 -0.034
Vdd/2 Allowed P2[4] 1.30 2.08 0.000 Allowed Allowed Allowed Allowed P2[4] P2[6] 2.60 Allowed
Vdd/2 0.02 P2[4] 0.009 1.34 2.13 0.034
RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) P2[4] P2[6] 0.042 RefHi BandGap RefHi BandGap 2.50
P2[4] P2[6] 0.042 2.70
Note AGND tolerance includes offsets local buffer PSoC block. Bandgap voltage 1.3V 0.02V.
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Table 11-13. 3.3V Analog Reference Specifications (continued)
Symbol Description RefLo Vdd/2 BandGap Unit
RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2)
Allowed Allowed Allowed Allowed
11.3.8 Analog PSoC Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-14. Analog PSoC Block Specifications
Symbol Description Unit Notes
Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap)
12.2
11.3.9 POR, SMP, Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-15. POR, SMP, Specifications
Symbol Description Units Notes
VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7
Value PPOR Trip (positive ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b
2.91 4.39 4.55 2.82 4.39 4.55 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00
2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90
2.98[5] 3.08 3.20 4.08 4.57 4.74[6] 4.82 4.91 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10
Notes Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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11.3.10 Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 11-16. Programming Specifications
Symbol Description Units Notes
IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR
Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (per block) Flash Endurance (total)[8] Flash Data Retention
50,000[7] 1,800,000
0.75
Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor.
11.4 Electrical Characteristics
11.4.1 Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note individual user module data sheets information maximum frequencies user modules. Table 11-17. Chip-Level Specifications
Symbol Description Units Notes
FIMO24
Internal Main Oscillator Frequency
23.4
24.6[9,10,11]
Trimmed 3.3V operation using factory trim values. figure page SLIMO Mode Trimmed 3.3V operation using factory trim values. figure page SLIMO Mode
FIMO6
Internal Main Oscillator Frequency
6.5[9,10,11]
FCPU1 FCPU2 F48M F24M F32K1 F32K2
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Speed Oscillator Frequency External Crystal Oscillator
0.93 0.93
32.768
24.6[9,10] 12.3[10,11] 49.2
[9,10,
Accuracy capacitor crystal dependent. duty cycle Refer Digital Block Specifications below.
24.6[10,
Notes 50,000 cycle flash endurance block will only guaranteed flash operating within voltage range. Voltage ranges 3.0V 3.6V 4.75V 5.25V. maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information. 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules
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Table 11-17. Chip-Level Specifications (continued)
Symbol Description Units Notes
F32K_U
Internal Speed Oscillator (ILO) Untrimmed Frequency
After reset before starts run, trimmed. System Resets section PSoC Technical Reference Manual details timing this multiple (x732) crystal frequency.
FPLL Jitter24M2 TPLLSLEW TPLLSLEWLO TOSACC
Frequency Period Jitter (PLL) Lock Time Lock Time Gain Setting External Crystal Oscillator Startup External Crystal Oscillator Startup
23.986
crystal oscillator frequency within final value Tosacc period. Correct operation assumes properly loaded maximum drive level 32.768 crystal. 3.0V 5.5V,
Jitter32k TXRST DC24M DCILO Step24M Fout48M Jitter24M1 FMAX TRAMP TPOWERUP
Period Jitter External Reset Pulse Width Duty Cycle Internal Speed Oscillator Duty Cycle Trim Step Size Output Frequency Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time Time from executing code
46.8
48.0
49.2[9, 12.3
Trimmed. Using factory trim values.
Power from System Resets section PSoC Technical Reference Manual.
Figure 11-4. Lock Timing Diagram
Enable
TPLLSLEW
FPLL Gain
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Figure 11-5. Lock Gain Setting Timing Diagram
Enable
TPLLSLEWLOW
FPLL Gain
Figure 11-6. External Crystal Oscillator Startup Timing Diagram
Select
F32K2
Figure 11-7. Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure 11-8. Period Jitter (ECO) Timing Diagram
Jitter32k
32K2
11.4.2 General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-18. GPIO Specifications
Symbol Description Unit Notes
FGPIO TRiseF TFallF TRiseS TFallS
GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload
12.3
Normal Strong Mode 4.75 5.25V, 4.75 5.25V, 5.25V, 5.25V,
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Figure 11-9. GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
11.4.3 Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V.
Table 11-19. Operational Amplifier Specifications
Symbol Description Unit
TROA
Rising Settling Time 0.1% Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Settling Time 0.1% Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Rising Slew Rate (20% 80%) Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Slew Rate (20% 80%) Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Noise (Power Medium, Opamp Bias High)
0.15 0.01 0.75
0.72 0.62 0.92 0.72
TSOA
SRROA
nV/rt-Hz
SRFOA
BWOA
ENOA
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Table 11-20. 3.3V Operational Amplifier Specifications
Symbol Description Units
TROA
Rising Settling Time 0.1% Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Settling Time 0.1% Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Rising Slew Rate (20% 80%) Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Slew Rate (20% 80%) Step load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Noise (Power Medium, Opamp Bias High)
0.31 0.24 0.67
3.92 0.72 5.41 0.72
TSOA
SRROA
nV/rt-Hz
SRFOA
BWOA ENOA
When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor.
Figure 11-10. Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level.
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Figure 11-11. Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
11.4.4 Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only.
Table 11-21. Power Comparator Specifications
Symbol Description Unit Notes overdrive comparator reference within VREFLPC.
TRLPC
response time
11.4.5 Digital Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-22. Digital Block Specifications
Function Description Unit Notes
Functions Timer
Maximum Block Clocking Frequency 4.75V) Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture 50[13] 50[13] 50[13] 50[13]
49.2 24.6 49.2 24.6 49.2 24.6 49.2
4.75V 5.25V. 3.0V 4.75V. 4.75V 5.25V. 4.75V 5.25V. 4.75V 5.25V.
Counter
Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input
Dead Band
Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency
Note minimum input pulse width based input synchronizers running nominal period).
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Table 11-22. Digital Block Specifications (continued)
Function Description Unit Notes
CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency 4.75V, Stop Bits Maximum Input Clock Frequency 4.75V, Stop Bits
49.2 24.6 24.6 49.2 24.6 49.2
4.75V 5.25V. Maximum data rate over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking.
Width Negated Between Transmissions 50[13]
Receiver
11.4.6 Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-23. Analog Output Buffer Specifications
Symbol TROB Description Rising Settling Time 0.1%, Step, 100pF Load Power Power High Falling Settling Time 0.1%, Step, 100pF Load Power Power High Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High Unit
0.55 0.55
TSOB SRROB SRFOB BWOB BWOB
Table 11-24. 3.3V Analog Output Buffer Specifications
Symbol TROB Description Rising Settling Time 0.1%, Step, 100pF Load Power Power High Falling Settling Time 0.1%, Step, 100pF Load Power Power High Rising Slew Rate (20% 80%), Step, 100pF Load Power Power High Falling Slew Rate (80% 20%), Step, 100pF Load Power Power High Small Signal Bandwidth, 20mVpp, 100pF Load Power Power High Large Signal Bandwidth, 1Vpp, 100pF Load Power Power High Unit
TSOB SRROB SRFOB BWOB BWOB
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11.4.7 External Clock Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-25. External Clock Specifications
Symbol Description Unit
FOSCEXT
Frequency High Period Period Power Switch
0.093 20.6 20.6
24.6 5300
Table 11-26. 3.3V External Clock Specifications
Symbol Description Unit
FOSCEXT FOSCEXT
Frequency with Clock divide Frequency with Clock divide greater High Period with Clock divide Period with Clock divide Power Switch
0.093 0.186 41.7 41.7
12.3 24.6 5300
11.4.8 Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-27. Programming Specifications
Symbol Description Unit Notes
TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TERASEALL TPROGRAM_HOT TPROGRAM_COLD
Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Flash Erase Time (Bulk) Flash Block Erase Flash Block Write Time Flash Block Erase Flash Block Write Time
100[14] 200[14]
Erase Blocks protection fields once 100°C -40°C
Note full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information
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11.4.9 Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only.
Table 11-28. Characteristics Pins
Symbol Description Standard Mode Fast Mode Unit
FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Set-up Time Repeated START Condition Data Hold Time Data Set-up Time Set-up Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
100[15]
Figure 11-12. Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This will automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Packaging Information
This section illustrates packaging specifications CY8C27x43 PSoC device, along with thermal impedances each package typical package capacitance crystal pins.
Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
12.1 Packaging Dimensions
Figure 12-1. 28-Pin (300 mil) Molded
51-85014
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Figure 12-2. 28-Pin (210-Mil) SSOP
51-85079
Figure 12-3. 28-Pin (300-Mil) SOIC
51-85026
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Figure 12-4. 44-Pin TQFP
51-85064
Figure 12-5. 48-Pin (300-Mil) SSOP
51-85061-C
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Figure 12-6. 48-Pin (7x7
001-12919
Figure 12-7. 48-Pin 7x7x 0.90 (Sawn Type)
001-13191
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Figure 12-8. 100-Pin TQFP
51-85048
51-85048
Important Note information preferred dimensions mounting packages, following Application Note Important Note Pinned vias thermal conduction required low-power PSoC device.
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12.1 Thermal Impedances
Table 12-1. Thermal Impedances Package Package Typical
12.2 Capacitance Crystal Pins
Table 12-2. Typical Package Capacitance Crystal Pins Package Package Capacitance
PDIP SSOP SOIC TQFP SSOP QFN** TQFP
POWER
oC/W
oC/W oC/W oC/W
PDIP SSOP SOIC TQFP SSOP TQFP
oC/W oC/W oC/W
achieve thermal impedance specified package, center thermal should soldered ground plane.
12.3 Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability.
Table 12-3. Solder Reflow Peak Temperature Package Minimum Peak Temperature* Maximum Peak Temperature
PDIP SSOP SOIC TQFP SSOP TQFP
220oC 240oC 220oC 220oC 220oC 220oC 220oC
260oC 260oC 260oC 260oC 260oC 260oC 260oC
*Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
This chapter presents development tools available current PSoC device families including CY8C27x43 family.
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
13.1 Software
13.1.1 PSoC Designer
core PSoC development software suite PSoC Designer, used generate PSoC firmware applications. PSoC Designer available free charge includes free compiler.
13.1.2 PSoC Programmer
Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge
13.3 Evaluation Tools
evaluation tools purchased from Cypress Online Store.
13.3.1 CY3210-MiniProg1
13.2 Development Kits
development kits purchased from Cypress Online Store.
13.2.1 CY3215-DK Basic Development
CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
13.3.2 CY3210-PSoCEval1
CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
13.2.2 CY3210-ExpressDK PSoC Express Development
CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
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13.3.3 CY3214-PSoCEvalUSB
CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
programmer includes three programming module cards supports multiple Cypress products. includes:
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
13.4.2 CY3207ISSP In-System Serial Programmer (ISSP)
CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. includes:
13.4 Device Programmers
device programmers purchased from Cypress Online Store.
13.4.1 CY3216 Modular Programmer
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular
Accessories (Emulation Programming)
Table 14-1. Emulation Programming Accessories Part Package Flex-Pod Kit[16] Foot Kit[17] Adapter[18]
CY8C29466-24PXI CY8C29466-24PVXI CY8C29466-24SXI CY8C29566-24AXI CY8C29666-24PVXI CY8C29666-24LFXI CY8C29866-24AXI CY8C29466-24PXI
PDIP SSOP SOIC TQFP SSOP TQFP PDIP
CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXX CY3250-29XXXQFN CY3250-29XXX CY3250-29XXX
CY3250-28PDIP-FK CY3250-28SSOP-FK CY3250-28SOIC-FK CY3250-44TQFP-FK CY3250-48SSOP-FK CY3250-48QFN-FK CY3250-100TQFP-FK CY3250-28PDIP-FK
Adapters found http://www.emulation.com.
Adapters found http://www.emulation.com.
14.1 Third Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards.
14.2 Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323".
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com
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Ordering Information
following table lists CY8C27x43 PSoC device's package features ordering codes.
Analog PSoC Blocks Switch Mode Pump Temperature Range Digital PSoC Blocks XRES Digital Pins Ordering Code Package
(300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC (300 Mil) SOIC (Tape Reel) TQFP TQFP (Tape Reel) (300 Mil) SSOP (300 Mil) SSOP (Tape Reel) TQFP TQFP[19] 48-Pin (7X7X (Sawn) 48-Pin (7X7X (Sawn)
CY8C29466-24PXI CY8C29466-24PVXI CY8C29466-24PVXIT CY8C29466-24SXI CY8C29466-24SXIT CY8C29566-24AXI CY8C29566-24AXIT CY8C29666-24PVXI CY8C29666-24PVXIT CY8C29666-24LFXI CY8C29866-24AXI CY8C29000-24AXI CY8C29666-24LTXI CY8C29666-24LTXIT
-40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
Analog Outputs
Flash (Bytes)
(Bytes)
Analog Inputs
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Ordering Code Definitions xxx-SPxx
Package Type: Thermal Rating: PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended LFX/LKX Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
Note This part used in-circuit debugging. available production.
Document Number: 38-12013 Rev.
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Document History Page
Document Title:CY8C29466, CY8C29566, CY8C29666, CY8C29866 PSoC®Programmable System-on-ChipDocument Number: 38-12013 Revision Submission Date Origin Change Description Change
131151 132848 133205 133656 227240 240108 247492 288849 722736
11/13/2003 01/21/2004 01/27/2004 02/09/2004 06/01/2004
Silicon
document (Revision **). information. First edition preliminary data sheet. Changed part numbers, increased SRAM data storage bytes. Changed part numbers removed 28-pin SOIC. Changes Overview section, 48-pin pinout, significant changes Electrical Specs. Added 28-lead (300 mil) SOIC part. information added Electrical Specifications chapter. standards, update device table, fine-tune pinouts, Reflow Peak Temp. table. Finalize. package clarifications. diagram. Power Comparator (LPC) AC/DC electrical spec. tables. CY8C20x34 PSoC Device Characteristics table. Update emulation pod/feet part numbers. non-production pinouts package diagrams. ISSP note pinout tables. Update package diagram revisions. Update typical recommended Storage Temperature industrial specs. Update branding convention. Dev. Tool section. Update copyright trademarks. Pinout CY8C29000 wrongly included details CY8C24X94. correct pinout CY8C29000 included this version. Added note digital signaling Analog Reference Specifications" section. Added note Ordering Information Changed title from "CY8C29466, CY8C29566, CY8C29666, CY8C29866 PSoC Mixed Signal Array Final Data Sheet" "CY8C29466, CY8C29566, CY8C29666, CY8C29866 PSoC® Programmable System-on-ChipTM" Updated data sheet template Added 48-Pin (Sawn) package diagram CY8C29666-24LTXI CY8C29666-24LTXIT part details Ordering Information table Updated GPIO, Chip-Level, Programming Specifications follows: Modified FIMO6 (page 27), TWRITE specifications (page Added (page 21), (page 21), DCILO (page 28), F32K_U (page 27), TPOWERUP (page 28), TERASEALL (page 34), TPROGRAM_HOT (page 34), TPROGRAM_COLD (page specifications
2503350
DFK/PYRS
2545030 2708295
07/29/08 04/22/2009
YARA
Document Number: 38-12013 Rev.
Page
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CY8C29466, CY8C29566 CY8C29666, CY8C29866
Sales, Solutions, Legal Information
18.1 Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
18.2 Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
18.3 PSoC Solutions
General Power/Low Voltage Precision Analog Drive 2.0b psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
Cypress Semiconductor Corporation, 2003-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 38-12013 Rev.
Revised April 2009
Page
PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
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