PSoC Programmable System-on-Chip Pull Pull Down, High Strong, Ope
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CY8C28243, CY8C28403, CY8C28413 PRELIMINARY CY8C28433, CY8C28445, CY8C28452 CY8C28513, CY8C28533, CY8C28545 CY8C28623, CY8C28643, CY8C28645
PSoC Programmable System-on-Chip
Pull Pull Down, High Strong, Open Drain Drive Modes GPIO Analog Input GPIO Analog Outputs GPIO Configurable Interrupt GPIO
Varied Resource Options Within PSoC Device Group Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 3.0V 5.25V Operating Voltage Operating Voltages Down 1.0V Using On-Chip Switched Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Advanced Reconfigurable Peripherals (PSoC Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Multiple configurations Dedicated ADC, ksps with Sample Hold Synchronized Independent Delta-Sigma ADCs Advanced Applications Limited Type Analog Blocks Provide: Dual Channel Capacitive Sensing Capability Comparators with Programmable Reference 10-bit Single-Slope ADCs Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Shift Register, CRC, Modules Full-Duplex UARTs Half-Duplex UARTs Multiple Variable Data Length SPIMasters Slaves Connectable GPIO Complex Peripherals Combining Blocks Precision, Programmable Clocking Internal ±2.5% 24/48 Main Oscillator Optional 32.768 Crystal Precise On-Chip Clocks Optional External Oscillator, Internal Speed, Power Oscillator Watchdog Sleep Functionality Flexible On-Chip Memory Bytes Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink, Drive GPIO
Additional System Resources Hardware Resources Each Resource Implements Slave, Master, Multi-Master Modes Operation Between Watchdog Sleep Timers User-Configurable Voltage Detection Flexible Internal Voltage References Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full Featured In-Circuit Emulator, Programmer Full Speed Emulation Flexible Functional Breakpoint Structure 128K Trace Memory
System Block Diagram
Port Port Port Port Port Port
PSoC CORE
System
Global Digital Interconnect SRAM Interrupt Controller SROM
Analog Drivers
Global Analog Interconnect Flash Sleep Watchdog
Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
Analog Input Muxing
Digital Clocks
MACs
Type Decimators Blocks
System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-48111 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised March 2009
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PSoC Functional Overview
PSoC family consists many devices with On-Chip Controllers. These devices designed replace multiple traditional based system components with cost single chip programmable component. PSoC device includes configurable analog blocks, digital blocks, interconnections. This architecture enables user create customized peripheral configurations match requirements each individual application. addition, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. CY8C28xxx group PSoC devices described this data sheet have multiple resource configuration options available. Therefore, every resource mentioned this data sheet available each CY8C28xxx subgroup. CY8C28x45 subgroup full feature resources described. There more segmented subgroups that allow designers device with only resources functionality necessary specific application. Table page determine resources available each CY8C28xxx subgroup. same information also presented more detail Ordering Information section. architecture this specific PSoC device family, shown System Block Diagram page consists four main areas: PSoC Core, Digital System, Analog System, System Resources. configurable global system allows device resources combined into complete custom system. PSoC CY8C28xxx family devices have ports that connect global digital analog interconnects, providing access digital blocks analog blocks.
alone combined with other blocks create 32-bit peripherals, which called user modules. digital blocks connected GPIO through series global buses that route signal pin. Figure Digital System Block Diagram[1]
Port Port Port Port Port Port
Digital Clocks From Core
System
Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBC00 DBC01 DCC02
DCC03
Output Configuration
Input Configuration
DBC10 DBC11 DCC12
DCC13
Output Configuration
Input Configuration
DBC20 DBC21 DCC22
DCC23
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable general Purpose (GPIO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microcontroller. Memory encompasses bytes Flash program storage, bytes SRAM data storage. PSoC device incorporates flexible internal clock generators, including internal main oscillator (IMO) accurate 2.5% over temperature voltage. power internal speed oscillator (ILO) provided sleep timer watch timer (WDT). 32.768 external crystal oscillator (ECO) available real time clock (RTC) optionally generate crystal-accurate system clock using PLL. PSoC GPIOs provide connections CPU, digital analog resources. Each pin's drive mode selected from options, which allows great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include:
PWMs bit, One-shot Multi-shot capability) PWMs with Dead band/Kill bit) Counters bit) Timers bit) Full-duplex 8-bit UARTs with selectable parity Half-duplex 8-bit UARTs with selectable parity Variable length slave master total slaves masters (8-bit) Supports operation slave, master, multi-master available System Resources) IrDA Pseudo Random Sequence Generators bit) Cyclical Redundancy Checker/Generator bit) Shift Register bit)
Digital System
Digital System composed configurable digital PSoC blocks. Each block 8-bit resource that used
Note CY8C28x52 devices have digital block They have digital rows with eight total digital blocks.
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Analog System
Analog System composed configurable analog blocks, each containing opamp circuit that allows creation complex analog signal flows. Some devices this PSoC family have analog multiplex that connect every GPIO pin. This also connect analog system analysis with comparators analog-to-digital converters. split into sections simultaneous dual-channel processing. Some more common PSoC analog functions (most available user modules) are:
Figure Analog System Block Diagram CY8C28x45 CY8C28x52 Devices
GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
P2[3]
P2[1]
Analog
Analog-to-digital converters 14-bit resolution, selectable Incremental Delta Sigma) Dedicated 10-bit with sample rates ksps Synchronized, simultaneous Delta Sigma ADCs Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers with drive) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible
P2[4] P2[2] P2[0]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
ACI4[1:0]
ACI5[1:0]
Block Array
ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03
ACE00 ACE01 ASE11
ASD13
ASE10
ASC23
Analog Reference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
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Figure Analog System Block Diagram CY8C28x43 Devices
GPIO P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6]
Figure Analog System Block Diagram CY8C28x33 Devices
GPIO
P0[7]
P0[4]
P0[5]
P0[2] P0[0] P2[6]
P0[3]
P0[6] P0[4] P0[1] P0[2]
Analog
P2[3]
P2[3] P2[1]
P0[0] AGNDIn RefIn P2[6]
P2[4] P2[2] P2[0]
P2[1]
Analog
P2[4]
Array Input Configuration
Array Input Configuration
ACI0[1:0] ACI1[1:0] ACI4[1:0] ACI5[1:0]
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
Block Array
ACC00 ASC10 ASD20 ACC01 ASD11 ASC21 ACC02 ASC12 ASD22 ACC03 ASD13 ASC23
ACC00 ASC10 ASD20
ACC01
ACE00 ACE01 ASE11
ASD11
ASE10
ASC21
Analog Reference
Analog Reference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Interface Digital System
RefHi RefLo AGND
Reference Generators
AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
Interface (Address Bus, Data Bus, Etc.)
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Figure Analog System Block Diagram CY8C28x23 Devices
P0[7] P0[5] P0[3] P0[4] P0[1] P2[3] P2[1] AGNDIn RefIn P0[2] P0[0] P2[6]
Figure Analog System Block Diagram CY8C28x13 Devices
GPIO
P0[5] P0[3] P0[1]
Analog
P0[6]
P0[7]
P0[6] P0[4] P0[2] P0[0]
P2[4]
ACI0[1:0]
Array Input Configuration
ACI1[1:0]
Array Input Configuration
ACI0[1:0] ACI1[1:0]
Block Array
ACE00 ASE10 ACE01 ASE11
Block Array
ACC00 ASC10 ASD20 ACC01 ASD11 ASC21
Analog Reference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Analog Reference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
Interface (Address Bus, Data Bus, Etc.)
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System Resources
System Resources, some which listed previous sections, provide additional capability useful complete systems. Additional resources include multiplier, multiple decimators, switch mode pump, voltage detection, power reset. Statements describing merits each system resource follow:
Table PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size Bytes Bytes Bytes Bytes Bytes Bytes PSoC Part Number CY8C29x66 CY8C28xxx CY8C27x43 CY8C24x94 Flash Size
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist general math digital filters. four decimators provide custom hardware filters digital signal processing applications such Delta-Sigma ADCs CapSense capacitive sensor measurement. resources provide communication over wires. Slave, master, multi-master modes supported. resources have hardware address detection capability. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter.
12/4[2] 4[3] 4[3] 3[4]
CY8C24x23A CY8C23x33 CY8C21x34 CY8C21x23 CY8C20x34
devices covered this data sheet have same architecture, specifications, ratings. However, amount some hardware resources varies from device device within group. following table lists resources available specific device subgroups covered this data sheet. Table CY8C28xxx Device Characteristics
Digital Blocks Regular Analog Blocks Limited Analog Blocks Decimators CapSense Analog Outputs Analog Inputs
PSoC Device Characteristics
There other PSoC device groups addition described this data sheet. These other PSoC device groups offer even more resource options. following table lists resources available specific PSoC device groups. PSoC device group covered this data sheet highlighted.
PSoC Part Number
CY8C28x03 CY8C28x13 CY8C28x23 CY8C28x33 CY8C28x43 CY8C28x45 CY8C28x52
Notes regular analog blocks four limited Type-E analog blocks Limited analog functionality. analog blocks CapSense.
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Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC® Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices. up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
PSoC Designer also supports language compilers developed specifically devices PSoC family.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC On-Chip Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools. Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Page
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers.
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Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
In-Circuit Emulator
cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse
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Document Conventions
Acronyms Used
following table lists acronyms that used this document. Acronym EEPROM GPIO IPOR PPOR PSoC® SLIMO SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator successive approximation register switched capacitor slow switch mode pump static random access memory
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated decimal.
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Pinouts
This section describes, lists, illustrates CY8C28xxx PSoC device pins pinout configurations. CY8C28xxx PSoC devices available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital However, Vss, Vdd, SMP, XRES capable Digital
20-Pin Part Pinout
Table 20-Pin Part Pinout (SSOP) Type Digital Analog Name Description CY8C28243 20-Pin PSoC Device
P0[6], P0[4], AIO, P0[2], AIO, P0[0], XRES P1[6], I2C1 P1[4], EXTCLK P1[2], I2C1 P1[0], XTALout, I2C0
P0[7] P0[7] Analog column input.[6] AIO, P0[5] AIO, P0[3] P0[5] Analog column P0[1] input. Analog column output.[6, SSOP P0[3] Analog column I2C0 SCL, P1[7] input. Analog column output.[6, I2C0 SDA, P1[5] P0[1] Analog column P1[3] input. I2C0 SCL, XTALin, P1[1] Output Switch Mode Pump (SMP) connection external components. P1[7] I2C0 Serial Clock (SCL). P1[5] I2C0 Serial Data (SDA). P1[3] P1[1] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Power Ground connection. P1[0] Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. P1[2] I2C1 Serial Data (SDA).[8] P1[4] Optional External Clock Input (EXTCLK). P1[6] I2C1 Serial Clock (SCL).[8] Input XRES Active high external reset with internal pull down. P0[0] Analog column input.[6] P0[2] Analog column input. Analog column output.[6, P0[4] Analog column input. Analog column output.[6, P0[6] Analog column input.[6] Power Supply voltage. LEGEND: Analog, Input, Output, Input, Analog Input.
Notes These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices details. CY8C28x52 CY8C28x23 devices have ADC. Therefore, this does function input these devices. CY8C28x13 CY8C28x03 devices have analog output buffers. Therefore, this does function analog column output these devices. CY8C28x52, CY8C28x13, CY8C28x33 devices only have block. Therefore, this GPIO does function these devices. CY8C28x33, CY8C28x23, CY8C28x13, CY8C28x03 devices have analog output buffer this pin. Therefore, this does function analog column output these devices.
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28-Pin Part Pinout
Table 28-Pin Part Pinout (SSOP)
Input Power Power Type Digital Analog Output Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] Direct switched capacitor block input.[10] Direct switched capacitor block input.[10] Switch Mode Pump (SMP) connection external components. I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Description
CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452 28-Pin PSoC Devices
P0[7] AIO, P0[5] AIO, P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] I2C0 SCL, P1[7] I2C0 SDA, P1[5] P1[3] I2C0 SCL, XTALin, P1[1]
Analog column input.[6] Analog column input. Analog column output.[6, Analog column input. Analog column output.[6, Analog column input.[6]
SSOP
P0[6], P0[4], AIO, P0[2], AIO, P0[0], P2[6], External VRef P2[4], External AGND P2[2], P2[0], XRES P1[6], I2C1 P1[4], EXTCLK P1[2], I2C1 P1[0], XTALout, I2C0
XRES Active high external reset with internal pull down. P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input.[6] Analog column input. Analog column output.[6, Analog column input. Analog column output.[6, Analog column input.[6] Supply voltage.
LEGEND: Analog, Input, Output, Input, Analog Input
Notes This direct switched capacitor block analog input CY8C28x03 CY8C28x13 devices. This direct switched capacitor block analog input CY8C28x03, CY8C28x13, CY8C28x23, CY8C28x33 devices.
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44-Pin Part Pinout
Table 44-Pin Part Pinout (TQFP)
Type Digital Analog Output Output Input Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] Description Direct switched capacitor block input.[10] Direct switched capacitor block input.[10]
CY8C28513, CY8C28533, CY8C28545 44-Pin PSoC Devices
P2[7], P0[1], P0[3], AIO, P0[5], AIO, P0[7], P0[6], P0[4], AIO, P0[2], AIO, P0[0], P2[6], External VRef P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] I2C0 SCL, P1[7] I2C0 SDA, P1[5] P1[3] I2C0 SCL, XTALin, P1[1] I2C0 SDA, XTALout, P1[0] I2C1 SDA, P1[2] EXTCLK, P1[4] I2C1 SCL, P1[6] I2C1 SDA, P3[0]
Switch Mode Pump (SMP) connection external components.
I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8] I2C1 Serial Data (SDA).[8] I2C1 Serial Clock (SCL).[8]
TQFP
P2[4], External AGND P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[6], P3[4], P3[2], I2C1
Active high external reset with internal pull down.
Power
P0[1] P2[7] LEGEND: Analog, Input, Output, Input, Analog Input.
Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input.[6] Analog column input. Analog column output.[6, Analog column input. Analog column output.[6, Analog column input.[6] Supply voltage. Analog column input.[6] Analog column input. Analog column output.[6, Analog column input. Analog column output.[6, Analog column input.[6]
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48-Pin Part Pinout
Table 48-Pin Part Pinout (QFN[12])
Type Digital Analog Output Power Input Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] Description Direct switched capacitor block input.[10] Direct switched capacitor block input.[10]
CY8C28623, CY8C28643, CY8C28645 48-Pin PSoC Devices
P2[5], P2[7], P0[1], P0[3], AIO, P0[5], AIO, P0[7], P0[6], P0[4], AIO, P0[2], AIO, P0[0], P2[6], External VRef
Switch Mode Pump (SMP) connection external components.
I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA).[8] Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL).[8]
P1[6] P5[0] P5[2] P3[0] I2C1 Serial Data (SDA).[8] P3[2] I2C1 Serial Clock (SCL).[8] P3[4] P3[6] XRES Active high external reset with internal pull down. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0]
Type Digital Analog Power
P5[1] I2C0 SCL, P1[7] I2C0 SDA, P1[5] P1[3] I2C0 SCL, XTALin, P1[1] I2C0 SDA, XTALout, P1[0] I2C1 SDA, P1[2] EXTCLK, P1[4] I2C1 SCL, P1[6] P5[0] P5[2]
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3]
(Top View)
P2[4], External AGND P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], XRES P3[6], P3[4], P3[2], I2C1 P3[0], I2C1
Name P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Description Analog column input.[6] Supply voltage. Analog column input.[6] Analog column input. Analog column output.[6, Analog column input. Analog column output.[6, Analog column input.[6]
Direct switched capacitor block input.[11] Direct switched capacitor block input.[11] External Analog Ground (AGND). External Voltage Reference (VRef).
Analog column input.[6] P0[2] Analog column input. Analog column output.[6, P0[4] Analog column input. Analog column output.[6, LEGEND: Analog, Input, Output, Input, Analog Input.
Note package center that must connected ground (Vss)
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56-Pin Part Pinout
56-pin SSOP part CY8C28000 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 56-Pin Part Pinout (SSOP)
Power Output Type Digital Analog Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE even data OCDO data output. P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] I2C1 Serial Data (SDA). I2C1 Serial Clock (SCL). Crystal Input (XTALin), I2C0 Serial Clock (SCL), ISSP-SCLK[5]. Ground connection. connection. connection. Crystal Output (XTALout), I2C0 Serial Data (SDA), ISSP-SDATA[5]. I2C1 Serial Data (SDA). Optional External Clock Input (EXTCLK). I2C1 Serial Clock (SCL). I2C0 Serial Clock (SCL). I2C0 Serial Data (SDA). connection. Switch Mode Pump (SMP) connection required external components. Direct switched capacitor block input. Direct switched capacitor block input. Description connection. Analog column input. Analog column input. Analog column output. Analog column input. Analog column output. Analog column input.
CY8C28000 56-Pin PSoC Device
P0[7] AIO, P0[5] AIO, P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2C0 SCL, P1[7] I2C0 SDA, P1[5] P1[3] SCLK, I2C0 SCL, XTALIn, P1[1] P0[6], P0[4], AIO, P0[2], AIO, P0[0], P2[6], External VRef P2[4], External AGND P2[2], P2[0], P4[6], P4[4], P4[2], P4[0], CCLK HCLK XRES P3[6], P3[4], P3[2], I2C1 P3[0], I2C1 P5[2], P5[0], P1[6], I2C1 P1[4], EXTCLK P1[2], I2C1 P1[0], XTALOut, I2C0 SDA, SDATA
SSOP
Production
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Table 56-Pin Part Pinout (SSOP) (continued)
Type Digital Analog Input Power Name Description
XRES Active high external reset with internal pull down. HCLK high-speed clock output. CCLK clock output. P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input. Analog column output. Analog column input. Analog column output. Analog column input. Supply voltage.
LEGEND: Analog, Input, Output, Input, Analog Input, On-Chip Debug.
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Register Reference
This section lists registers CY8C28xxx PSoC devices. detailed register information, reference PSoC Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices.
Register Conventions
register conventions specific this section listed following table. Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Register Mapping Tables
CY8C28xxx PSoC devices have total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank registers instructions access. When registers Bank accessed instructions. When cleared registers Bank accessed instructions. Note following register mapping tables, blank fields reserved should accessed.
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CY8C28x03 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 I2C1_DR Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access specific. MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access Name Addr (0,Hex) CPU_SCR1 CPU_F MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 Blank fields Reserved should accessed.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
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CY8C28x03 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 SADC_TSCR0 SADC_TSCR1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) Access specific. GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM Access Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
*Address dual purpose, "Mapping Exceptions" page
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CY8C28x13 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access specific. MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access Name Addr (0,Hex) DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 Blank fields Reserved should accessed.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
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CY8C28x13 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMUX_CFG1 Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
Access specific.
*Address dual purpose, "Mapping Exceptions" page
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CY8C28x23 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access specific. MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 DEC0_DH DEC0_DL DEC1_DH DEC1_DL Access ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 Blank fields Reserved should accessed.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
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CY8C28x23 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) Access specific. I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC_CR5 DEC1_CR0 DEC0_CR0 DEC_CR3 Access Name Addr (1,Hex) CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
*Address dual purpose, "Mapping Exceptions" page
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CY8C28x33 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access specific. DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 Addr (0,Hex) DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 Blank fields Reserved should accessed.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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PRELIMINARY
CY8C28xxx
CY8C28x33 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR2 AMUX_CFG1 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
Access specific.
*Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x43 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) Access CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 ACB03CR2 Blank fields Reserved should accessed.
Access specific.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x43 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 SADC_TSCR0 SADC_TSCR1 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) Access specific. GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access Name SADC_TSCMPL SADC_TSCMPH Addr (1,Hex) CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 Access Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
*Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x45 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 SADC_DH SADC_DL TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 I2C1_DR Access Name DBC20DR0 DBC20DR1 DBC20DR2 DBC20CR0 DBC21DR0 DBC21DR1 DBC21DR2 DBC21CR0 DCC22DR0 DCC22DR1 DCC22DR2 DCC22CR0 DCC23DR0 DCC23DR1 DCC23DR2 DCC23CR0 Addr (0,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) Access DAC1_D DAC0_D CPU_SCR1 CPU_F IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT I2C1_SCR I2C1_MSCR DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 CUR_PP STK_PP Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (0,Hex) Access
DCC13CR0 ACB03CR2 Blank fields Reserved should accessed.
Access specific.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x45 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 SADC_TSCR0 SADC_TSCR1 ACE_AMD_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 I2C1_CFG TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 Access Name DBC20FN DBC20IN DBC20OU DBC20CR1 DBC21FN DBC21IN DBC21OU DBC21CR1 DCC22FN DCC22IN DCC22OU DCC22CR1 DCC23FN DCC23IN DCC23OU DCC23CR1 Addr (1,Hex) GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR SADC_CR0 SADC_CR1 SADC_CR2 SADC_CR3 SADC_CR4 I2C0_ADDR I2C1_ADDR AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 Access ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR Name SADC_TSCMPL SADC_TSCMPH ACE_AMD_CR1 Addr (1,Hex) IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F Access GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 Name RDI2RI RDI2SYN RDI2IS RDI2LT0 RDI2LT1 RDI2RO0 RDI2RO1 RDI2DSM Addr (1,Hex) Access
Blank fields Reserved should accessed.
Access specific.
*Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x52 Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Addr (0,Hex) DBC00DR0 DBC00DR1 DBC00DR2 DBC00CR0 DBC01DR0 DBC01DR1 DBC01DR2 DBC01CR0 DCC02DR0 DCC02DR1 DCC02DR2 DCC02CR0 DCC03DR0 DCC03DR1 DCC03DR2 DCC03CR0 DBC10DR0 DBC10DR1 DBC10DR2 DBC10CR0 DBC11DR0 DBC11DR1 DBC11DR2 DBC11CR0 DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 DCC13DR1 DCC13DR2 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2 ACB02CR3 ACB02CR0 ACB02CR1 ACB02CR2 ACB03CR3 ACB03CR0 ACB03CR1 AMX_IN AMUX_CFG CLK_CR3 ARF_CR CMP_CR0 ASY_CR CMP_CR1 Access Name Addr (0,Hex) Access Name ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3 DEC0_DH DEC0_DL DEC1_DH DEC1_DL DEC2_DH DEC2_DL DEC3_DH DEC3_DL MUL1_X MUL1_Y MUL1_DH MUL1_DL ACC1_DR1 ACC1_DR0 ACC1_DR3 ACC1_DR2 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI0DSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Addr (0,Hex) Access DAC1_D DAC0_D CPU_SCR1 CPU_F DEC_CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT CUR_PP STK_PP Name Addr (0,Hex) Access
DCC13CR0 ACB03CR2 Blank fields Reserved should accessed.
Access specific.
RDI1DSM CPU_SCR0 *Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
CY8C28x52 Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Addr (1,Hex) DBC00FN DBC00IN DBC00OU DBC00CR1 DBC01FN DBC01IN DBC01OU DBC01CR1 DCC02FN DCC02IN DCC02OU DCC02CR1 DCC03FN DCC03IN DCC03OU DCC03CR1 DBC10FN DBC10IN DBC10OU DBC10CR1 DBC11FN DBC11IN DBC11OU DBC11CR1 DCC12FN DCC12IN DCC12OU DCC12CR1 DCC13FN DCC13IN DCC13OU DCC13CR1 ACE0_CR1 ACE0_CR2 ACE0_CR3 ACE_CMP_GI_EN ACE_ALT_CR0 ACE_ABF_CR0 ACE_AMX_IN ACE_CMP_CR0 ACE_CMP_CR1 ACE_AMD_CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN CMP_GO_EN1 AMD_CR1 ALT_CR0 ALT_CR1 CLK_CR2 AMUX_CFG1 Access Name Addr (1,Hex) AMUX_CLK RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDIODSM RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 RDI1DSM I2C0_ADDR GDI_O_IN_CR GDI_E_IN_CR GDI_O_OU_CR GDI_E_OU_CR RTC_H RTC_M RTC_S RTC_CR DEC3_CR0 DEC2_CR0 DEC_CR5 DEC1_CR0 DEC_CR4 DEC0_CR0 DEC_CR3 ACE01CR1 ACE01CR2 ASE11CR0 ACE_CLK_CR0 ACE_CLK_CR1 ACE_CLK_CR3 ACE_PWM_CR ACE_ADC0_CR ACE_ADC1_CR ACE_AMD_CR1 Access Name Addr (1,Hex) IDAC_CR0 CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU DEC0_CR DEC1_CR DEC2_CR DEC3_CR MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 IDAC_CR1 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IDAC_CR2 IMO_TR ILO_TR BDG_TR ECO_TR MUX_CR4 MUX_CR5 Access Name Addr (1,Hex) Access
Blank fields Reserved should accessed.
Access specific.
*Address dual purpose, "Mapping Exceptions" page
Document Number: 001-48111 Rev.
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CY8C28xxx
Electrical Specifications
This section presents electrical specifications CY8C28xxx PSoC devices. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC, except where noted. Specifications devices running greater than valid -40oC 70oC 82oC. Figure Voltage versus Frequency
5.25
4.75
following table lists units measure that used this section. Table Units Measure Symbol
Kbit Vrms
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Document Number: 001-48111 Rev.
Voltage 3.00
Frequency
Symbol ksps
Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond kilo-samples second sigma: standard deviation volts
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CY8C28xxx
Absolute Maximum Ratings
Table Absolute Maximum Ratings Symbol Description TSTG Storage Temperature +100 Units Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrade reliability.
VIOZ IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch-up Current
-0.5 Vss0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units Notes temperature rise from ambient junction package specific. Thermal Impedances page user must limit power consumption comply with this requirement.
Document Number: 001-48111 Rev.
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CY8C28xxx
Electrical Characteristics
Chip Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip Level Specifications Symbol Description Supply Voltage Supply Current 3.00 5.25 Units Notes Conditions 5.0V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions 3.3V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions with internal slow speed oscillator, 3.3V, Conditions with internal slow speed oscillator, 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Trimmed appropriate Vdd.
IDD3
Supply Current
ISBH ISBXTL ISBXTLH VREF IXRES
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal.[13] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal high temperature.[13] Reference Voltage (Bandgap)
1.280
1.300
1.320
Note Standby (sleep) current includes functions (POR, LVD, WDT, Sleep Timer) needed reliable system operation. This should compared with devices that have similar functions enabled.
Document Number: 001-48111 Rev.
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CY8C28xxx
General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications Symbol Description Pull Resistor Pull Down Resistor High Output Level Units Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifiers covered these specifications components both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Table Operational Amplifier Specifications Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) IEBOA Input Capacitance (Port Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias) Symbol VOSOA 35.0 Units V/oC Notes
CMRROA Common Mode Rejection Ratio Power Power Medium Power High
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
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Table Operational Amplifier Specifications (continued) Symbol GOLOA Description Open Loop Gain Power Power Medium Power High VOHIGHOA High Output Voltage Swing (internal signals) Power Power Medium Power High VOLOWOA Output Voltage Swing (internal signals) Power Power Medium Power High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High PSRROA Supply Voltage Rejection Ratio Units Notes Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
1200 2400 4600
1600 3200 6400
(Vdd 2.25) (Vdd 1.25V) Vdd.
Table 3.3V Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range 1.65 1.32 35.0 Units V/oC Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum Specification applicable high power. other bias modes (except high power, high opamp bias), minimum Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA
CMRROA Common Mode Rejection Ratio Power Power Medium Power High GOLOA Open Loop Gain Power Power Medium Power High
VOHIGHOA High Output Voltage Swing (internal signals) Power Power Medium Power High only
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Table 3.3V Operational Amplifier Specifications (continued) Symbol Description 1200 2400 4600 1600 3200 6400 Units (Vdd 2.25) (Vdd 1.25V) Vdd. Notes VOLOWOA Output Voltage Swing (internal signals) Power Power Medium Power High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
PSRROA
Type-E Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifiers covered these specifications components Limited Type Analog PSoC blocks. Table Type-E Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Units V/oC Gross tested Package dependent. Temp 25oC. Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port Analog Pins) CINOA VCMOA GOLOA ISOA Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current
Table 3.3V Type-E Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Units V/oC Gross tested Package dependent. Temp 25oC. Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA[14] Input Leakage Current (Port Analog Pins) CINOA VCMOA GOLOA ISOA Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current
Note Atypical behavior: IEBOA Port below 25°C; over temperature. Port Pins lowest leakage
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Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol VREFLPC VOSLPC ISLPC Description power comparator (LPC) reference voltage range voltage offset supply current Units Notes
Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Units V/°C Notes
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB
PSRROB
Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio
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Table 3.3V Analog Output Buffer Specifications Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High VOHIGHOB High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Symbol VOSOB TCVOSOB VCMOB ROUTOB Units V/°C Notes
Output Voltage Swing (Load ohms Vdd/2) Power Power High
ISOB PSRROB
Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio
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Switch Mode Pump Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Switch Mode Pump (SMP) Specifications Symbol VPUMP VPUMP IPUMP VBAT5V VBAT3V VBATSTART VPUMP_Line Description Output Voltage 4.75 5.25 Units Notes Configuration footnote.[15] Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.[15] Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.[15] trip voltage 3.25V. trip voltage 5.0V. Configuration footnote.[15] trip voltage 5.0V. Configuration footnote.[15] trip voltage 3.25V. Configuration footnote.[15] Configuration footnote.[15] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[15] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[15] Load 5mA. Configuration footnote.[15] Load trip voltage 3.25V.
Output Voltage
3.00
3.25
3.60
Available Output Current VBAT 1.5V, VPUMP 3.25V VBAT 1.8V, VPUMP 5.0V Input Voltage Range from Battery Input Voltage Range from Battery
Minimum Input Voltage from Battery Start Pump Line Regulation (over VBAT range)
VPUMP_Load
Load Regulation
VPUMP_Ripple FPUMP DCPUMP
Output Voltage Ripple (depends capacitor/load) Efficiency Switching Frequency Switching Duty Cycle
mVpp
Note inductor, capacitor, Schottky diode. Figure
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Figure Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Analog Reference Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Table Analog Reference Specifications Symbol VBG5 Description Bandgap Voltage Reference AGND Vdd/2[16] AGND BandGap[16] AGND P2[4] (P2[4] Vdd/2)[16] AGND BandGap[16] AGND BandGap[16] AGND Block Block Variation (AGND Vdd/2)[16] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) 1.28 Vdd/2 0.02 2.52 P2[4] 0.013 1.27 2.03 -0.034 Vdd/2 1.21 3.75 P2[6] 2.478 P2[4] 1.218 P2[4] P2[6] 0.058 2.50 4.02 Vdd/2 1.369 1.20 2.489 P2[6] P2[4] 1.368 P2[4] P2[6] 0.042 1.30 Vdd/2 2.60 P2[4] 2.08 0.000 Vdd/2 P2[6] P2[4] P2[4] P2[6] 2.60 4.16 Vdd/2 1.30 1.30 P2[6] P2[4] 1.30 P2[4] P2[6] 1.32 Vdd/2 0.02 2.72 P2[4] 0.013 1.34 2.13 0.034 Vdd/2 1.382 4.05 P2[6] 2.722 P2[4] 1.382 P2[4] P2[6] 0.058 2.70 4.29 Vdd/2 1.231 1.40 2.711 P2[6] P2[4] 1.232 P2[4] P2[6] 0.042 Units
Note AGND tolerance includes offsets local buffer PSoC block.
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Table 3.3V Analog Reference Specifications Symbol VBG33 Description Bandgap Voltage Reference 3.3V AGND Vdd/2[16] AGND BandGap[16] AGND P2[4] (P2[4] Vdd/2) AGND BandGap[16] AGND BandGap[16] AGND Block Block Variation (AGND Vdd/2)[16] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) 1.30 Vdd/2 P2[4] 1.30 2.08 0.000 1.32 Vdd/2 0.02 P2[4] 0.009 1.34 2.13 0.034 1.28 Vdd/2 0.02 Allowed P2[4] 0.009 1.27 2.03 -0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.042 RefHi BandGap 2.50 RefHi BandGap Allowed RefLo Vdd/2 BandGap Allowed RefLo BandGap Allowed RefLo BandGap P2[6] (P2[6] 0.5V) Allowed RefLo P2[4] BandGap (P2[4] Vdd/2) Allowed RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) P2[4] P2[6] 0.036 Units
P2[4] P2[6] 2.60
P2[4] P2[6] 0.042 2.70
P2[4] P2[6]
P2[4] P2[6] 0.036
Note Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V.
Analog PSoC Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog PSoC Block Specifications Symbol Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) 12.24 Units Notes
Analog Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Specifications Symbol RVDD Description Switch Resistance Common Analog Resistance Initialization Switch Units Notes 2.7V 2.4V 2.7V
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SAR10 Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR10 Specifications Description Integral nonlinearity Differential nonlinearity Active current consumption Input current into P2[5] when configured SAR10 ADC's VREF input. VVREFSAR10 Input reference voltage P2[5] when configured SAR10 ADC's external voltage reference. Symbol INLSAR10 DNLSAR10 ISAR10 IVREFSAR10 -2.5 -1.5 4.95 Units Notes 10-bit resolution 10-bit resolution internal voltage reference buffer disabled this configuration. When VREF buffered inside SAR10 ADC, voltage level P2[5] (when configured external reference voltage) must always least less than chip supply voltage level pin. (VVREFSAR10 (Vdd
VOSSAR10
Offset voltage
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Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV table below refer bits VLT_CR register. PSoC Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices, more information VLT_CR register. Table Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Value PPOR Trip (positive ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value PUMP Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.91 4.39 4.55 2.82 4.39 4.55 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00 Units Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72 2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90
2.98[17] 3.08 3.20 4.08 4.57 4.74[18] 4.82 4.91 3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10
Notes Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Description Supply Current During Programming Verify Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[19] FlashDR Flash Data Retention Symbol IDDP VILP Units Driving internal pull-down resistor. Driving internal pull-down resistor. Notes
0.75 Erase/write cycles block. Erase/write cycles. Years
50,000 1,800,000
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Description Internal Main Oscillator Frequency Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency 23.4 0.091 0.091 24.6[20] 24.6[20, 12.3[21,22] Units Notes Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Refer Digital Block Specifications below.
49.2[20,21,23]
Digital PSoC Block Frequency Internal Speed Oscillator Frequency External Crystal Oscillator Frequency
24.6[21, 32.768 23.986 1700 2800 2620 3800
Accuracy capacitor crystal dependent. duty cycle. Multiple (x732) crystal frequency.
Jitter24M2 Period Jitter (PLL) TPLLSLEW Lock Time TPLLSLEWS Lock Time Gain Setting
TOSACC
External Crystal Oscillator Startup External Crystal Oscillator Startup
crystal oscillator frequency within final value Tosacc period. Correct operation assumes properly loaded maximum drive level 32.768 crystal. 3.0V 5.5V,
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Period Jitter (IMO) Maximum Frequency Signal Input Output. Supply Ramp Time
46.8
48.0
49.2[20,22]
Trimmed. Utilizing factory trim values.
12.3
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
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Figure Lock Timing Diagram
Enable
TPLLSLEW
FPLL Gain
Figure Lock Gain Setting Timing Diagram
Enable
TPLLSLEWLOW
FPLL Gain
Figure External Crystal Oscillator Startup Timing Diagram
Select
F32K2
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ECO) Timing Diagram
Jitter32k
32K2
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General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload 12.3 Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifiers covered these specifications components both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Units Notes
0.72 0.62
TSOA
0.15
0.92 0.72
SRROA
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Table Operational Amplifier Specifications (continued) Symbol SRFOA Description Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Noise Power Medium, Opamp Bias High 0.01 Units Notes
BWOA
ENOA
0.75
nV/rt-H
Table 3.3V Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Low, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Slew Rate (80% 20%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Noise Power Medium, Opamp Bias High Units Notes
3.92 0.72
TSOA
0.31
5.41 0.72
SRROA
SRFOA
0.24
BWOA ENOA
0.67
nV/rt-H
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When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor (TBD dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure Typical AGND Noise with P2[4] Bypass
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level. Figure Typical Opamp Noise
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Type-E Operational Amplifier Specifications
Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Operational Amplifiers covered these specifications components Limited Type Analog PSoC blocks. Table Type-E Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, Overdrive Units Notes
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol TRLPC Description Response Time Units Notes overdrive comparator reference within VREFLPC.
Analog Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Specifications Symbol Description Switch Rate 3.17 Units Notes
Digital Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Digital Block Specifications Function Description Maximum Block Clocking Frequency 4.75V) Functions Maximum Block Clocking Frequency 4.75V) Timer Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Kill Pulse Width: Band Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) 50[24] 50[24] 50[24] 50[24] 49.2 24.6 49.2 24.6 49.2 24.6 49.2 49.2 Units Notes 4.75V 5.25V. 3.0V 4.75V. 4.75V 5.25V.
4.75V 5.25V.
4.75V 5.25V. 4.75V 5.25V.
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Table Digital Block Specifications (continued) Function Description CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM Maximum Input Clock Frequency SPIS Transmitter Receiver 24.6 24.6 49.2 24.6 49.2 Units Notes
Maximum data rate over clocking.
Maximum Input Clock Frequency Width Negated Between Transmissions 50[24] Full Range 4.75V, Stop Bits Full Range 4.75V, Stop Bits
Maximum data rate 3.16 over clocking. Maximum data rate 6.30 over clocking. Maximum data rate 3.16 over clocking. Maximum data rate 6.30 over clocking.
Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol Description TROB Rising Settling Time 0.1%, Step, Load Power Power High TSOB Falling Settling Time 0.1%, Step, Load Power Power High SRROB Rising Slew Rate (20% 80%), Step, Load Power Power High SRFOB Falling Slew Rate (80% 20%), Step, Load Power Power High BWOB Small Signal Bandwidth, 20mVpp, Load Power Power High BWOB Large Signal Bandwidth, 1Vpp, Load Power Power High Units Notes
0.65 0.65
0.65 0.65
Note minimum input pulse width based input synchronizers running nominal period).
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Table 3.3V Analog Output Buffer Specifications Symbol TROB TSOB SRROB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High Units Notes
SRFOB
BWOB
BWOB
SAR10 Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR10 Specifications Symbol FINSAR10 FSSAR10 Description Input clock frequency SAR10 Sample rate SAR10 SAR10 Resolution bits 1.538 118.3 Units ksps Notes 10-bit resolution, sample rate ADC's input clock divided
External Clock Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Units Notes
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Table 3.3V External Clock Specifications Symbol FOSCEXT FOSCEXT Description Frequency with Clock divide 1[25] Frequency with Clock divide greater[26] High Period with Clock divide Period with Clock divide Power Switch 0.093 0.186 41.7 41.7 12.3 24.6 5300 Units Notes
Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time SCLK Fall Time SCLK Data Setup Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units Notes
Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
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Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Characteristics Pins Symbol Description Standard Mode Fast Mode 100[27] Units Notes
Clock Frequency FSCLI2C THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C Period Clock HIGH Period Clock THIGHI2C TSUSTAI2C Setup Time Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time STOP Condition Free Time Between STOP START TBUFI2C Condition TSPI2C Pulse Width spikes suppressed input filter.
Figure Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Packaging Information
This section illustrates packaging specifications CY8C28xxx PSoC devices, along with thermal impedances each package typical package capacitance crystal pins. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 20-Pin (210-Mil) SSOP
51-85077
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Figure 28-Pin (210-Mil) SSOP
51-85079*C
Figure 44-Pin TQFP
51-85155
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Figure 48-Pin (7x7
001-13191
Important Note information preferred dimensions mounting packages, following Application Note Figure 56-Pin SSOP Package
51-85062
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Thermal Impedances
Table Thermal Impedances Package Package SSOP SSOP TQFP SSOP Typical [28]
Capacitance Crystal Pins
Table Typical Package Capacitance Crystal Pins Package SSOP SSOP TQFP SSOP Package Capacitance
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP SSOP TQFP SSOP Minimum Peak Temperature[29] Maximum Peak Temperature
Notes POWER Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
This section presents development tools available current PSoC device families including CY8C28xxx family.
Software
PSoC Designer core PSoC development software suite PSoC Designer. Utilized thousands PSoC developers, this robust software been facilitating PSoC designs over half decade. PSoC Designer available free charge PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC Programmer available free charge PSoC Compilers CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items. CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
Development Kits
development kits purchased from Cypress Online Store. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advanced emulation features supported PSoC Designer. includes:
Evaluation Tools
evaluation tools purchased from Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator CY8C29x66 PSoC Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
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CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Device Programmers
device programmers purchased from Cypress Online Store. CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP programmer needs PSoC ISSP software. compatible with PSoC Programmer software. latest PSoC ISSP software this downloaded from http://www.cypress.com. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part CY8C28243-24PVXI CY8C28403-24PVXI CY8C28413-24PVXI CY8C28433-24PVXI CY8C28445-24PVXI CY8C28452-24PVXI CY8C28513-24AXI CY8C28533-24AXI CY8C28545-24AXI CY8C28623-24LTXI CY8C28643-24LTXI CY8C28645-24LTXI 3rd-Party Tools Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards. Package SSOP SSOP Kit[30] CY3250-28XXX CY3250-28XXX Foot Kit[31] CY3250-20SSOP-FK CY3250-28SSOP-FK Adapter[32]
TQFP
CY3250-28XXX
CY3250-44TQFP-FK
Adapters found http://www.emulation.com.
CY3250-28XXXQFN CY3250-48QFN-FK
Build PSoC Emulator into Your Board details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com/an2323.
Notes contains emulation pod, flex-cable (connects ICE), feet, device samples. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
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Ordering Information
following table lists CY8C28xxx PSoC devices package features ordering codes. Regular Analog Blocks Limited Analog Blocks
Temperature Range
10-bit
Analog Outputs
Ordering Code
Flash (KBytes)
Digital Pins
(KBytes)
Analog Inputs
Digital Blocks
Decimators
CapSense
28-Pin (210 Mil) SSOP 28-Pin (210 Mil) SSOP (Tape Reel) 28-Pin (210 Mil) SSOP 28-Pin (210 Mil) SSOP (Tape Reel) 44-Pin TQFP 44-Pin TQFP (Tape Reel) 48-Pin Sawn 48-Pin Sawn (Tape Reel) 28-Pin (210 Mil) SSOP 28-Pin (210 Mil) SSOP (Tape Reel) 44-Pin TQFP 44-Pin TQFP (Tape Reel) 20-Pin (210 Mil) SSOP 20-Pin (210 Mil) SSOP (Tape Reel) 48-Pin Sawn 48-Pin Sawn (Tape Reel) 28-Pin (210 Mil) SSOP 28-Pin (210 Mil) SSOP (Tape Reel) 44-Pin TQFP
CY8C28403-24PVXI CY8C28403-24PVXIT CY8C28413-24PVXI CY8C28413-24PVXIT CY8C28513-24AXI CY8C28513-24AXIT CY8C28623-24LTXI CY8C28623-24LTXIT CY8C28433-24PVXI CY8C28433-24PVXIT CY8C28533-24AXI CY8C28533-24AXIT CY8C28243-24PVXI CY8C28243-24PVXIT CY8C28643-24LTXI CY8C28643-24LTXIT CY8C28445-24PVXI CY8C28445-24PVXIT CY8C28545-24AXI
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Regular Analog Blocks
Limited Analog Blocks
Temperature Range
10-bit
Analog Outputs
Ordering Code
Flash (KBytes)
Digital Pins
(KBytes)
Analog Inputs
Digital Blocks
Decimators
CapSense
44-Pin TQFP (Tape Reel) 48-Pin Sawn 48-Pin Sawn (Tape Reel) 28-Pin (210 Mil) SSOP 28-Pin (210 Mil) SSOP (Tape Reel) 56-Pin SSOP
CY8C28545-24AXIT CY8C28645-24LTXI CY8C28645-24LTXIT CY8C28452-24PVXI CY8C28452-24PVXIT CY8C28000-24PVXI
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Ordering Code Definitions
xxxx Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free LTX/LFX/LKX Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress Thermal Rating: Commercial Industrial Extended
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Document History Page
Document Title: CY8C28243, CY8C28403, CY8C28413, CY8C28433, CY8C28445, CY8C28452, CY8C28513, CY8C28533, CY8C28545, CY8C28623, CY8C28643, CY8C28645 PSoC® Programmable System-on-Chip Document Number: 001-48111 Origin Submission Revision Description Change Change Date 2593460 BTK/PYRS 10/20/08 document (Revision **). 2652217 BTK/PYRS 02/02/09 Extensive updates content. Added registers maps. Updated Getting Started section Updated Development Tools section Added some SAR10 specifications. Added more analog system figures 2675937 03/18/09 Updated Analog Reference Specifications tables Minor content updates 2679015 03/26/2009 Post external web.
Sales, Solutions, Legal Information
Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Power/Low Voltage Precision Analog Drive 2.0b psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
Cypress Semiconductor Corporation, 2008-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 001-48111 Rev.
Revised March 2009
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PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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