PSoC® Programmable System-on-Chip Powerful Harvard Architecture P
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PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 5.25V Operating Voltage Operating Voltages Down 1.0V Using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC® Blocks) Rail-to-Rail Analog PSoC Blocks Provide: 14-Bit ADCs 9-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UARTs Multiple SPIMasters Slaves Connectable GPIO Pins Complex Peripherals Combining Blocks Precision, Programmable Clocking Internal 2.5% 24/48 Oscillator 24/48 with Optional Crystal Optional External Oscillator, Internal Oscillator Watchdog Sleep Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink GPIO Pull Pull down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Four Analog Outputs GPIO Configurable Interrupt GPIO
Additional System Resources Slave, Master, Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Complete Development Tools Free Development Software (PSoC DesignerTM) Full Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory
Logic Block Diagram
Port Port Port Port Port Port
PSoC CORE
System
Global Digital Interconnect SRAM Bytes Interrupt Controller
Analog Drivers
Global Analog Interconnect Flash Sleep Watchdog
SROM
CPUCore (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Block Array
Analog Ref.
Analog Input Muxing
Digital Clocks
Multiply Accum.
Decimator System Resets
Internal Voltage Ref.
Switch Mode Pump
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 38-12012 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2009
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PSoC Functional Overview
PSoC® family consists many Programmable System-on-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with one, cost single-chip programmable device. PSoC devices include configurable blocks analog digital logic, well programmable interconnects. This architecture allows user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, illustrated left, comprised four main areas: PSoC Core, Digital System, Analog System, System Resources. Configurable global busing allows device resources combined into complete custom system. PSoC CY8C27x43 family have five ports that connect global digital analog interconnects, providing access digital blocks analog blocks.
Digital System
Digital System composed digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Figure Digital System Block Diagram
Port Port Port Port Port Port
Digital Clocks FromCore
System
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. utilizes interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, bytes SRAM data storage, EEPROM emulated using Flash. Program Flash utilizes four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate 2.5% over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. crystal accuracy desired, (32.768 external crystal oscillator) available Real Time Clock (RTC) optionally generate crystal-accurate system clock using PLL. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. PSoC GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
Input Configuration
DBB10 DBB11 DCB12
DCB13
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations include those listed below.
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity slave master slave multi-master available System Resource) Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown table titled "PSoC Device Characteristics" page
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Analog System
Analog System composed configurable blocks, each comprised opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) listed below.
Figure Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
Analog-to-digital converters with 14-bit resolution, selectable Incremental, Delta Sigma, SAR) Filters pole band-pass, low-pass, notch) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds) DACs with 9-bit resolution) Multiplying DACs with 9-bit resolution) High current output drivers (four with drive Core Resource) 1.3V reference System Resource) DTMF Dialer Modulators Correlators Peak detectors Many other topologies possible
P2[3]
P2[4] P2[2] P2[0]
P2[1]
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACI2[1:0]
ACI3[1:0]
Block Array
ACB00 ASC10 ASD20 ACB01 ASD11 ASC21 ACB02 ASC12 ASD22 ACB03 ASD13 ASC23
Analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks, shown figure below.
Interface Digital System RefHi RefLo AGND
Analog Reference
Reference Generators AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
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Additional System Resources
System Resources, some which have been previously listed, provide additional capability useful complete systems. Additional resources include multiplier, decimator, switch mode pump, voltage detection, power reset. Statements describing merits each system resource below.
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming information, PSoC® Programmable System-on-ChipTechnical Reference Manual CY8C28xxx PSoC devices. date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. Multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist general math digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter.
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups.The PSoC device covered this data sheet highlighted below. Table PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C24x23 CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34 Flash Size
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
4[1] 4[2] 3[2]
Bytes Bytes Bytes Bytes Bytes Bytes
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
Notes Limited analog functionality. analog blocks CapSense.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built support third party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family.
Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Programmable System-on-Chip Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user selectable functions. PSoC development process summarized following four steps: Select Components Configure Components Organize Connect Generate, Verify, Debug
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, programmable system-on-chip varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
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Document Conventions
Acronyms Used
This table lists acronyms used this data sheet. Table Acronyms Acronym EEPROM GPIO ISSP IPOR PPOR PSoC® SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose in-circuit emulator integrated development environment input/output in-system serial programming imprecise power reset least-significant voltage detect most-significant program counter programmable gain amplifier power reset precision power reset Programmable System-on-Chippulse width modulator read only memory switched capacitor switch mode pump static random access memory
Units Measure
units measure table located section Electrical Specifications page Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
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Pinouts
CY8C27x43 PSoC device available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital However, Vss, Vdd, SMP, XRES capable Digital
8-Pin Part Pinout
Table Definitions 8-Pin PDIP
Power
Type Digital
Power
Analog
Name
P0[5] P0[3] P1[1] P1[0] P0[2] P0[4]
Description
Analog column input column output. Analog column input column output. Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Analog column input column output. Analog column input column output. Supply voltage.
Figure CY8C27143 8-Pin PSoC Device
P0[5] P0[3] I2CSCL,XTALin, P1[1]
2PDIP
P0[4], P0[2], P1[0],XTALout,I2CSDA
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
20-Pin Part Pinout
Table Definitions 20-Pin SSOP, SOIC
Power Input Power
Type Digital
Power
Analog
Name
P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6]
Description
Analog column input. Analog column input column output. Analog column input column output. Analog column input. Switch Mode Pump (SMP) connection external components required. Serial Clock (SCL). Serial Data (SDA). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
Figure CY8C27243 20-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1]
SSOP SOIC
P0[6], P0[4], P0[2], P0[0], XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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28-Pin Part Pinout
Table Definitions 28-Pin PDIP, SSOP, SOIC
Power Input Power Type
Digital
Analog
Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Description Analog column input. Analog column input column output. Analog column input column output. Analog column input.
Figure CY8C27443 28-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] I2CSCL,P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin, P1[1]
Power
P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6]
Direct switched capacitor block input. Direct switched capacitor block input. Switch Mode Pump (SMP) connection external components required. Serial Clock (SCL). Serial Data (SDA). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
PDIP SSOP SOIC
P0[6], P0[4], P0[2], P0[0], P2[6],ExternalVRef P2[4],ExternalAGND P2[2], P2[0], XRES P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2CSDA
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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44-Pin Part Pinout
Table Definitions 44-Pin TQFP
Type
Digital
Analog
Name P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]
Description Direct switched capacitor block input. Direct switched capacitor block input.
Figure CY8C27543 44-Pin PSoC Device
P0[6], P0[4], P0[2], P0[0], P2[6],ExternalVRef P2[4], External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2]
Power Power Input Power
Switch Mode Pump (SMP) connection external components required.
P1[0] P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7]
Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
Document Number: 38-12012 Rev.
P3[1] I2CSCL, P1[7] SDA, P1[5] P1[3] I2CSCL,XTALin,P1[1] I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P3[0]
Serial Clock (SCL). Serial Data (SDA).
P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3]
P2[7] P0[1], P0[3], P0[5], P0[7],
TQFP
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48-Pin Part Pinout
Table 48-Pin Part Pinout (SSOP)
Input Power Type Digital Power Analog Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4]
Figure CY8C27643 48-Pin PSoC Device
Description Analog column input. Analog column input column output. Analog column input column output. Analog column input.
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] I2CSCL, P1[7] I2CSDA, P1[5] P1[3] I2CSCL,XTALin,P1[1]
Direct switched capacitor block input. Direct switched capacitor block input.
SSOP
Switch Mode Pump (SMP) connection external components required.
P0[6], P0[4], P0[2], P0[0], P2[6],External VRef P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4],EXTCLK P1[2] P1[0],XTALout,I2C
Serial Clock (SCL). Serial Data (SDA). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA.* Optional External Clock Input (EXTCLK).
Active high external reset with internal pull down.
Direct switched capacitor block input. Direct switched capacitor block input.
External Analog Ground (AGND).
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Table 48-Pin Part Pinout (SSOP)
P2[6] P0[0] P0[2] P0[4] P0[6]
Power
External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
LEGEND: Analog, Input, Output. These ISSP pins, which High (Power Reset). PSoC Mixed-Signal Array Technical Reference Manual details.
Table 48-Pin Part Pinout (QFN)*
Type Digital Analog Input Power Power Name P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P4[6] Active high external reset with internal pull down. Optional External Clock Input (EXTCLK). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK**. Ground connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA**. Serial Clock (SCL). Serial Data (SDA). Switch Mode Pump (SMP) connection external components required.
P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P5[3]
Figure CY8C27643 48-Pin PSoC Device
Description Direct switched capacitor block input.
P2[5] P2[7] P0[1], P0[3], A,IO P0[5], A,IO P0[7], P0[6], P0[4], A,IO P0[2], A,IO P0[0], P2[6],ExternalVRef P2[4],External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] XRES P3[6] P3[4] P3[2] P3[0]
Direct switched capacitor block input.
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I2CSDA,P1[5] P1[3] I2CSCL,XTALin,P1[1] I2CSDA,XTALout,P1[0] P1[2] EXTCLK,P1[4] P1[6] P5[0] P5[2]
P5[1] I2CSCL,P1[7]
(Top View
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Table 48-Pin Part Pinout (QFN)*
Power P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
LEGEND: Analog, Input, Output. package center that must connected ground (Vss). These ISSP pins, which High (Power Reset). PSoC Mixed-Signal Array Technical Reference Manual details.
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56-Pin Part Pinout
56-pin SSOP part CY8C27002 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Table 56-Pin Part Pinout (SSOP)
Power Power Type Digital Analog Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE even data OCDO data output. P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P5[0] P5[2] P3[0] P3[2] P3[4] P3[6] Optional External Clock Input (EXTCLK). Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK*. Supply voltage. connection. connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA*. Serial Clock (SCL). Serial Data (SDA). connection. Switch Mode Pump (SMP) connection required external components. Direct switched capacitor block input. Direct switched capacitor block input.
Figure CY8C27002 56-Pin PSoC Device
Description connection. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
P0[7] AIO, P0[5] AIO, P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[7] P4[5] P4[3] P4[1] OCDE OCDO P3[7] P3[5] P3[3] P3[1] P5[3] P5[1] SCL, P1[7] SDA, P1[5] P1[3] SCLK, SCL, XTALIn, P1[1] P0[6], P0[4], P0[2], P0[0], P2[6], External VRef P2[4], External AGND P2[2], P2[0], P4[6] P4[4] P4[2] P4[0] CCLK HCLK XRES P3[6] P3[4] P3[2] P3[0] P5[2] P5[0] P1[6] P1[4], EXTCLK P1[2] P1[0], XTALOut, SDA, SDATA
SSOP
Production
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Table 56-Pin Part Pinout (SSOP)
Input Power XRES HCLK CCLK P4[0] P4[2] P4[4] P4[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Direct switched capacitor block input. Direct switched capacitor block input. External Analog Ground (AGND). External Voltage Reference (VRef). Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage. Active high external reset with internal pull down. high-speed clock output. clock output.
LEGEND: Analog, Input, Output, On-Chip Debug. These ISSP pins, which High (Power Reset). PSoC Mixed-Signal Array Technical Reference Manual details.
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Register Reference
This chapter lists registers CY8C27x43 PSoC device. detailed register information, reference PSoC Programmable System-on-Chip Technical Reference Manual.
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields reserved must accessed.
Register Conventions
register conventions specific this section listed following table. Table Register Conventions Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Table Register Bank Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2 PRT5DR PRT5IE PRT5GS PRT5DM2 Name Name Name
DBB00DR0 AMX_IN DBB00DR1 DBB00DR2 DBB00CR0 ARF_CR DBB01DR0 CMP_CR0 DBB01DR1 ASY_CR Blank fields Reserved must accessed.
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
Access specific.
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL
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Table Register Bank Table: User Space (continued)
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1 PRT5DM0 PRT5DM1 PRT5IC0 PRT5IC1 Name Name Name Name
DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 DBB10DR0 ACB00CR3 DBB10DR1 ACB00CR0 DBB10DR2 ACB00CR1 DBB10CR0 ACB00CR2 DBB11DR0 ACB01CR3 DBB11DR1 ACB01CR0 DBB11DR2 ACB01CR1 DBB11CR0 ACB01CR2 DCB12DR0 ACB02CR3 DCB12DR1 ACB02CR0 DCB12DR2 ACB02CR1 DCB12CR0 ACB02CR2 DCB13DR0 ACB03CR3 DCB13DR1 ACB03CR0 DCB13DR2 ACB03CR1 DCB13CR0 ACB03CR2 Blank fields Reserved must accessed.
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access specific.
DEC_CR0 DEC_CR1 MUL_X MUL_Y MUL_DH MUL_DL ACC_DR1 ACC_DR0 ACC_DR3 ACC_DR2 CPU_F
CPU_SCR1 CPU_SCR0
Table Register Bank Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name
Blank fields Reserved must accessed.
ASC10CR0 ASC10CR1 ASC10CR2 ASC10CR3 ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3 ASC12CR0 ASC12CR1 ASC12CR2 ASC12CR3 ASD13CR0 ASD13CR1 ASD13CR2 ASD13CR3 ASD20CR0 ASD20CR1 ASD20CR2 ASD20CR3 ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3 ASD22CR0 ASD22CR1 ASD22CR2 ASD22CR3 Access specific.
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
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Table Register Bank Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN DBB01IN DBB01OU AMD_CR1 ALT_CR0 DCB02FN ALT_CR1 DCB02IN CLK_CR2 DCB02OU DCB03FN DCB03IN DCB03OU DBB10FN ACB00CR3 DBB10IN ACB00CR0 DBB10OU ACB00CR1 ACB00CR2 DBB11FN ACB01CR3 DBB11IN ACB01CR0 DBB11OU ACB01CR1 ACB01CR2 DCB12FN ACB02CR3 DCB12IN ACB02CR0 DCB12OU ACB02CR1 ACB02CR2 DCB13FN ACB03CR3 DCB13IN ACB03CR0 DCB13OU ACB03CR1 ACB03CR2 Blank fields Reserved must accessed.
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 RDI1RI RDI1SYN RDI1IS RDI1LT0 RDI1LT1 RDI1RO0 RDI1RO1 Access specific.
ASC23CR0 ASC23CR1 ASC23CR2 ASC23CR3
OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR
CPU_F
CPU_SCR1 CPU_SCR0
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Electrical Specifications
This chapter presents electrical specifications CY8C27x43 PSoC device. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40°C 85°C 100°C, except where noted. Specifications devices running greater than valid -40°C 70°C 82°C. Figure Voltage versus Frequency
5.25
4.75 Voltage 3.00
following table lists units measure that used this chapter. Table Units Measure Symbol
atin
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol
Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
Kbit Vrms
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Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Table Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100 Unit
Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65oC degrade reliability.
VIOZ IMIO IMAIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Maximum Current into Port Configured Analog Driver Electro Static Discharge Voltage Latch Current
-0.5 Vss- 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Unit Notes temperature rise from ambient junction package specific. "Thermal Impedances" page user must limit power consumption comply with this requirement.
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Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications Symbol Description Supply Voltage Supply Current 3.00 5.25 Unit Notes Conditions 5.0V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions 3.3V, MHz, SYSCLK doubler disabled. MHz, 93.75 kHz, 93.75 kHz. Conditions with internal slow speed oscillator, 3.3V, Conditions with internal slow speed oscillator, 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Conditions with properly loaded, max, 32.768 crystal. 3.3V, Trimmed appropriate Vdd. Trimmed appropriate Vdd.
IDD3
Supply Current
ISBH ISBXTL
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.[3] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal.[3]
ISBXTLH Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal high temperature.[3] VREF Reference Voltage (Bandgap) Silicon VREF Reference Voltage (Bandgap) Silicon
1.275 1.280
1.300 1.300
1.325 1.320
Notes Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This must compared with devices that have similar functions enabled. Refer "Ordering Information" page
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General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications Symbol Description Pull Resistor Pull down Resistor High Output Level Unit Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 5.25 5.25 Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC.
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Typical parameters apply 25°C design guidance only. Table Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High 35.0 Unit V/oC Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Notes
TCVOSOA Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) IEBOA Input Capacitance (Port Analog Pins) CINOA VCMOA Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias)
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Table Operational Amplifier Specifications (continued) Symbol CMRROA Description Common Mode Rejection Ratio Power Power Medium Power High Open Loop Gain Power Power Medium Power High Unit Notes Specification applicable high power. other bias modes (except high power, high opamp bias), minimum Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
GOLOA
VOHIGHOA High Output Voltage Swing (internal signals) Power Power Medium Power High VOLOWOA Output Voltage Swing (internal signals) Power Power Medium Power High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High PSRROA Supply Voltage Rejection Ratio Table 3.3V Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range
1200 2400 4600
1600 3200 6400
(Vdd 2.25) (Vdd 1.25V) Vdd.
1.65 1.32
35.0
Unit V/oC
Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA
Gross tested Package dependent. Temp 25oC. common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
CMRROA
Common Mode Rejection Ratio Power Power Medium Power High
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Table 3.3V Operational Amplifier Specifications (continued) Symbol GOLOA Description Open Loop Gain Power Power Medium Power High Unit Notes Specification applicable high power. other bias modes (except high power, high opamp bias), minimum
VOHIGHOA High Output Voltage Swing (internal signals) Power Power Medium Power High only VOLOWOA Output Voltage Swing (internal signals) Power Power Medium Power High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
1200 2400 4600
1600 3200 6400
(Vdd 2.25) (Vdd 1.25V) Vdd.
PSRROA
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Unit
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Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Unit V/°C
VOLOWOB
ISOB PSRROB
Table 3.3V Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB VOHIGHOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High High Output Voltage Swing (Load ohms Vdd/2) Power Power High Output Voltage Swing (Load ohms Vdd/2) Power Power High Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio Units V/°C
VOLOWOB
ISOB PSRROB
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Switch Mode Pump Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Switch Mode Pump (SMP) Specifications Symbol VPUMP VPUMP IPUMP VBAT5V VBAT3V VBATSTART VPUMP_Line Description Output Voltage 4.75 5.25 Unit Notes Configuration footnote.[5] Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.[5] Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.[5] trip voltage 3.25V. trip voltage 5.0V. Configuration footnote.[5] trip voltage 5.0V. Configuration footnote.[5] trip voltage 3.25V. Configuration footnote.[5] Configuration footnote.[5] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[5] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page
Output Voltage
3.00
3.25
3.60
Available Output Current VBAT 1.5V, VPUMP 3.25V VBAT 1.8V, VPUMP 5.0V Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery Start Pump Line Regulation (over VBAT range)
VPUMP_Load
Load Regulation
VPUMP_Ripple Output Voltage Ripple (depends capacitor/load) FPUMP DCPUMP Efficiency Switching Frequency Switching Duty Cycle
mVpp Configuration footnote.[5] Load Configuration footnote.[5] Load trip voltage 3.25V.
Note inductor, capacitor, Schottky diode. Figure
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Figure Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Analog Reference Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Note Avoid using P2[4] digital signaling when using analog resource that depends Analog Reference. Some coupling digital signal appear AGND. Table Silicon Revision Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2[6] AGND BandGap[6] AGND P2[4] (P2[4] Vdd/2)[6] AGND BandGap[6] AGND BandGap[6] AGND Block Block Variation (AGND Vdd/2)[6] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) 1.274 Vdd/2 0.030 0.043 P2[4] 0.013 0.009 0.018 -0.034 Vdd/2 0.140 0.112 P2[6] 0.113 P2[4] 0.130 P2[4] P2[6] 0.133 0.112 Vdd/2 0.051 0.082 P2[6] 0.084 P2[4] 0.056 P2[4] P2[6] 0.057 1.30 Vdd/2 0.004 0.010 P2[4] 0.000 Vdd/2 0.018 0.018 P2[6] 0.018 P2[4] 0.016 P2[4] P2[6] 0.016 Vdd/2 0.024 0.023 P2[6] 0.025 P2[4] 0.026 P2[4] P2[6] 0.026 1.326 Vdd/2 0.003 0.024 P2[4] 0.014 0.009 0.018 0.034 Vdd/2 0.103 0.076 P2[6] 0.077 P2[4] 0.098 P2[4] P2[6] 0.100 0.076 Vdd/2 0.098 0.129 P2[6] 0.134 P2[4] 0.107 P2[4] P2[6] 0.110 Unit
Note AGND tolerance includes offsets local buffer PSoC block.
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Table Silicon Revision Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2[7] AGND BandGap[7] AGND P2[4] (P2[4] Vdd/2)[7] AGND BandGap[7] AGND BandGap[7] AGND Block Block Variation (AGND Vdd/2)[7] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) 1.28 Vdd/2 0.030 0.043 P2[4] 0.011 0.009 0.018 -0.034 Vdd/2 0.06 P2[6] 0.06 P2[4] 0.06 P2[4] P2[6] 0.06 0.06 Vdd/2 0.051 0.06 P2[6] 0.04 P2[4] 0.056 P2[4] P2[6] 0.056 1.30 Vdd/2 P2[4] 0.000 Vdd/2 0.01 0.01 P2[6] 0.01 P2[4] 0.01 P2[4] P2[6] 0.01 0.01 Vdd/2 0.01 0.01 P2[6] 0.01 P2[4] 0.01 P2[4] P2[6] 0.01 1.32 Vdd/2 0.007 0.024 P2[4] 0.011 0.009 0.018 0.034 Vdd/2 0.06 P2[6] 0.06 P2[4] 0.06 P2[4] P2[6] 0.06 0.06 Vdd/2 0.06 0.06 P2[6] 0.04 P2[4] 0.056 P2[4] P2[6] 0.056 Unit
Table Silicon Revision 3.3V Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2[8] AGND BandGap[8] AGND P2[4] (P2[4] Vdd/2) AGND BandGap[8] AGND BandGap[8] AGND Block Block Variation (AGND Vdd/2)[8] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) RefHi BandGap RefLo Vdd/2 BandGap 1.274 Vdd/2 0.027 Allowed P2[4] 0.008 0.009 0.018 -0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.075 Allowed Allowed P2[4] P2[6] 0.009 P2[4] P2[6] 0.057 1.30 Vdd/2 0.003 P2[4] 0.001 0.000 1.326 Vdd/2 0.002 P2[4] 0.009 0.009 0.018 0.034 Unit
Note AGND tolerance includes offsets local buffer PSoC block.
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Table Silicon Revision 3.3V Analog Reference Specifications (continued) Symbol Description RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) Allowed Allowed Allowed P2[4] P2[6] 0.048 P2[4] P2[6] 0.022 P2[4] P2[6] 0.092 Unit
Table Silicon Revision 3.3V Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2[8] AGND BandGap[8] AGND P2[4] (P2[4] Vdd/2) AGND BandGap[8] AGND BandGap[8] AGND Block Block Variation (AGND Vdd/2)[8] RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) 1.28 Vdd/2 0.027 Allowed P2[4] 0.008 0.009 0.018 -0.034 Allowed Allowed Allowed Allowed P2[4] P2[6] 0.06 Allowed Allowed Allowed Allowed Allowed P2[4] P2[6] 0.048 P2[4] P2[6] 0.01 P2[4] P2[6] 0.048 P2[4] P2[6] 0.01 P2[4] P2[6] 0.057 1.30 Vdd/2 P2[4] 0.000 1.32 Vdd/2 0.005 P2[4] 0.009 0.009 0.018 0.034 Unit
Analog PSoC Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog PSoC Block Specifications Symbol Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) 12.2 Unit
Note AGND tolerance includes offsets local buffer PSoC block. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V.
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Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV table below refer bits VLT_CR register. PSoC Programmable System-on-Chip Technical Reference Manual more information VLT_CR register. Table Specifications Symbol VPPOR0R VPPOR1R VPPOR2R VPPOR0 VPPOR1 VPPOR2 VPH0 VPH1 VPH2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Value PPOR Trip (positive ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value PPOR Trip (negative ramp) PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] PPOR Hysteresis PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value PUMP Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.91 4.39 4.55 2.82 4.39 4.55 2.92 3.02 3.13 4.00 4.48 4.64 4.73 4.81 Unit Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
2.86 2.96 3.07 3.92 4.39 4.55 4.63 4.72
2.98[9] 3.08 3.20 4.08 4.57 4.74[10] 4.82 4.91
2.96 3.03 3.18 4.11 4.55 4.63 4.72 4.90
3.02 3.10 3.25 4.19 4.64 4.73 4.82 5.00
3.08 3.16 3.32 4.28 4.74 4.82 4.91 5.10
Notes Always greater than above PPOR (PORLEV falling supply. Always greater than above PPOR (PORLEV falling supply.
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Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Description Supply Current During Programming Verify Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENP Flash Endurance (per block) 50,000 FlashENT Flash Endurance (total)[11] FlashDR Flash Data Retention
Symbol IDDP VILP
0.75
Unit Years
Notes
Driving internal pull-down resistor. Driving internal pull-down resistor.
Erase/write cycles block. Erase/write cycles.
1,800,0
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information
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Electrical Characteristics
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications Symbol FIMO FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Description Internal Main Oscillator Frequency Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Speed Oscillator Frequency External Crystal Oscillator Frequency 23.4 0.93 0.93 32.768 23.986 1700 2800 24.6[12] 24.6[12,13] 12.3[13,14] 49.2[12,13, 24.6[13, 2620 3800 Unit Notes Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Trimmed. Utilizing factory trim values. Refer Digital Block Specifications below.
Accuracy capacitor crystal dependent. duty cycle. Multiple (x732) crystal frequency.
Jitter24M2 Period Jitter (PLL) TPLLSLEW Lock Time TPLLSLEWS Lock Time Gain Setting
TOSACC
External Crystal Oscillator Startup External Crystal Oscillator Startup
crystal oscillator frequency within final value Tosacc period. Correct operation assumes properly loaded maximum drive level 32.768 crystal. 3.0V 5.5V, -40°C 85°C.
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time
46.8
48.0
49.2[12,14]
Trimmed. Utilizing factory trim values.
12.3
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
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Figure Lock Timing Diagram
Enable
TPLLSLEW
FPLL Gain
Figure Lock Gain Setting Timing Diagram
Enable
TPLLSLEWLOW
FPLL Gain
Figure External Crystal Oscillator Startup Timing Diagram
Select
F32K2
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ECO) Timing Diagram
Jitter32k
32K2
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General Purpose Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Unit Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Unit
0.72 0.62
TSOA
0.15 0.01
0.92 0.72
SRROA
SRFOA
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Table Operational Amplifier Specifications (continued) Symbol BWOA Description Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Noise (Power Medium, Opamp Bias High) 0.75 Unit nV/rt-Hz
ENOA
Table 3.3V Operational Amplifier Specifications Symbol Description Rising Settling Time from 0.1% load, Unity Gain) TROA Power Low, Opamp Bias Power Low, Opamp Bias High TSOA Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Noise (Power Medium, Opamp Bias High) Units nV/rt-Hz
3.92 0.72
0.31 0.24 0.67
5.41 0.72
SRROA SRFOA BWOA ENOA
When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level.
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Figure Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Unit Notes overdrive comparator reference within VREFLPC.
Digital Block Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Digital Block Specifications Function Description 49.2 24.6 50[16] 50[16] 49.2 24.6 49.2 24.6 4.75V 5.25V 4.75V 5.25V Unit Notes 4.75V 5.25V 3.0V 4.75V Maximum Block Clocking Frequency 4.75V) Functions Maximum Block Clocking Frequency 4.75V) Timer Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input
Notes minimum input pulse width based input synchronizers running nominal period). Refer Table page
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Table Digital Block Specifications (continued) Function Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Maximum Input Clock Frequency [16] Silicon Silicon Silicon Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency [17] Silicon Silicon Silicon Maximum Input Clock Frequency with 4.75V, Stop Bits 50[16] 50[16] 49.2 49.2 4.75V 5.25V 4.75V 5.25V Description Unit Notes
24.6
50[16]
16.4 24.6 49.2
Maximum data rate over clocking.
Maximum data rate 2.05 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 2.05 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking.
16.4 24.6 49.2
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Analog Output Buffer Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High 0.65 0.65 0.65 0.65 Unit
Table 3.3V Analog Output Buffer Specifications Symbol TROB TSOB SRROB SRFOB BWOB BWOB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High Unit
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External Clock Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Unit
Table 3.3V External Clock Specifications Symbol FOSCEXT FOSCEXT Description Frequency with Clock divide 1[18] Frequency with Clock divide greater[19] High Period with Clock divide Period with Clock divide Power Switch 0.093 0.186 41.7 41.7 12.3 24.6 5300 Unit
Programming Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Unit Notes
Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
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Specifications
following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Characteristics Pins Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Set-up Time Repeated START Condition Data Hold Time Data Set-up Time Set-up Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter. Standard Mode Fast Mode 100[20] Unit
Figure Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Packaging Information
This section illustrates packaging specifications CY8C27x43 PSoC device, along with thermal impedances each package typical package capacitance crystal pins. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 8-Pin (300-Mil) PDIP
51-85075
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Figure 20-Pin (210-Mil) SSOP
51-85077
Figure 20-Pin (300-Mil) Molded SOIC
51-85024
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Figure 28-Pin (300-Mil) Molded
51-85014
Figure 28-Pin (210-Mil) SSOP
51-85079
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Figure 28-Pin (300-Mil) Molded SOIC
51-85026
Figure 44-Pin TQFP
51-85064
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Figure 48-Pin (300-Mil) SSOP
51-85061 51-85061-C
Figure 48-Pin 7X7X 0.90 (Sawn Type)
001-13191
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Figure 48-Pin (7x7
51-85152
Important Note information preferred dimensions mounting packages, following Application Note
Thermal Impedances
Table Thermal Impedances Package Package PDIP SSOP SOIC PDIP SSOP SOIC TQFP SSOP
POWER
Capacitance Crystal Pins
Table Typical Package Capacitance Crystal Pins Package PDIP SSOP SOIC PDIP SSOP SOIC TQFP SSOP Package Capacitance Typical oC/W
oC/W oC/W oC/W oC/W
oC/W oC/W oC/W oC/W
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Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Silicon Package PDIP SSOP SOIC PDIP SSOP SOIC TQFP SSOP Minimum Peak Temperature** 220oC 220oC 220oC 220oC 220oC 220oC 220oC 220oC 220oC Maximum Peak Temperature 240oC 240oC 240oC 240oC 240oC 240oC 240oC 240oC 240oC Silicon Minimum Peak Temperature* 240oC 240oC 220oC 240oC 240oC 220oC 220oC 220oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC 260oC 260oC 260oC 260oC
*Refer Table page **Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
This chapter presents development tools available current PSoC device families including CY8C27x43 family.
iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
Software
PSoC DesignerAt core PSoC development software suite PSoC Designer. Utilized thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under DESIGN RESOURCES Software Drivers. PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge CY3202-C iMAGEcraft Compiler CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com, click Online Store shopping cart icon bottom page, click PSoC (Programmable System-on-Chip) view current list available items.
CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
Development Kits
development kits purchased from Cypress Online Store. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
Evaluation Tools
evaluation tools purchased from Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
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Device Programmers
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24SXI CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24SXI CY8C27543-24AXI CY8C27643-24PVXI CY8C27643-24LFXI Package PDIP SSOP SOIC PDIP SSOP SOIC TQFP SSOP Flex-Pod Kit[21] CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXX CY3250-27XXXQFN Foot Kit[22] CY3250-8PDIP-FK CY3250-20SSOP-FK CY3250-20SOIC-FK CY3250-28PDIP-FK CY3250-28SSOP-FK CY3250-28SOIC-FK CY3250-44TQFP-FK CY3250-48SSOP-FK CY3250-48QFN-FK Adapter[23] Adapters found http://www.emulation.com.
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
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3rd-Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com/an2323.
Ordering Information
following table lists CY8C27x43 PSoC device's package features ordering codes. Table CY8C27x43 PSoC Device Features Ordering Information
Analog Blocks (Columns Digital Blocks (Rows Switch Mode Pump Temperature Range XRES Digital Pins Ordering Code Package Analog Outputs Analog Inputs Flash (Bytes) (Bytes)
CY8C27x43 Silicon These parts lead free offer following improvements. DEC_CR1 register selections enhanced allow digital block decimator clock source, bits CPU_SCR1 register readable, accuracy analog reference enhanced (see Electrical Specifications chapter). silicon errata fixed silicon (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC Mil) SOIC (Tape Reel) (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC (300 Mil) SOIC (Tape Reel) TQFP TQFP (Tape Reel) (300 Mil) SSOP (300 Mil) SSOP (Tape Reel) (7x7) (7x7) (Tape Reel) SSOP (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) (300 Mil) SOIC Mil) SOIC (Tape Reel) (300 Mil) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel) CY8C27143-24PXI CY8C27243-24PVXI CY8C27243-24PVXIT CY8C27243-24SXI CY8C27243-24SXIT CY8C27443-24PXI CY8C27443-24PVXI CY8C27443-24PVXIT CY8C27443-24SXI CY8C27443-24SXIT CY8C27543-24AXI CY8C27543-24AXIT CY8C27643-24PVXI CY8C27643-24PVXIT CY8C27643-24LFXI CY8C27643-24LFXIT CY8C27002-24PVXI[24] CY8C27143-24PI CY8C27243-24PVI CY8C27243-24PVIT CY8C27243-24SI CY8C27243-24SIT CY8C27443-24PI CY8C27443-24PVI CY8C27443-24PVIT -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
CY8C27x43 Silicon Silicon recommended designs.
Note This part used in-circuit debugging. available production.
Document Number: 38-12012 Rev.
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Table CY8C27x43 PSoC Device Features Ordering Information (continued)
Analog Blocks (Columns Digital Blocks (Rows Switch Mode Pump Temperature Range XRES Digital Pins Ordering Code Package Analog Outputs Flash (Bytes) Analog Inputs (Bytes)
(300 Mil) SOIC (300 Mil) SOIC (Tape Reel) TQFP TQFP (Tape Reel) (300 Mil) SSOP (300 Mil) SSOP (Tape Reel) (7x7) (7x7) (Tape Reel) (7X7X 0.90 (Sawn) (7X7X 0.90 (Sawn)
CY8C27443-24SI CY8C27443-24SIT CY8C27543-24AI CY8C27543-24AIT CY8C27643-24PVI CY8C27643-24PVIT CY8C27643-24LFI CY8C27643-24LFIT CY8C27643-24LTXI CY8C27643-24LTXIT
-40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C -40C +85C
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Ordering Code Definitions
xxx-SPxx
Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free LFX/LKX Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress Thermal Rating: Commercial Industrial Extended
Document Number: 38-12012 Rev.
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Document History Page
Document Title: CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC® Programmable System-on-ChipDocument Number: 38-12012 Revision Submission Date 127087 128780 128992 129283 129442 130129 130651 131298 229416 7/01/2003 7/29/2003 8/14/2003 8/28/2003 9/09/2003 10/13/2003 10/28/2003 11/18/2003 Origin Change Silicon. Description Change document (Revision **).
Engineering electrical spec additions, Core Architecture links, corrections NWJ. some text, tables, drawings, format. Interrupt controller table fixed, refinements Electrical Spec section Register chapter. Significant changes Electrical Specifications section. Changes made Electrical Spec section. Added 20/28-Lead SOIC packages pinouts. Revised document Silicon Revision Refinements Electrical Specification section chapter. Revisions GDI, RDI, Digital Block chapters. Revisions Digital Block Spec miscellaneous register changes. data sheet format organization. Reference PSoC Programmable System-on-Chip Technical Reference Manual additional information. Title change. Added Silicon information this data sheet. standards, update device table, swap 48-pin SSOP Reflow Peak Temp. table. color logo. Re-add pinout ISSP notation. preferred dimensions mounting packages. Update Transmitter Receiver Digital Block Electrical Specifications. Power Comparator (LPC) AC/DC electrical spec. tables. Dev. Tool section. CY8C20x34 PSoC Device Characteristics table. pinout package diagram. ISSP note pinout tables. Update package diagram revisions. Update typical recommended Storage Temperature industrial specs. Update branding convention. Update copyright trademarks. Added note Analog Reference Specification table Ordering Information. Changed title from CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC Mixed Signal Array Final Data Sheet" "CY8C27143, CY8C27243, CY8C27443, CY8C27543, CY8C27643 PSoC® Programmable System-on-ChipTM". Updated data sheet template. Added 48-Pin (Sawn) package outline diagram Ordering information details CY8C27643-24LTXI CY8C27643-24LTXIT parts
247529 355555
523233
2545030 2696188
07/29/08 04/22/2009
YARA DPT/PYRS
Document Number: 38-12012 Rev.
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Sales, Solutions, Legal Information
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Cypress Semiconductor Corporation, 2003-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 38-12012 Rev.
Revised April 2009
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PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
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