PSoC® Programmable System-on-Chip Powerful Harvard Architecture P
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CY8C23433, CY8C23533
PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 5.25V Operating Voltage Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC Blocks) Rail-to-Rail analog PSoC Blocks Provide: 14-Bit ADCs 8-Bit DACs Programmable Gain Amplifiers Programmable Filters Comparators Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UART Multiple SPIMasters Slaves Connectable GPIO Pins Complex Peripherals Combining Blocks High-Speed 8-Bit Optimized Motor Control Precision, Programmable Clocking Internal ±2.5% 24/48 Oscillator High Accuracy with Optional Crystal Optional External Oscillator, Internal Oscillator Watchdog Sleep Flexible On-Chip Memory Bytes Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Programmable Configurations Sink GPIO Pull Pull Down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Analog Outputs GPIO Configurable Interrupt GPIO Additional System Resources CSlave, Master, Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-chip Precision Voltage Reference
Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory
Logic Block Diagram
Port Port Port Port Analog Drivers
PSoC CORE
System
Global Digital Interconnect SRAM Bytes Interrupt Controller
Global Analog Interconnect Flash Sleep Watchdog
SROM
CPUCore (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
Blocks
ANALOG SYSTEM
Analog Block Array
Columns Blocks Analog
SAR8
Analog Input Muxing
Digital Clocks
Multiply Accum.
Decimator
System Resets
Internal Voltage Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-44369 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised December 2008
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PSoC Functional Overview
PSoC family consists many mixed-signal array with On-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with cost single-chip programmable device. PSoC devices include configurable blocks analog digital logic, programmable interconnects. This architecture allows user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, shown Logic Block Diagram page consists four main areas: PSoC Core, Digital System, Analog System, System Resources. Configurable global busing allows combining device resources into complete custom system. PSoC CY8C23x33 family have three ports that connect global digital analog interconnects, providing access four digital blocks four analog blocks.
Digital System
Digital System consists digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Figure Digital System Block Diagram
Port Port Port Port
Digital Clocks FromCore
System
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. uses interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, bytes SRAM data storage, EEPROM emulated using Flash. Program Flash uses four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator) accurate ±2.5% over temperature voltage. also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. crystal accuracy desired, (32.768 external crystal oscillator) available Real Time Clock (RTC) optionally generate crystal-accurate system clock using PLL. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. PSoC GPIOs provide connection CPU, digital analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also capability generate system interrupt high level, level, change from last read.
GIE[7:0] GIO[7:0] Global Digital Interconnect GOE[7:0] GOO[7:0]
Digital peripheral configurations are:
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity master slave slave master available System Resource) Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown table titled PSoC Device Characteristics page
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Analog System
Analog system consists 8-bit four configurable blocks. programmable 8-bit optimized that runs Ksps, with monotonic guarantee. also features support motor control application. Each analog block consists opamp circuit allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) are:
Figure Analog System Block Diagram
P0[7] P0[5] P0[3] P0[1] AGNDIn RefIn P0[6] P0[4] P0[2] P0[0] P2[6]
P2[3]
P2[4] P2[2] P2[0]
P2[1]
Filters band pass, low-pass) Amplifiers with selectable gain 48x) Instrumentation amplifiers with selectable gain 93x) Comparators with selectable thresholds)
Array Input Configuration
-bit DAC) Multiplying -bit DAC) High current output drivers (two with drive) 1.3V reference System Resource) DTMF dialer Modulators Correlators Peak detectors Many other topologies possible
P0[7:0]
ACI2[3:0] ACI0[1:0] ACI1[1:0]
Block Array
ACB00 ACB01 ASD11 ASC21
Analog blocks arranged column three, which includes (Continuous Time) (Switched Capacitor) blocks. Analog Column contains SAR8 block rather than standard blocks.
8-Bit
Analog Reference
Interface Digital System RefHi RefLo AGND Reference Generators AGNDIn RefIn Bandgap
Interface (Address Bus, Data Bus, Etc.)
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Additional System Resources
System Resources, some which listed previous sections, provide additional capability useful complete systems. Additional resources include multiplier, decimator, voltage detection, power reset. Brief statements describing merits each system resource follow:
Getting Started
quickest path understanding PSoC silicon reading this data sheet using PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. in-depth information, along with detailed programming information, refer PSoC Mixed-Signal Array Technical Reference Manual. latest Ordering, Packaging, Electrical Specification information, refer latest PSoC device data sheets http://www.cypress.com/psoc. determine which PSoC device meets your requirements, navigate through PSoC Decision Tree Application Note AN2209 http://www.cypress.com select Application Notes under Design Resources.
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist both general math digital filters. decimator provides custom hardware filter digital signal processing applications including creation Delta Sigma ADCs. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs.
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PSoC development. Cypress Online Store site
Technical Training Modules
Free PSoC technical training modules available users PSoC. Training modules cover designing, debugging, advanced analog CapSense. http://www.cypress.com.
PSoC Device Characteristics
Depending PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups. Table PSoC Device Characteristics Analog Columns Analog Blocks Analog Outputs Analog Inputs Digital Blocks Digital Digital Rows PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 CY8C23X33 SAR8
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com, click Design Support located page, select CYPros Consultants.
Technical Support
PSoC application engineers take pride fast accurate response. They reached with 4-hour guaranteed response http://www.cypress.com/support.
2[1]
4[2] 4[2] 3[3]
Application Notes
long list application notes assist every aspect your design effort. view PSoC application notes,
CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34
Notes complete column, plus Continuous Time Block. Limited analog functionality. analog blocks CapSense.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer application runs Windows 4.0, Windows 2000, Windows Millennium (Me), Windows (refer section PSoC Designer Subsystems page PSoC Designer helps customer select operating configuration PSoC, write application code that uses PSoC, debug application. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, CYASM macro assembler CPUs. PSoC Designer also supports high-level language compiler developed specifically devices family. Figure PSoC Designer Subsystems
PSoC Designer Software Subsystems
Device Editor Device Editor subsystem allows user select different onboard analog digital components called user modules using PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. PSoC Designer sets power initialization tables selected PSoC block configurations creates source code application framework. framework contains software operate selected components and, project uses more than operating configuration, contains routines switch between different sets PSoC block configurations time. PSoC Designer print configuration sheet given project configuration during application programming conjunction with Device Data Sheet. Once framework generated, user application-specific code flesh framework. also possible change selected components regenerate framework. Design Browser
Results
PSoC Designer
Graphical Designer Interface
Context Sensitive Help
Commands
Importable Design Database Device Database Application Database Project Database User Modules Library PSoC Configuration Sheet
Design Browser allows users select import preconfigured designs into user's project. Users easily browse catalog preconfigured designs facilitate time-to-design. Examples provided tools include 300-baud modem, master slave, controller, magnetic card reader. Application Editor
PSoC Designer Core Engine
Application Editor edit your language Assembly language source code. also assemble, compile, link, build. Assembler. macro assembler allows assembly code merged seamlessly with code. link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compiler. language compiler available that supports PSoC family devices. Even have never worked language before, product quickly allows create complete programs PSoC family devices. embedded, optimizing compiler provides features tailored PSoC architecture. comes complete with embedded libraries providing port operations, standard keypad display support, extended math functionality.
Manufacturing Information File
Emulation
In-Circuit Emulator
Device Programmer
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Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing designer test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
resolution. user module parameters permit establish pulse width duty cycle. User modules also provide tested software your development time. user module application programming interface (API) provides high level functions control respond hardware events run-time. also provides optional interrupt service routines that adapt needed. functions documented user module data sheets that viewed directly PSoC Designer IDE. These data sheets explain internal operation user module provide performance specifications. Each data sheet describes each user module parameter documents setting each register controlled user module. development process starts when open project bring Device Editor, graphical user interface (GUI) configuring hardware. pick user modules need your project them onto PSoC blocks with point-and-click simplicity. Next, build signal chains interconnecting user modules each other pins. this stage, also configure clock source connections enter parameter values directly selecting values from drop-down menus. When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides high-level user module functions. Figure User Module/Source Code Development Flows
Hardware Tools
In-Circuit Emulator cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operate with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
Device Editor
User Module Selection Placement Parameter -ization Source Code Generator
Designing with User Modules
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. Each block several registers that determine function connectivity other blocks, multiplexers, buses pins. Iterative development cycles permit adapt hardware software. This substantially lowers risk having select different part meet final design requirements. speed development process, PSoC Designer Integrated Development Environment (IDE) provides library pre-built, pre-tested hardware peripheral functions, called "User Modules." User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties. standard User Module library contains over common peripherals such ADCs, DACs Timers, Counters, UARTs, other uncommon peripherals such DTMF Generators Bi-Quad analog filter sections. Each user module establishes basic register settings that implement selected function. also provides parameters that allow tailor precise configuration your particular application. example, Pulse Width Modulator User Module configures more digital PSoC blocks, each bits
Interface
Generate Application
Application Editor
Project Manager Source Code Editor Build Manager
Build
Debugger
Storage Inspector Event Breakpoint Manager
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next step write your main program, sub-routines using PSoC Designer's Application Editor subsystem. Application Editor includes Project Manager that allows open project source code files (including generated code files) from hierarchal view. source code editor provides syntax coloring advanced edit features both assembly language. File search capabilities include simple string searches recursive "grep-style" patterns. single mouse click invokes Build Manager. employs professional-strength "makefile" system automatically analyze file dependencies compiler assembler necessary. Project-level options control optimization strategies used compiler linker. Syntax errors displayed console window. Double clicking error message takes directly offending line source code. When correct, linker builds file image suitable programming. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Table Acronyms Used (continued) Acronym Description pulse width modulator random access memory read only memory switched capacitor
Units Measure
units measure table located section Electrical Specifications page Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated decimal.
Document Conventions
Acronyms Used
following table lists acronyms that used this document. Table Acronyms Used Acronym EEPROM GPIO IPOR PPOR PSoC® alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose input/output imprecise power reset least-significant voltage detect most-significant program counter power reset precision power reset Programmable System-on-ChipPage Description
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Pinouts
PSoC CY8C23X33 available 32-pin 28-pin SSOP packages. Every port (labeled with "P"), except following table figure, capable Digital
32-Pin Part Pinout
Table Definitions 32-Pin (QFN) Power Input Power Digital Analog Name AVref P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] GPIO GPIO Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input Connection Serial Clock (SCL) Serial Data (SDA) Connection GPIO GPIO, Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK* Ground Connection GPIO, Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA* GPIO GPIO, External Clock Connection GPIO Direct Switched Capacitor Block Input Direct Switched Capacitor Block Input External Analog Ground (AGnd) External Voltage Reference (VRef) Analog Column Input Input Analog Column Input Input Connection Analog Column Input Input Analog Column Input Input Supply Voltage Analog Column Input Input Analog Column Input, Column Output Input Analog Column Input, Column Output Input Analog Column Input.and Input
GPIO, P2[7] GPIO, P2[5] P2[3] P2[1] AVref, P3[0] SCL, P1[7] SDA, P1[5]
Type
Description
Figure CY8C23533 32-Pin PSoC Device
P0[1], P0[3], P0[5], P0[7], P0[6], P0[4],
P3[0][4] GPIO/ADC Vref (optional)
(Top View)
XRES Active High External Reset with Internal Pull Down
LEGEND: Analog, Input, Output. Note Even though P3[0] port, resides left side pinout.
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GPIO P1[3] SCL, XTALin, P1[1] SDA, XTALout, P1[0] GPIO P1[2] GPIO, EXTCLK, P1[4]
P0[2], P0[0], P2[6], Vref P2[4], AGnd P2[2], P2[0], XRES P1[6], GPIO
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28-Pin Part Pinout
Table Definitions 28-Pin (SSOP) Number CY8C23433 Name Figure CY8C23433 28-Pin PSoC Device Description
AIO, P0[7] P0[5] P0[3] AIO, P0[1] P0[6], AIO, AnColMux P0[4], AIO, AnColMux P0[2], AIO, AnColMux P0[0], AIO, AnColMux P2[6], VREF P2[4], AGND P2[2], P2[0], P3[1], P1[6], P1[4], EXTCLK P1[2], P1[0],IO,XTALout,ISSP SDA,I2C
Analog
Digital
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5]
Analog Column Analog Column Column Analog Column Column Analog Column GPIO GPIO Direct Switched Capacitor Input Direct Switched Capacitor Input GPIO/ADC Vref (optional) GPIO GPIO, Xtal Input, SCL, ISSP Ground GPIO, Xtal Output, SDA, ISSP GPIO GPIO, External Clock GPIO GPIO Direct Switched Capacitor Input Direct Switched Capacitor Input External Analog Ground (AGnd) Analog Voltage Reference (VRef) Analog Column Analog Column Analog Column Analog Column Supply Voltage
P2[7] P2[5] AIO, P2[3] AIO, P2[1] AVref, P3[0] SCL, P1[7] SDA, P1[5] P1[3] SCL,ISSP SCL,XTALin,IO, P1[1]
SSOP
AVref
P2[3] P2[1] P3[0][5] P1[7] P1[5] P1[3] P1[1][6] P1[0][6] P1[2] P1[4] P1[6] P3[1][7]
Power
P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6]
Power
LEGEND: Analog, Input, Output.
Notes Even though P3[0] port, resides left side pinout. ISSP pin, which High POR. Even though P3[1] even port, resides right side pinout.
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Register Reference
This section lists registers CY8C23433 PSoC device using mapping tables, offset order.
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields reserved must accessed.
Register Conventions
Abbreviations Used register conventions specific this section listed following table. Table Abbreviations Convention Description Read register bits Write register bits Logical register bits Clearable register bits Access specific
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Table Register Bank Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2
DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0
AMX_IN
ARF_CR CMP_CR0 ASY_CR CMP_CR1 SARADC_DL SARADC_CR0 SARADC_CR1 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3 ACB01CR0 ACB01CR1 ACB01CR2
ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1
I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL DEC_CR0 DEC_CR1 MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2
CPU_F
Gray fields reserved.
Access specific.
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Table Register Bank Table: User Space (continued)
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
Gray fields reserved. Access specific.
CPU_SCR1 CPU_SCR0
Table Register Bank Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1
DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU
CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0
AMD_CR1 ALT_CR0
TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACB00CR3 ACB00CR0 ACB00CR1 ACB00CR2 ACB01CR3
ASD11CR0 ASD11CR1 ASD11CR2 ASD11CR3
ASC21CR0 ASC21CR1 ASC21CR2 ASC21CR3
SARADC_TRS SARADC_TRCL SARADC_TRCH SARADC_CR2 SARADC_LCR
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP
IMO_TR ILO_TR BDG_TR ECO_TR
Gray fields reserved.
Access specific.
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Table Register Bank Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
Gray fields reserved.
ACB01CR0 ACB01CR1 ACB01CR2
RDI0RO0 RDI0RO1
CPU_F
FLS_PR1
CPU_SCR1 CPU_SCR0
Access specific.
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Electrical Specifications
This section presents electrical specifications CY8C23433 PSoC device. latest electrical specifications, visit http://www.cypress.com/psoc. Specifications valid -40°C 85°C 100°C, except where noted. Refer Table page electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure Voltage versus Frequency Figure Frequency Trim Options
5.25
SLIMO Mode=1
4.75 Voltage 3.00 Frequency 4.75 Voltage
SLIMO Mode
5.25
SLIMO Mode=0
following table lists units measure that used this section. Table Units Measure
Symbol Kbit Vrms decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Unit Measure degree Celsius Symbol micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts pico ampere pico farad peak-to-peak parts million picosecond samples second sigma: standard deviation volts Unit Measure
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3.60
3.00
SLIMO Mode=1
SLIMO Mode=0
Frequency
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Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Table Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100 Units Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65°C degrade reliability.
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch-up Current
-0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units temperature rise from ambient junction package specific. Thermal Impedances Package page user must limit power consumption comply with this requirement. Notes
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Electrical Characteristics
Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Chip-Level Specifications Symbol Description Supply Voltage Supply Current 5.25 Units Notes Specifications page Conditions 5.0V, 25°C, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. SLIMO mode MHz. Conditions 3.3V, 25°C, MHz, SYSCLK doubler disabled, MHz, 93.75 kHz, 93.75 kHz, analog power off. SLIMO mode MHz. Conditions with internal slow speed oscillator, 3.3V, -40°C 55°C, analog power off. Conditions with internal slow speed oscillator, 3.3V, 55°C 85°C, analog power off. Conditions with properly loaded, max, 32.768 crystal. 3.3V, -40°C 55°C, analog power off. Conditions with properly loaded, max, 32.768 crystal. 55°C 85°C, analog power off. Trimmed appropriate Vdd. 3.0V
IDD3
Supply Current
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT.[8]
ISBH
Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperature.[8] Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal.[8]
ISBXTL
ISBXTLH
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal high temperature.[8] Reference Voltage (Bandgap)
VREF
1.28
1.30
1.33
Note Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This must compared with devices that have similar functions enabled.
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General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol Pull Resistor Pull down Resistor High Output Level Description Units 4.75 5.25V (maximum even port pins (for example, P0[2], P1[4]), maximum port pins (for example, P0[3], P1[5])). maximum combined budget. 4.75 5.25V (maximum even port pins (for example, P0[2], P1[4]), maximum port pins (for example, P0[3], P1[5])). maximum combined budget. 5.25 5.25 Gross tested Package dependent. Temp 25°C Package dependent. Temp 25°C Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
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Operational Amplifier Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Operational Amplifier component both Analog Continuous Time PSoC blocks Analog Switched PSoC blocks. guaranteed specifications measured Analog Continuous Time PSoC block. Typical parameters apply 25°C design guidance only. Table Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Common Mode Voltage Range (high power high opamp bias) 35.0 Units V/°C Gross tested Package dependent. Temp 25°C common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA
GOLOA
Open Loop Gain Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High
VOHIGHOA High Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High VOLOWOA Output Voltage Swing (internal signals) Power Low, Opamp Bias High Power Medium, Opamp Bias High Power High, Opamp Bias High ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High
1200 2400 4600
1600 3200 6400
(Vdd 2.25) (Vdd 1.25V)
PSRROA Supply Voltage Rejection Ratio
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Table 3.3V Operational Amplifier Specifications Symbol VOSOA Description Input Offset Voltage (absolute value) Power Low, Opamp Bias High Power Medium, Opamp Bias High High Power Volts Only Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range 1.65 1.32 35.0 Units V/°C Gross tested Package dependent. Temp 25°C common-mode input voltage range measured through analog output buffer. specification includes limitations imposed characteristics analog output buffer. Specification applicable high power. other bias modes (except high power, high opamp bias), minimum Notes
TCVOSOA Average Input Offset Voltage Drift IEBOA CINOA VCMOA
GOLOA
Open Loop Gain Power Low, Opamp Bias Power Medium, Opamp Bias Power High, Opamp Bias
VOHIGHOA High Output Voltage Swing (internal signals) Power Low, Opamp Bias Power Medium, Opamp Bias Power High only VOLOWOA Output Voltage Swing (internal signals) Power Low, Opamp Bias Power Medium, Opamp Bias Power High, Opamp Bias ISOA Supply Current (including associated AGND buffer) Power Low, Opamp Bias High Power Medium, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias Power High, Opamp Bias High Supply Voltage Rejection Ratio
1200 2400 4600
1600 3200 6400
(Vdd 2.25) (Vdd 1.25V)
PSRROA
Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Units
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Analog Output Buffer Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol VOSOB TCVOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Average Input Offset Voltage Drift Common-Mode Input Voltage Range Output Resistance Power Power High VOHIGHOB High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Output Voltage Swing (Load ohms Vdd/2) Power Power High ISOB Supply Current Including Bias Cell Load) Power Power High PSRROB Supply Voltage Rejection Ratio Table 3.3V Analog Output Buffer Specifications Symbol VOSOB VCMOB ROUTOB Description Input Offset Voltage (Absolute Value) Common-Mode Input Voltage Range Output Resistance Power Power High Units V/°C VOUT (Vdd 1.25) Notes Units V/°C Notes
VOUT >(Vdd 1.25)
TCVOSOB Average Input Offset Voltage Drift
VOHIGHOB High Output Voltage Swing (Load ohms Vdd/2) Power Power High VOLOWOB Output Voltage Swing (Load ohms Vdd/2) Power Power High ISOB Supply Current Including Bias Cell Load) Power Power High Supply Voltage Rejection Ratio
PSRROB
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Analog Reference Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. guaranteed specifications measured through Analog Continuous Time PSoC blocks. power levels AGND refer power Analog Continuous Time PSoC block. power levels RefHi RefLo refer Analog Reference Control register. limits stated AGND include offset error AGND buffer local Analog Continuous Time PSoC block. Reference control power high. Table Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2 AGND BandGap AGND P2[4] (P2[4] Vdd/2) AGND BandGap AGND BandGap AGND Block Block Variation (AGND Vdd/2) RefHi Vdd/2 BandGap RefHi BandGap RefHi BandGap P2[6] (P2[6] 1.3V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 1.3V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 1.3V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 1.3V) 1.28 Vdd/2 0.04 0.048 P2[4] 0.011 0.009 0.022 -0.034 Vdd/2 0.10 0.06 1.30 Vdd/2 0.01 0.030 P2[4] 0.008 0.010 0.000 Vdd/2 1.33 Vdd/2 0.007 0.024 P2[4] 0.011 0.016 0.018 0.034 Vdd/2 0.10 0.06 Units
P2[6] 0.113 P2[6] 0.018 P2[6] 0.077 P2[4] 0.130 P2[4] P2[6] 0.133 0.112 Vdd/2 0.04 0.06 P2[4] 0.016 P2[4] P2[6] 0.016 Vdd/2 0.024 P2[4] 0.098 P2[4] P2[6]+ 0.100 0.076 Vdd/2 0.04 0.06
P2[6] 0.084 P2[6] 0.025 P2[6] 0.134 P2[4] 0.056 P2[4] P2[6] 0.057 P2[4] 0.026 P2[4] P2[6] 0.026 P2[4] 0.107 P2[4] P2[6] 0.110
Table 3.3V Analog Reference Specifications Symbol Description Bandgap Voltage Reference AGND Vdd/2 AGND BandGap AGND P2[4] (P2[4] Vdd/2) AGND BandGap AGND BandGap AGND Column Column Variation (AGND Vdd/2) RefHi Vdd/2 BandGap RefHi BandGap P2[4] 0.008 0.009 0.027 -0.034 1.28 Vdd/2 0.03 1.30 Vdd/2 0.01 Allowed P2[4] 0.001 0.005 0.010 0.000 Allowed Allowed P2[4] 0.009 0.015 0.018 0.034 1.33 Vdd/2 0.005 Units
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Table 3.3V Analog Reference Specifications (continued) Symbol Description RefHi BandGap P2[6] (P2[6] 0.5V) RefHi P2[4] BandGap (P2[4] Vdd/2) RefHi P2[4] P2[6] (P2[4] Vdd/2, P2[6] 0.5V) RefHi BandGap RefLo Vdd/2 BandGap RefLo BandGap RefLo BandGap P2[6] (P2[6] 0.5V) RefLo P2[4] BandGap (P2[4] Vdd/2) RefLo P2[4]-P2[6] (P2[4] Vdd/2, P2[6] 0.5V) P2[4] P2[6] 0.048 P2[4] P2[6] 0.075 Allowed Allowed P2[4] P2[6] 0.009 Allowed Allowed Allowed Allowed Allowed P2[4]- P2[6] 0.022 P2[4] P2[6] 0.092 P2[4] P2[6] 0.057 Units
Analog PSoC Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog PSoC Block Specifications Symbol Description Resistor Unit Value (Continuous Time) Capacitor Unit Value (Switch Cap) 12.2 80[9] Units
Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Note bits PORLEV following table refer bits VLT_CR register. PSoC Mixed-Signal Array Technical Reference Manual more information VLT_CR register. Table Specifications Symbol VPPOR1 VPPOR2 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.82 4.55 2.920 3.02 3.13 4.48 4.64 4.73 4.81 2.95 4.70 2.99[10] 3.09 3.20 4.55 4.75 4.83 4.95 Units Notes must greater than equal 2.5V during startup reset from Watchdog.
2.850 2.95 3.06 4.37 4.50 4.62 4.71
Notes design guarantee parameter, tested value Always greater than above VPPOR (PORLEV=01) falling supply.
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Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV Description Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (total)[11] 50,000 1,800,000 0.75 Units Years Erase/write cycles block Erase/write cycles Driving internal pull down resistor Driving internal pull down resistor Notes VddIWRITE Supply Voltage Flash Write Operations
FlashENPB Flash Endurance (per block) FlashENT FlashDR Flash Data Retention
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer 0xthe Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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SAR8 Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR8 Specifications Symbol Description 5.25 Units Notes voltage level P3[0] (when configured reference voltage) must always maintained less than chip supply voltage level pin. VADCVREF Vdd. VADCVREF Reference voltage P3[0] when configured reference voltage
IADCVREF (limited range)
Current when P3[0] configured VREF Integral Non-linearity Integral Non-linearity accommodating shift offset 0x80
-1.5 -1.2[12]
+1.5 +1.2
maximum over sub-range exceeding 1/16 full-scale range. 0x7F 0x80 points specs excluded here conversion monotonic over full range conversion monotonic over full range. 0x7F 0x80 transition specs excluded here.
(limited range)
Differential Non-linearity Differential Non-linearity excluding 0x7F-0x80 transition
-2.3
+2.3
Notes converters require stable input voltage during sampling period. voltage into SAR8 changes more than during sampling period then accuracy specifications
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Electrical Characteristics
Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V Chip-Level Specifications Symbol
FIMO24
Description
Internal Main Oscillator Frequency
23.4
24.6[13],[14],[15]
Units
Notes
Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode
FIMO6
Internal Main Oscillator Frequency
5.75
6.35[13],[14],[15] Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode 24.6[13],[14] 12.3 49.2
[13],[14] [13],[14],[16]
FCPU1 FCPU2 F48M F24M F32K1 F32K2 FPLL Jitter24M2 TPLLSLEW TOSACC
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Digital PSoC Block Frequency Internal Speed Oscillator Frequency External Crystal Oscillator Frequency Period Jitter (PLL) Lock Time External Crystal Oscillator Startup External Crystal Oscillator Startup
0.093 0.093
32.768 23.986 1700 2800
Refer Digital Block Specifications. Accuracy capacitor crystal dependent. duty cycle.
24.6[14],[16] 2620 3800
multiple (x732) crystal frequency. crystal oscillator frequency within final value Tosacc period. Correct operation assumes properly loaded maximum drive level 32.768 crystal. 3.0V 5.5V, 85°C.
TPLLSLEWSLOW Lock Time Gain Setting
Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1R FMAX TRAMP
Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Period Jitter (IMO) Root Mean Squared Maximum frequency signal input output. Supply Ramp Time
46.8
48.0 49.2[13],[15] 12.3
Trimmed. Using factory trim values.
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
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Figure Lock Timing Diagram
Enable
TPLLSLEW
FPLL Gain
Figure Lock Gain Setting Timing Diagram
Enable
TPLLSLEWLOW
FPLL Gain
Figure External Crystal Oscillator Startup Timing Diagram
Select
F32K2
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ECO) Timing Diagram
Jitter32k
32K2
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General Purpose Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload 12.3 Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Power High Opamp Bias High supported 3.3V. Table Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High Power High, Opamp Bias High 0.15 0.01 0.75 0.72 0.62 0.92 0.72 Units
TSOA
SRROA
SRFOA
BWOA
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Table 3.3V Operational Amplifier Specifications Symbol TROA Description Rising Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Settling Time from 0.1% load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Rising Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Falling Slew Rate (20% 80%)(10 load, Unity Gain) Power Low, Opamp Bias Power Medium, Opamp Bias High Gain Bandwidth Product Power Low, Opamp Bias Power Medium, Opamp Bias High 0.31 0.24 0.67 3.92 0.72 5.41 0.72 Units
TSOA
SRROA
SRFOA
BWOA
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When bypassed capacitor P2[4], noise analog ground signal distributed each block reduced factor dB). This frequencies above corner frequency defined on-chip 8.1k resistance external capacitor. Figure Typical AGND Noise with P2[4] Bypass
dBV/rtHz 10000
0.01
1000
0.001
0.01
Freq (kHz)
frequencies, opamp noise proportional 1/f, power independent, determined device geometry. high frequencies, increased power level reduces noise spectrum level. Figure Typical Opamp Noise
nV/rtHz 10000 PH_BH PH_BL PM_BL PL_BL 1000
0.001
0.01
Freq (kHz)
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Power Comparator Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC
Digital Block Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V Digital Block Specifications Symbol Timer Description Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 50[17] 50[17] 49.2 49.2 4.75V 5.25V 4.75V 5.25V 50[17] 50[17] 49.2 24.6 49.2 24.6 Units 4.75V 5.25V 4.75V 5.25V Notes
Maximum Input Clock Frequency
24.6
Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions
50[17]
24.6 49.2 24.6 49.2
Maximum data rate over clocking.
Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits
Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking.
Note minimum input pulse width based input synchronizers running nominal period).
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Analog Output Buffer Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High 0.65 0.65 0.65 0.65 Units
TSOB
SRROB
SRFOB
BWOB
BWOB
Table 3.3V Analog Output Buffer Specifications Symbol TROB Description Rising Settling Time 0.1%, Step, Load Power Power High Falling Settling Time 0.1%, Step, Load Power Power High Rising Slew Rate (20% 80%), Step, Load Power Power High Falling Slew Rate (80% 20%), Step, Load Power Power High Small Signal Bandwidth, 20mVpp, Load Power Power High Large Signal Bandwidth, 1Vpp, Load Power Power High Units
TSOB
SRROB
SRFOB
BWOB
BWOB
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External Clock Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Units
Table 3.3V External Clock Specifications Symbol FOSCEXT FOSCEXT Description Frequency with Clock divide 1[18] Frequency with Clock divide greater[19] High Period with Clock divide Period with Clock divide Power Switch 0.093 0.186 41.7 41.7 12.3 24.6 5300 Units
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Description Units Notes
SAR8 Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR8 Specifications[20] Symbol Freq3 Freq5 Input clock frequency Input clock frequency Description 3.075 3.075 Units
Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met. sample rate this 3.0/8=375KSPS
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Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C TSUDATI2C TBUFI2C TSPI2C Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Setup Time Free Time Between STOP START Condition Pulse Width spikes suppressed input filter. Description Standard Mode Fast Mode
[21]
Units
THDDATI2C Data Hold Time TSUSTOI2C Setup Time STOP Condition
Table Characteristics Pins 3.0V (Fast Mode Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C TSUDATI2C TBUFI2C TSPI2C Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Setup Time Free Time Between STOP START Condition Pulse Width spikes suppressed input filter. Description Standard Mode Fast Mode Units
THDDATI2C Data Hold Time TSUSTOI2C Setup Time STOP Condition
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data Figure I2C-bus specification) before line released. line trmax tSU;DAT 1000 1250 (according Standard-Mode
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Packaging Information
This section illustrates packaging specifications CY8C23x33 PSoC device, along with thermal impedances each package, solder reflow peak temperature, typical package capacitance crystal pins. Figure 32-Pin (5x5
NOTE
VIEW
BOTTOM VIEW SIDE VIEW
NOTES: HATCH AREA SOLDERABLE EXPOSED
CYPRESS COMPANY CONFIDENTIAL
TITLE SIZE
BASED JEDEC MO-248 PACKAGE WEIGHT: 0.0388g DIMENSIONS MILLIMETERS
0.55 PACKAGE OUTLINE EPAD (SAWN TYPE)
PART
001-42168
001-42168
LQ32
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Figure 28-Pin (210-Mil) SSOP
51-85079
Thermal Impedances
Table Thermal Impedances Package Package SSOP 95°C/W Typical JA[22] 19.4°C/W
Capacitance Crystal Pins
Table Typical Package Capacitance Crystal Pins Package SSOP Package Capacitance
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP Minimum Peak Temperature [23] Maximum Peak Temperature 240°C 240°C 260°C 260°C
Notes POWER Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Ordering Information
following table lists CY8C23X33 PSoC device family package features ordering codes. Table CY8C23X33 PSoC Device Family Features Ordering Information
Analog Outputs Analog Blocks (Columns Digital Pins Analog Inputs Digital Blocks (Rows Temperature Range
(Tape Reel) (210 Mil) SSOP (210 Mil) SSOP (Tape Reel)
CY8C23533-24LQXI CY8C23533-24LQXIT CY8C23433-24PVXI CY8C23433-24PVXIT
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Document Number: 001-44369 Rev.
Page
XRES
Ordering Code
Package
Flash (Kbytes)
(Bytes)
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CY8C23433, CY8C23533
Document History Page
Document Title: CY8C23433, CY8C23533 PSoC® Programmable System-on-ChipDocument Number: 001-44369 Revision 2044848 2482967 Orig. Change KIY/AESA HMI/AESA Submission Date 01/30/2008 05/14/2008 Data sheet creation Moved from Preliminary Final. Part number changed CY8C23433, CY8C23533. Adjusted placement block diagram; updated description DAC; updated package pinout description, updated spec, Added Flash Vdd, spec. Updated package diagram 001-42168 Updated data sheet template. Changed title "CY8C23433, CY8C23533 PSoC® Programmable System-on-ChipTM" Updated package diagram 001-42168 Changed names registers page "SARADC_C0" "SARADC_CR0" "SARADC_C1" "SARADC_CR1" Description Change
2616862 OGNE/AESA
12/05/2008
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Document Number: 001-44369 Rev.
Revised December 2008
Page
PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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