Automotive Extended Temperature PSoC® Programmable System-on-Chip

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Automotive Extended Temperature PSoC® Programmable System-on-Chip

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CY8C21334, CY8C21534
Automotive Extended Temperature PSoC® Programmable System-on-Chip
Qualified Powerful Harvard Architecture Processor Processor Speeds Power High Speed 4.75V 5.25V Operating Voltage Automotive Temperature Range: -40°C +125°C Advanced Peripherals (PSoC Blocks) Analog Type PSoC Blocks Provide: Comparators with References 10-Bit Single Dual, Channel Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full- Half-Duplex UART Master Slave Connectable GPIO Pins Complex Peripherals Combining Blocks Capacitive Sensing Application Capability Flexible On-Chip Memory Flash Program Storage Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes
EEPROM Emulation Flash Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Bytes Trace Memory Precision, Programmable Clocking Internal Oscillator Internal Speed, Power Oscillator Watchdog Sleep Functionality Optional External Oscillator, Programmable Configurations Sink, Drive GPIO Pull Pull Down, High Strong, Open Drain Drive Modes GPIO Analog Input GPIO Configurable Interrupt GPIO Versatile Analog Common Internal Analog Simultaneous Connection Combinations Additional System Resources CMaster, Slave, Multi-Master operation Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
Logic Block Diagram
Cypress Semiconductor Corporation Document Number:38-12038 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised 2009
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PSoC Functional Overview
PSoC family consists many devices with On-Chip Controllers. These devices designed replace multiple traditional MCU-based system components with one, cost single-chip programmable component. PSoC device includes configurable blocks analog digital logic, programmable interconnect. This architecture allows user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. PSoC architecture, illustrated "Logic Block Diagram" page comprises four main areas: Core, System Resources, Digital System, Analog System. Configurable global resources allow device resources combined into complete custom system. Each CY8C21x34 PSoC device includes four digital blocks four analog blocks. Depending PSoC package, general purpose (GPIO) also included. GPIO provide access global digital analog interconnects.
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) Full Half-Duplex 8-bit UART with selectable parity master slave master, slave, multi-master Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Figure Digital System Block Diagram
Port Port Port Port
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (internal main oscillator) (internal speed oscillator). core, called M8C, powerful processor with speeds MHz. MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such digital clocks increased flexibility, functionality implementing master, slave, multi-master, internal voltage reference that provides absolute value 1.3V number PSoC subsystems, various system resets supported M8C. Digital System composed array digital PSoC blocks, which configured into number digital peripherals. digital blocks connected GPIO through series global buses that route signal pin. This frees designs from constraints fixed peripheral controller. Analog System composed four analog PSoC blocks, supporting comparators analog-to-digital conversion with bits precision.
Digital Clocks From Core
System
Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
DBB00 DBB01 DCB02
Input Configuration
DCB03
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital System
Digital System composed four digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user modules. Digital peripheral configurations include those listed.
Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown Table page
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Analog System
Analog System composed four configurable blocks, allowing creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some common PSoC analog functions this device (most available user modules) listed.
Analog Multiplexer System Analog connect every GPIO pin. Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. additional analog input multiplexer provides second path bring Port pins analog array. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
Analog-to-digital converters (single dual, with 10-bit resolution) Pin-to-pin comparator Single-ended comparators with absolute (1.3V) reference 8-bit reference 1.3V reference System Resource)
Track pad, finger sensing. Chip-wide that allows analog input from pin. Crosspoint connection between combination.
most PSoC devices, analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks. CY8C21x34 devices provide limited functionality Type analog blocks. Each column contains Type block Type block. Refer PSoC Programmable System-on-ChipTechnical Reference Manual detailed information CY8C21x34's Type analog blocks. Figure Analog System Block Diagram
From Port
Additional System Resources
System Resources, some which have been previously listed, provide additional capability useful complete systems. Brief statements describing merits each system resource presented.
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V voltage reference provides absolute reference analog system, including ADCs DACs. Versatile analog multiplexer system.
Array Input Configuration
ACI0[1:0]
ACI1[1:0]
ACOL1MUX Analog
Array
ACE00 ASE10 ACE01 ASE11
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PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have varying number digital analog blocks. following table lists resources available specific PSoC device groups. PSoC device covered this data sheet highlighted Table Table PSoC Device Characteristics
Analog Columns Analog Outputs Analog Inputs Analog Blocks Digital Blocks Digital Digital Rows SRAM Size PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC® Programmable System-on-Chip Technical Reference Manual CY8C21x34 PSoC devices. up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
4[2] 4[2]
Bytes Bytes Bytes Bytes Bytes
Flash Size
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
CY8C24x23A[1] CY8C23x33 CY8C21x34[1] CY8C21x23 CY8C20x34
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
3[2, Bytes
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
Notes Automotive qualified devices available this group. Limited analog functionality. analog blocks CapSenseblock.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family. Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC On-Chip Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug property, other information need successfully implement your design.
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver
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Document Conventions
Acronyms Used
following table lists acronyms that used this document. Acronym EEPROM GPIO IPOR PPOR PSoC SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor static random access memory
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, `01010100b' `01000011b'). Numbers indicated `h', `b', `0x' decimal.
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Pinouts
CY8C21x34 PSoC device available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital connection common analog bus. However, Vss, Vdd, XRES capable Digital
20-Pin Part Pinout
Table 20-Pin Part Pinout (SSOP)
Type Name Digital Analog Input Power Power Power P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Active high external reset with internal pull down. Analog column input. Analog column input. Analog column input. Analog column input. Supply voltage. Optional External Clock Input (EXTCLK). Serial Clock (SCL), ISSP-SCLK[4]. Ground connection. Serial Data (SDA), ISSP-SDATA[4]. Description Analog column input. Analog column input. Analog column input, CMOD capacitor pin. Analog column input, CMOD capacitor pin. Ground connection. Serial Clock (SCL). Serial Data (SDA).
Figure CY8C21334 20-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, P1[1]
SSOP
P0[6], P0[4], P0[2], P0[0], XRES P1[6], P1[4], EXTCLK P1[2], P1[0],
LEGEND Analog, Input, Output, Analog Input.
Note These ISSP pins, which High when coming (Power Reset). PSoC Technical Reference Manual details.
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28-Pin Part Pinout
Table 28-Pin Part Pinout (SSOP)
Type Digital Analog Name Description
Figure CY8C21534 28-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, P1[1]
Power Power Input
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6]
Analog column input. Analog column input. Analog column input, CMOD capacitor pin. Analog column input, CMOD capacitor pin.
Ground connection. Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP-SCLK[4]. Ground connection. Serial Data (SDA), ISSP-SDATA[4]. Optional External Clock Input (EXTCLK).
SSOP
P0[6], P0[4], P0[2], P0[0], P2[6], P2[4], P2[2], P2[0], XRES P1[6], P1[4], EXTCLK P1[2], P1[0],
XRES Active high external reset with internal pull down. P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Analog column input. Analog column input. Analog column input Analog column input. Supply voltage.
Power
LEGEND Analog, Input, Output, Analog Input.
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Registers
Register Conventions
This section lists registers CY8C21x34 PSoC device. detailed register information, reference PSoC Technical Reference Manual. register conventions specific this section listed following table. Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields Reserved must accessed.
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Table Register Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 Addr (0,Hex) Access Name DBB00DR0 AMX_IN DBB00DR1 AMUX_CFG DBB00DR2 PWM_CR DBB00CR0 DBB01DR0 CMP_CR0 DBB01DR1 DBB01DR2 CMP_CR1 DBB01CR0 DCB02DR0 ADC0_CR DCB02DR1 ADC1_CR DCB02DR2 DCB02CR0 DCB03DR0 TMP_DR0 DCB03DR1 TMP_DR1 DCB03DR2 TMP_DR2 DCB03CR0 TMP_DR3 ACE00CR1 ACE00CR2 ACE01CR1 ACE01CR2 Blank fields Reserved must accessed. Addr (0,Hex) Access Addr (0,Hex) ASE11CR0 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name ASE10CR0 Access Name Addr (0,Hex) Access
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3 INT_MSK0 INT_MSK1 INT_VC RES_WDT
DEC_CR0 DEC_CR1
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
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Table Register Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 Addr (1,Hex) Access Name DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN CMP_GO_EN DBB01IN DBB01OU AMD_CR1 ALT_CR0 DCB02FN DCB02IN DCB02OU CLK_CR3 DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 ACE00CR1 ACE00CR2 ACE01CR1 ACE01CR2 Blank fields Reserved must accessed. Addr (1,Hex) Access Addr (1,Hex) ASE11CR0 RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific. Name ASE10CR0 Access Name Addr (1,Hex) Access
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IMO_TR ILO_TR BDG_TR ECO_TR
CPU_F
DAC_CR CPU_SCR1 CPU_SCR0
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Electrical Specifications
This section presents electrical specifications CY8C21x34 PSoC device. most date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Specifications valid -40oC 125oC 135oC specified, except where noted. Figure Voltage versus Frequency
5.25
4.75 Voltage
Frequency (nominal setting)
following table lists units measure that used this chapter. Table Units Measure Symbol
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megabaud megabits second megahertz megaohm microampere microfarad microhenry microsecond microvolts
Symbol Vrms
Unit Measure microvolts root-mean-square microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
Kbit Mbaud Mbps
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Absolute Maximum Ratings
Symbol TSTG Description Storage Temperature Typ. +125 Units Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Storage temperatures above 65oC degrade reliability. Maximum combined storage operational time +125°C 7000 hours.
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch-up Current
-0.5 2000
+125 +6.0
Human Body Model ESD.
Operating Temperature
Symbol Description Ambient Temperature Junction Temperature Typ. +125 +135 Units temperature rise from ambient junction package specific. Thermal Impedances page user must limit power consumption comply with this requirement. Notes
Electrical Characteristics
Chip-Level Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Chip-Level Specifications Symbol Description Supply Voltage Supply Current, 4.75 Typ. 5.25 Units Notes table titled Specifications" page Conditions 5.25V, -40°C 125°C, MHz, disabled. MHz, 93.75 kHz, 0.366 kHz. 5.25V, -40oC 55°C. 5.25V, 55oC 125°C.
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. High temperature range. Reference Voltage (Bandgap) 1.25
ISBH
VREF
1.30
1.35
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General Purpose Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table GPIO Specifications Symbol Pull Resistor Pull down Resistor High Output Level Description Units 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C.
Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Operational Amplifier Specifications Symbol VOSOA IEBOA[5] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/°C Gross tested Package dependent. Temp 25°C. Notes
TCVOSOA Average Input Offset Voltage Drift
Note Atypical behavior: IEBOA Port below 25°C; over temperature. Port Pins lowest leakage
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Analog Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Analog Specifications Symbol RVDD Description Switch Resistance Common Analog Resistance Initialization Switch Units Notes
Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Specifications Symbol VPPOR2 Description Value PPOR Trip PORLEV[1:0] 4.55 4.70 Units Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from watchdog.
VLVD6 VLVD7
Value Trip VM[2:0] 110b VM[2:0] 111b
4.62 4.71
4.73 4.81
4.83 4.95
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Programming Specifications Symbol IDDP VILP VIHP IILP IIHP VOLV VOHV Description Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying VILP P1[0] P1[1] During Programming Verify Input Current when Applying VIHP P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (total) Flash Data Retention[8]
4.75 6400
0.75
Units Years
Notes
VddIWRITE Supply Voltage Flash Write Operations
Driving internal pull down resistor. Driving internal pull down resistor.
FlashENPB Flash Endurance (per block)[6] FlashENT FlashDR
Erase/write cycles block. Erase/write cycles.
Notes full temperature range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information. maximum block endurance cycles allowed. Flash data retention based condition 7000 hours 125°C remaining time 65°C.
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Electrical Characteristics
Chip-Level Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Chip-Level Specifications Symbol FIMO24 FCPU1 FBLK5 F32K1 Description Frequency Nominal) Digital PSoC Block Frequency0(5V Nominal) Internal Speed Oscillator Frequency
24.96
Units
Notes
Internal Main Oscillator Frequency 23.04
0.09[9]
12.48[9] 24.96[9] Refer Digital Block Specifications below. This specification applies when been trimmed. During power untrimmed minimum frequency kHz.
Jitter32kR Jitter32kP TXRST DC24M Step24M Jitter24M1 FMAX TRAMP
Period Jitter Peak-to-Peak Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Peak-to-Peak Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time
2500
12.48[9]
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
F24M
Figure Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Note Accuracy derived from Internal Main Oscillator with appropriate trim range.
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General Purpose Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 12.48[9]
Figure GPIO Timing Diagram
GPIO Output oltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, Overdrive Units Notes
Analog Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Analog Specifications Symbol Switch Rate Description 3.17 Units Notes
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Digital Block Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Digital Block Specifications Function Functions Timer Description Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Without Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS Maximum Input Clock Frequency (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 50[10] 50[10] 24.96[9] 50[10] 50[10] Units Notes 24.96[9] 24.96
24.96[9] 24.96[9]
24.96[9]
24.96[9] 24.96[9]
Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions
50[10]
4.16[9] 2.08[9] 8.32[9]
Maximum data rate 2.08 Mbps over clocking.
Transmitter Maximum Input Clock Frequency Receiver Maximum Input Clock Frequency
Maximum baud rate 1.04 Mbaud over clocking. Maximum baud rate 3.12 Mbaud over clocking.
24.96[9]
Note minimum input pulse width based input synchronizers running nominal period).
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External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 Typ. 24.24 5300 Units Notes
Programming Specifications following table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Typ. Units Notes
Data Hold Time from Falling Edge SCLK
Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 125°C. Typical parameters apply 25°C design guidance only. Table Characteristics Pins Symbol FSCLI2C Description Clock Frequency Standard Mode 100[11] 100[12] Fast Mode Units Notes
400[11]
THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C THIGHI2C TSUSTAI2C Period Clock HIGH Period Clock
Time Repeated START Condition
THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Time STOP Condition TBUFI2C TSPI2C
Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
Note FSCLI2C derived from SysClk PSoC. This specification assumes that SysClk operating MHz, nominal. SysClk lower frequency, then FSCLI2C specification adjusts accordingly Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement TSUDATI2C must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax +TSUDATI2C 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Figure Definition Timing Fast/Standard Mode
TLOW TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
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Packaging Information
This section illustrates packaging specifications CY8C21x34 PSoC device, along with thermal impedances each package. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer drawings located Figure 20-Pin (210-MIL) SSOP
51-85077
Figure 28-Pin (210-Mil) SSOP
51-85079
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Thermal Impedances
Table Thermal Impedances Package Package SSOP SSOP Typical JA[13] oC/W oC/W Typical oC/W oC/W
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP SSOP Minimum Peak Temperature[14] 240oC 240oC Maximum Peak Temperature 260oC 260oC
Notes Power Higher temperatures required based solder melting point. Typical temperatures solder 220+/-5oC with Sn-Pb 245+/-5oC with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
This section presents development tools available CY8C21x34 family.
Software
PSoC Designer core PSoC development software suite PSoC Designer. Utilized thousands PSoC developers, this robust software been facilitating PSoC designs years. PSoC Designer available free charge http://www.cypress.com. PSoC Designer comes with free compiler. PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge
Evaluation Tools
evaluation tools purchased from Cypress Online Store. online store (www.cypress.com/shop) also most date information contents, descriptions, availability. CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, RS-232 port, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Development Kits
development kits purchased from Cypress Online Store. online store (www.cypress.com/shop) also most date information contents, descriptions, availability. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view contents specific memory locations. Advanced emulation features also supported through PSoC Designer. includes:
CY3235-ProxDet CapSense Proximity Detection Demonstration allows quick easy demonstration PSoC CapSense-enabled device (CY8C21x34) accurately sense proximity hand finger along length wire antenna. includes:
Proximity Detection Demo Board w/Antenna Debugging/Communication Bridge Cable feet) Supporting Software CY3235-ProxDet Quick Start Guide CY8C24894 PSoC device I2C-USB Bridge CY8C21434 PSoC device Proximity Detection Demo Board
ICE-Cube Unit 28-Pin PDIP Emulation CY8C29466-24PXI 28-Pin CY8C29466-24PXI PDIP PSoC Device Samples (two) PSoC Designer Software ISSP Cable MiniEval Socket Programming Evaluation board Backward Compatibility Cable (for connecting legacy Pods) Universal 110/220 Power Supply (12V) European Plug Adapter Cable Getting Started Guide Development Registration form
CY3213A-CapSense CY3213A-CapSense Training includes hardware example projects help designers learn implement PSoC CapSense their design using CY8C21x34 family. training board included that hard-wired buttons sliders well control communication. training includes following:
Training board (CY8C21x34) PSoC Designer Example Project User Module Mini Programmer unit module cable
CY3280-BK1 Universal CapSense Control designed easy prototyping debug CapSense designs with pre-defined control circuitry plug-in hardware. comes with control boards CY8C20x34 CY8C21x34 devices well breadboard module button(5)/slider module.
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CY3210-21X34 Evaluation (EvalPod) PSoC EvalPods pods that connect In-Circuit Emulator (CY3215-DK kit) allow debugging capability. They also function standalone device without debugging capability. EvalPod 28-pin footprint bottom easy connection development kits other hardware. EvalPod prototyping headers easy connection device's pins. CY3210-21X34 provides evaluation CY8C21x34 PSoC device family.
28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note: CY3207ISSP needs special software compatible with PSoC Programmer. This software free downloaded from http://www.cypress.com. includes:
Device Programmers
device programmers purchased from Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part Number CY8C21334-12PVXE CY8C21534-12PVXE Package SSOP SSOP Kit[15] CY3250-21X34 CY3250-21X34 Foot Kit[16] CY3250-20SSOP-FK CY3250-28SSOP-FK Adapter[17] Adapters found http://www.emulation.com.
Third Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under Design Resources Evaluation Boards.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com.
Notes contains emulation pod, flex-cable (connects ICE), feet, device samples. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
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Ordering Information
following table lists CY8C21x34 PSoC device's package features ordering codes. Table PSoC Device Features Ordering Information Temperature Range XRES
Feedback
Digital Pins
Ordering Code
Package
(210-Mil) SSOP (210-Mil) SSOP (Tape Reel) (210-Mil) SSOP (210-Mil) SSOP (Tape Reel)
CY8C21334-12PVXE CY8C21334-12PVXET CY8C21534-12PVXE CY8C21534-12PVXET
-40°C +125°C -40°C +125°C -40°C +125°C -40°C +125°C
Ordering Code Definitions
xxx-12xx
Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: PSoC Company Cypress Thermal Rating: Automotive -40°C +85°C Commercial Industrial Automotive Extended -40°C +125°C
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Analog Outputs
Flash (Bytes)
SRAM (Bytes)
Analog Blocks
Analog Inputs
Digital Blocks
CY8C21334, CY8C21534
Document History Page
Document Title: CY8C21334, CY8C21534 Automotive Extended Temperature PSoC® Programmable System-on-ChipDocument Number: 38-12038 Revision 350496 395740 422602 Orig. Change Submission Date 04/18/05 09/14/05 02/03/06 Description Change silicon document (Revision **). Update ISBH Chip-Level Specification notes qual. Update copyright, code, Perform logo. Make data sheet Final. Modify Storage Temperature recommended usage related notes. Update Chip-Level Spec., FCPU1. ISSP note pinout tables. Implement standard. corporate address. Update trademarks. Post www.cypress.com Changed Drive GPIO under Programmable Configurations Sink, Drive GPIO Changed Analog-to-digital converters (single dual, with 8-bit resolution) under Analog-to-digital converters (single dual, with 10-bit resolution) Updated template. Added Note Ordering Information section. Changed title from PSoC Mixed-Signal Array PSoC Programmable System-on-Chip Updated Getting Started section. Replaced Designing with User Modules section with Designing with PSoC Designer section. Updated Features list PSoC Functional Overview section. Updated some Specification values conform +/-4% accurate order magnitude changes). Added note specifications section clarify SysClk dependency. Added Development Tool Selection section. Deleted some inapplicable redundant information. Changed title. Updated Bookmarks.
2101387 2641945
AESA
02/20/08
OGNE/PYRS 01/21/09
2703345
VIVG/PYRS
05/07/09
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Sales, Solutions, Legal Information
Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit www.cypress.com/sales.
Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
Cypress Semiconductor Corporation, 2005-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
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PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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Automotive Extended Temperature PSoC® Programmable System-on-Chip

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