PSoC® Programmable System-on-Chip Powerful Harvard Architecture P
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PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor: Processor Speeds Multiply, 32-Bit Accumulate Power High Speed 3.0V 5.25V Operating Voltage Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC Blocks) Analog Type PSoC Blocks provide: Single Dual 8-Bit Comparators Four) Eight Digital PSoC Blocks provide: 32-Bit Timers, Counters, PWMs Shot, Multi Shot Mode Support Timers PWMs with Deadband Support Digital Block Shift Register, CRC, Modules Full Duplex UART Multiple SPIMasters Slaves, Variable Data Length Support: .,16-bit Connected GPIO Pins Complex Peripherals Combining Blocks Shift Function Support Detection Powerful Synchronize Feature Support. Analog Module Operations Synchronized Digital Blocks External Signals. High Speed 10-Bit with Sample Hold Optimized Embedded Control Precision, Programmable Clocking: Internal 24/48 Oscillator across Industrial Temperature Range High Accuracy with Optional Crystal Optional External Oscillator, Internal/External Oscillator Watchdog Sleep Flexible On-Chip Memory: Bytes Flash Program Storage 50,000 Erase/Write Cycles Byte SRAM Data Storage In-System Serial Programming (ISSPTM) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Optimized CapSense Resource: IDAC Support Source Current Replace External Resistor Dedicated Clock Resources CapSense: CSD_CLK: 1/2/4/8/16/32/128/256 Derive from SYSCLK CNT_CLK: 1/2/4/8 Derive from CSD_CLK Dedicated 16-Bit Timers/Counters CapSense Scanning Support Dual Channels Simultaneous Scanning
Programmable Configurations: Sink GPIO Pull Pull down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Configurable Interrupt GPIO Additional System Resources: CSlave, Master, MultiMaster kHz, Supports Hardware Addressing Feature Watchdog Sleep Timers User Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference Supports Block into Digital Peripheral Logic
Level Block Diagram
Port Port Port Port Port Analog Drivers
PSoC Core
Global Digital Interconnect SRAM Interrupt Controller SROM
Global Analog Interconnect Flash Sleep Watchdog
Core (M8C)
Multiple Clock Sources (Includes IMO, ILO, PLL, ECO)
DIGITAL SYSTEM
Digital Block Array
ANALOG SYSTEM
Analog Input Muxing(L,R) Analog
Analog Block Array
System
CapSense Digital Resource
10-bit
Digital Clocks
MACs
System Resets
Internal Voltage Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-43084 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised March 2009
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PSoC® Functional Overview
PSoC® family consists many On-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with cost single-chip programmable device. PSoC devices include configurable blocks analog digital logic, programmable interconnects. This architecture enables user create customized peripheral configurations that match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts packages. PSoC architecture, shown Figure consists four main areas: PSoC Core, Digital System, Analog System, System Resources. Configurable global busing allows combining device resources into complete custom system. PSoC family have five ports connecting global digital analog interconnects, providing access eight digital blocks analog blocks.
Digital System
Digital System composed eight digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Figure Digital System Block Diagram
Port Port Port Port Port
Digital Clocks From Core
System
Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBC00 DBC01 DCC02
DCC03
Output Configuration
PSoC Core
PSoC Core powerful engine that supports rich feature set. core includes CPU, memory, clocks, configurable GPIO (General Purpose IO). core powerful processor with speeds MHz, providing four MIPS 8-bit Harvard architecture microprocessor. uses interrupt controller with vectors, simplify programming real time embedded events. Program execution timed protected using included Sleep Watch Timers (WDT). Memory encompasses Flash program storage, bytes SRAM data storage, EEPROM emulated using Flash. Program Flash uses four protection levels blocks bytes, allowing customized software protection. PSoC device incorporates flexible internal clock generators, including (internal main oscillator). also doubled digital system. power (internal speed oscillator) provided Sleep timer WDT. crystal accuracy required, (32.768 external crystal oscillator) available Real Time Clock (RTC), optionally generate crystal-accurate system clock using PLL. clocks, together with programmable clock dividers System Resource), provide flexibility integrate almost timing requirement into PSoC device. PSoC GPIOs provide connection CPU, digital, analog resources device. Each pin's drive mode selected from eight options, allowing great flexibility external interfacing. Every also generate system interrupt high level, level, change from last read.
Input Configuration
DBC00 DBC01 DCC02 DCC03
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
Digital peripheral configurations are:
PWMs 32-Bit) PWMs with Dead band 32-Bit) Counters 32-Bit) Timers 32-Bit) UART with Selectable Parity Two) Master Slave Two) Shift Register 32-Bit) Slave Master (One Available System Resource) Cyclical Redundancy Checker/Generator 32-Bit) IrDA Two) Pseudo Random Sequence Generators 32-Bit)
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This provides choice system resources your application. Family resources shown Table page
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Analog System
Analog System consists 10-bit configurable blocks. programmable 10-bit optimized that could ksps with (true 3.0V Vref 3.0V). External filters required input channels antialiasing. This ensures that out-of-band content folded into input signal band. Reconfigurable analog resources allow creating complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) are:
Additional System Resources
System Resources, some which listed previous sections, provide additional capability useful complete systems. Additional resources include MAC, voltage detection, power reset. merits each system resource are:
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. Additional Digital resources clocks optimized CSD. Support "RTC" block into digital peripheral logic. multiply accumulate (MAC) provides fast 8-bit multiplier with 32-bit accumulate, assist both general math digital filters. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.3V reference provides absolute reference analog system, including ADCs DACs.
Analog-to-Digital converters (Single Dual, with 8-bit resolution) Pin-to-pin Comparator Single ended comparators with absolute (1.3V) reference 5-bit reference 1.3V reference System Resource)
Analog blocks provided columns four, which include CT-E (Continuous Time) SC-E (Switched Capacitor) blocks. These devices provide limited functionality Type analog blocks. Figure Analog System Block Diagram
Array Input Configuration
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. following table lists resources available specific PSoC device groups. Table PSoC Device Characteristics PSoC Part Number Digital Analog Columns Analog Blocks Page
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ACE00 ASE10
ACE01 ASE11
ACE10
ACE11
CY8C29x66 CY8C27x66 CY8C27x43 CY8C22x45 CY8C21x34 CY8C21345 CY8C24x23 CY8C24x33
Block Array
AmuxL
AmuxR P0[0:7]
ACI2[3:0]
Analog Reference
Interface Digital System Reference Generators
Limited analog functionality.
AGND
Bandgap
Interface (Address Bus, Data Bus, Etc.)
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Analog Outputs
ACI0[1:0]
ACI1[1:0]
ACI1[1:0]
ACI1[1:0]
Analog Inputs
Digital Blocks
Digital Rows
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Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices. up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC programmable system-on-chip controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
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Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, programmable system-on-chip varieties.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
In-Circuit Emulator
cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects using port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Document Conventions
Acronyms Used
following table lists acronyms that used this data sheet. Table Acronyms Acronym EEPROM GPIO IPOR PPOR PSoC® Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose in-circuit emulator integrated development environment input/output imprecise power reset least significant voltage detect most significant program counter power reset precision power reset Programmable System-on-Chip pulse width modulator random access memory read only memory switched capacitor switch mode pump
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image In-Circuit Emulator (ICE) where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated decimal.
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Pinouts
This PSoC device family available variety packages that listed following tables. Every port (labeled with "P") capable Digital However, Vss, Vdd, XRES capable Digital
CY8C22345, CY8C21345 28-Pin SOIC
Table Definitions Type Input Power Digital Analog Power Power Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1]* P1[0]* P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Supply Voltage Compare Column Active High Reset with Internal Pull Down Optional External Clock Input (EXT-CLK) Serial Clock (SCL), ISSP-SCLK Ground Connection Serial Clock (SCL), ISSP-SDATA Ground Connection Serial Clock (SCL) Serial Data (SDA) Compare Column Optional External Vref Description Integration Capacitor Integration Capacitor Figure Diagram
P0[7] P0[5] P0[3] P0[1] P2[7] ADC_Ext_Vref, P2[5] P2[3] P2[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, P1[1]
SOIC
P0[6], P0[4], P0[2], P0[0], P2[6], P2[4], P2[2], P2[0], XRES P1[6], P1[4], EXTCLK P1[2], P1[0], SDATA
LEGEND: Analog, Input, Output, M=Analog input, Analog right input, Analog left input, ISSP which POR.
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CY8C22545 44-Pin TQFP
Table Definitions Type Power Input Power Power Digital Power Analog Name P2[5] P2[3] P2[1] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]* P1[0]* P1[2] P1[4] P1[6] P3[0] P3[2] P3[4] P3[6] XRES P4[0] P4[2] P4[4] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] Compare Column Ground Connection Active High Reset with Internal Pull Down Optional External Clock Input (EXTCLK) Crystal (XTALin), Serial Clock (SCL), SCLK Ground Connection Crystal (XTALout), Serial Data (SDA), SDATA Serial Clock (SCL) Serial Data (SDA) Ground Connection Supply Voltage
ADC_Ext_Vref, P2[5] P2[3] P2[1] P4[5] P4[3] P4[1] P3[7] P3[5] P3[3]
Figure Diagram Description
P0[5], P0[7], P2[7], P0[1], P0[3], P0[4], P0[2], P0[0], P2[6], P1[6] P3[0] P2[4], P2[2], P2[0], P4[4], P4[2], P4[0], XRES P3[6], P3[4], P3[2], P0[6],
Optional External Vref
TQFP
P1[3] SCL, XTALin, P1[1]
SCL, P1[7] SDA, P1[5]
P3[1]
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SDA, XTALout, P1[0]
P1[2] EXTCLK, P1[4]
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Table Definitions (continued) Type Digital Power Analog Name P0[6] P0[7] P0[5] P0[3] P0[1] P2[7] Compare Column Supply Voltage Integration Capacitor Integration Capacitor Description
LEGEND: Analog, Input, Output, M=Analog input, Analog right input, Analog left input, ISSP which POR.
Register Reference
This section lists registers this PSoC device family mapping tables. detailed register information, refer PSoC Programmable System-on Chip Technical Reference Manual.
Register Mapping Tables
PSoC device total register address space bytes. register space also referred space broken into parts. Flag register determines which bank user currently When set, user said "extended" address space "configuration" registers. Note following register mapping tables, blank fields Reserved must accessed.
Register Conventions
Abbreviations Used register conventions specific this section listed following table. Table Abbreviations Convention Description Read write register bit(s) Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
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Table Register Bank Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
CSD0_DR0_L CSD0_DR1_L CSD0_CNT_L CSD0_CR0 CSD0_DR0_H CSD0_DR1_H CSD0_CNT_H CSD0_CR1 CSD1_DR0_L CSD1_DR1_L CSD1_CNT_L CSD1_CR0 CSD1_DR0_H CSD1_DR1_H CSD1_CNT_H CSD_CR1 DBC00DR0 AMX_IN DBC00DR1 AMUX_CFG DBC00DR2 PWM_CR DBC00CR0 ARF_CR DBC01DR0 CMP_CR0 DBC01DR1 ASY_CR DBC01DR2 CMP_CR1 DBC01CR0 DCC02DR0 ADC0_CR DCC02DR1 ADC1_CR DCC02DR2 SADC_DH DCC02CR0 SADC_DL DCC03DR0 TMP_DR0 DCC03DR1 TMP_DR1 DCC03DR2 TMP_DR2 DCC03CR0 TMP_DR3 DBC10DR0 DBC10DR1 DBC10DR2 ACB00CR1* DBC10CR0 ACB00CR2* DBC11DR0 DBC11DR1 DBC11DR2 ACB01CR1* DBC11CR0 ACB01CR2* DCC12DR0 DCC12DR1 DCC12DR2 DCC12CR0 DCC13DR0 Shaded fields Reserved must accessed.
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2 PRT4DR PRT4IE PRT4GS PRT4DM2
ASD11CR0* PWMVREF0 PWMVREF1 IDAC_MODE PWM_SRC TS_CR0 TS_CMPH TS_CMPL TS_CR1 STK_PP IDX_PP MVR_PP MVW_PP I2C0_CFG I2C0_SCR I2C0_DR I2C0_MSCR INT_CLR0 INT_CLR1 INT_CLR2 INT_CLR3 INT_MSK3 INT_MSK2 INT_MSK0 INT_MSK1 INT_VC RES_WDT DEC_DH DEC_DL _CR0* DEC_CR1* MUL0_X MUL0_Y MUL0_DH MUL0_DL ACC0_DR1 ACC0_DR0 ACC0_DR3 ACC0_DR2 RDI0RI RDI0SYN CPU_T1 RDI0IS CPU_T2 RDI0LT0 CPU_X RDI0LT1 RDI0RO0 CPU_PCH RDI0RO1 CPU_SP RDI0DSM CPU_F RDI1RI CPU_TST0 RDI1SYN CPU_TST1 RDI1IS CPU_TST2 RDI1LT0 TST3 RDI1LT1 DAC1_D Access specific. different meaning.
ASC10CR0*
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Table Register Bank Table: User Space (continued)
Access Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (1,Hex) Name Name Name Name Name
DCC13DR1 DCC13DR2 DCC13CR0 Shaded fields Reserved must accessed.
RDI1RO0 DAC0_D RDI1RO1 CPU_SCR1 RDI1DSM CPU_SCR0 Access specific. different meaning.
Table Register Bank Table: Configuration Space
Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name ASC10CR0*
CMP0CR1 CMP0CR2 VDAC50CR0 CMP1CR1 CMP1CR2 VDAC51CR0 CSCMPCR0 CSCMPGOEN CSLUTCR0 CMPCOLMUX CMPPWMCR CMPFLTCR CMPCLK1 CMPCLK0 DBC00FN CLK_CR0 DBC00IN CLK_CR1 DBC00OU ABF_CR0 DBC00CR1 AMD_CR0 DBC01FN CMP_GO_EN DBC01IN CMP_GO_EN1 DBC01OU AMD_CR1 DBC01CR1 ALT_CR0 DCC02FN ALT_CR1 DCC02IN CLK_CR2 DCC02OU DBC02CR1 CLK_CR3 DCC03FN TMP_DR0 DCC03IN TMP_DR1 DCC03OU TMP_DR2 DBC03CR1 TMP_DR3 DBC10FN DBC10IN DBC10OU ACB00CR1* DBC10CR1 ACB00CR2* Shaded fields Reserved must accessed.
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1 PRT4DM0 PRT4DM1 PRT4IC0 PRT4IC1
ASD11CR0* GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 DAC_CR1# OSC_GO_EN OSC_CR4 OSC_CR3 GDI_O_IN_CR OSC_CR0 GDI_E_IN_CR OSC_CR1 GDI_O_OU_CR OSC_CR2 GDI_E_OU_CR VLT_CR RTC_H VLT_CMP RTC_M ADC0_TR* RTC_S ADC1_TR* RTC_CR V2BG_TR SADC_CR0 IMO_TR SADC_CR1 ILO_TR SADC_CR2 BDG_TR SADC_CR3TRIM ECO_TR SADC_CR4 MUX_CR4 I2C0_AD MUX_CR5 MUX_CR6 MUX_CR7 RDI0RI RDI0SYN CPU_T1 RDI0IS CPU_T2 RDI0LT0 CPU_X Access specific. different meaning.
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Table Register Bank Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
DBC11FN DBC11IN DBC11OU ACB01CR1* DBC11CR1 ACB01CR2* DCC12FN DCC12IN DCC12OU DBC12CR1 DCC13FN DCC13IN DCC13OU DBC13CR1 Shaded fields Reserved must accessed.
RDI0LT1 CPU_PCL RDI0RO0 CPU_PCH RDI0RO1 CPU_SP RDI0DSM CPU_F RDI1RI FLS_PR0 RDI1SYN RDI1IS FLS_PR1 RDI1LT0 RDI1LT1 FAC_CR0 RDI1RO0 DAC_CR0# RDI1RO1 CPU_SCR1 RDI1DSM CPU_SCR0 Access specific. different meaning.
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Electrical Specifications
This section presents electrical specifications this PSoC device family. latest electrical specifications, check most recent data sheet visiting http://www.cypress.com/psoc. Specifications valid -40°C 85°C 100°C, except where noted. Specifications devices running greater than valid -40°C 70°C 82°C. Figure Voltage versus Operating Frequency
5.25
4.75 Voltage 3.00
following table lists units measure that used this section. Table Units Measure Symbol Kbit Vrms decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm micro ampere micro farad micro henry microsecond micro volts micro volts root-mean-square Unit Measure degree Celsius Symbol Unit Measure micro watts milli-ampere milli-second milli-volts nano ampere nanosecond nanovolts pico ampere pico farad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
rati
Frequency
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Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Table Absolute Maximum Ratings Symbol Description TSTG Storage Temperature VIOz IMIO Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tristate Maximum Current into Port Electro Static Discharge Voltage Latch Current -0.5 2000 +100 +6.0 Units Human Body Model Notes Higher storage temperatures reduce data retention time
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units Notes temperature rise from ambient junction package specific. Table page user must limit power consumption comply with this requirement.
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CY8C21345, CY8C22345, CY8C22545
Electrical Characteristics
Chip Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C, design guidance only, unless specified otherwise. Table Chip Level Specifications Symbol Description Supply Voltage Supply Current 5.25 Units Notes Table page Conditions 5.0V, 25°C, MHz, disabled. 93.75 93.75 Conditions 3.3V 25°C, Disabled MHz, 93.75 93.75 Conditions with internal slow speed oscillator, 3.3V -40°C 55°C Conditions with internal slow speed oscillator, 3.3V 55°C 85°C Conditions with properly loaded, max, 32.768 crystal. 3.3V, -40°C 55°C Conditions with properly loaded, max, 32.768 crystal. 55°C 85°C Trimmed appropriate
IDD3
Supply Current
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDTa Sleep (Mode) Current with POR, LVD, Sleep Timer, high temperaturea Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, external crystal high temperature Reference Voltage (Bandgap)
ISBH
ISBXTL
ISBXTLH
VREF
1.275
1.325
Standby current includes functions (POR, LVD, WDT, Sleep Time) needed reliable system operation. This must compared with devices that have similar functions enabled.
General Purpose Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only, unless otherwise specified. Table GPIO Specifications Symbol Description Pull Resistor Pull down Resistor High Output Level Units 4.75 5.25V maximum combined budget) 4.75 5.25V (100 maximum combined budget) 5.25 5.25 Notes
Output Level
0.75
Input Level Input High Level
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Table GPIO Specifications (continued) Symbol COUT Description Input Hysterisis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output Units Notes Gross tested Package dependent. Temp 25°C Package dependent. Temp 25°C
Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Operational Amplifier Specifications Symbol VOSOA IEBOAa CINOA VCMOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Units V/°C Gross tested Package dependent. Temp 25°C Notes
TCVOSOA Average Input Offset Voltage Drift
Atypical behavior: IEBOA Port below 25°C; over temperature. Port Pins lowest leakage
Table 3.3V Operational Amplifier Specifications Symbol VOSOA TCVOSOA IEBOAa CINOA VCMOA Description Input Offset Voltage (absolute value) Average Input Offset Voltage Drift Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Units V/°C Gross tested Package dependent. Temp 25°C Notes
a.Atypical behavior: IEBOA Port below 25°C; over temperature. Port Pins lowest leakage
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol VREFLPC VOSLPC Description power comparator (LPC) reference voltage range voltage offset Units
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SAR10 Specifications
Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR10 Specifications Symbol Vadcvref Description Reference voltage P2[5] when configured reference voltage 5.25 Units Notes When VREF buffered inside ADC, voltage level P2[5] (when configured reference voltage) must always maintained least less than chip supply voltage level pin. (Vadcvref Vdd) Disables internal voltage reference buffer 3.0V Vref 3.0V 3.0V Vref 3.0V 3.0V Vref 3.0V 3.0V Vref 3.0V
Iadcvref bits
Current when P2[5] configured VREF Integral Nonlinearity
-2.5 -5.0 -1.5 -4.0
bits Differential Nonlinearity Sample second
ksps Resolution bits
Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Specifications Symbol Rgnd Description Switch Resistance Common Analog Resistance Initialization Switch Units 3.00 Notes
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Specifications Symbol VPPOR1 VPPOR2 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.82 4.55 2.95 4.70 Units Notes must greater than equal 3.0V during startup, reset from XRES pin, reset from Watchdog.
VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7
2.95 3.06 4.37 4.50 4.62 4.71
3.02 3.13 4.48 4.64 4.73 4.81
3.09 3.20 4.55 4.75 4.83 4.95
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol Description VddIWRITE Supply Voltage Flash Write Operations IDDP VILP Supply Current during Programming Verify Input Voltage during Programming Verify VIHP Input High Voltage during Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] during Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] during Programming Verify VOLV Output Voltage during Programming Verify VOHV Output High Voltage during Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)a FlashDR Flash Data Retention 2.70 50,000 1,800,000 0.75 Units Years Erase/write cycles block Erase/write cycles Driving internal pull down resistor Driving internal pull down resistor Notes
maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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Electrical Characteristics
Chip Level Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V Chip-Level Specifications
Symbol FIMO24 Description Internal Main Oscillator Frequency 22.8 Min(%) 25.2a,b,c Max(%) Units Notes Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode only SLIMO mode Refer Table page adjusted with factory trim values until after starts running. "System Resets" section Technical Reference Manual.
FIMO6
Internal Main Oscillator Frequency
5.75
6.35a,b,c
FCPU1 FCPU2 FBLK5 FBLK33 F32K1 F32KU
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Untrimmed Internal Speed Oscillator Frequency
0.93 0.93
24.6a,b 12.3b,c 49.2a,b,d 24.6
Jitter32k TXRST DC24M FMAX TRAMP
Period Jitter External Reset Pulse Width Duty Cycle Maximum frequency signal input output Supply Ramp Time
12.3
Jitter24M1 Period Jitter (IMO)
Valid only 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. Refer individual user module data sheets information maximum frequencies user modules.
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ILO) Timing Diagram
Jitter32k
32K1
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General Purpose Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, Units 3.0V Notes
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC
Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Analog Specifications Symbol Switch Rate Description 3.17 Units Notes
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Digital Block Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 25°C design guidance only. Table 3.3V Digital Block Specifications Function Functions Timer Description Maximum Block Clocking Frequency 4.75V) Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Without Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) Maximum Input Clock Frequency 49.2 49.2 24.6 24.6 49.2 24.6 49.2 4.75V 5.25V 4.75V 5.25V Maximum data rate over clocking Maximum data rate 3.08 over clocking Maximum data rate 6.15 over clocking Maximum data rate 3.08 over clocking Maximum data rate 6.15 over clocking
49.2 24.6
Units
Notes
4.75V 5.25V 3.0V 4.75V 4.75V 5.25V 4.75V 5.25V
49.2 24.6 49.2 24.6
CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits
minimum input pulse width based input synchronizers running nominal period).
External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Units
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Table 3.3V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.093 12.3 Units Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.186
24.6
High Period with Clock divide Period with Clock divide Power Switch
41.7 41.7
5300
SAR10 Specifications
Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table SAR10 Specifications Symbol Freq3 Freq5 Description Input clock frequency Input clock frequency Units
Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK FSCLK3 TERASEB TWRITE TDSCLK TDSCLK3 Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Frequency SCLK3 Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units 3.6V Vdd; Load 3.6; Load Notes
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Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C THDSTAI2C Description Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Setup Time Repeated START Condition Data Hold Time Data Setup Time Setup Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed Input Filter Standard Mode Fast Mode Units
TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C
100a
Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
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Packaging Information
This section provides packaging specifications this PSoC device with thermal impedances each package, typical package capacitance crystal pins.
Packaging Dimensions
Figure 28-Pin SOIC
NOTE
JEDEC MO-119 BODY LENGTH DIMENSION DOES INCLUDE MOLD PROTRUSION/END FLASH,BUT DOES INCLUDE MOLD MISMATCH MEASURED MOLD PARTING LINE. MOLD PROTRUSION/END FLASH SHALL EXCEED 0.010 (0.254 SIDE DIMENSIONS INCHES MIN. MAX.
0.291[7.39] 0.300[7.62]
PACKAGE WEIGHT 0.85gms
0.394[10.01] 0.419[10.64]
0.026[0.66] 0.032[0.81]
PART S28.3 STANDARD PKG. SZ28.3 LEAD FREE PKG.
0.697[17.70] 0.713[18.11] 0.092[2.33] 0.105[2.67]
SEATING PLANE
0.004[0.10] 0.013[0.33] 0.050[1.27] TYP. 0.019[0.48] 0.004[0.10] 0.0118[0.30] 0.015[0.38] 0.050[1.27]
0.0091[0.23] 0.0125[3.17]
51-85026
Figure 44-Pin TQFP
12.00±0.25 10.00±0.10 MIN. 0.37±0.05 STAND-OFF 0.05 MIN. 0.15 MAX. 0.08 MIN. 0.20 MAX. 0.25 GAUGE PLANE
0.08 MIN. 0.20 MIN. 0.20 MIN. 0.80 B.S.C. 1.00 REF.
0-7° 0.60±0.15
DETAIL
NOTE: JEDEC MS-026
SEATING PLANE 1.60 MAX. 12°±1° (8X)
BODY LENGTH DIMENSION DOES INCLUDE MOLD PROTRUSION/END FLASH MOLD PROTRUSION/END FLASH SHALL EXCEED 0.0098 (0.25 SIDE BODY LENGTH DIMENSIONS PLASTIC BODY SIZE INCLUDING MOLD MISMATCH DIMENSIONS MILLIMETERS
1.40±0.05 0.10 0.20 MAX. DETAIL
51-85064
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Thermal Impedances
Table Thermal Impedances Package Package SOIC TQFP POWER Typical 68°C/W 61°C/W
Capacitance Crystal Pins
Table Typical Package Capacitance Crystal Pins Package SOIC TQFP Package Capacitance
Ordering Information
following table lists package features ordering codes this PSoC device family. Table PSoC Device Family Features Ordering Information Analog Outputs Analog Blocks (Columns Flash (Kbytes) Digital Pins Analog Inputs Digital Blocks (Rows Temperature Range (Bytes)
Package
Ordering Code
SOIC SOIC TQFP
CY8C21345-24SXI CY8C22345-24SXI CY8C22545-24AXI
512B
-40°C +85°C -40°C +85°C -40°C +85°C
Ordering Code Definitions
xxx-SPxx
Package Type: PDIP SOIC SSOP TQFP Speed: Part Number Family Code (21, Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress Semiconductor Thermal Rating: Commercial Industrial Extended
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Document History Page
Document Title: CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-ChipDocument Number: 001-43084 Revision 2251907 2506377 Orig. Change PMP/AESA EIJ/AESA Submission Date Data sheet Changed data sheet status "Preliminary". Changed part numbers CY8C22x45. Updated data sheet template. Added 56-Pin information. Added: "You must filters intended input channels anti-aliasing. This ensures that out-of-band content folded into Input Signal Band." Section Analog System page Corrected Minimum Electro Static Discharge Voltage Table page Updated Features page PSoC Core page Analog System page Changed DBC, Register Tables Table page Table page Removed reference Table page Changed IDD3 value Table page Typ:3.3 Added "3.0V 3.6V -40C 85C, guarantee accuracy only" Table page Updated data sheet template. Updated data sheet status "Final". Updated block diagram page Removed CY8C22045 56-Pin information. Added part numbers CY8C21345, CY8C22345, CY8C22545. more details, 31271. Confirmed CY8C22345 CY8C21345 have same pinout page Confirmed that accuracy Table page Updated Table SAR10 Specifications Table Programming Specifications. Title changed "CY8C21345, CY8C22345, CY8C22545 PSoC® Programmable System-on-ChipTM" Updated INL, information Table page Development Tools page TDSCLK parameter Table page Updated section Features page Added parameter "F32KU" added Min% parameter "FIMO6" Table page according updated SLIMO spec. Description Change
2558750
PMP/AESA
08/28/2008
2606793
NUQ/AESA
11/19/2008
2615697 2631733
PMP/AESA PMP/PYRS
12/03/2008 01/07/2009
2648800 2658078 2667311
JHU/AESA HMI/AESA JHU/AESA
01/28/2009 02/11/2009 03/16/2009
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