PSoC® Programmable System-on-Chip Powerful Harvard Architecture P

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PSoC® Programmable System-on-Chip Powerful Harvard Architecture P

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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor Processor Speeds power high speed 2.4V 5.25V Operating Voltage Operating Voltages Down 1.0V using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC® Blocks) Analog Type PSoC Blocks provide: Comparators with Refs Single Dual 8-Bit Channel Digital PSoC Blocks provide: 32-Bit Timers, Counters, PWMs Modules Full-Duplex UART, SPIMaster Slave Connectable GPIO Pins Complex Peripherals Combining Blocks Flexible On-Chip Memory Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Complete Development Tools Free Development Software (PSoC DesignerTM) Full-Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Precision, Programmable Clocking Internal ±2.5% 24/48 Oscillator Internal Oscillator Watchdog Sleep Programmable Configurations Sink, Drive GPIO Pull Pull Down, High Strong, Open Drain Drive Modes GPIO Analog Inputs GPIO Configurable Interrupt GPIO
Versatile Analog Common Internal Analog Simultaneous Connection Combinations Capacitive Sensing Application Capability Additional System Resources Master, Slave Multi-Master Watchdog Sleep Timers User-Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
Logic Block Diagram
Cypress Semiconductor Corporation Document Number: 38-12025 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2009
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PSoC Functional Overview
PSoC family consists many Mixed-Signal Array with On-Chip Controller devices. These devices designed replace multiple traditional MCU-based system components with cost single-chip programmable component. PSoC device includes configurable blocks analog digital logic, programmable interconnect. This architecture enables user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. PSoC architecture, shown Figure consists four main areas: Core, System Resources, Digital System, Analog System. Configurable global resources allow combining device resources into complete custom system. Each CY8C21x34 PSoC device includes four digital blocks four analog blocks. Depending PSoC package, general purpose (GPIO) also included. GPIO provide access global digital analog interconnects.
Digital System
Digital System consists digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Digital peripheral configurations include following.
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity master slave slave multi-master Cyclical Redundancy Checker/Generator bit) IrDA Pseudo Random Sequence Generators bit)
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (internal main oscillator) (internal speed oscillator). core, called M8C, powerful processor with speeds MHz. four MIPS 8-bit Harvard architecture microprocessor. System Resources provide following additional capabilities:
digital blocks connected GPIO through series global buses that route signal pin. buses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This allows optimum choice system resources your application. Family resources shown Table page Figure Digital System Block Diagram
Port Port Port Port
Digital clocks increase flexibility PSoC mixed-signal arrays. functionality implement master slave. internal voltage reference, MultiMaster, that provides absolute value 1.3V number PSoC subsystems. switch mode pump (SMP) that generates normal operating voltages single battery cell. Various system resets supported M8C.
Digital Clocks FromCore
System
ToAnalog System
DIGITAL SYSTEM
Digital PSoC Block Array
DBB00 DBB01 DCB02 DCB03
Analog System consists four analog PSoC blocks, supporting comparators analog-to-digital conversion bits precision.
Input Configuration
Digital System consists array digital PSoC blocks that configured into number digital peripherals. digital blocks connected GPIO through series global buses that route signal pin, freeing designs from constraints fixed peripheral controller.
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
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Analog System
Analog System consists configurable blocks that allow creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some common PSoC analog functions this device (most available user modules) are:
Analog Multiplexer System Analog connect every GPIO pin. Pins connected individually combination. also connects analog system analysis with comparators analog-to-digital converters. additional analog input multiplexer provides second path bring Port pins analog array. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
Analog-to-digital converters (single dual, with 8-bit 10-bit resolution) Pin-to-pin comparator Single-ended comparators with absolute (1.3V) reference 8-bit reference 1.3V reference System Resource)
Track pad, finger sensing. Chip-wide that allows analog input from pin. Crosspoint connection between combinations.
most PSoC devices, analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks. CY8C21x34 devices provide limited functionality Type analog blocks. Each column contains Type block Type block. Refer PSoC Programmable System-on-ChipTechnical Reference Manual detailed information CY8C21x34's Type analog blocks. Figure Analog System Block Diagram
When designing capacitive sensing applications, refer signal-to-noise system level requirement found Application Note AN2403 Cypress site http://www.cypress.com.
Additional System Resources
System Resources, some which listed previous sections, provide additional capability useful complete systems. Additional resources include switch mode pump, voltage detection, power reset. Brief statements describing merits each system resource follow.
Array Input Configuration
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal voltage reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter. Versatile analog multiplexer system.
ACI0[1:0]
ACI1[1:0]
ACOL1MUX Analog MuxBus
Array
ACE00 ASE10 ACE01 ASE11
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PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks analog blocks. Table lists resources available specific PSoC device groups. PSoC device covered this data sheet highlighted this table. Table PSoC Device Characteristics Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks SRAM Size Digital PSoC Part Number CY8C29x66 CY8C27x43 CY8C24x94 Flash Size
up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Bytes Bytes
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34
4[1] Bytes 4[1] Bytes
Cypros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
3[2] Bytes
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC® Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
Notes Limited analog functionality. analog blocks CapSense.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family.
Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional Integrated Development Environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug
property, other information need successfully implement your design.
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver
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Document Conventions
Acronyms Used
following table lists acronyms that used this document. Table Acronyms Used Acronym EEPROM GPIO IPOR PPOR PSoC® SLIMO SRAM Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current external crystal oscillator electrically erasable programmable read-only memory full scale range general purpose graphical user interface human body model in-circuit emulator internal speed oscillator internal main oscillator input/output imprecise power reset least-significant voltage detect most-significant program counter phase-locked loop power reset precision power reset Programmable System-on-Chippulse width modulator switched capacitor slow switch mode pump static random access memory
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
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Information
CY8C21x34 PSoC device available variety packages which listed following tables. Every port (labeled with "P") capable Digital connection common analog bus. However, Vss, Vdd, SMP, XRES capable Digital
16-Pin Part Pinout
Figure CY8C21234 16-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] M,I2C SCL,P1[1]
SOIC
P0[6], P0[4], P0[2], P0[0], P1[4], EXTCLK, P1[2],M P1[0], SDA,
Table Definitions CY8C21234 16-Pin (SOIC) Digital Power Power Power Power Type Analog Name P0[7] P0[5] P0[3] P0[1] P1[1] P1[0] P1[2] P1[4] P0[0] P0[2] P0[4] P0[6] Description Analog column input. Analog column input. Analog column input, integrating input. Analog column input, integrating input. Switch Mode Pump (SMP) connection required external components. Ground connection. Serial Clock (SCL), ISSP-SCLK[3]. Ground connection. Serial Data (SDA), ISSP-SDATA[3]. Optional External Clock Input (EXTCLK). Analog column input. Analog column input. Analog column input. Analog column input. Supply voltage.
LEGEND Analog, Input, Output, Analog Input.
Note These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details.
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20-Pin Part Pinout
Figure CY8C21334 20-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] M,I2C SCL,P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL,P1[1]
SSOP
P0[6], P0[4], P0[2], P0[0], XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA,
Table Definitions CY8C21334 20-Pin (SSOP) Type Digital Analog Power Power Input Power Name P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Description Analog column input. Analog column input. Analog column input, integrating input. Analog column input, integrating input. Ground connection. Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP-SCLK[3]. Ground connection. Serial Data (SDA), ISSP-SDATA[3]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Analog column input. Analog column input. Analog column input. Analog column input. Supply voltage.
LEGEND Analog, Input, Output, Analog Input.
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28-Pin Part Pinout
Figure CY8C21534 28-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] M,P2[7] M,P2[5] P2[3] P2[1] M,I2C SCL,P1[7] M,I2C SDA, P1[5] M,P1[3] M,I2C SCL,P1[1]
SSOP
P0[6], P0[4], P0[2], P0[0], P2[6],M P2[4],M P2[2],M P2[0],M XRES P1[6],M P1[4], EXTCLK,M P1[2],M P1[0],I2C SDA,
Table Definitions CY8C21534 28-Pin (SSOP) Type Digital Power Power Input Power Analog Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description Analog column input. Analog column input column output. Analog column input column output, integrating input. Analog column input, integrating input.
Direct switched capacitor block input. Direct switched capacitor block input. Ground connection. Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP-SCLK[3]. Ground connection. Serial Data (SDA), ISSP-SDATA[3]. Optional External Clock Input (EXTCLK). Active high external reset with internal pull down. Direct switched capacitor block input. Direct switched capacitor block input.
Analog column input. Analog column input. Analog column input Analog column input. Supply voltage.
LEGEND Analog, Input, Output, Analog Input.
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32-Pin Part Pinout
Figure CY8C21434 32-Pin PSoC Device Figure CY8C21634 32-Pin PSoC Device
Figure CY8C21434 32-Pin Sawn PSoC Device
P0[3], P0[5], P0[7], P0[6], P0[4], P0[2],
Figure CY8C21634 32-Pin Sawn PSoC Device
P0[3], P0[5], P0[7], P0[6], P0[4], P0[2], SDA, P1[5] P1[3] SCL, P1[1] SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6]
P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] SCL, P1[7]
(Top View)
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SDA, P1[5] P1[3] SCL, P1[1] SDA, P1[0] P1[2] EXTCLK, P1[4] P1[6]
P0[0], P2[6], P2[4], P2[2], P2[0], P3[2], P3[0], XRES
P0[1] P2[7] P2[5] P2[3] P2[1] SCL, P1[7]
(Top View)
P0[0], P2[6], P2[4], P2[2], P2[0], P3[2], P3[0], XRES
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Table Definitions CY8C21434/CY8C21634 32-Pin (QFN)[4] Digital Power Power Power Input Power Power Type Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] Description Analog column input, integrating input.
CY8C21434 part. Switch Mode Pump (SMP) connection required external components CY8C21634 part. CY8C21434 part. Ground connection CY8C21634 part. Serial Clock (SCL). Serial Data (SDA). Serial Clock (SCL), ISSP-SCLK[3]. Ground connection. Serial Data (SDA), ISSP-SDATA[3] Optional External Clock Input (EXTCLK). Active high external reset with internal pull down.
Analog column input. Analog column input. Analog column input. Analog column input. Supply voltage. Analog column input. Analog column input. Analog column input, integrating input. Ground connection.
LEGEND Analog, Input, Output, Analog Input.
Note center package must connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, must electrically floated connected other signal.
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56-Pin Part Pinout
56-pin SSOP part CY8C21001 On-Chip Debug (OCD) PSoC device. Note This part only used in-circuit debugging. available production. Figure CY8C21001 56-Pin PSoC Device
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] OCDE OCDO P3[3] P3[1] SCL, P1[7] SDA, P1[5] P1[3] SCLK, SCL, P1[1] P0[6], P0[4], P0[2], P0[0], P2[6] P2[4] P2[2] P2[0] P3[2] P3[0] CCLK HCLK XRES P1[6] P1[4], EXTCLK P1[2] P1[0], SDA, SDATA
SSOP
Table Definitions CY8C21001 56-Pin (SSOP) Type Digital Power Analog Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] OCDE OCDO Description Ground connection. Analog column input. Analog column input column output. Analog column input column output. Analog column input.
Power Power Power
Direct switched capacitor block input. Direct switched capacitor block input. connection. connection. connection. connection. even data data output. Switch Mode Pump (SMP) connection required external components. Ground connection. Ground connection.
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Table Definitions CY8C21001 56-Pin (SSOP) (continued) Type Digital Analog Name P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES HCLK CCLK P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description
Power
connection. connection. Serial Clock (SCL). Serial Data (SDA). connection. IFMTEST. Crystal Input (XTALin), Serial Clock (SCL), ISSP-SCLK[3]. Ground connection. connection. connection. Crystal Output (XTALout), Serial Data (SDA), ISSP-SDATA[3]. VFMTEST. Optional External Clock Input (EXTCLK). connection. connection. connection. connection. connection. connection. Active high external reset with internal pull down. high-speed clock output. clock output.
Input
connection. connection.
Power
Analog column input. Analog column input column output. Analog column input column output. Analog column input. Supply voltage.
LEGEND: Analog, Input, Output, On-Chip Debug.
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Register Reference
This chapter lists registers CY8C21x34 PSoC device. detailed register information, refer PSoC Programmable System-on-Chip Technical Reference Manual.
Register Conventions
register conventions specific this section listed Table Table Register Conventions Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields Reserved must accessed. Table Register Table: User Space
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
Blank fields Reserved must accessed.
PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 PRT2DR PRT2IE PRT2GS PRT2DM2 PRT3DR PRT3IE PRT3GS PRT3DM2
ASE11CR0 Access specific.
ASE10CR0
CUR_PP STK_PP IDX_PP MVR_PP MVW_PP I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 INT_CLR3 INT_MSK3
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Table Register Table: User Space (continued)
Access Access Access Access Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Addr (0,Hex) Name Name Name Name
DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0
AMX_IN AMUXCFG PWM_CR CMP_CR0 CMP_CR1 ADC0_CR ADC1_CR TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ACE00CR1 ACE00CR2 ACE01CR1 ACE01CR2 Blank fields Reserved must accessed.
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific.
INT_MSK0 INT_MSK1 INT_VC RES_WDT
DEC_CR0 DEC_CR1
CPU_F
DAC_D CPU_SCR1 CPU_SCR0
Table Register Table: Configuration Space
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
Blank fields Reserved must accessed.
PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 PRT2DM0 PRT2DM1 PRT2IC0 PRT2IC1 PRT3DM0 PRT3DM1 PRT3IC0 PRT3IC1
ASE11CR0 Access specific.
ASE10CR0
GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU
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Table Register Table: Configuration Space (continued)
Access Access Access Access Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Addr (1,Hex) Name Name Name Name
DBB00FN CLK_CR0 DBB00IN CLK_CR1 DBB00OU ABF_CR0 AMD_CR0 DBB01FN CMP_GO_EN DBB01IN DBB01OU AMD_CR1 ALT_CR0 DCB02FN DCB02IN DCB02OU CLK_CR3 DCB03FN TMP_DR0 DCB03IN TMP_DR1 DCB03OU TMP_DR2 TMP_DR3 ACE00CR1 ACE00CR2 ACE01CR1 ACE01CR2 Blank fields Reserved must accessed.
RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access specific.
MUX_CR0 MUX_CR1 MUX_CR2 MUX_CR3 OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR IMO_TR ILO_TR BDG_TR ECO_TR CPU_F FLS_PR1 DAC_CR CPU_SCR1 CPU_SCR0
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Electrical Specifications
This section presents electrical specifications CY8C21x34 PSoC device. date electrical specifications, visit site http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC specified, except where noted. Refer Table page electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure Voltage versus Frequency
5.25 5.25
Figure Frequency Trim Options
SLIMO Mode=1
4.75 Voltage 4.75 Voltage
SLIMO Mode
SLIMO Mode=0
ratin
3.60 3.00 2.40 Frequency
3.00 2.40
SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1
IMOFrequency
Table lists units measure that used this section. Table Units Measure Symbol Kbit Vrms Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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Absolute Maximum Ratings
Table Absolute Maximum Ratings Symbol Description TSTG Storage Temperature +100 Units Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrade reliability.
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch-up Current
-0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units Notes temperature rise from ambient junction package specific. Table page user must limit power consumption comply with this requirement.
Electrical Characteristics
Chip-Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Chip-Level Specifications Symbol Supply Voltage Supply Current, Description 2.40 5.25 Units Notes Table page Conditions 5.0V, 25oC, MHz, disabled. MHz, 93.75 kHz, 0.366 kHz. Conditions 3.3V, 25oC, MHz, clock doubler disabled. kHz, 23.4 kHz, 0.091 kHz. Conditions 2.55V, 25oC, MHz, clock doubler disabled. kHz, 23.4 kHz, 0.091 kHz.
IDD3
Supply Current, using SLIMO mode.
IDD27
Supply Current, using SLIMO mode.
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Table Chip-Level Specifications (continued) Symbol ISB27 VREF VREF27 AGND Description Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground Units Notes 2.55V, 40oC. 3.3V, -40oC 85oC. Trimmed appropriate Vdd. 3.0V 5.25V. Trimmed appropriate Vdd. 2.4V 3.0V.
1.28 1.16 VREF 0.003
1.30 1.30 VREF
1.32 1.33 VREF 0.003
General Purpose Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol Pull Resistor Pull down Resistor High Output Level Description Units 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). 5.25. 5.25. Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC. Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Table 2.7V GPIO Specifications Symbol Pull Resistor Pull down Resistor High Output Level Description Units (6.25 Typ), 3.0V maximum, combined budget). 3.0V maximum combined budget). 3.0. Notes
Output Level
0.75
Input Level
0.75
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Table 2.7V GPIO Specifications (continued) Symbol COUT Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output Description Units Gross tested Package dependent. Temp 25oC. Package dependent. Temp 25oC. Notes 3.0.
Operational Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Operational Amplifier Specifications Symbol VOSOA IEBOA[5] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25oC. Notes
TCVOSOA Average Input Offset Voltage Drift
Table 3.3V Operational Amplifier Specifications Symbol VOSOA IEBOA[5] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25oC. Notes
TCVOSOA Average Input Offset Voltage Drift
Note Atypical behavior: IEBOA Port below 25°C; over temperature. Port Pins lowest leakage
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Table 2.7V Operational Amplifier Specifications Symbol VOSOA IEBOA[5] CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25oC. Notes
TCVOSOA Average Input Offset Voltage Drift
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol Description VREFLPC power comparator (LPC) reference voltage range ISLPC supply current VOSLPC voltage offset Switch Mode Pump Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Switch Mode Pump (SMP) Specifications Symbol Description 4.75 5.25 Units Notes Configuration footnote.[6] Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.[6] Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.[6] Average, neglecting ripple. trip voltage 2.55V. Configuration footnote.[6] trip voltage 5.0V. trip voltage 3.25V. trip voltage 2.55V. Configuration footnote.[6] trip voltage 5.0V. Configuration footnote.[6] trip voltage 3.25V. Configuration footnote.[6] trip voltage 2.55V. Configuration footnote.[6] 100. 1.25V -40oC. Page VPUMP5V Output Voltage from Pump VPUMP3V 3.3V Output Voltage from Pump VPUMP2V 2.6V Output Voltage from Pump IPUMP Available Output Current VBAT 1.8V, VPUMP 5.0V VBAT 1.5V, VPUMP 3.25V VBAT 1.3V, VPUMP 2.55V Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery Start Pump Units Notes
3.00
3.25
3.60
2.45
2.55
2.80
VBAT5V VBAT3V VBAT2V VBATSTA
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Table Switch Mode Pump (SMP) Specifications (continued) Symbol
Line
Description
Units
Notes Configuration footnote.[6] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[6] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[6] Load Configuration footnote.[6] Load trip voltage 3.25V. load 1mA, VPUMP 2.55V, VBAT 1.3V, inductor, capacitor, Schottky diode.
VPUMP_ Line Regulation (over range)
VPUMP_ Load Regulation
Load
VPUMP_ Output Voltage Ripple (depends cap/load)
Ripple
mVpp
Efficiency
Efficiency
FPUMP DCPUMP
Switching Frequency Switching Duty Cycle
Figure Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Note inductor, capacitor, Schottky diode. Figure
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Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Analog Specifications Symbol RVDD Description Switch Resistance Common Analog Resistance Initialization Switch Units Notes 2.7V 2.4V 2.7V
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value PUMP Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.36 2.82 4.55 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.40 2.95 4.70 2.51[7] 2.99[8] 3.09 3.20 4.55 4.75 4.83 4.95 2.62[9] 3.09 3.16 3.32[10] 4.74 4.83 4.92 5.12 Units Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89
Notes
Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply. Always greater than above VLVD0. Always greater than above VLVD3.
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Programming Specifications Symbol Description VddIWRITE Supply Voltage Flash Write Operations IDDP Supply Current During Programming Verify VILP Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[11] FlashDR Flash Data Retention 2.70 50,000 1,800, 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles). full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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Electrical Characteristics
Chip-Level Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency 23.4 24.6[12,13,14] Units Notes Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode only SLIMO mode Refer Digital Block Specifications.
FIMO6
Internal Main Oscillator Frequency
5.75
6.35[12,13,14]
FCPU1 FCPU2 FBLK5 FBLK33 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency0(5V Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Period Jitter Peak-to-Peak Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Peak-to-Peak Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time
0.93 0.93 46.8
1400 48.0
24.6[12,13] 12.3[13,14] 49.2[12,13,15] 24.6[13,15] 49.2[12,14]
Trimmed. Using factory trim values.
12.3
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
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Table 2.7V Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency 11.5 12.7[16,17,18] Units Notes Trimmed 2.7V operation using factory trim values. Figure page SLIMO mode Trimmed 2.7V operation using factory trim values. Figure page SLIMO mode only SLIMO mode Refer Digital Block Specifications.
FIMO6
Internal Main Oscillator Frequency
5.75
6.35[16,17,18]
FCPU1 FBLK27 F32K1 Jitter32k Jitter32k TXRST FMAX TRAMP
Frequency (2.7V Nominal) Digital PSoC Block Frequency (2.7V Nominal) Internal Speed Oscillator Frequency Period Jitter Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency signal input output. Supply Ramp Time
0.093
1400
3.15[16,17] 12.5[16,17,18] 12.3
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ILO) Timing Diagram
Jitter32k
32K1
Notes 2.4V 3.0V. Accuracy derived from Internal Main Oscillator with appropriate trim range. Application Note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information maximum frequency user modules.
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General Purpose Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Table 2.7V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 3.0V, 3.0V, 3.0V, 3.0V,
Figure GPIO Timing Diagram
GPIO Output Voltage
TRiseF TRiseS
TFallF TFallS
Operational Amplifier Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Operational Amplifier Specifications Symbol TCOMP Description Comparator Mode Response Time, Overdrive Units Notes 3.0V. 2.4V 3.0V.
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC. Page
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Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Analog Specifications Symbol Description Switch Rate 3.17 Units Notes
Digital Block Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V Digital Block Specifications Function Functions Timer Description Maximum Block Clocking Frequency 4.75V) Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Without Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 49.2 49.2 4.75V 5.25V. 4.75V 5.25V. 50[19] 49.2 24.6 49.2 24.6 49.2 24.6 Units 4.75V 5.25V. 4.75V 5.25V. Notes 4.75V 5.25V. 3.0V 4.75V.
Maximum Input Clock Frequency
24.6
Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions
24.6 49.2 24.6 49.2
Maximum data rate over clocking.
Transmitter Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency with 4.75V, Stop Bits
Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking. Maximum data rate 3.08 over clocking. Maximum data rate 6.15 over clocking.
Note minimum input pulse width based input synchronizers running nominal period).
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Table 2.7V Digital Block Specifications Function Functions Timer Counter Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, With Without Capture Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency 12.7 12.7 100[20] 12.7 12.7 12.7 12.7 Units Notes 2.4V 3.0V.
Maximum Input Clock Frequency
12.7
Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions
6.35 12.7 12.7
Maximum data rate 3.17 over clocking.
Transmitter Maximum Input Clock Frequency Receiver Maximum Input Clock Frequency
Maximum data rate 1.59 over clocking. Maximum data rate 1.59 over clocking.
External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Units
Note minimum input pulse width based input synchronizers running nominal period).
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Table 3.3V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.093 12.3 Units Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.186
24.6
High Period with Clock divide Period with Clock divide Power Switch
41.7 41.7
5300
Table 2.7V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.093 3.080 Units Notes Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.186
6.35
High Period with Clock divide Period with Clock divide Power Switch
5300
Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Units Notes
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Table Programming Specifications (continued) Symbol TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units Notes
Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Set-up Time Repeated START Condition Data Hold Time Data Set-up Time Set-up Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter. Standard Mode Fast Mode Units
100[21]
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Table 2.7V Characteristics Pins (Fast Mode Supported) Symbol FSCLI2C THDSTAI2C TLOWI2C THIGHI2C TSUSTAI2C THDDATI2C TSUDATI2C TSUSTOI2C TBUFI2C TSPI2C Description Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock HIGH Period Clock Time Repeated START Condition Data Hold Time Data Set-up Time Time STOP Condition Free Time Between STOP START Condition Pulse Width spikes suppressed input filter. Standard Mode Fast Mode Units
Figure Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
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Packaging Information
This section shows packaging specifications CY8C21x34 PSoC device with thermal impedances each package. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 16-Pin (150-Mil) SOIC
DIMENSIONS INCHES[MM] MIN. REFERENCE JEDEC MS-012
0.150[3.810] 0.157[3.987] 0.230[5.842] 0.244[6.197]
MAX.
PACKAGE WEIGHT 0.15gms
PART S16.15 STANDARD PKG. SZ16.15 LEAD FREE PKG.
0.386[9.804] 0.393[9.982] 0.061[1.549] 0.068[1.727] 0.050[1.270]
SEATING PLANE
0.010[0.254] 0.016[0.406]
0.004[0.102] 0.0138[0.350] 0.0192[0.487]
0.004[0.102] 0.0098[0.249]
0°~8°
0.016[0.406] 0.035[0.889]
0.0075[0.190] 0.0098[0.249]
51-85068
Figure 20-Pin (210-MIL) SSOP
51-85077
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Figure 28-Pin (210-Mil) SSOP
51-85079
Figure 32-Pin (5x5 0.93 MAX)
E-PAD this product 3.53 3.53 (+/-0.11
51-85188
Document Number: 38-12025 Rev.
Page
Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Figure 32-Pin (5x5 0.60 MAX)
E-PAD this product 3.53 3.53 (+/-0.11
001-06392
Figure 32-Pin 0.4MM) (SAWN 1.85 2.85 EPAD
001-44368
Document Number: 38-12025 Rev.
Page
Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Figure 32-Pin Sawn Package
001-30999
Figure 32-Pin Thin Sawn Package
001-42168
Important Note information preferred dimensions mounting packages, following Application Note
Document Number: 38-12025 Rev.
Page
Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Figure 56-Pin (300-Mil) SSOP
51-85062
Thermal Impedances
Table Thermal Impedances Package Package SOIC SSOP SSOP QFN[23] 0.60 QFN[23] 0.93 Typical [22] oC/W oC/W oC/W oC/W oC/W Typical oC/W oC/W oC/W oC/W oC/W
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SOIC SSOP SSOP Minimum Peak Temperature[24] 240oC 240oC 240oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC
Notes Power achieve thermal impedance specified package, center thermal must soldered ground plane Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Development Tool Selection
This section presents development tools available current PSoC device families including CY8C21x34 family.
240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
Software
PSoC DesignerAt core PSoC development software suite PSoC Designer. Used thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under DESIGN RESOURCES Software Drivers. PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operates directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free ofcharge Compilers PSoC Designer comes with free HI-TECH Lite compiler. HI-TECH Lite compiler free, supports PSoC devices, integrates fully with PSoC Designer PSoC Express, runs Windows versions 32-bit Vista. Compilers with additional features available additional cost from their manufactures.
CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
HI-TECH PSoC available from http://www.htsoft.com. ImageCraft Cypress Edition Compiler available from http://www.imagecraft.com.
Evaluation Tools
evaluation tools purchased from Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices through MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects through provided cable. includes:
Development Kits
development kits purchased from Cypress Online Store. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Device Programmers
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note CY3207ISSP needs special software compatible with PSoC Programmer. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part CY8C21234-24S CY8C21334-24PVXI CY8C21434-24LFXI CY8C21534-24PVXI CY8C21634-24LFXI Package SOIC SSOP SSOP Flex-Pod Kit[25] CY3250-21X34 CY3250-21X34 CY3250-21X34QFN CY3250-21X34 CY3250-21X34QFN Foot Kit[26] CY3250-16SOIC-FK CY3250-20SSOP-FK CY3250-32QFN-FK CY3250-28SSOP-FK CY3250-32QFN-FK Adapter Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
Third-Party Tools
Several tools have been specially designed following 3rd-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, Application Note AN2323 "Debugging Build PSoC Emulator into Your Board".
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB.
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Ordering Information
Switch Mode Pump Temperature Range XRES
Feedback
Digital Pins
Ordering Code
Package
(150-Mil) SOIC (150-Mil) SOIC (Tape Reel) (210-Mil) SSOP (210-Mil) SSOP (Tape Reel) (210-Mil) SSOP (210-Mil) SSOP (Tape Reel) (5x5 0.93 MAX) [27] (5x5 0.93 MAX) (Tape Reel) (5x5 0.60 MAX)
[28]
CY8C21234-24SXI CY8C21234-24SXIT CY8C21334-24PVXI CY8C21334-24PVXIT CY8C21534-24PVXI CY8C21534-24PVXIT CY8C21434-24LFXI CY8C21434-24LFXIT CY8C21434-24LKXI CY8C21434-24LKXIT CY8C21634-24LFXI CY8C21634-24LFXIT CY8C21434-24LTXI CY8C21434-24LTXIT CY8C21434-24LCXI CY8C21434-24LCXIT CY8C21434-24LQXI CY8C21434-24LQXIT CY8C21634-24LTXI CY8C21634-24LTXIT CY8C21001-24PVXI
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°Cto +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
12[27] 12[27] 16[27] 16[27] 24[27]
[27]
28[27] 28[27] 28[27] 28[27] 26[27] 26[27] 28[27] 28[27] 28[27] 28[27] 26[27] 26[27] 26[27]
(5x5 0.60 MAX) [28] (Tape Reel) (5x5 0.93 MAX)
[28]
(5x5 0.93 MAX) [28] (Tape Reel) (5x5 1.00 MAX) SAWN (5x5 1.00 MAX) SAWN [28] (Tape Reel) (5x5 0.40 MAX) SAWN QFN[28] (5x5 0.40 MAX) SAWN QFN[28] (Tape Reel) (5x5 0.60 MAX) THIN SAWN (5x5 0.60 MAX) THIN SAWN (Tape Reel) (5x5 0.93 MAX) SAWN [28] (5x5 0.93 MAX) SAWN [28] (Tape Reel) SSOP
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Notes Digital Pins also connect common analog mux. Refer section 32-Pin Part Pinout page differences.
Document Number: 38-12025 Rev.
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Analog Outputs
Analog Inputsa
Flash (Bytes)
SRAM (Bytes)
Analog Blocks
Digital Blocks
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Ordering Code Definitions
xxx-24xx
Package Type: Thermal Rating: PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended LFX/LKX Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
Document Number: 38-12025 Rev.
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Feedback
CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Document History Page
Document Title: PSoC® Programmable System-on-ChipDocument Number: 38-12025 Revision 227340 235992 Orig. Change Submission Date Description Change silicon document (Revision **). Updated Overview Electrical Spec. chapters, along with revisions 24-pin pinout part. Revised register mapping tables. Added SSOP 28-pin part. Changed title include part Changed 28-pin SSOP from CY8C21434 CY8C21534. Changed 28-pin SSOP from pin. Added block architecture diagram. Update Electrical Specifications. Added another 32-pin part: CY8C21634. Verify data sheet standards from memo. Analog Input applicable outs. Update PSoC Characteristics table. Update diagrams specs. Final. Update 2.7V GPIO spec. Reflow Peak Temp. table. Chip-Level Specification changes. Update links CY.com Portal. Re-add pinout ISSP notation. register names. Clarify feature. Update Electrical Specifications. Update Reflow Peak Temp. table. E-PAD dimensions. ThetaJC Thermal Impedance table. 20-pin package order number. logo. Update copyright. color logo. preferred dimensions mounting packages. Update Transmitter Receiver Digital Block Electrical Specifications. Clarify thermal connection info. Replace 16-pin 300-MIL SOIC with correct 150-MIL. Update 32-pin E-Pad dimensions rev. Update branding convention. 32-pin 0.60 thickness package diagram, CY8C21434-24LKXI. Update thermal resistance data. 56-pin SSOP on-chip debug non-production part, CY8C21001-24PVXI. Update typical recommended Storage Temperature industrial specs. Update copyright trademarks. CapSense requirement reference. Dev. Tool section. CY8C20x34 PSoC Device Characteristics table. Power Comparator (LPC) AC/DC electrical spec. tables. Update rev. 32-Lead (5x5 0.60 MAX) package diagram. Added 32-Pin Sawn diagram, package diagram, ordering information. Added thin sawn package diagram. Added Note Ordering Information section. Changed title from PSoC Mixed-Signal Array PSoC Programmable System-on-Chip Updated 32-Pin Sawn package dimension CY8C21434-24LTXIT Updated Getting Started, Development Tools, Designing with PSoC Designer Sections
248572
277832
285293 301739 329104
352736
390152 413404 430185
677717
2147847 2273246 2618124
UVS/PYRS UVS/AESA
02/27/08 04/01/08
OGNE/PYRS 12/09/08
2684145
SNV/AESA
04/06/2009
Document Number: 38-12025 Rev.
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CY8C21634, CY8C21534 CY8C21434, CY8C21334, CY8C21234
Sales, Solutions, Legal Information
Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Power/Low Voltage Precision Analog Drive 2.0b psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
Cypress Semiconductor Corporation, 2004-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 38-12025 Rev.
Revised April 2009
Page
PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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PSoC® Programmable System-on-Chip Powerful Harvard Architecture P

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