PSoC® Programmable System-on-Chip Powerful Harvard Architecture P

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PSoC® Programmable System-on-Chip Powerful Harvard Architecture P

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CY8C21123, CY8C21223, CY8C21323
PSoC® Programmable System-on-Chip
Powerful Harvard Architecture Processor: Processor Speeds Power High Speed 2.4V 5.25V Operating Voltage Operating Voltages down 1.0V using On-Chip Switch Mode Pump (SMP) Industrial Temperature Range: -40°C +85°C Advanced Peripherals (PSoC® Blocks): Four Analog Type PSoC Blocks Provide: Comparators with Refs Single Dual 8-Bit Four Digital PSoC Blocks Provide: 32-Bit Timers, Counters, PWMs Modules Full Duplex UART, SPIMaster Slave: Connectable GPIO Pins Complex Peripherals Combining Blocks Flexible On-Chip Memory: Flash Program Storage 50,000 Erase/Write Cycles Bytes SRAM Data Storage In-System Serial Programming (ISSP) Partial Flash Updates Flexible Protection Modes EEPROM Emulation Flash Complete Development Tools: Free Development Software (PSoC Designer Full Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure Bytes Trace Memory Precision, Programmable Clocking: Internal ±2.5% 24/48 Oscillator Internal Oscillator Watchdog Sleep Programmable Configurations: Sink, Drive GPIO Pull Pull Down, High Strong, Open Drain Drive Modes GPIO Eight Analog Inputs GPIO Configurable Interrupt GPIO
Additional System Resources: CMaster, Slave MultiMaster Watchdog Sleep Timers User Configurable Voltage Detection Integrated Supervisory Circuit On-Chip Precision Voltage Reference
Logic Block Diagram
Port Port
PSoC CORE
SystemBus
Global Digital Interconnect
Global Analog Interconnect Flash Sleep Watchdog
SRAM Interrupt Controller
SROM
Core (M8C)
Clock Sources (Includes ILO)
DIGITAL SYSTEM
Digital PSoC Block Array
ANALOG SYSTEM
Analog PSoC Block Array
Analog Ref.
Digital Clocks
System Resets
itch Mode Pump
Internal Voltage Ref.
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 38-12022 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2009
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PSoC Functional Overview
PSoC family consists many programmable system-on-chip controller devices. These devices designed replace multiple traditional MCU-based system components with cost single-chip programmable component. PSoC device includes configurable blocks analog digital logic, programmable interconnect. This architecture allows user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. PSoC architecture, shown Figure consists four main areas: Core, System Resources, Digital System, Analog System. Configurable global resources allow combining device resources into complete custom system. Each PSoC device includes four digital blocks. Depending PSoC package, analog comparators General Purpose (GPIO) also included. GPIO provide access global digital analog interconnects.
Digital System
Digital System consists four digital PSoC blocks. Each block 8-bit resource that used alone combined with other blocks form 32-bit peripherals, which called user module references. Digital peripheral configurations include:
PWMs bit) PWMs with Dead band bit) Counters bit) Timers bit) UART with selectable parity four) master slave slave, master, MultiMaster (one available System Resource) Cyclical Redundancy Checker/Generator bit) IrDA four) Pseudo Random Sequence Generators bit)
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (internal main oscillator) (internal speed oscillator). core, called M8C, powerful processor with speeds MHz. four MIPS 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such digital clocks increase flexibility PSoC Programmable System-on-Chips, functionality implementing master, slave, MultiMaster, internal voltage reference that provides absolute value 1.3V number PSoC subsystems, switch mode pump (SMP) that generates normal operating voltages single battery cell, various system resets supported M8C. Digital System consists array digital PSoC blocks, which configured into number digital peripherals. digital blocks connected GPIO through series global that route signal pin. This frees designs from constraints fixed peripheral controller. Analog System consists four analog PSoC blocks, supporting comparators analog-to-digital conversion bits precision.
digital blocks connected GPIO through series global that route signal pin. busses also allow signal multiplexing performing logic operations. This configurability frees your designs from constraints fixed peripheral controller. Digital blocks provided rows four, where number blocks varies PSoC device family. This provides optimum choice system resources your application. Family resources shown Table page Figure Digital System Block Diagram
Port Port
DigitalClocks FromCore
System
Analog System
DIGITAL SYSTEM
Digital PSoC Block Array
Input Configuration
DBB00 DBB01 DCB02
DCB03
Output Configuration
GIE[7:0] GIO[7:0]
Global Digital Interconnect
GOE[7:0] GOO[7:0]
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Analog System
Analog System consists four configurable blocks allow creation complex analog signal flows. Analog peripherals very flexible customized support specific application requirements. Some more common PSoC analog functions (most available user modules) are:
Additional System Resources
System Resources, some which listed previous sections, provide additional capability useful complete systems. Additional resources include switch mode pump, voltage detection, power reset. merits each system resource are.
Analog-to-digital converters (single dual, with 8-bit 10-bit resolution) Pin-to-pin comparators (one) Single-ended comparators with absolute (1.3V) reference 8-bit reference 1.3V reference System Resource)
Digital clock dividers provide three customizable clock frequencies applications. clocks routed both digital analog systems. Additional clocks generated using digital PSoC blocks clock dividers. module provides communication over wires. Slave, master, multi-master modes supported. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal voltage reference provides absolute reference analog system, including ADCs DACs. integrated switch mode pump (SMP) generates normal operating voltages from single 1.2V battery cell, providing cost boost converter.
most PSoC devices, analog blocks provided columns three, which includes (Continuous Time) (Switched Capacitor) blocks. CY8C21x23 devices provide limited functionality Type analog blocks. Each column contains block block. number blocks device family listed Table Figure CY8C21x23 Analog System Block Diagram
Array Input Configuration
PSoC Device Characteristics
Depending your PSoC device characteristics, digital analog systems have digital blocks, analog blocks. Table lists resources available specific PSoC device groups. PSoC device covered this data sheet highlighted. Table PSoC Device Characteristics
ACI0[1:0]
ACI1[1:0]
Digital Rows Digital Blocks Analog Inputs Analog Outputs Analog Columns Analog Blocks
Digital
SRAM Size Bytes Bytes
PSoC Part Number
ACOL1MUX
CY8C29x66 CY8C27x43
Array
ACE00 ASE10
ACE01 ASE11
CY8C24x94
CY8C24x23A CY8C21x34 CY8C21x23 CY8C20x34
4[1] Bytes 4[1] Bytes 3[2] Bytes
Notes Limited analog functionality analog blocks CapSense
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Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming details, PSoC® Programmable System-on-ChipTechnical Reference Manual CY8C28xxx PSoC devices. date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built support third party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Programmable System-on-Chip Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
Application Notes
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
CYPros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
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Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user selectable functions. PSoC development process summarized following four steps: Select Components Configure Components Organize Connect Generate, Verify, Debug
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, programmable system-on-chip varieties.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Document Conventions
Acronyms Used
This table lists acronyms used this data sheet. Table Acronyms Acronym EEPROM GPIO ISSP IPOR PPOR PSoC SRAM
Description alternating current analog-to-digital converter application programming interface central processing unit continuous time digital-to-analog converter direct current electrically erasable programmable read-only memory full scale range general purpose in-circuit emulator integrated development environment input/output in-system serial programming imprecise power reset least-significant voltage detect most-significant program counter programmable gain amplifier power reset precision power reset Programmable System-on-Chippulse width modulator read only memory switched capacitor switch mode pump static random access memory
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Units Measure
units measure table located section Electrical Specifications page Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal. Document Number: 38-12022 Rev. Page
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Information
This section describes, lists, illustrates CY8C21x23 PSoC device pins pinout configurations. Every port (labeled with "P") capable Digital However, Vss, Vdd, SMP, XRES capable Digital
8-Pin Part Pinout
Table Definitions CY8C21123 8-Pin SOIC Power Type Digital Power Analog Name P0[5] P0[3] P1[1] P1[0] P0[2] P0[4] Description Analog Column Input Analog Column Input Serial Clock (SCL), ISSP-SCLK[3] Ground Connection Serial Data (SDA), ISSP-SDATA[3] Analog Column Input Analog Column Input Supply Voltage Figure CY8C21123 8-Pin SOIC
P0[5] P0[3] SCL, P1[1] SOIC6 P0[4], P0[2], P1[0], I2CSDA
LEGEND: Analog, Input, Output.
16-Pin Part Pinout
Table Definitions CY8C21223 16-Pin SOIC Power Power Type Digital Power Power Analog Name P0[7] P0[5] P0[3] P0[1] P1[1] P1[0] P1[2] P1[4] P0[0] P0[2] P0[4] P0[6] Optional External Clock Input (EXTCLK) Analog Column Input Analog Column Input Analog Column Input Analog Column Input Supply Voltage Description Analog Column Input Analog Column Input Analog Column Input Analog Column Input Switch Mode Pump (SMP) Connection required External Components Ground Connection Serial Clock (SCL), ISSP-SCLK[3] Ground Connection Serial Data (SDA), ISSP-SDATA[3] Figure CY8C21223 16-Pin SOIC
P0[7] P0[5] P0[3] P0[1] I2CSCL, P1[1]
SOIC
P0[6], P0[4], P0[2], P0[0], P1[4],EXTCLK P1[2] P1[0], I2CSDA
LEGEND Analog, Input, Output.
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Table Definitions CY8C21223 16-Pin
P0[5], P0[7], SCL, P1[1] SDA, P1[0] P1[3] P0[3] P0[1] SCL, P1[7] SDA, P1[5] (Top View) P0[4], VREF XRES P1[4] P1[6]
Type Digital Power Input Power Analog
Name P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[6] P1[4] XRES P0[4] P0[7] P0[5] EXTCLK
Description Analog Column Input Analog Column Input Serial Clock (SCL) Serial Data (SDA) Serial Clock (SCL), ISSP-SCLK[3] Ground Connection Serial Data (SDA), ISSP-SDATA[3]
Figure CY8C21223 16-Pin
Active High External Reset with Internal Pull Down VREF Supply Voltage Analog Column Input Analog Column Input Connect
LEGEND Analog, Input, Output.
Notes These ISSP pins, which High (Power Reset). PSoC Programmable System-on-Chip Technical Reference Manual details. center package must connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, must electrically floated connected other signal.
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20-Pin Part Pinout
Table Definitions CY8C21323 20-Pin SSOP Type Digital Analog Power Power Input Power Name P0[7] P0[5] P0[3] P0[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] Description Analog Column Input Analog Column Input Analog Column Input Analog Column Input Ground Connection Serial Clock (SCL) Serial Data (SDA) Serial Clock (SCL), ISSP-SCLK[3] Ground connection Serial Data (SDA), ISSP-SDATA[3] Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down Analog Column Input Analog Column Input Analog Column Input Analog Column Input Supply Voltage Figure CY8C21323 20-Pin SSOP
P0[7] P0[5] P0[3] P0[1] SCL, P1[7] SDA, P1[5] P1[3] SCL, P1[1]
SSOP
P0[6], P0[4], P0[2], P0[0], XRES P1[6] P1[4],EXTCLK P1[2] P1[0],I2C
LEGEND Analog, Input, Output.
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24-Pin Part Pinout
Table Definitions CY8C21323 24-Pin QFN[5] Type Digital Analog Name P0[1] Power Power Power Input P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] Description Analog Column Input Switch Mode Pump (SMP) Connection required External Components Ground connection Serial Clock (SCL) Serial Data (SDA) Serial Clock (SCL), ISSP-SCLK[3] Connection Ground Connection Serial Data (SDA), ISSP-SDATA[3] Optional External Clock Input (EXTCLK) Active High External Reset with Internal Pull Down Connection Analog Column Input Analog Column Input Analog Column Input Analog Column Input Supply Voltage Ground Connection Analog Column Input Analog Column Input Analog Column Input Figure CY8C21323 24-Pin
P0[3], P0[5], P0[7], P0[6],
SCL, P1[1]
Power Power
LEGEND Analog, Input, Output.
Note center package must connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, must electrically floated connected other signal.
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SDA, P1[0]
P1[2] EXTCLK, P1[4]
P0[1] SCL, P1[7] SDA, P1[5] P1[3]
(Top View)
P0[4], P0[2], P0[0], XRES P1[6]
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Register Reference
This section lists registers CY8C21x23 PSoC device. detailed register information, refer PSoC Programmable System-on-Chip Technical Reference Manual.
Register Mapping Tables
PSoC device total register address space bytes. register space referred space divided into banks. Flag register (CPU_F) determines which bank user currently When user Bank Note following register mapping tables, blank fields Reserved must accessed.
Register Conventions
register conventions specific this section listed following table. Table Register Conventions Convention Description Read register bit(s) Write register bit(s) Logical register bit(s) Clearable register bit(s) Access specific
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Table Register Bank Table: User Space
Name PRT0DR PRT0IE PRT0GS PRT0DM2 PRT1DR PRT1IE PRT1GS PRT1DM2 Addr (0,Hex) DBB00DR0 DBB00DR1 DBB00DR2 DBB00CR0 DBB01DR0 DBB01DR1 DBB01DR2 DBB01CR0 DCB02DR0 DCB02DR1 DCB02DR2 DCB02CR0 DCB03DR0 DCB03DR1 DCB03DR2 DCB03CR0 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 ADC0_CR ADC1_CR CMP_CR1 CMP_CR0 PWM_CR AMX_IN Access Name Addr (0,Hex) ASE11CR0 Access Name ASE10CR0 Addr (0,Hex) Access specific. DEC_CR0 DEC_CR1 INT_MSK0 INT_MSK1 INT_VC RES_WDT INT_CLR3 INT_MSK3 I2C_CFG I2C_SCR I2C_DR I2C_MSCR INT_CLR0 INT_CLR1 Access Name Addr (0,Hex) Access
Blank fields Reserved must accessed.
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Table Register Bank Table: User Space (continued)
Name Addr (0,Hex) Blank fields Reserved must accessed. ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 Access Name Addr (0,Hex) Access Name RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Addr (0,Hex) Access specific. CPU_SCR1 CPU_SCR0 Access CPU_F Name Addr (0,Hex) Access
Table Register Bank Table: Configuration Space
Name PRT0DM0 PRT0DM1 PRT0IC0 PRT0IC1 PRT1DM0 PRT1DM1 PRT1IC0 PRT1IC1 Addr (1,Hex) Blank fields Reserved must accessed. Access Name Addr (1,Hex) ASE11CR0 Access Name ASE10CR0 Addr (1,Hex) Access specific. GDI_O_IN GDI_E_IN GDI_O_OU GDI_E_OU Access Name Addr (1,Hex) Access
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Table Register Bank Table: Configuration Space (continued)
Name Addr (1,Hex) DBB00FN DBB00IN DBB00OU DBB01FN DBB01IN DBB01OU DCB02FN DCB02IN DCB02OU DCB03FN DCB03IN DCB03OU Blank fields Reserved must accessed. ACE01CR1 ACE01CR2 ACE00CR1 ACE00CR2 CLK_CR3 TMP_DR0 TMP_DR1 TMP_DR2 TMP_DR3 AMD_CR1 ALT_CR0 CLK_CR0 CLK_CR1 ABF_CR0 AMD_CR0 CMP_GO_EN Access Name Addr (1,Hex) RDI0RI RDI0SYN RDI0IS RDI0LT0 RDI0LT1 RDI0RO0 RDI0RO1 Access Name Addr (1,Hex) Access specific. CPU_SCR1 CPU_SCR0 FLS_PR1 CPU_F IMO_TR ILO_TR BDG_TR ECO_TR OSC_GO_EN OSC_CR4 OSC_CR3 OSC_CR0 OSC_CR1 OSC_CR2 VLT_CR VLT_CMP ADC0_TR ADC1_TR Access Name Addr (1,Hex) Access
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Electrical Specifications
This section presents electrical specifications CY8C21x23 PSoC device. date electrical specifications, check have latest data sheet visiting http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC, except where noted. Refer Table page electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure Voltage versus Frequency
5.25 5.25
Figure Voltage versus Frequency
SLIMO Mode=1
4.75 Voltage 4.75 Voltage
SLIMO Mode
SLIMO Mode=0
rati
3.60
3.00 2.40 Frequency
3.00
2.40
SLIMO SLIMO Mode=1 Mode=0 SLIMO SLIMO Mode=1 Mode=1
Frequency
following table lists units measure that used this section. Table Units Measure Symbol Kbit Vrms
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square
Symbol
Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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Absolute Maximum Ratings
Exceeding maximum ratings shorten useful life device. User guidelines tested. Table Absolute Maximum Ratings Symbol Description TSTG Storage Temperature Units Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C. Extended duration storage temperatures above 65°C degrade reliability. +6.0 Human Body Model +100
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tristate Maximum Current into Port Electro Static Discharge Voltage Latch Current
-0.5 2000
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units Notes temperature rise from ambient junction package specific. SeeTable page user must limit power consumption comply with this requirement.
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Electrical Characteristics
Chip-Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Chip-Level Specifications Symbol Description Supply Voltage Supply Current, 2.40 5.25 Units Notes specifications, Table page Conditions 5.0V, 25oC, MHz, SYSCLK doubler disabled. 93.75 0.366 kHz. Conditions 3.3V, 25oC, MHz, clock doubler disabled. 23.4 0.091 Conditions 2.55V, 25oC, MHz, clock doubler disabled. 23.4 0.091 2.55V, 40°C 3.3V, -40°C 85°C
IDD3
Supply Current,
IDD27
Supply Current,
ISB27
VREF VREF27 AGND
Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. temperature range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, internal slow oscillator active. Reference Voltage (Bandgap) Reference Voltage (Bandgap) Analog Ground
1.28 1.16 VREF 0.003
1.30 1.30 VREF
1.32 1.330 VREF+ 0.003
Trimmed appropriate Vdd. 3.0V 5.25V Trimmed appropriate Vdd. 2.4V 3.0V
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General Purpose Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol Pull Resistor Pull down Resistor High Output Level Description Units 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 4.75 5.25V total loads, even port pins (for example, P0[2], P1[4]), port pins (for example, P0[3], P1[5])). maximum combined budget. 5.25 5.25 Gross tested Package dependent. Temp 25°C Package dependent. Temp 25°C Notes
Output Level
0.75
COUT
Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Table lists guaranteed maximum minimum specifications voltage temperature ranges: 2.4V 3.0V -40°C 85°C. Typical parameters apply 2.7V 25°C design guidance only. Table 2.7V GPIO Specifications Symbol Description Pull Resistor Pull down Resistor High Output Level Units Notes (6.25 Typ), 3.0V maximum, combined budget). 3.0V maximum combined budget). Gross tested Package dependent. Temp 25°C Package dependent. Temp 25°C
COUT
Output Level Input Level Input High Level Input Hysteresis Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
0.75 0.75
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Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Amplifier Specifications Symbol VOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25°C Notes
TCVOSOA Average Input Offset Voltage Drift
Table 3.3V Amplifier Specifications Symbol VOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25°C Notes
TCVOSOA Average Input Offset Voltage Drift
Table 2.7V Amplifier Specifications Symbol VOSOA IEBOA CINOA VCMOA GOLOA ISOA Description Input Offset Voltage (absolute value) Input Leakage Current (Port Analog Pins) Input Capacitance (Port Analog Pins) Common Mode Voltage Range Open Loop Gain Amplifier Supply Current Units V/oC Gross tested Package dependent. Temp 25°C Notes
TCVOSOA Average Input Offset Voltage Drift
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Switch Mode Pump Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Switch Mode Pump (SMP) Specifications Symbol VPUMP5V Description Output Voltage from Pump 4.75 5.25 Units Notes Configuration footnote.[6] Average, neglecting ripple. trip voltage 5.0V. Configuration footnote.[6] Average, neglecting ripple. trip voltage 3.25V. Configuration footnote.[6] Average, neglecting ripple. trip voltage 2.55V. Configuration footnote.[6] trip voltage 5.0V. trip voltage 3.25V. trip voltage 2.55V. Configuration footnote.[6] trip voltage 5.0V. Configuration footnote.[6] trip voltage 3.25V. Configuration footnote.[6] trip voltage 2.55V. Configuration footnote.[6] 100. 1.25V -40oC.
VPUMP3V
3.3V Output Voltage from Pump
3.00
3.25
3.60
VPUMP2V
2.6V Output Voltage from Pump
2.45
2.55
2.80
IPUMP
Available Output Current VBAT 1.8V, VPUMP 5.0V VBAT 1.5V, VPUMP 3.25V VBAT 1.3V, VPUMP 2.55V Input Voltage Range from Battery Input Voltage Range from Battery Input Voltage Range from Battery Minimum Input Voltage from Battery Start Pump Line Regulation (over range)
VBAT5V VBAT3V VBAT2V VBATSTART VPUMP_Line
Configuration footnote.[6] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page Configuration footnote.[6] "Vdd Value PUMP Trip" specified VM[2:0] setting Specification, Table page mVpp Configuration footnote.[6] Load Configuration footnote.[6] Load trip voltage 3.25V. load 1mA, VPUMP 2.55V, VBAT 1.3V, inductor, capacitor, Schottky diode.
VPUMP_Load
Load Regulation
VPUMP_Ripple Output Voltage Ripple (depends cap/load) Efficiency Efficiency
FPUMP DCPUMP
Switching Frequency Switching Duty Cycle
Note inductor, capacitor, Schottky diode. Figure page
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Figure Basic Switch Mode Pump Circuit
PUMP
Battery
PSoC
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 VPUMP0 VPUMP1 VPUMP2 VPUMP3 VPUMP4 VPUMP5 VPUMP6 VPUMP7 Description Value PPOR Trip PORLEV[1:0] PORLEV[1:0] PORLEV[1:0] Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Value PUMP Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b 2.36 2.82 4.55 2.45 2.92 3.02 3.13 4.48 4.64 4.73 4.81 2.55 3.02 3.10 3.25 4.64 4.73 4.82 5.00 2.40 2.95 4.70 2.51[7] 2.99[8] 3.09 3.20 4.55 4.75 4.83 4.95 2.62[9] 3.09 3.16 3.32[10] 4.74 4.83 4.92 5.12 Units Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog.
2.40 2.85 2.95 3.06 4.37 4.50 4.62 4.71 2.45 2.96 3.03 3.18 4.54 4.62 4.71 4.89
Notes Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply. Always greater than above VLVD0. Always greater than above VLVD3.
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLV VOHV FlashENPB FlashENT FlashDR Description Supply Voltage Flash Write Operations Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify Flash Endurance (per block) Flash Endurance (total)[11] Flash Data Retention 2.70 50,000 1,800,000
0.75
Units Years
Notes
Driving internal pull down resistor Driving internal pull down resistor
Erase/write cycles block Erase/write cycles
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each (and forth limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles).For full industrial range, user must employ temperature sensor user module (FlashTemp) feed result temperature argument before writing. Refer Flash APIs Application Note AN2015 http://www.cypress.com under Application Notes more information.
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Electrical Characteristics
Chip-Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V Chip-Level Specifications Symbol FIMO24 Description Internal Main Oscillator Frequency 23.4 24.6
[12,13,14]
Units
Notes Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode Trimmed 3.3V operation using factory trim values. Figure page SLIMO mode only SLIMO mode Refer Digital Block Specifications.
FIMO6
Internal Main Oscillator Frequency
5.75
6.35[12,13,14]
FCPU1 FCPU2 FBLK5 FBLK33 F32K1 Jitter32k Jitter32k TXRST DC24M Step24M Fout48M Jitter24M1 FMAX TRAMP
Frequency Nominal) Frequency (3.3V Nominal) Digital PSoC Block Frequency Nominal) Digital PSoC Block Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Period Jitter Peak-to-Peak Period Jitter External Reset Pulse Width Duty Cycle Trim Step Size Output Frequency Peak-to-Peak Period Jitter (IMO) Maximum frequency signal input output. Supply Ramp Time
0.93 0.93 46.8
1400 48.0
24.6[12,13] 12.3[13,14] 49.2[12,13,15] 24.6[13,15] 49.2
[12,14]
Trimmed. Using factory trim values.
12.3
Notes 4.75V 5.25V. Accuracy derived from Internal Main Oscillator with appropriate trim range. 3.0V 3.6V. application note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information trimming operation 3.3V. individual user module data sheets information maximum frequencies user modules.
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Table 2.7V Chip-Level Specifications Symbol FIMO12 Description Internal Main Oscillator Frequency 11.5
12.7
[16,17,18]
Units
Notes
Trimmed 2.7V operation using factory trim values. Figure page SLIMO mode Trimmed 2.7V operation using factory trim values. Figure page SLIMO mode only SLIMO mode Refer Digital Block Specifications.
FIMO6
Internal Main Oscillator Frequency
6.35[16,17,18]
FCPU1 FBLK27 F32K1 Jitter32k Jitter32k TXRST FMAX TRAMP
Frequency (2.7V Nominal) Digital PSoC Block Frequency (2.7V Nominal) Internal Speed Oscillator Frequency Period Jitter Peak-to-Peak Period Jitter External Reset Pulse Width Maximum frequency signal input output Supply Ramp Time
0.093
1400
3.15[16,17] 12.5
[16,17,18]
12.3
Figure Period Jitter (IMO) Timing Diagram
Jitter24M1
Figure Period Jitter (ILO) Timing Diagram
Jitter32k
F32K1
Notes 2.4V 3.0V. Accuracy derived from Internal Main Oscillator with appropriate trim range. application note AN2012 "Adjusting PSoC Microcontroller Trims Dual Voltage-Range Operation" information maximum frequency user modules.
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General Purpose Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 5.25V, 5.25V, 5.25V, 5.25V,
Table 2.7V GPIO Specifications Symbol FGPIO TRiseF TFallF TRiseS TFallS Description GPIO Operating Frequency Rise Time, Normal Strong Mode, Cload Fall Time, Normal Strong Mode, Cload Rise Time, Slow Strong Mode, Cload Fall Time, Slow Strong Mode, Cload Units Notes Normal Strong Mode 3.0V, 3.0V, 3.0V, 3.0V,
Figure GPIO Timing Diagram
GPIO
TRiseF TRiseS
TFallF TFallS
Amplifier Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Settling times, slew rates, gain bandwidth based Analog Continuous Time PSoC block. Table 3.3V Amplifier Specifications Symbol TCOMP1 TCOMP2 Description Comparator Mode Response Time, mVpp Signal Centered Comparator Mode Response Time, 2.5V Input, 0.5V Overdrive Units
Table 2.7V Amplifier Specifications Symbol TCOMP1 TCOMP2 Description Comparator Mode Response Time, mVpp Signal Centered Comparator Mode Response Time, 1.5V Input, 0.5V Overdrive Units
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Digital Block Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table 3.3V Digital Block Specifications Function Functions Timer Description Maximum Block Clocking Frequency 4.75V) Maximum Block Clocking Frequency 4.75V) Capture Pulse Width Maximum Frequency, Capture Maximum Frequency, With Without Capture Counter Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) Maximum Input Clock Frequency 49.2 49.2 24.6 24.6 24.6 Maximum data rate 3.08 over clocking Maximum data rate 3.08 over clocking Maximum data rate over clocking 4.75V 5.25V 4.75V 5.25V
[19]
49.2 24.6
Units
Notes 4.75V 5.25V 3.0V 4.75V 4.75V 5.25V
49.2 24.6 49.2 24.6
4.75V 5.25V
CRCPRS Maximum Input Clock Frequency (CRC Mode) SPIM SPIS Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Maximum Input Clock Frequency Maximum Input Clock Frequency
Note minimum input pulse width based input synchronizers running nominal period).
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Table 2.7V Digital Block Specifications Function Functions Timer Counter Description Maximum Block Clocking Frequency Capture Pulse Width Maximum Frequency, With Without Capture Enable Pulse Width Maximum Frequency, Enable Input Maximum Frequency, Enable Input Dead Band Kill Pulse Width: Asynchronous Restart Mode Synchronous Restart Mode Disable Mode Maximum Frequency CRCPRS (PRS Mode) CRCPRS (CRC Mode) SPIM SPIS Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Maximum Input Clock Frequency Width Negated Between Transmissions Transmitter Receiver Maximum Input Clock Frequency Maximum Input Clock Frequency 12.7 12.7 12.7 6.35 12.7 12.7 Maximum data rate 1.59 over clocking Maximum data rate 1.59 over clocking Maximum data rate 3.17 over clocking 100[20] 12.7 12.7 12.7 12.7 Units Notes 2.4V 3.0V
Note minimum input pulse width based input synchronizers running nominal period).
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External Clock Specifications following tables list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.093 20.6 20.6 24.6 5300 Units Notes
Table 3.3V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.093 12.3 Units Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.186
24.6
High Period with Clock divide Period with Clock divide Power Switch
41.7 41.7
5300
Table 2.7V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.093 6.06
Units
Notes Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. frequency external clock greater than MHz, clock divider must greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT
Frequency with Clock divide greater
0.186
12.12
High Period with Clock divide Period with Clock divide Power Switch
83.4 83.4
5300
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK3 TDSCLK2 Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units Notes
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C Clock Frequency Description Standard Mode 2500 Fast Mode 100[20] Units
THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C Period Clock THIGHI2C TSUSTAI2C HIGH Period Clock Setup Time Repeated START Condition
THDDATI2C Data Hold Time TSUDATI2C Data Setup Time0 TSUSTOI2C Setup Time STOP Condition TBUFI2C TSPI2C Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
Note Fast-Mode I2C-bus device used Standard-Mode I2C-bus system, requirement tSU;DAT must then met. This automatically becomes case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
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Table 2.7V Characteristics Pins (Fast Mode Supported) Symbol FSCLI2C Clock Frequency Description Standard Mode Fast Mode Units
THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C Period Clock THIGHI2C TSUSTAI2C HIGH Period Clock Setup Time Repeated START Condition
THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time STOP Condition TBUFI2C TSPI2C Free Time Between STOP START Condition Pulse Width spikes suppressed input filter.
Figure Definition Timing Fast/Standard Mode
TLOWI2C TSUDATI2C THDSTAI2C
TSPI2C TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
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Packaging Information
This section illustrates packaging specifications CY8C21x23 PSoC device, along with thermal impedances each package minimum solder reflow peak temperature. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions
Packaging Dimensions
Figure 8-Pin (150-Mil) SOIC
DIMENSIONS INCHES[MM] MIN. MAX. OPTIONAL, ROUND SINGLE LEADFRAME RECTANGULAR MATRIX LEADFRAME REFERENCE JEDEC MS-012
0.230[5.842] 0.244[6.197]
0.150[3.810] 0.157[3.987]
PACKAGE WEIGHT 0.07gms
PART S08.15 STANDARD PKG. SZ08.15 LEAD FREE PKG.
0.189[4.800] 0.196[4.978]
SEATING PLANE
0.010[0.254] 0.016[0.406]
0.061[1.549] 0.068[1.727] 0.004[0.102] 0.050[1.270] 0.004[0.102] 0.0098[0.249] 0°~8° 0.016[0.406] 0.035[0.889] 0.0075[0.190] 0.0098[0.249]
0.0138[0.350] 0.0192[0.487]
51-85066
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Figure 16-Pin (150-Mil) SOIC
51-85022
Figure 16-Pin
001-09116
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Figure 20-Pin (210-MIL) SSOP
51-85077
Figure 24-Pin (4x4)
SIDE VIEW VIEW
0.05 3.90 4.10 2.45 2.55 3.70 3.80 3.90 4.10 2.49
SOLDERABLE EXPOSED
BOTTOM VIEW
0.23±0.05 2.49 0.45 PIN1 0.20 1.00 MAX. 0.05 MAX. 0.80 MAX. 0.20 REF.
3.70 3.80
0.30-0.50 0°-12° SEATING PLANE 0.42±0.18 (4X) 2.45 2.55
0.50
NOTES: HATCH SOLDERABLE EXPOSED METAL.
REFERENCE JEDEC#: MO-220 PACKAGE WEIGHT: 0.042g DIMENSIONS [MIN/MAX] PACKAGE CODE PART LF24A LY24A DESCRIPTION STANDARD LEAD FREE
51-85203
Important Note information preferred dimensions mounting packages, following Application Note Note that pinned vias thermal conduction required power 48-pin PSoC devices. Document Number: 38-12022 Rev. Page
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Thermal Impedances
Table Thermal Impedances Package Package SOIC SOIC SSOP
[22]
Typical [21] 186°C/W 125°C/W 46°C/W 117°C/W 40°C/W
Solder Reflow Peak Temperature
Table lists minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SOIC SOIC SSOP Minimum Peak Temperature[23] 240°C 240°C 240°C 240°C 240°C Maximum Peak Temperature 260°C 260°C 260°C 260°C 260°C
Notes POWER achieve thermal impedance specified package, center thermal must soldered ground plane. Higher temperatures required based solder melting point. Typical temperatures solder 220+/-5°C with Sn-Pb 245+/-5°C with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Ordering Information
following table lists CY8C21x23 PSoC device's package features ordering codes. Table CY8C21x23 PSoC Device Features Ordering Information XRES
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Temperature Range
Digital Pins
Ordering Code
Package
8-Pin (150-Mil) SOIC 8-Pin (150-Mil) SOIC (Tape Reel) 16-Pin (150-Mil) SOIC 16-Pin (150-Mil) SOIC (Tape Reel) 16-Pin (3x3)
CY8C21123-24SXI CY8C21123-24SXIT CY8C21223-24SXI CY8C21223-24SXIT CY8C21223-24LGXI
-40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
20-Pin (210-Mil) SSOP CY8C21323-24PVXI 20-Pin (210-Mil) SSOP CY8C21323-24PVXIT (Tape Reel) 24-Pin (4x4) 24-Pin (4x4) (Tape Reel) CY8C21323-24LFXI CY8C21323-24LFXIT
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE).
Ordering Code Definitions
xxx-24xx
Package Type: PDIP Pb-Free SOIC Pb-Free SSOP Pb-Free Pb-Free TQFP Pb-Free Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress Thermal Rating: Commercial Industrial Extended
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Analog Outputs
Analog Blocks
(Bytes)
Analog Inputs
Flash (Bytes)
Digital PSoC Blocks
Switch Mode Pump
CY8C21123, CY8C21223, CY8C21323
Document History Page
Document Title: CY8C21123, CY8C21223, CY8C21323 PSoC® Programmable System-on-ChipDocument Number:38-12022 Orig. Submission Rev. Description Change Change Date 133248 silicon document (Revision **). 208900 part, package update ordering codes Pb-free. 212081 Expand prepare Preliminary version. 227321 Team Update specs., data, format. 235973 Updated Overview Electrical Spec. chapters, along with 24-pin pinout. Added CMP_GO_EN register (1,64h) mapping table. 290991 Update data sheet standards memo. device table. part numbers pinouts fine tune. Change 20-pin SSOP CY8C21323. Reflow Temp. table. Update diagrams specs. 301636 Chip-Level Specification changes. Update links CY.com Portal. 324073 Obtained clearer SOIC package. Update Thermal Impedances Solder Reflow tables. Re-add pinout ISSP notation. type-o. register names. Update Electrical Specifications. logo. Update copyright. Make data sheet Final. 2588457 KET/HMI/ 10/22/2008 package information page Converted data sheet template. AESA Added 16-Pin package diagram. 2618175 OGNE/PYRS 12/09/08 Added Note Ordering Information Section. Changed title from PSoC Mixed-Signal Array PSoC Programmable System-on-Chip. Updated `Development Tools' `Designing with PSoC Designer' sections pages 2682782 MAXK/AESA 04/03/2009 Corrected pinout. 2699713 MAXK 04/29/09 Minor correct paragraph style Pinout. change content.
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Cypress Semiconductor Corporation, 2004-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
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PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips.
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