CapSenseApplications Power CapSenseBlock Configurable Capacitive

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

CapSenseApplications Power CapSenseBlock Configurable Capacitive

Datasheet Thumbnail

Top Searches for this datasheet

CY8C20x46, CY8C20x66
CapSenseApplications
Power CapSenseBlock Configurable Capacitive Sensing Elements Supports Combination CapSense Buttons, Sliders, Touchpads, TouchScreens, Proximity Sensors Powerful Harvard Architecture Processor Processor Speeds Running Power High Speed Interrupt Controller 1.71V 5.5V Operating Voltage Temperature Range: 40°C +85°C Flexible On-Chip Memory Program Storage Size Options CY8C20x46: Flash CY8C20x66: Flash 50,000 Erase/Write Cycles 2048 Bytes SRAM Data Storage Partial Flash Updates Flexible Protection Modes In-System Serial Programming (ISSP) Full-Speed Maps) Eight Uni-Directional Endpoints Bi-Directional Control Endpoint Compliant Dedicated Byte Buffer Internal 3.3V Output Regulator Available 48-Pin 48-Pin SSOP packages only Operating voltage with enabled: 3.15 3.45V when supply voltage around 3.3V 4.35 5.25V when supply voltage around 5.0V Complete Development Tools Free Development Tool (PSoC DesignerTM) Full-Featured, In-Circuit Emulator Programmer Full Speed Emulation Complex Breakpoint Structure 128K Trace Memory Precision, Programmable Clocking Internal 5.0% 6/12/24 Main Oscillator Internal Speed Oscillator Watchdog Sleep Optional External Crystal 0.25% Accuracy with External Components
Programmable Configurations Sink Current GPIO Pull High Open Drain Drive Modes GPIO CMOS Drive Mode Ports Analog Inputs GPIO Configurable Inputs GPIO Selectable, Regulated Digital Port Configurable Input Threshold Port 3.0V, Total Port Source Current Source Current Mode Ports Hot-Swap Capability Port1 GPIO Versatile Analog Common Internal Analog Simultaneous Connection Combinations High PSRR Comparator Dropout Voltage Regulator Analog Array Additional System Resources CSlave Selectable kHz, kHz, Implementation Requires Clock Stretching Implementation During Sleep Modes with Less Than Hardware Address Detection SPIMaster Slave Configurable Between 46.9 Three 16-Bit Timers Watchdog Sleep Timers Internal Voltage Reference Integrated Supervisory Circuit Package Options 16-Pin 24-Pin 32-Pin 48-Pin (CY8C20x66 only) 48-Pin SSOP
Cypress Semiconductor Corporation Document Number: 001-12696 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised October 2008
Feedback
CY8C20x46, CY8C20x66
Block Diagram
Port
Port
Port
Port
Port
1.8/2.5/3V
PWRSYS (Regulator)
PSoC CORE
SYSTEM Global Analog Interconnect SRAM Interrupt Controller Supervisory (SROM) 16K/32K Flash Nonvolatile Memory Sleep Watchdog
Core (M8C)
6/12/24 Internal Main Oscillator (IMO)
Internal Speed Oscillator (ILO)
Multiple Clock Sources
CAPSENSE SYSTEM
Comparators CapSense Module
Analog Reference
Analog
SYSTEM
Slave
Internal Voltage References
System Resets
Master/ Slave
Three 16-Bit Programmable Timers
Digital Clocks
SYSTEM RESOURCES
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
PSoC® Functional Overview
PSoC family consists many Mixed-Signal Array with OnChip Controller devices. These devices designed replace multiple traditional MCU-based components with one, cost single-chip programmable component. PSoC device includes configurable analog digital blocks, well programmable interconnect. This architecture allows user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. architecture this device family, illustrated above, comprised three main areas: Core, CapSense Analog System, System Resources (including full-speed port). common, versatile allows connection between analog system. Each CY8C20x46/CY8C20x66 PSoC device includes dedicated CapSense block that provides sensing scanning control circuitry capacitive sensing applications. Depending PSoC package, general purpose (GPIO) also included. GPIO provides access analog mux. Figure Analog System Block Diagram
IDAC
Analog Global
Reference Buffer
Cinternal
Comparator
Refs
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (internal main oscillator) (internal speed oscillator). core, called M8C, powerful processor with speeds MHz. four-MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such configurable slave/SPI master-slave communication interface, three 16-bit programmable timers, various system resets supported M8C. Analog System composed CapSense PSoC block internal 1.2V analog reference, which together support capacitive sensing inputs.
CapSenseCounters
CSCLK CapSense Clock Select Oscillator
Analog Multiplexer System Analog connect every GPIO pin. Pins connected individually combination. also connects analog system analysis with CapSense block comparator. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Other multiplexer applications include:
CapSense Analog System
Analog System contains capacitive sensing hardware. Several hardware algorithms supported. This hardware performs capacitive sensing scanning without requiring external components. Capacitive sensing configurable each GPIO pin. Scanning enabled CapSense pins completed quickly easily across multiple ports.
Complex capacitive sensing interfaces, such sliders touchpads. Chip-wide that allows analog input from pin. Crosspoint connection between combinations.
When designing capacitive sensing applications, refer latest signal-to-noise signal level requirements Application Notes, which found under http://www.cypress.com Documentation Application Notes. general, unless otherwise noted relevant Application Notes, minimum signal-to-noise ratio (SNR) CapSense applications 5:1.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Additional System Resources
System Resources, some which have been previously listed, provide additional capability useful complete systems. Additional resources include voltage detection power reset. merits each system resource listed here:
Getting Started
quickest path understanding PSoC silicon reading this data sheet using PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. in-depth information, along with detailed programming information, reference PSoC MixedSignal Array Technical Reference Manual, which found http://www.cypress.com/psoc. up-to-date Ordering, Packaging, Electrical Specification information, reference latest PSoC device data sheets http://www.cypress.com.
slave/SPI master-slave module provides 50/100/400 communication over wires. communication over wires runs speeds 46.9 (lower slower system clock). hardware address recognition feature reduces already power consumption eliminating need intervention until packet addressed target device received. Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power-On-Reset) circuit eliminates need system supervisor. internal reference provides absolute reference capacitive sensing. 5.5V maximum input, 1.8/2.5/3V-selectable output, lowdropout regulator (LDO) provides regulation IOs. registercontrolled bypass mode allows user disable LDO. Standard Cypress PSoC tools available debugging CY8C20x46/CY8C20x66 family parts. However, additional trace length minimal ground plane FlexPod create noise problems that make difficult debug Power PSoC design. custom bonded On-Chip Debug (OCD) device available 48-pin package. device recommended debugging designs that have high current and/or high analog accuracy requirements. package compact connected through high density connector.
Development Kits
Development Kits available from following distributors: Digi-Key, Avnet, Arrow, Future. Cypress Online Store contains development kits, compilers, accessories PSoC development. Cypress Online Store site http://www.cypress.com/shop/. Under Product Categories click PSoC® Mixed Signal Arrays view current list available items.
Technical Training Modules
Free PSoC technical training modules available users PSoC. Training modules cover designing, debugging, advanced analog CapSense.
Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant http://www.cypress.com, click Support located page, select CYPros Consultants.
Technical Support
PSoC application engineers take pride fast accurate response. They reached with four hour guaranteed response http://www.cypress.com/support.
Application Notes
long list application notes assists every aspect your design effort. view PSoC application notes, http://www.cypress.com site select Application Notes under Documentation list located page. Application notes sorted date default.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Development Tools
PSoC Designeris Microsoft® Windows-based, integrated development environment Programmable System-onChip (PSoC) devices. PSoC Designer application runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family. Code Generation Tools PSoC Designer supports multiple third-party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merged seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer debug environment that provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started. In-Circuit Emulator cost, high functionality (In-Circuit Emulator) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
PSoC Designer Software Subsystems
System-Level View system-level view drag-and-drop visual embedded system design environment based PSoC Express. this view solve design problems same might think about system. Select input output devices based upon system requirements. communication interface define interface system (registers). Define when output device changes state based upon any/all other system devices. Based upon design, PSoC Designer automatically selects more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.x. choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. tool also supports easy development multiple configurations dynamic reconfiguration. Dynamic reconfiguration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over onchip resources. views project share common code editor, builder, common debug, emulation, programming tools.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select Components Configure Components Organize Connect Generate, Verify, Debug
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system-level inputs, outputs, communication interfaces each other with valuator functions. system-level view selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog-todigital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library pre-built, pre-tested hardware peripheral components. system-level view these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2Cbus, example), logic control they interact with another (called valuators). chip-level view components called "user modules." User modules make selecting implementing peripheral devices simple, come analog, digital, mixed-signal varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Configuration Files" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high-level functions control respond hardware events time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger (access clicking Connect icon). PSoC Designer downloads image In-Circuit Emulator (ICE) where runs full speed. PSoC Designer debugging capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, debug interface provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver property, other information need successfully implement your design.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Document Conventions
Acronyms Used
following table lists acronyms that used this document. Table Acronyms Acronym GPIO PPOR PSoC® SLIMO SRAM Description alternating current application programming interface central processing unit direct current full scale range general purpose graphical user interface in-circuit emulator internal speed oscillator internal main oscillator input/output least-significant voltage detect most-significant power reset precision power reset Programmable System-on-Chipslow static random access memory
Units Measure
units measure table located Electrical Specifications section. Units Measure lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Information
This section describes, lists, illustrates CY8C20x46/CY8C20x66 PSoC device pins pinout configurations. CY8C20x46/CY8C20x66 PSoC device available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital connection common analog bus. However, Vss, Vdd, XRES capable Digital
16-Pin Part Pinout
Table 16-Pin Part Pinout(2)
Power
Type Digital
IOHR IOHR IOHR IOHR Power IOHR IOHR IOHR Input
Analog
Name
P2[5] P2[3] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] XRES P0[4] P0[7] P0[3]
Description
Crystal output (XOut). Crystal input (XIn). SCL, SDA, MISO. CLK. ISSP CLK(1), SCL, MOSI. Ground connection. ISSP DATA(1), SDA, CLK. Optional external clock (EXTCLK) Active high external reset with internal pull down. Supply voltage. Integrating input.
Figure CY8C20246, CY8C20266 16-Pin PSoC Device
P0[1]
Integrating input.
LEGEND Analog, Input, Output, High Output Drive, Regulated Output.
Notes These ISSP pins, which High (Power Reset). During power reset event, device P1[1] P1[0] disturb bus. alternate pins encounter issues.
Document Number: 001-12696 Rev.
DATA1, SDA, CLK, P1[0]
CLK, P1[3] CLK1, MOSI, P1[1]
XOut, P2[5] XIn, P2[3] SCL, P1[7] SDA, MISO, P1[5]
P0[1], P0[3], P0[7],
(Top View)
P0[4], XRES P1[4], EXTCLK, P1[2],
Page
Feedback
CY8C20x46, CY8C20x66
24-Pin Part Pinout
Table 24-Pin Part Pinout(2,
P0[1], P0[3], P0[5], P0[7], P0[6],
Type Digital Analog Name
Power Power Power IOHR IOHR IOHR IOHR Input IOHR IOHR IOHR IOHR P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1]
Description
Crystal output (XOut). Crystal input (XIn). SCL, SDA, MISO. CLK. ISSP CLK(1), SCL, MOSI. connection. Ground connection. ISSP DATA(1), SDA, CLK. Optional external clock input (EXTCLK). Active high external reset with internal pull down.
Figure CY8C20346, CY8C20366 24-Pin PSoC Device
XOut, P2[5] XIn, P2[3]
Supply voltage.
Integrating input. Integrating input. Center must connected ground.
LEGEND Analog, Input, Output, High Output Drive, Regulated Output.
Note center (CP) package must connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, should electrically floated connected other signal.
Document Number: 001-12696 Rev.
DATA2, SDA, CLK, P1[0] P1[2] EXTCLK, P1[4]
CLK2, MOSI, P1[1]
P2[1] SCL, P1[7] SDA, MISO, P1[5] CLK, P1[3]
(Top View)
P0[4], P0[2], P0[0], P2[0], XRES P1[6],
Page
Feedback
CY8C20x46, CY8C20x66
32-Pin Part Pinout
Table 32-Pin Part Pinout
Power Power Power IOHR IOHR IOHR IOHR Input
Type Digital
IOHR IOHR IOHR IOHR Power
P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3]
Integrating input. Crystal output (XOut) Crystal input (XIn)
SCL, SDA, MISO. CLK. ISSP CLK(1), SCL, MOSI. Ground connection. ISSP DATA(1), SDA., Optional external clock input (EXTCLK). Active high external reset with internal pull down.
P0[1] P2[7] XOut, P2[5] XIn, P2[3] P2[1] P3[3] P3[1] SCL, P1[7]
Analog
Name
Description
Figure CY8C20446, CY8C20466 32-Pin PSoC Device
(Top View)
CLK4, SCL, MOSI, P1[1] DATA1, SDA, CLK, P1[0] 1[2]
MISO 1[5] 1[3]
Supply voltage.
Integrating input. Ground connection. Center must connected ground.
LEGEND Analog, Input, Output, High Output Drive, Regulated Output.
Document Number: 001-12696 Rev.
XTCLK 1[4] 1[6]
P0[0], P2[6], P2[4], P2[2], P2[0], P3[2], P3[0], XRES
Page
Feedback
CY8C20x46, CY8C20x66
48-Pin SSOP Part Pinout
Table 48-Pin SSOP Part Pinout(2) Analog Digital Figure CY8C20546, CY8C20566-48-Pin SSOP PSoC Device Name
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] IOHR IOHR IOHR IOHR IOHR IOHR IOHR IOHR P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] connection connection connection connection connection SCL, SDA, MISO CLK(1), SCL, MOSI Ground DATA(1), SDA, connection connection connection XTAL XTAL
Description
P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1]
SSOP
P0[6] P0[4] P0[2] P0[0] P2[6] P2[4] P2[2] P2[0] P3[6] P3[4] P3[2] P3[0] XRES P1[6] P1[4] P1[2] P1[0]
Analog
Digital
connection
Name
P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Power
Description
XRES P3[0] P3[2] P3[4] P3[6] P2[0]
connection connection Active high external reset with internal pull down
Power
LEGEND Analog, Input, Output, Connection, High Output Drive, Regulated Output Option.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
48-Pin Part Pinout
Table 48-Pin Part Pinout
IOHR IOHR Power Power IOHR IOHR IOHR IOHR Input IOHR IOHR
Analog
Digital
Figure CY8C20666 48-Pin PSoC Device
P0[6], P0[4], P0[3], P0[5 P0[7], P0[1], P0[2], P0[0], P2[6], P2[4],AI P2[2],AI P2[0],AI P4[2], P4[0],AI P3[6],AI P3[4], P3[2], P3[0 XRES P1[6],
Name
P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] DVdd P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2]
Description
connection. Crystal output (XOut). Crystal input (XIn).
P2[7] XOut, P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] SCL, P1[7]
SDA, MISO, P1[5]
(Top View)
SCL, SDA, MISO. connection. connection. CLK. ISSP CLK(1), SCL, MOSI. Ground connection.
Supply voltage. ISSP DATA(1), SDA, CLK. Optional external clock input (EXTCLK). Active high external reset with internal pull down.
Analog
Digital
P3[4]
Name
P0[6] Supply voltage. connection. connection.
P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4]
Power
P0[7] P0[5] P0[3] P0[1] Center must connected ground. Integrating input. Ground connection.
Power Power
LEGEND Analog, Input, Output, Connection High Output Drive, Regulated Output.
Document Number: 001-12696 Rev.
CLK, P1[3] CLK6, SCL, MOSI, P1[1] DVdd DATA1, SDA, CLK, P1[0] 1[2] EXTCLK, P1[4]
Description
Page
Feedback
CY8C20x46, CY8C20x66
48-Pin Part Pinout
48-pin part CY8C20066 On-Chip Debug (OCD) PSoC device. Note that this part only used in-circuit debugging.(4) Table 48-Pin Part Pinout
IOHR IOHR Power Power IOHR IOHR IOHR IOHR
Analog
Digital
Figure CY8C20066 48-Pin PSoC Device
OCDO P0[6], P0[4], P0[3], P0[5 P0[7], OCDE
Name
OCDOE P2[7] P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] P1[7] P1[5] CCLK HCLK P1[3] P1[1] DVdd P1[0] P1[2]
Description
mode direction pin. Crystal output (XOut). Crystal input (XIn).
OCDO P2[7] XOut, P2[5] P2[3] P2[1] P4[3] P4[1] P3[7] P3[5] P3[3] P3[1] SCL, P1[7] P0[1],
P0[2], P0[0], P2[6], P2[4], P2[2], P2[0], P4[2], P4[0], P3[6], P3[4], P3[2], P3[0], XRES P1[6],
(Top View)
SDA, MISO. clock output. high speed clock output. CLK. ISSP CLK(1), SCL, MOSI. Ground connection.
Supply voltage. ISSP DATA(1), SDA, CLK.
Optional external clock input (EXTCLK). Active high external reset with internal pull down.
Analog
Digital
Name
P0[0] P0[2] P0[4] P0[6] OCDO OCDE Supply voltage.
IOHR IOHR Input
P1[4] P1[6] XRES
Power
P3[0] P3[2] P3[4] P3[6] P4[0] P4[2] P2[0] P2[2] P2[4] P2[6]
Power Power
P0[7] P0[5] P0[3] P0[1] Center must connected ground. Integrating input. Ground connection.
LEGEND Analog, Input, Output, Connection High Output Drive, Regulated Output. Note This part available limited quantities In-Circuit Debugging during prototype development. available production volumes.
Document Number: 001-12696 Rev.
SDA, MISO, P1[5] CCLK HCLK CLK, P1[3] CLK6, SCL, MOSI, P1[1] DVdd DATA1, SDA, CLK, P1[0] 1[2] EXTCLK, P1[4]
SCL,
even data data output.
Description
Page
Feedback
CY8C20x46, CY8C20x66
Electrical Specifications
This section presents electrical specifications CY8C20x46/CY8C20x66 PSoC devices. most up-to-date electrical specifications, confirm that have most recent data sheet going http://www.cypress.com/psoc. Figure Voltage versus Frequency Figure Frequency Trim Options
5.5V
5.5V
Voltage
ratin
Voltage
SLIMO Mode
SLIMO Mode
SLIMO Mode
1.71V Frequency
1.71V
Frequency
following table lists units measure that used this section. Table Units Measure Symbol
Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilo samples second kilohm megahertz megaohm microampere microfarad microhenry microsecond microwatts
Symbol milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak
Unit Measure
Kbit ksps
parts million picosecond samples second sigma: standard deviation volts
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Comparator User Module Electrical Specifications
following table lists guaranteed maximum minimum specifications. Unless stated otherwise, specifications entire device voltage temperature operating range: -40°C 85°C, 1.71V 5.5V. Table Comparator User Module Electrical Specifications Symbol TCOMP Offset Current PSRR Input Range Supply voltage Supply voltage Description Comparator Response Time Units Average current, overdrive Power Supply Rejection Ratio Power Supply Rejection Ratio Conditions overdrive
Electrical SpecificationsAbsolute Maximum
Table User Module Electrical Specifications Symbol Input Input Voltage Range Input Capacitance Resolution 8-Bit Sample Rate 23.4375 Bits ksps Settings Data Clock MHz. Sample Rate 0.001/(2^Resolution/Data clock) Data Clock MHz. Sample Rate 0.001/(2^Resolution/Data clock) configuration configuration This gives maximum code Description Units Conditions
10-Bit Sample Rate
5.859
ksps
Accuracy IADC FCLK Offset Error Operating Current Data Clock 2.25 Source chip's internal main oscillator. device data sheet accuracy. guaranteed. %FSR resolution Equivalent switched input resistance 10-bit resolution.
Monotonicity PSRR Power Supply Rejection Ration PSRR (Vdd>3.0V) PSRR (2.2 3.0) PSRR (2.0 2.2) PSRR (Vdd 2.0) Gain Error Input Resistance
(500fF*Data- (400fF*Data- (300fF*DataClock) Clock) Clock)
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Ratings
Table Absolute Maximum Ratings Symbol TSTG Description Storage Temperature Conditions Higher storage temperatures reduces data retention time. Recommended Storage Temperature +25°C 25°C. Extended duration storage temperatures above 85oC degrades reliability. +125 Units
VIOZ IMIO
Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch-up Current Human Body Model accordance with JESD78 standard
-0.5 -0.5 2000
+6.0
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Operational Temperature temperature rise from ambient junction package specific. table Thermal Impedances Package page user must limit power consumption comply with this requirement. Conditions Units
+100
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Chip-Level Specifications Symbol IDD24 IDD12 IDD6 ISB0 ISB1 Description Supply Voltage Supply Current, Conditions table Specifications page Conditions 3.0V, 25oC, MHz. CapSense running MHz, sourcing current Conditions 3.0V, 25oC, MHz. CapSense running MHz, sourcing current Conditions 3.0V, 25oC, MHz. CapSense running MHz, sourcing current 3.0V, 25oC, regulator turned 3.0V, 25oC, regulator turned 1.71 2.88 Units
Supply Current,
1.71
Supply Current,
1.16
Deep Sleep Current Standby Current with POR, Sleep Timer
1.07
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
General Purpose Specifications
following tables list guaranteed maximum minimum specifications voltage temperature ranges: 3.0V 5.5V -40°C 85°C, 2.4V 3.0V -40°C 85°C, 1.71V 2.4V -40°C 85°C, respectively. Typical parameters apply 3.3V 25°C design guidance only. Table 3.0V 5.5V GPIO Specifications Symbol VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 VOH10 Description Pull Resistor High Output Voltage Port Pins High Output Voltage Port Pins High Output Voltage Port Pins with Regulator Disabled Port High Output Voltage Port Pins with Regulator Disabled Port High Output Voltage Port Pins with Regulator Enabled High Output Voltage Port Pins with Regulator Enabled maximum source current maximum source current maximum source current maximum source current 3.1V, maximum sourcing 3.1V, maximum source current Conditions Units
2.85
3.00
2.20
High Output Voltage 2.7V, maximum Port Pins with Enabled 2.5V source current 2.7V, maximum High Output Voltage Port Pins with Enabled 2.5V source current High Output Voltage 2.7V, maximum Port Pins with Enabled 1.8V source current High Output Voltage 2.7V, maximum Port Pins with Enabled 1.8V source current Output Voltage 3.3V, maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5])
2.35
2.50
2.75
1.90
1.60
1.80
1.20
0.75
CPIN
Input Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitance Package dependent Temp 25oC
2.00
0.001
0.80
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Table 2.4V 3.0V GPIO Specifications Symbol VOH1 VOH2 VOH3 VOH4 VOH5A VOH6A Description Pull Resistor High Output Voltage Port Pins High Output Voltage Port Pins High Output Voltage Port Pins with Regulator Disabled Port High Output Voltage Port Pins with Regulator Disabled Port High Output Voltage Port Pins with Enabled 1.8V High Output Voltage Port Pins with Enabled 1.8V Output Voltage Conditions maximum source current maximum source current maximum source current maximum source current 2.4V, maximum source current 2.4V, maximum source current maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]) Units
1.50
1.80
1.20
0.75
CPIN
Input Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins
Package dependent Temp 25oC
0.001
0.72
Table 1.71V 2.4V GPIO Specifications Symbol VOH1 VOH2 VOH3 VOH4 Description Pull Resistor High Output Voltage Port Pins High Output Voltage Port Pins High Output Voltage Port Pins with Regulator Disabled Port High Output Voltage Port Pins with Regulator Disabled Port Output Voltage maximum source current maximum source current maximum source current maximum source current maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]) Conditions Units
Input Voltage
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Table 1.71V 2.4V GPIO Specifications (continued) Symbol CPIN Description Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins Package dependent Temp 25oC Conditions 0.65 0.001 Units
Table 17.DC Characteristics Interface Symbol Rusbi Rusba Vohusb Volusb Rps2 Rext Description Pull Resistance Pull Resistance Static Output High Static Output Differential Input Sensitivity Differential Input Common Mode Range Single Ended Receiver Threshold Transceiver Capacitance Hi-Z State Data Line Leakage PS/2 Pull Resistance External Series Resistor series with each line 21.78 With idle While receiving traffic Conditions 0.900 1.425 22.0 22.22 1.575 3.090 Units
Analog Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Analog Specifications Symbol RGND Description Switch Resistance Common Analog Resistance Initialization Switch Conditions Units
maximum voltage measuring RGND 1.8V
Power Comparator Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Comparator Specifications Symbol VLPC ILPC VOSLPC Description Power Comparator (LPC) common mode supply current voltage offset Conditions Maximum voltage limited Units
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Specifications Symbol VPPOR0 VPPOR1 VPPOR2 VPPOR3 VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Description Value PPOR Trip PORLEV[1:0] 00b, HPOR PORLEV[1:0] 00b, HPOR PORLEV[1:0] 01b, HPOR PORLEV[1:0] 10b, HPOR Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b Conditions must greater than equal 1.71V during startup, reset from XRES pin, reset from watchdog. 1.61 2.40[5] 2.64[6] 2.85[7] 2.95 3.06 1.84 1.75[8] 4.62 1.66 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 1.90 1.80 4.73 1.71 2.41 2.66 2.95 2.51 2.78 2.99 3.09 3.20 2.32 1.84 4.83 Units
Programming Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Programming Specifications Symbol VddIWRITE IDDP VILP VIHP IILP IIHP VOLP VOHP Description Supply Voltage Flash Write Operations Supply Current During Programming Verify Input Voltage During Programming Verify Input High Voltage During Programming Verify Input Current when Applying Vilp P1[0] P1[1] During Programming Verify Input Current when Applying Vihp P1[0] P1[1] During Programming Verify Output Voltage During Programming Verify Output High Voltage During Programming Verify appropriate General Purpose Specifications page table page VOH4 Table page Erase/write cycles block Following maximum Flash write cycles; ambient temperature 55°C appropriate General Purpose Specifications page appropriate General Purpose Specifications page table pages Driving internal pull down resistor Conditions 1.71 Units
Driving internal pull down resistor
0.75
FlashENPB FlashDR
Flash Write Endurance Flash Data Retention
50,000
Cycles Years
Notes Always greater than above VPPOR1 voltage falling supply. Always greater than above VPPOR2 voltage falling supply. Always greater than above VPPOR3 voltage falling supply. Always greater than above VPPOR0 voltage falling supply.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Chip-Level Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Chip-Level Specifications Symbol FMAX FCPU F32K1 FIMO24 FIMO12 FIMO6 DCIMO TRAMP TXRST TXRST2 Description Maximum Operating Frequency Maximum Processing Frequency Internal Speed Oscillator Frequency Internal Main Oscillator Frequency Setting Internal Main Oscillator Frequency Setting Internal Main Oscillator Frequency Setting Duty Cycle Supply Ramp Time External Reset Pulse Width Power After supply voltage valid External Reset Pulse Width after Power Applies after part booted Conditions 22.8 11.4 25.2 12.6 Units
General Purpose Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table GPIO Specifications Symbol FGPIO Description GPIO Operating Frequency Conditions Normal Strong Mode Port TRise23 TRise23L Rise Time, Strong Mode, Cload Ports Rise Time, Strong Mode Supply, Cload Ports Rise Time, Strong Mode, Cload Ports Rise Time, Strong Mode Supply, Cload Ports Fall Time, Strong Mode, Cload Ports 3.6V, 1.71 3.0V, 1.71V<Vdd<2.4V 2.4V<Vdd<5.5V Units
TRise01 TRise01L
3.6V, enabled disabled 1.71 3.0V, enabled disabled 3.6V,
TFall TFallL
Fall Time, Strong Mode Supply, Cload 1.71 3.0V, Ports
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Figure GPIO Timing Diagram
GPIO Output Voltage
TRise23 TRise01 TRise23L TRise01L
TFall TFallL
Table 24.AC Characteristics Data Timings Symbol Tdrate Tdjr1 Tdjr2 Tudj1 Tudj2 Tfdeop Tfeopt Tfeopr Tfst Description Full speed data rate Receiver data jitter tolerance Receiver data jitter tolerance Driver differential jitter Driver differential jitter Source jitter differential transition Source interval Receiver interval Width interval during differential transition Conditions Average rate next transition pair transition next transition pair transition transition 12-0.25% -18.5 -3.5 -4.0 0.25% 18.5 Units
Table 25.AC Characteristics Driver Symbol Vcrs Description Transition rise time Transition fall time Rise/fall time matching Output signal crossover voltage Conditions 90.00 111.1 Units
Comparator Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Power Comparator Specifications Symbol TLPC Description Comparator Response Time, Overdrive Conditions overdrive does include offset voltage. Units
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Analog Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Analog Specifications Symbol Switch Rate Description Conditions Maximum voltage when measuring switch rate 1.8Vp-p Units
External Clock Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description Conditions 0.750 20.6 20.6 25.2 5300 Units
Programming Specifications
Figure Waveform
SCLK (P1[1])
RSCLK
FSCLK
SDATA (P1[0])
TSSCLK
HSCLK
TDSCLK
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TWRITE TDSCLK Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Block Write Time Data Delay from Falling Edge SCLK Conditions Units
TERASEB Flash Erase Time (Block)
TDSCLK3 Data Delay from Falling Edge SCLK TDSCLK2 Data Delay from Falling Edge SCLK 1.71 Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Specifications Symbol Description FSPIM Maximum Input Clock Frequency Selection, Master 2.4V<Vdd<5.5V Conditions Output clock frequency half input clock rate. Units
FSPIS
Output clock frequency half Maximum Input Clock Frequency Selection, input clock rate Master(21)1.71V<Vdd<2.4V Maximum Input Clock Frequency Selection, Slave 2.4<Vdd<5.5V Maximum Input Clock Frequency Selection, Slave 1.71V<Vdd<2.4V Width Negated Between Transmissions
Specifications
following table lists guaranteed maximum minimum specifications entire voltage temperature ranges. Table Characteristics Pins Symbol FSCLI2C THDSTAI2C Description Conditions Standard Mode Fast Mode 100[9] Units
Clock Frequency Hold Time (repeated) START Condition. After this period, first clock pulse generated. TLOWI2C Period Clock THIGHI2C HIGH Period Clock TSUSTAI2C Setup Time Repeated START Condition THDDATI2C Data Hold Time TSUDATI2C Data Setup Time TSUSTOI2C Setup Time STOP Condition Free Time Between STOP START TBUFI2C Condition TSPI2C Pulse Width spikes suppressed input filter.
Figure Definition Timing Fast/Standard Mode
TLOWI2C
TSUDATI2C
THDSTAI2C
TSPI2C
TBUFI2C
THDSTAI2C THDDATI2C THIGHI2C TSUSTAI2C TSUSTOI2C
Note Fast-Mode I2C-bus device used Standard Mode I2C-bus system, requirement tSU;DAT must then met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU;DAT 1000 1250 (according Standard-Mode I2C-bus specification) before line released.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Packaging Information
This section illustrates packaging specifications CY8C20x46/CY8C20x66 PSoC device, along with thermal impedances each package. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions Figure 16-Pin Chip Lead (Sawn)
001-09116
Figure 24-Pin (4x4
001-13937
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Figure 32-Pin (5x5
001-42168
Figure 48-Pin (300 MIL) SSOP
.020
0.395 0.420 0.292 0.299
DIMENSIONS INCHES MIN.
MAX.
0.620 0.630
0.088 0.092
0.095 0.110
SEATING PLANE GAUGE PLANE
.010
0.005 0.010
0.025
0.004
0.008 0.0135 0.008 0.016 0°-8°
0.024 0.040
51-85061
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Figure 48-Pin (7x7
001-13191
Important Note
information preferred dimensions mounting packages, following Application Note Pinned vias thermal conduction required power PSoC device.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Thermal Impedances
Table Thermal Impedances Package Package QFN[11] QFN[11] SSOP QFN[11] Typical [10] 32.69oC/W 20.90oC/W 19.51oC/W 69oC/W 17.68oC/W
Solder Reflow Peak Temperature
Following minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP Minimum Peak Temperature[12] 240oC 240oC 240oC 220oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC
Notes Power achieve thermal impedance specified package, center thermal should soldered ground plane. Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Development Tool Selection
This section presents development tools available current PSoC device families including CY8C20x46/ CY8C20x66 family.
Development Kits
development kits purchased from Cypress Online Store. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface allows users run, halt, single step processor view content specific memory locations. Advance emulation features also supported through PSoC Designer. includes:
Software
PSoC DesignerAt core PSoC development software suite PSoC Designer. Utilized thousands PSoC developers, this robust software been facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under Software. PSoC ExpressAs newest addition PSoC development software suite, PSoC Express first visual embedded system design tool that allows user create entire PSoC project generate schematic, BOM, data sheet without writing single line code. Users work directly with application objects such LEDs, switches, sensors, fans. PSoC Express available free charge PSoC Programmer Flexible enough used bench development, suitable factory programming, PSoC Programmer works either standalone programming application operate directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC ICE-Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge CY3202-C iMAGEcraft Compiler CY3202 optional upgrade PSoC Designer that enables iMAGEcraft compiler. purchased from Cypress Online Store. http://www.cypress.com/shop/ under Product Categories, click PSoC® Mixed Signal Arrays view current list available items.
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (may used with ICE-Cube InCircuit Emulator). provides access buses, voltage reference, switches, upgradeable modules more. includes:
PSoC Express Software Express Development Board Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Evaluation Tools
evaluation tools purchased from Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 allows user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
Device Programmers
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Modular Programmer Base Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production-programming environment. Note CY3207ISSP needs special software compatible with PSoC Programmer. includes:
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Accessories (Emulation Programming)
Table Emulation Programming Accessories Part Number CY8C20246-24LKXI CY8C20266-24LKXI CY8C20346-24LQXI CY8C20366-24LQXI CY8C20446-24LQXI CY8C20466-24LQXI CY8C20546-24PVXI CY8C20566-24PVXI CY8C20666-24LTXI Package SSOP SSOP Flex-Pod Kit[13] CY3250-20266QFN CY3250-20266QFN CY3250-20366QFN CY3250-20366QFN CY3250-20466QFN CY3250-20466QFN CY3250-20X66 CY3250-20X66 CY3250-20666QFN Foot Kit[14] CY3250-16QFN-FK CY3250-16QFN-FK CY3250-24QFN-FK CY3250-24QFN-FK CY3250-32QFN-FK CY3250-32QFN-FK CY3250-48SSOP-FK CY3250-48SSOP-FK CY3250-48QFN-FK Adapter[15] note note note note note note note note note
Third-Party Tools
Several tools have been specially designed following third-party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under Documentation Evaluation Boards.
Build PSoC Emulator into Your Board
details emulate your circuit before going volume production using on-chip debug (OCD) non-production PSoC device, refer Application Note "Debugging Build PSoC Emulator into Your Board AN2323" http://www.cypress.com/ AN2323.
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Ordering Information
following table lists CY8C20x46 CY8C20x66 PSoC devices package features ordering codes. Table PSoC Device Features Ordering Information Package (3x3 (3x3 (Tape Reel) (4x4 (4x4 (Tape Reel) (5x5 (5x5 (Tape Reel) 48-Pin SSOP 48-Pin SSOP (Tape Reel) (3x3 (3x3 (Tape Reel) (4x4 (4x4 (Tape Reel) (5x5 (5x5 (Tape Reel) 48-Pin SSOP 48-Pin SSOP (Tape Reel) (7x7 (7x7 (Tape Reel) (7x7 (OCD)(4) Ordering Code CY8C20246-24LKXI CY8C20246-24LKXIT CY8C20346-24LQXI CY8C20346-24LQXIT CY8C20446-24LQXI CY8C20446-24LQXIT CY8C20546-24PVXI CY8C20546-24PVXIT CY8C20266-24LKXI CY8C20266-24LKXIT CY8C20366-24LQXI CY8C20366-24LQXIT CY8C20466-24LQXI CY8C20466-24LQXIT CY8C20566-24PVXI CY8C20566-24PVXIT CY8C20666-24LTXI CY8C20666-24LTXIT CY8C20066-24LTXI Flash SRAM CapSense (Bytes) (Bytes) Blocks 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 2048 Digital Analog XRES Pins Inputs 13[16] 13[16] 20[16] 20[16] 28[16] 28[16] 36[16] 36[16] 13[16] 13[16] 20[16] 20[16] 28[16] 28[16] 36[16] 36[16] 36[16] 36[16] 36[16]
Notes Dual-function Digital Pins also connect common analog mux.
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Document History Page
Document Title: CY8C20x46 CY8C20x66 CapSenseApplications Document Number: 001-12696 Revision 766857 1242866 Origin Change Submission Date Description Change silicon document (Revision **). features. Update applicable sections. Update specs. 24-pin pinout moving pins inside. Update package revisions. Update Emulation Programming Accessories table. Added 48-Pin SSOP Part Pinout Modified symbol RVDD RGND Table Analog Specification Added footnote Table Analog Specification Added FLASH Parts. Updated Notes, Package Diagrams Ordering Information table. Updated Thermal Impedance Solder Reflow tables Converted from Preliminary Final Fixed broken links. Updated data sheet template. Added operating voltage ranges with resolution changed from 10-bit 8-bit Included specifications table Included Comparator specification table Included Voh7, Voh8, Voh9, Voh10 specs Flash data retention condition added Note Input leakage spec changed GPIO rise time ports ports made common Programming specifications updated Included Programming cycle timing diagram specification updated 3.0<Vdd<2.4 changed from Added specification Added P1[0] Updated package diagrams Updated thermal impedances packages Updated FGPIO parameter Table Updated voltage ranges FSPIM FSPIS Table Update Development Tools, Designing with PSoC Designer. Edit, links, notes table format. Update formula, TRise parameter names GPIO figure, Switch Rate note. Update maximum data Table Specifications.
2174006
AESA
2587518
TOF/JASM/MNU/
10/13/08
Document Number: 001-12696 Rev.
Page
Feedback
CY8C20x46, CY8C20x66
Sales, Solutions, Legal Information
Worldwide Sales Design Support
Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
Products
PSoC Clocks Buffers Wireless Memories Image Sensors psoc.cypress.com clocks.cypress.com wireless.cypress.com memory.cypress.com image.cypress.com
PSoC Solutions
General Power/Low Voltage Precision Analog Drive 2.0b psoc.cypress.com/solutions psoc.cypress.com/low-power psoc.cypress.com/lcd-drive psoc.cypress.com/can psoc.cypress.com/usb
CapSenseTM, PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corporation. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
Cypress Semiconductor Corporation, 2007-2008. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number: 001-12696 Rev.
Revised October 2008
Page
Feedback

CapSenseApplications Power CapSenseBlock Configurable Capacitive

Top Searches for this datasheet

Other recent searches