CapSensePSoC® Programmable System-on-Chip Power, Configurable Cap

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CapSensePSoC® Programmable System-on-Chip Power, Configurable Cap

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CY8C20224, CY8C20324 CY8C20424, CY8C20524
CapSensePSoC® Programmable System-on-Chip
Power, Configurable CapSense Configurable capacitive sensing elements 2.4V 5.25V operating voltage operating current Active 3.0V, MHz) Sleep 3.3V) Supports capacitive buttons Supports slider proximity sensing Supports General Purpose (GPIO) pins Drive LEDs other outputs Configurable behavior (fading, strobing) color mixing (RBG LEDs) Pull High Open Drain, CMOS drive modes GPIO Internal ±5.0% or12 main oscillator Internal speed oscillator external component count external crystal oscillator components external voltage regulator required
High Performance CapSense Ultra fast scan speed-1 (nominal) Reliable finger detection through thick acrylic Excellent noise immunity Industry Best Flexibility Flash program storage 50,000 Erase Write cycles bytes SRAM data storage Bootloader ease field reprogramming Partial Flash updates Flexible Flash protection modes Interrupt controller In-System Serial Programming (ISSP) Free complete development tool (PSoC DesignerTM) Full Featured, In-Circuit Emulator Programmer Full speed emulation Complex breakpoint structure 128K trace memory Additional System Resources Configurable communication speeds Slave Master Slave Watchdog Sleep timers Internal voltage reference Integrated supervisory circuit
Logic Block Diagram
Port Port Port Port
PSoC CORE
System
Global Analog Interconnect SRAM Bytes Interrupt Controller SROM Flash Sleep Watchdog
Core (M8C)
6/12 Internal Main Oscillator
ANALOG SYSTEM
CapSense Basic Block
Analog Ref.
Slave/SPI Master-Slave
System Resets
Analog
SYSTEM RESOURCES
Cypress Semiconductor Corporation Document Number: 001-41947 Rev.
Champion Court
Jose, 95134-1709
408-943-2600 Revised April 2009
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PSoC® Functional Overview
PSoC family consists many mixed-signal arrays with on-chip controller devices. These devices designed replace multiple traditional based system components with one, cost single chip programmable component. PSoC device includes configurable analog digital blocks, programmable interconnect. This architecture allows user create customized peripheral configurations, match requirements each individual application. Additionally, fast CPU, Flash program memory, SRAM data memory, configurable included range convenient pinouts. PSoC architecture this device family comprised three main areas: Core, System Resources, CapSense Analog System. common, versatile allows connection between analog system. Each PSoC device includes dedicated CapSense block that provides sensing scanning control circuitry capacitive sensing applications. Depending PSoC package, general purpose (GPIO) also included. GPIO provide access analog mux. Figure Analog System Block Diagram
IDAC
Analog Global
Reference Buffer
Cinternal
Comparator
Refs
PSoC Core
PSoC Core powerful engine that supports rich instruction set. encompasses SRAM data storage, interrupt controller, sleep watchdog timers, (internal main oscillator) (internal speed oscillator). core, called M8C, powerful processor with speeds MHz. 2-MIPS, 8-bit Harvard architecture microprocessor. System Resources provide additional capability, such configurable slave master-slave communication interface various system resets supported M8C. Analog System composed CapSense PSoC block internal 1.8V analog reference. Together, they support capacitive sensing inputs.
Sense Counters
CSCLK CapSense Clock Select Relaxation Oscillator (RO)
Analog Multiplexer System Analog connects every GPIO pin. Pins connected individually combination. also connects analog system analysis with CapSense block comparator. Switch control logic enables selected pins precharge continuously under hardware control. This enables capacitive measurement applications such touch sensing. Analog Multiplexer System device family optimized basic CapSense functionality. supports sensing CapSense buttons, proximity sensors, single slider. Other multiplexer applications include:
CapSense Analog System
Analog System contains capacitive sensing hardware. Several hardware algorithms supported. This hardware performs capacitive sensing scanning without requiring external components. Capacitive sensing configurable each GPIO pin. Scanning enabled CapSense pins completed quickly easily across multiple ports.
Capacitive slider interface. Chip-wide that allows analog input from pin. Crosspoint connection between combinations.
When designing capacitive sensing applications, refer latest signal noise signal level requirements application notes, which found http://www.cypress.com DESIGN RESOURCES Application Notes. general, unless otherwise noted relevant application notes, minimum signal-to-noise ratio (SNR) requirement CapSense applications 5:1.
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Typical Application Figure illustrates typical application: CapSense multimedia keys notebook computer with slider, four buttons, four LEDs. Figure CapSense Multimedia Button-Board Application
Getting Started
quickest understand PSoC silicon read this data sheet then PSoC Designer Integrated Development Environment (IDE). This data sheet overview PSoC integrated circuit presents specific pin, register, electrical specifications. depth information, along with detailed programming information, PSoC® Programmable System-on-Chip Technical Reference Manual CY8C28xxx PSoC devices. up-to-date ordering, packaging, electrical specification information, latest PSoC device data sheets www.cypress.com/psoc.
Application Notes Additional System Resources
System Resources, some which previously listed, provide additional capability useful complete systems. Additional resources include voltage detection power reset. Brief statements describing merits each system resource follow.
Application notes excellent introduction wide variety possible PSoC designs. They located here: www.cypress.com/psoc. Select Application Notes under Documentation tab.
Development Kits
PSoC Development Kits available online from Cypress www.cypress.com/shop through growing number regional global distributors, which include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, Newark.
slave master-slave module provides 100, communication over wires. communication over three four wires runs speeds 46.9 (lower slower system clock). Voltage Detection (LVD) interrupts signal application falling voltage levels, while advanced (Power Reset) circuit eliminates need system supervisor. internal 1.8V reference provides absolute reference capacitive sensing. maximum input, fixed output, dropout regulator (LDO) provides regulation IOs. register controlled bypass mode allows user disable LDO.
Training
Free PSoC technical training demand, webinars, workshops) available online www.cypress.com/training. training covers wide variety topics skill levels assist your designs.
Cypros Consultants
Certified PSoC Consultants offer everything from technical assistance completed PSoC designs. contact become PSoC Consultant www.cypress.com/cypros.
Solutions Library
Visit growing library solution focused designs www.cypress.com/solutions. Here find various application designs that include firmware hardware design files that enable complete your designs quickly.
Technical Support
assistance with technical issues, search KnowledgeBase articles forums www.cypress.com/support. cannot find answer your question, call technical support 1-800-541-4736.
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Development Tools
PSoC Designer Microsoft® Windows-based, integrated development environment Programmable System-on-Chip (PSoC) devices. PSoC Designer runs Windows Windows Vista. This system provides design database management project, integrated debugger with In-Circuit Emulator, in-system programming support, built-in support third-party assemblers compilers. PSoC Designer also supports language compilers developed specifically devices PSoC family. Code Generation Tools PSoC Designer supports multiple third party compilers assemblers. code generation tools work seamlessly within PSoC Designer interface have been tested with full range debugging tools. choice yours. Assemblers. assemblers allow assembly code merge seamlessly with code. Link libraries automatically absolute addressing compiled relative mode, linked with other software modules absolute addressing. Language Compilers. language compilers available that support PSoC family devices. products allow create complete programs PSoC family devices. optimizing compilers provide features tailored PSoC architecture. They come complete with embedded libraries providing port operations, standard keypad display support, extended math functionality. Debugger PSoC Designer Debugger subsystem provides hardware in-circuit emulation, allowing test program physical system while providing internal view PSoC device. Debugger commands allow designer read program read write data memory, read write registers, read write registers, clear breakpoints, provide program run, halt, step control. debugger also allows designer create trace buffer registers memory locations interest. Online Help System online help system displays online, context-sensitive help user. Designed procedural quick reference, each functional subsystem context-sensitive help. This system also provides tutorials links FAQs Online Support Forum designer getting started.
PSoC Designer Software Subsystems
System-Level View drag-and-drop visual embedded system design environment based PSoC Express. system level view create model your system inputs, outputs, communication interfaces. define when output device changes state based upon other system devices. Based upon design, PSoC Designer automatically selects more PSoC Mixed-Signal Controllers that match your system requirements. PSoC Designer generates embedded code, then compiles links into programming file specific PSoC device. Chip-Level View chip-level view more traditional integrated development environment (IDE) based PSoC Designer 4.4. Choose base device work with then select different onboard analog digital components called user modules that PSoC blocks. Examples user modules ADCs, DACs, Amplifiers, Filters. Configure user modules your chosen application connect them each other proper pins. Then generate your project. This prepopulates your project with APIs libraries that program your application. device editor also supports easy development multiple configurations dynamic reconfiguration. Dynamic configuration allows changing configurations time. Hybrid Designs begin system-level view, allow choose configure your user modules, routing, generate code, then switch chip-level view gain complete control over on-chip resources. views project share common code editor, builder, common debug, emulation, programming tools.
In-Circuit Emulator
cost, high functionality In-Circuit Emulator (ICE) available development support. This hardware capability program single devices. emulator consists base unit that connects port. base unit universal operates with PSoC devices. Emulation pods each device family available separately. emulation takes place PSoC device target board performs full speed MHz) operation.
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Designing with PSoC Designer
development process PSoC device differs from that traditional fixed function microprocessor. configurable analog digital hardware blocks give PSoC architecture unique flexibility that pays dividends managing specification change during development lowering inventory costs. These configurable resources, called PSoC Blocks, have ability implement wide variety user-selectable functions. PSoC development process summarized following four steps: Select components Configure components Organize Connect Generate, Verify, Debug property, other information need successfully implement your design.
Organize Connect
build signal chains chip level interconnecting user modules each other pins, connect system level inputs, outputs, communication interfaces each other with valuator functions. system-level view, selecting potentiometer driver control variable speed driver setting valuators control speed based input from selects, places, routes, configures programmable gain amplifier (PGA) buffer input from potentiometer, analog digital converter (ADC) convert potentiometer's output digital signal, control fan. chip-level view, perform selection, configuration, routing that have complete control over on-chip resources.
Select Components
Both system-level chip-level views provide library prebuilt, pretested hardware peripheral components. system-level view, these components called "drivers" correspond inputs thermistor, example), outputs brushless fan, example), communication interfaces (I2C-bus, example), logic control they interact with another (called valuators). chip-level view, components called "user modules". User modules make selecting implementing peripheral devices simple, come analog, digital, mixed signal varieties.
Generate, Verify, Debug
When ready test hardware configuration move developing code project, perform "Generate Application" step. This causes PSoC Designer generate source code that automatically configures device your specification provides software system. Both system-level chip-level designs generate software based your design. chip-level design provides application programming interfaces (APIs) with high level functions control respond hardware events run-time interrupt service routines that adapt needed. system-level design also generates main() program that completely controls chosen application contains placeholders custom code strategic positions allowing further refine software without disrupting generated code. complete code development environment allows develop customize your applications assembly language, both. last step development process takes place inside PSoC Designer's Debugger subsystem. Debugger downloads image where runs full speed. Debugger capabilities rival those systems costing many times more. addition traditional single-step, run-to-breakpoint watch-variable features, Debugger provides large trace buffer allows define complex breakpoint events that include monitoring address data values, memory locations external signals.
Configure Components
Each components select establishes basic register settings that implement selected function. They also provide parameters properties that allow tailor their precise configuration your particular application. example, Pulse Width Modulator (PWM) User Module configures more digital PSoC blocks, each bits resolution. user module parameters permit establish pulse width duty cycle. Configure parameters properties correspond your chosen application. Enter values directly selecting values from drop-down menus. Both system-level drivers chip-level user modules documented data sheets that viewed directly PSoC Designer. These data sheets explain internal operation component provide performance specifications. Each data sheet describes each user module parameter driver
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Document Conventions
Acronyms Used
following table lists acronyms that used this document. Table List Acronyms Acronym GPIO PPOR PSoC® SLIMO SRAM Description Alternating Current Application Programming Interface Central Processing Unit Direct Current General Purpose Graphical User Interface In-Circuit Emulator Internal Speed Oscillator Internal Main Oscillator Input Output Least Significant Voltage Detect Most Significant Power Reset Precision Power Reset Programmable System-on-Chip® Slow Static Random Access Memory
Units Measure
units measure table located Electrical Specifications section. Table page lists abbreviations used measure PSoC devices.
Numeric Naming
Hexadecimal numbers represented with letters uppercase with appended lowercase (for example, `14h' `3Ah'). Hexadecimal numbers also represented `0x' prefix, coding convention. Binary numbers have appended lowercase (for example, 01010100b' `01000011b'). Numbers indicated `h', `b', decimal.
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Pinouts
This section describes, lists, illustrates CY8C20224, CY8C20324, CY8C20424, CY8C20524 PSoC device pins pinout configurations. PSoC device available variety packages which listed illustrated following tables. Every port (labeled with "P") capable Digital connection common analog bus. However, Vss, Vdd, XRES capable Digital
16-Pin Part Pinout
Figure CY8C20224 16-Pin PSoC Device
P0[1], P0[3], P0[7],
CLK, SCL, MOSI P1[1]
CLK, P1[3]
Table 16-Pin Part Pinout (COL) Digital Power Input Power Analog Name P2[5] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] XRES P0[4] P0[7] P0[3] P0[1] Description
SCL, SDA, MISO CLK[1], SCL, MOSI Ground connection DATA[1], Optional external clock input (EXTCLK) Active high external reset with internal pull down Supply voltage Integrating input Integrating input
Analog, Input, Output, High Output Drive
Note These ISSP pins, that High (Power Reset). Refer PSoC Programmable System-on-Chip Technical Reference Manual details.
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DATA, SDA, P1[0]
XRES
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24-Pin Part Pinout
Figure CY8C20324 24-Pin PSoC Device
P0[1], P0[3], P0[5], P0[7], P0[6], EXTCLK, P1[4] P0[4], P0[2], P0[0], P2[0], XRES P1[6],
Table 24-Pin Part Pinout (QFN [2]) Digital Power Input Power Power Analog Name P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P0[0] P0[2] P0[4] P0[6] P0[7] P0[5] P0[3] P0[1] Description
SCL, SDA, MISO CLK[1], SCL, MOSI connection Ground connection DATA[1], Optional external clock input (EXTCLK) Active high external reset with internal pull down
Supply voltage
Integrating input Integrating input Center connected ground
Analog, Input, Output, High Output Drive
Note center package connected ground (Vss) best mechanical, thermal, electrical performance. connected ground, electrically floated connected other signal.
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DATA*, SDA, P1[0] P1[2]
CLK*, MOSI, P1[1]
SCL, SDA, MISO, CLK,
P2[5] P2[3] P2[1] P1[7] P1[5] P1[3]
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28-Pin Part Pinout
Figure CY8C20524 28-Pin PSoC Device
Table 28-Pin Part Pinout (SSOP) Digital Analog Power Power Input Power Name P0[7] P0[5] P0[3] P0[1] P2[7] P2[5] P2[3] P2[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] Description
Integrating Input Integrating Input
Ground connection SCL, SDA, MISO CLK[1], SCL, MOSI Ground connection Data[1], Optional External Clock Input (EXTCLK) Active high external reset with internal pull down
Supply voltage
Analog, Input, Output, High Output Drive
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32-Pin Part Pinout
Figure CY8C20424 32-Pin PSoC Device
P0[3], P0[7], P0[6], P0[4], P0[5], P0[2],
CLK, P1[3]
SDA, MISO, P1[5]
CLK*, SCL, MOSI, P1[1]
DATA*, SDA, P1[0]
EXTCLK, P1[4]
P1[2]
Table 32-Pin Part Pinout (QFN [2]) Input Digital Power Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] P1[5] P1[3] P1[1] P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] Page Active high external reset with internal pull down Optional external clock input (EXTCLK) SCL, SDA, MISO CLK[1], SCL, MOSI Ground connection DATA[1], Integrating Input Description
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P1[6]
XRES
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Table 32-Pin Part Pinout (QFN [2]) (continued) Power Power Digital Power Analog Name P0[4] P0[6] P0[7] P0[5] P0[3] Integrating input Ground connection Center connected ground Supply voltage Description
Analog, Input, Output, High Output Drive
48-Pin Part Pinout
48-Pin part table diagram CY8C20024 On-Chip Debug (OCD) PSoC device. This part only used in-circuit debugging. available production. Figure CY8C20024 PSoC Device
P0[3], P0[5], P0[7], P0[6], OCDO OCDE
P0[4], P0[2], P0[0], P2[6], P2[4], P2[2], P2[0], P3[2], P3[0], XRES P1[6], P1[4], EXTCLK,
P1[2] DATA*, SDA, P1[0]
HCLK
CLK, P1[3]
CLK*, SCL, MOSI, P1[1]
Table 48-Pin Part Pinout (QFN [2]) Digital Analog Name P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] P1[7] SCL, connection Integrating Input Description
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CCLK
P0[1] P2[7] P2[5] P2[3] P2[1] P3[3] P3[1] SCL, P1[7] SDA, MISO, P1[5]
(Top View)
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Table 48-Pin Part Pinout (QFN [2]) (continued) Power Power Power Input Power Digital Analog Name P1[5] P1[3] P1[1] CCLK HCLK P1[0] P1[2] P1[4] P1[6] XRES P3[0] P3[2] P2[0] P2[2] P2[4] P2[6] P0[0] P0[2] P0[4] P0[6] OCDO OCDE P0[7] P0[5] P0[3] Integrating input Ground connection connection Center connected ground Supply voltage data output even data connection connection connection Active high external reset with internal pull down connection connection connection Optional external clock input (EXTCLK) SDA, MISO connection connection connection connection CLK[1], SCL, MOSI Ground connection clock output high speed clock output DATA[1],
Description
Analog, Input, Output, Connection High Output Drive.
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Electrical Specifications
This section presents electrical specifications CY8C20224, CY8C20324, CY8C20424, CY8C20524 PSoC devices. latest electrical specifications, visit http://www.cypress.com/psoc. Specifications valid -40oC 85oC 100oC specified, except where noted. Refer Table page electrical specifications internal main oscillator (IMO) using SLIMO mode. Figure Voltage versus Frequency Frequency Trim Options
5.25 5.25
SLIMO SLIMO SLIMO Mode=1 Mode=1 Mode=0
4.75 Voltage 4.75 Voltage
rati
3.60
3.00 2.70 2.40
3.00 2.70 2.40
SLIMO SLIMO Mode=1 Mode=0 SLIMO Mode=1
SLIMO Mode=0
Frequency
Frequency
following table lists units measure that used this section. Table Units Measure Symbol Kbit Vrms Unit Measure degree Celsius decibels femto farad hertz 1024 bytes 1024 bits kilohertz kilohm megahertz megaohm microampere microfarad microhenry microsecond microvolts microvolts root-mean-square Symbol Unit Measure microwatts milli-ampere milli-second milli-volts nanoampere nanosecond nanovolts picoampere picofarad peak-to-peak parts million picosecond samples second sigma: standard deviation volts
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Absolute Maximum Ratings
Table Absolute Maximum Ratings Symbol TSTG Description Storage Temperature +100 Units Notes Higher storage temperatures reduces data retention time. Recommended storage temperature +25oC 25oC. Extended duration storage temperatures above 65oC degrades reliability.
VIOZ IMIO
Ambient Temperature with Power Applied Supply Voltage Relative Input Voltage Voltage Applied Tri-state Maximum Current into Port Electro Static Discharge Voltage Latch-up Current
-0.5 2000
+6.0
Human Body Model ESD.
Operating Temperature
Table Operating Temperature Symbol Description Ambient Temperature Junction Temperature +100 Units Notes temperature rise from ambient junction package specific. Table page user must limit power consumption comply with this requirement.
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Electrical Characteristics
Chip Level Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Chip Level Specifications Symbol Description Supply Voltage IDD12 Supply Current, IDD6 ISB27 Supply Current, Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Slow Oscillator Active. Temperature Range. Sleep (Mode) Current with POR, LVD, Sleep Timer, WDT, Internal Slow Oscillator Active. 2.40 5.25 Units Notes Conditions 3.0V, 25oC, MHz. Conditions 3.0V, 25oC, MHz. 2.55V, 40oC. 3.3V, -40oC 85oC.
General Purpose Specifications Unless otherwise noted, Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V GPIO Specifications Symbol VOH1 VOH2 VOH3 VOH4 VOH5 VOH6 VOH7 VOH8 VOH9 Pull Resistor High Output Voltage Port Pins High Output Voltage Port Pins High Output Voltage Port Pins with Regulator Disabled High Output Voltage Port Pins with Regulator Disabled High Output Voltage Port Pins with 3.0V Regulator Enabled High Output Voltage Port Pins with 3.0V Regulator Enabled High Output Voltage Port Pins with 2.4V Regulator Enabled High Output Voltage Port Pins with 2.4V Regulator Enabled High Output Voltage Port Pins with 1.8V Regulator Enabled Description Units 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. IOH<10 3.1V, maximum sourcing 3.1V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V, maximum source current IOs. 3.0V 3.6V 85oC Maximum source current IOs. Notes
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Table 3.3V GPIO Specifications (continued) Symbol VOH10 Description High Output Voltage Port Pins with 1.8V Regulator Enabled Units Notes 3.0V 3.6V 85oC Maximum source current IOs. 3.0V, maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]). 3.0V 5.25V 3.0V 5.25V Gross tested Package dependent temperature 25oC Package dependent temperature 25oC
Output Voltage
0.75
COUT
Input Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
Table 2.7V GPIO Specifications Symbol VOH1 VOH2 Pull Resistor High Output Voltage Port Pins with Regulator Disabled High Output Voltage Port Pins with Regulator Disabled Output Voltage Description 0.75 Units maximum source current IOs. maximum source current IOs. maximum sink current even port pins (for example, P0[2] P1[4]) sink current port pins (for example, P0[3] P1[5]). IOL=5 Maximum sink current even port pins (for example, P0[2] P3[4]) sink current port pins (for example, P0[3] P2[5]). 2.4V 3.0V 2.4V 3.0V 2.4V 2.7V 2.7V 3.0V Gross tested Package dependent temperature 25oC Package dependent temperature 25oC Notes
VOLP1
Output Voltage Port Pins
VIH1 VIH2 COUT
Input Voltage Input High Voltage Input High Voltage Input Hysteresis Voltage Input Leakage (Absolute Value) Capacitive Load Pins Input Capacitive Load Pins Output
0.75
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Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Analog Specifications Symbol Description Switch Resistance Common Analog Units Notes 2.7V 2.4V 2.7V
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C. These design guidance only. Table Power Comparator Specifications Symbol VREFLPC ISLPC VOSLPC Description power comparator (LPC) reference voltage range supply current voltage offset Units Notes
Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Specifications Symbol Description 2.39 2.54 2.75 2.85 2.96 4.52 2.36 2.60 2.82 2.45 2.71 2.92 3.02 3.13 4.73 2.40 2.65 2.95 2.51[3] 2.78[4] 2.99[5] 3.09 3.20 4.83 Units Notes greater than equal 2.5V during startup, reset from XRES pin, reset from Watchdog. Value PPOR Trip VPPOR0 PORLEV[1:0] VPPOR1 PORLEV[1:0] VPPOR2 PORLEV[1:0] VLVD0 VLVD1 VLVD2 VLVD3 VLVD4 VLVD5 VLVD6 VLVD7 Value Trip VM[2:0] 000b VM[2:0] 001b VM[2:0] 010b VM[2:0] 011b VM[2:0] 100b VM[2:0] 101b VM[2:0] 110b VM[2:0] 111b
Notes Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply. Always greater than above VPPOR (PORLEV falling supply.
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Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Programming Specifications Symbol Description VddIWRITE Supply Voltage Flash Write Operations IDDP Supply Current During Programming Verify VILP Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total)[6] FlashDR Flash Data Retention 2.70 -1.0 50,000 1,800,0 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
Note maximum 50,000 block endurance cycles allowed. This balanced between operations 36x1 blocks 50,000 maximum cycles each, 36x2 blocks 25,000 maximum cycles each, 36x4 blocks 12,500 maximum cycles each limit total number cycles 36x50,000 that single block ever sees more than 50,000 cycles).
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Electrical Characteristics
Chip Level Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V Chip-Level Specifications Symbol FCPU1 F32K1 FIMO12 Description Frequency (3.3V Nominal) Internal Speed Oscillator Frequency Internal Main Oscillator Stability (Commercial Temperature)[7] 0.75 11.4 12.6 12.6 Units Notes only SLIMO Mode Trimmed 3.3V operation using factory trim values. Figure page SLIMO Mode Trimmed 3.3V operation using factory trim values. Figure page SLIMO Mode
FIMO6
Internal Main Oscillator Stability (Commercial Temperature)
5.70
6.30
DCIMO TRAMP TXRST
Duty Cycle Supply Ramp Time External Reset Pulse Width
Table 2.7V Chip Level Specifications Symbol FCPU1A FCPU1B F32K1 FIMO12 Description Frequency (2.7V Nominal) Frequency (2.7V Minimum) Internal Speed Oscillator Frequency Internal Main Oscillator Stability (Commercial Temperature)[7] 0.75 0.75 11.0 3.25 12.9 Units Notes 2.4V 3.0V. 2.7V 3.0V. Trimmed 2.7V operation using factory trim values. Figure page SLIMO Mode Trimmed 2.7V operation using factory trim values. Figure page SLIMO Mode
FIMO6
Internal Main Oscillator Stability (Commercial Temperature)
5.60
6.40
DCIMO TRAMP TXRST
Duty Cycle Supply Ramp Time External Reset Pulse Width
Note ambient,
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General Purpose Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V GPIO Specifications Symbol Description FGPIO GPIO Operating Frequency TRise023 Rise Time, Strong Mode, Cload Ports TRise1 Rise Time, Strong Mode, Cload Port TFall Fall Time, Strong Mode, Cload Ports Table 2.7V GPIO Specifications Symbol FGPIO Description GPIO Operating Frequency Units Notes Normal Strong Mode, Port 3.0V, 3.0V, 3.0V, Units Notes Normal Strong Mode, Port 3.6V 4.75V 5.25V, 3.6V, 3.6V 4.75V 5.25V,
TRise023 Rise Time, Strong Mode, Cload Ports TRise1 Rise Time, Strong Mode, Cload Port TFall Fall Time, Strong Mode, Cload Ports
Figure GPIO Timing Diagram
GPIO Output Voltage
TRise023 TRise1
TFall
Comparator Amplifier Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Operational Amplifier Specifications Symbol TCOMP Description Comparator Response Time, Overdrive Units Notes 3.0V 2.4V 3.0V
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Analog Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Analog Specifications Symbol Description Switch Rate 3.17 Units Notes
Power Comparator Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 25°C. These design guidance only. Table Power Comparator Specifications Symbol TRLPC Description response time Units Notes overdrive comparator reference within VREFLPC.
External Clock Specifications Table Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table External Clock Specifications Symbol FOSCEXT Frequency High Period Period Power Switch Description 0.750 12.6 5300 Units Notes
Table 3.3V External Clock Specifications Symbol FOSCEXT Description Frequency with Clock divide 0.750 12.6 Units Notes Maximum frequency 3.3V. With clock divider external clock must adhere maximum frequency duty cycle requirements.
High Period with Clock divide Period with Clock divide Power Switch
41.7 41.7
5300
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Table 2.7V External Clock Specifications Symbol Description 0.75 3.08
Units
Notes 2.4V 3.0V. Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. 2.7V 3.0V. Maximum frequency 2.7V. With clock divider external clock must adhere maximum frequency duty cycle requirements. 2.4V 3.0V. frequency external clock greater than MHz, clock divider greater. this case, clock divider ensures that fifty percent duty cycle requirement met. 2.7V 3.0V. frequency external clock greater than MHz, clock divider greater. this case, clock divider ensures that fifty percent duty cycle requirement met.
FOSCEXT1A Frequency with Clock divide (2.7V Nominal)
FOSCEXT1B Frequency with Clock divide (2.7V Minimum)
0.75
6.30
FOSCEXT2A Frequency with Clock divide greater (2.7V Nominal)
6.35
FOSCEXT2B Frequency with Clock divide greater (2.7V Minimum)
12.6
High Period with Clock divide Period with Clock divide Power Switch
5300
Programming Specifications Table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Programming Specifications Symbol TRSCLK TFSCLK TSSCLK THSCLK FSCLK TERASEB TWRITE TDSCLK TDSCLK3 TDSCLK2 Description Rise Time SCLK Fall Time SCLK Data Time Falling Edge SCLK Data Hold Time from Falling Edge SCLK Frequency SCLK Flash Erase Time (Block) Flash Block Write Time Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Data Delay from Falling Edge SCLK Units Notes
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Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table 3.3V Specifications Symbol FSPIM FSPIS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width Negated Between Transmissions 2.05 Units Notes Output clock frequency half input clock rate.
Table 2.7V Specifications Symbol FSPIM FSPIS Description Maximum Input Clock Frequency Selection, Master Maximum Input Clock Frequency Selection, Slave Width Negated Between Transmissions 3.15 1.025 Units Notes Output clock frequency half input clock rate
Specifications Table Table list guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C 85°C, 3.0V 3.6V -40°C 85°C, 2.4V 3.0V -40°C 85°C respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Table Characteristics Pins 3.0V Symbol FSCLI2C Description Clock Frequency Standard Mode Fast Mode Units Notes
THDSTAI2C Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock TLOWI THIGHI2C HIGH Period Clock TSUSTAI2C Setup Time Repeated START Condition Data Hold Time THDDATI TSUDATI2C Data Setup Time TSUSTOI2C Setup Time STOP Condition TBUFI2C TSPI2C Free Time Between STOP START Condition Pulse Width spikes suppressed input filter
100[8]
Note Fast Mode device used Standard Mode system requirement tSU; met. This automatically case device does stretch period signal. such device does stretch period signal, must output next data line trmax tSU; 1000 1250 (according Standard Mode specification) before line released.
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Table 2.7V Characteristics Pins (Fast Mode Supported) Symbol FSCLI2C
Description Clock Frequency.
Standard Mode
Fast Mode
Units
Notes
THDSTAI Hold Time (repeated) START Condition. After this period, first clock pulse generated. Period Clock. TLOWI2C THIGHI
HIGH Period Clock.
TSUSTAI Setup Time Repeated START Condition. THDDATI Data Hold Time. TSUDATI Data Setup Time.
TSUSTOI2C TBUFI2C TSPI2C
Setup Time STOP Condition. Free Time Between STOP START Condition. Pulse Width spikes suppressed input filter.
Figure Definition Timing Fast Standard Mode
LOWI2C SUDATI2C HDSTAI2C
SPI2C BUFI2C
HDSTAI2C HDDATI2C HIGHI2C SUSTAI2C SUSTOI2C
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Packaging Dimensions
This section illustrates packaging specifications CY8C20224, CY8C20324, CY8C20424, CY8C20524 PSoC devices, along with thermal impedances each package. Important Note Emulation tools require larger area target than chip's footprint. detailed description emulation tools' dimensions, refer document titled PSoC Emulator Dimensions Figure 16-Pin (3x3 MAX)
001-09116
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Figure 24-Pin (4x4
001-13937
CYPRESS
Figure 28-Pin (210-Mil) SSOP
51-85079
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Figure 32-Pin (5x5 0.60 MAX)
001-06392
Figure 32-Pin (5X5X 0.60 Max)
001-48913
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Figure 48-Pin (7x7
001-12919
Important information preferred dimensions mounting packages, following application note important note that pinned vias thermal conduction required power 48-pin PSoC devices.
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Thermal Impedances
Table Thermal Impedances Package Package QFN[10] SSOP QFN[10] QFN[10] Typical oC/W oC/W oC/W oC/W oC/W
Solder Reflow Peak Temperature
Table lists minimum solder reflow peak temperature achieve good solderability. Table Solder Reflow Peak Temperature Package SSOP Minimum Peak Temperature [11] 240oC 240oC 240oC 240oC 240oC Maximum Peak Temperature 260oC 260oC 260oC 260oC 260oC
Notes Power achieve thermal impedance specified package, center thermal soldered ground plane. Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications.
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Development Tool Selection
Software
PSoC DesignerAt core PSoC development software suite PSoC Designer. This used thousands PSoC developers. This robust software facilitating PSoC designs half decade. PSoC Designer available free charge http://www.cypress.com under DESIGN RESOURCES Software Drivers. PSoC Programmer PSoC Programmer flexible enough used bench development also suitable factory programming. PSoC Programmer works either standalone programming application operates directly from PSoC Designer PSoC Express. PSoC Programmer software compatible with both PSoC Cube In-Circuit Emulator PSoC MiniProg. PSoC programmer available free charge Compilers PSoC Designer comes with free HI-TECH Lite compiler. HI-TECH Lite compiler free, supports PSoC devices, integrates fully with PSoC Designer PSoC Express, runs Windows versions 32-bit Vista. Compilers with additional features available additional cost from their manufactures.
Development Kits
development kits sold Cypress Online Store. CY3215-DK Basic Development CY3215-DK prototyping development with PSoC Designer. This supports in-circuit emulation software interface enables users run, halt, single step processor view content specific memory locations. PSoC Designer supports advance emulation features also. includes:
PSoC Designer Software ICE-Cube In-Circuit Emulator Flex-Pod CY8C29x66 Family Cat-5 Adapter Mini-Eval Programming Board 240V Power Supply, Euro-Plug Adapter iMAGEcraft Compiler (Registration Required) ISSP Cable Cable Blue Cat-5 Cable CY8C29466-24PXI 28-PDIP Chip Samples
HI-TECH PSoC available from http://www.htsoft.com. ImageCraft Cypress Edition Compiler available from http://www.imagecraft.com.
CY3210-ExpressDK PSoC Express Development CY3210-ExpressDK advanced prototyping development with PSoC Express (used with ICE-Cube In-Circuit Emulator). provides access buses, voltage reference, switches, upgradeable modules, more. includes:
PSoC Express Software Express Development Board Four Modules Proto Modules MiniProg In-System Serial Programmer MiniEval Evaluation Board Jumper Wire Cable Serial Cable (DB9) 240V Power Supply, Euro-Plug Adapter CY8C24423A-24PXI 28-PDIP Chip Samples CY8C27443-24PXI 28-PDIP Chip Samples CY8C29466-24PXI 28-PDIP Chip Samples
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Evaluation Tools
evaluation tools sold Cypress Online Store. CY3210-MiniProg1 CY3210-MiniProg1 enables user program PSoC devices MiniProg1 programming unit. MiniProg small, compact prototyping programmer that connects provided cable. includes:
Device Programmers
device programmers purchased from Cypress Online Store. CY3216 Modular Programmer CY3216 Modular Programmer features modular programmer MiniProg1 programming unit. modular programmer includes three programming module cards supports multiple Cypress products. includes:
MiniProg Programming Unit MiniEval Socket Programming Evaluation Board 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample 28-Pin CY8C27443-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
Modular Programmer Base Three Programming Module Cards MiniProg Programming Unit PSoC Designer Software Getting Started Guide Cable
CY3207ISSP In-System Serial Programmer (ISSP) CY3207ISSP production programmer. includes protection circuitry industrial case that more robust than MiniProg production programming environment. Note that CY3207ISSP needs special software compatible with PSoC Programmer. includes:
CY3210-PSoCEval1 CY3210-PSoCEval1 features evaluation board MiniProg1 programming unit. evaluation board includes module, potentiometer, LEDs, plenty breadboarding space meet your evaluation needs. includes:
CY3207 Programmer Unit PSoC ISSP Software 240V Power Supply, Euro-Plug Adapter Cable
Evaluation Board with Module MiniProg Programming Unit 28-Pin CY8C29466-24PXI PDIP PSoC Device Sample PSoC Designer Software Getting Started Guide Cable
CY3214-PSoCEvalUSB CY3214-PSoCEvalUSB evaluation features development board CY8C24794-24LFXI PSoC device. Special features board include both capacitive sensing development debugging support. This evaluation board also includes module, potentiometer, LEDs, enunciator plenty bread boarding space meet your evaluation needs. includes:
PSoCEvalUSB Board Module MIniProg Programming Unit Mini Cable PSoC Designer Example Projects Getting Started Guide Wire Pack
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Accessories (Emulation Programming)
Table Emulation Programming Accessories Part Number CY8C20224-12LKXI CY8C20324-12LQXI CY8C20524-12PVXI CY8C20424-12LKXI Third Party Tools Several tools specially designed following third party vendors accompany PSoC devices during development production. Specific details each these tools found http://www.cypress.com under DESIGN RESOURCES Evaluation Boards. Package SSOP Flex-Pod [12] available CY3250-20334QFN CY3250-20534 CY3250-20434QFN Foot [13] available CY3250-24QFN-FK CY3250-28SSOP-FK CY3250-32QFN-FK Prototyping Module CY3210-20X34 CY3210-20X34 CY3210-20X34 CY3210-20X34 Adapter [14] AS-24-28-01ML-6 AS-32-28-03ML-6
Build PSoC Emulator into Your Board details emulating circuit before going volume production using on-chip debug (OCD) non-production PSoC device, refer application note AN2323 "Build PSoC Emulator into Your Board".
Notes Flex-Pod includes practice flex-pod practice PCB, addition flex-pods. Foot includes surface mount feet that soldered target PCB. Programming adapter converts non-DIP package footprint. Specific details ordering information each adapters found http://www.emulation.com.
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Ordering Information
Table lists CY8C20224, CY8C20324, CY8C20424, CY8C20524 PSoC devices package features ordering codes. Table PSoC Device Features Ordering Information
Package Ordering Code Maximum Maximum Maximum Flash SRAM Number Number Number (Bytes) (Bytes) Buttons Sliders LEDs Configurable Behavior (Fade, Strobe) Proximity Sensing
16-Pin (3x3 0.60 MAX) CY8C20224-12LKXI 16-Pin (3x3 0.60 MAX) CY8C20224-12LKXIT (Tape Reel) 24-Pin (4x4 0.60 MAX) CY8C20324-12LQXI 24-Pin (4x4 0.60 MAX) CY8C20324-12LQXIT (Tape Reel) 28-Pin (210-Mil) SSOP 28-Pin (210-Mil) SSOP (Tape Reel) CY8C20524-12PVXI CY8C20524-12PVXIT
32-Pin (5x5 0.60 MAX) CY8C20424-12LKXI 32-Pin (5x5 0.60 MAX) CY8C20424-12LKXIT (Tape Reel) 32-Pin (5X5 0.60 MAX) (Sawn) 32-Pin (5X5 0.60 MAX) (Sawn) CY8C20424-12LQXI CY8C20424-12LQXIT
Note sales information, contact local Cypress sales office Field Applications Engineer (FAE). Figure Ordering Code Definitions xxx- Package Type:
PDIP Pb-Free Commercial SOIC Pb-Free Industrial SSOP Pb-Free Extended LFX/LKX/LQX= Pb-Free TQFP Pb-Free
Thermal Rating:
Speed: Part Number Family Code Technology Code: CMOS Marketing Code: Cypress PSoC Company Cypress
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Document History Page
Document Title: CY8C20224, CY8C20324, CY8C20424, CY8C20524, CapSensePSoC® Programmable System-on-ChipDocument Number: 001-41947 Revision 1734104 2542938 2610469 2634376 Orig. Change YHW/AESA RLRM/AESA SNV/PYRS DRSW Submission Date 07/28/2008 11/20/08 01/12/09 Description Change parts document (Revision **). Corrected Ordering Information format. Updated package diagram 001-13937 Updated data sheet template. Updated VOH5, VOH7, VOH9 specifications. Removed part number CY3250-20234QFN from 'CY8C20224-12LKXI' flex-pod Changed title from CapSenseMultimedia PSoC® Mixed-Signal Array CapSenseMultimedia PSoC® Programmable System-on-ChipAdded CY8C20524 parts Ordering Information table Updated `Development Tools' `Designing with PSoC Designer' sections pages Updated `Development Tools Selection' section page Changed status from `Preliminary' `Final' Changed 16-Pin from Added 32-Pin Sawn package diagram Added devices CY8C20424-12LQXI CY8C20424-12LQXIT Ordering Information table
2693024
DPT/PYRS
04/16/2009
Sales, Solutions, Legal Information
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Cypress maintains worldwide network offices, solution centers, manufacturer's representatives, distributors. find office closest you, visit cypress.com/sales.
Products
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PSoC Solutions
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Cypress Semiconductor Corporation, 2008-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
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PSoC Designerand Programmable System-on-Chipare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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