CapSense Express- Configurable CapSense Expresscontroller allows

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CapSense Express- Configurable CapSense Expresscontroller allows

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CY8C20160
CapSense Express- Configurable
CapSense Expresscontroller allows control configurable capacitive sensing buttons GPIOs driving LEDs interrupt signals based various button conditions. GPIOs also configurable waking device from sleep based interrupt input. user ability configure buttons, outputs, parameters, through specific commands sent port. have flexibility mapping capacitive buttons standard GPIO functions such interrupt output input, drive, digital mapping input output using simple logical operations. This enables easy trace routing reduces size stack CapSense Express products designed easy integration into complex products.
configurable supporting CapSensebuttons drive Interrupt outputs WAKE interrupt input Bi-directional sleep control User defined input output 2.4V 2.9V, 3.10V 3.6V, 4.75V 5.25V operating voltage Industrial temperature range: -40°C +85°C slave interface configuration data transfer rate kbps Reduce cost Internal oscillator external oscillators crystal Free development tool external tuning components operating current Active current: Deep sleep current: Available 16-pin 16-pin SOIC packages
Architecture
logic block diagram shows internal architecture CY8C20160. user configure registers with parameters needed adjust operation sensitivity CapSense system. CY8C20160 supports standard serial communication interface that allows host configure device read sensor information real time through easy register access.
CapSense Express Core
CapSense Express core powerful configuration control block. encompasses SRAM data storage, interrupt controller, sleep watchdog timers. System resources provide additional capability, such configurable slave communication interface various system resets. Analog System contains CapSense PSoC block which supports capacitive sensing inputs.
Cypress Semiconductor Corporation Document Number:001-17347 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised January 2009
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CY8C20160
Logic Block Diagram
External 2.40V 2.90V, 3.10V 3.60V, 4.75V 5.25V CapSense ExpressCore SYSTEM
Configurable
512B SRAM
Flash
Interrupt Controller
Configuration Control Engine
Sleep Watchdog
Clock Sources
(Internal Main Oscillator)
SYSTEM
CapSense Block
Slave
Voltage Current Reference
System Reset
POR/LVD
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CY8C20160
Pinouts
Figure Diagram
(TOP VIEW)
Table Definitions COL[1] Number Name GP0[0] GP0[1]
Description Configurable CapSense GPIO Configurable CapSense GPIO clock data Configurable CapSense GPIO Configurable CapSense GPIO Ground connection Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Active HIGH external reset with internal pull down Configurable CapSense GPIO Supply voltage Configurable CapSense GPIO Integrating capacitor input. external capacitance required only cannot achieved. Typical range Configurable CapSense GPIO
GP1[0] GP1[1] GP1[2] GP1[3] GP1[4] XRES GP0[2] GP0[3] CSInt GP0[4]
Note available Configurable configured package. After chosen, remaining package locked available functionality.
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Figure Diagram SOIC
GP0[3] CSInt GP0[4] GP0[0] GP0[1] I2CSCL I2CSDA GP1[0]
Table Definitions SOIC[1] Number Name GP0[3] CSInt GP0[4] GP0[0] GP0[1]
GP0[2] XRES GP1[4] GP1[3] GP1[2] GP1[1]
SOIC (Top View)
Description Configurable CapSense GPIO Integrating Capacitor Input. external capacitance required only cannot achieved. Typical range Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO clock data Configurable CapSense GPIO Configurable CapSense GPIO Ground connection Configurable CapSense GPIO Configurable CapSense GPIO Configurable CapSense GPIO Active HIGH external reset with internal pull down Configurable CapSense GPIO Supply voltage
GP1[0] GP1[1] GP1[2] GP1[3] GP1[4] XRES GP0[2]
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CY8C20160
CapSense Analog System
CapSense analog system contains capacitive sensing hardware which supports CapSense Successive Approximation (CSA) algorithm. This hardware performs capacitive sensing scanning without external components. Capacitive sensing configurable each pin.
Interface
modes operation interface are:
Device register configuration status read write controller Command execution
Additional System Resources
System Resources provide additional capability useful complete systems. Additional resources voltage detection Power Reset (POR).
address programmable during configuration. locked prevent accidental change setting flag configuration register.
Device Addressing
device address contained upper seven bits first byte read write transaction. first byte transaction used master address slave. byte contains bit. this master performs write operation addressed slave. this master performs read operation from addressed slave. LSB(B0) eliminated when fixing device address. example, slave address 02h, then required address 0000010 bit) excluding LSB. write operation performed, address 00000100(04h). read operation performed, address 00000101(05h). Table provides examples addressing.
slave provides 100, communication over wires. Voltage Detection (LVD) interrupts signal application falling voltage levels advanced (Power Reset) circuit eliminates need system supervisor.
internal 1.8V reference provides stable internal reference that capacitive sensing functionality affected minor changes.
Table Examples Addressing Slave Address Defined 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) 0(W) 1(R) Address sent Hex) Master
CapSense Express Software Tool
easy software tool integrated with PSoC Express available configuring tuning CapSense Express devices. Refer application note "CapSenseExpress Software Tool AN42137" details software tool.
CapSense Express Register
CapSense Express supports user configurable registers through which device functionality parameters configured. details, refer CY8C201xx Register Reference Guide.
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Modes Operation
CapSense Express devices configured operate following three modes meet different power consumption requirements:
Deep Sleep Mode
Deep sleep mode provides lowest power consumption because there operation running. this mode, device woken only using external GPIO interrupt. sleep timer interrupt cannot wake device from deep sleep mode. This treated continuous sleep mode without periodic wakeups. Refer application note "CapSense Express Power Sleep Considerations AN44209" details different sleep modes.
Active Mode Sleep Mode Deep Sleep Mode
Active Mode
active mode, device blocks including CapSense system powered. Typical active current consumption device across operating voltage range
Bi-Directional Sleep Control
CY8C20160 requires dedicated sleep control allow reliable communication case sleep mode enabled. This achieved pulling sleep control wake device start communication. sleep control configured GPIO. sleep control feature enabled, device less GPIO available CapSense GPIO functions. sleep control also configured interrupt output from CY8C20160 host acknowledge finger press button. enable bi-directional feature, user must I2C-USB bridge program.
Sleep Mode
Sleep mode provides intermediate power operation mode. enabled configuring corresponding device register. When enabled, device enters sleep mode wakes after specified sleep interval. scans capacitive sensors before going back sleep again. device also wake from sleep mode with GPIO interrupt. following sleep intervals supported CapSense Express. sleep interval configured through registers.
1.95 (512 15.6
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Electrical Specifications
Absolute Maximum Ratings
Parameter TSTG Description Storage temperature +100 Unit Notes Higher storage temperatures reduce data retention time. Recommended storage temperature +25°C 25°C (0°C 50°C). Extended duration storage temperatures above 65°C degrade reliability
VIOZ IMIO
Ambient temperature with power applied Supply voltage relative input voltage voltage applied tri-state Maximum current into GPIO Electro static discharge voltage Latch current
-0.5 2000
+6.0
Human body model
Operating Temperature
Parameter Description Ambient temperature Junction temperature +100 Unit Notes
Electrical Characteristics
Chip Level Specifications
Parameter Description Supply voltage Supply current Deep sleep mode current with active. temperature range Deep seep mode current with active Deep sleep mode current with active 2.40 5.25 Unit Conditions 3.10V, 25°C 2.55V, 40°C Notes
3.3V, -40°C 85°C 5.25V, -40°C 85°C
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3.3V General Purpose Specifications
This table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C <TA<85°C, 3.10V 3.6V -40°C<TA<85°C respectively. Typical parameters apply 3.3V 25°C. These design guidance only. Parameter VOH1 VOH2 VOH3 VOH4 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins output voltage 0.75 Unit 3.10V, maximum source current IOs. 3.10V, maximum source current IOs. VDD> 3.10V, maximum source current IOs. mA,VDD 3.10V, maximum source current IOs. VDD> 3.10V, maximum sink current even port pins sink current port pins. 3.10V 3.6V. Gross tested Package dependent. Temp 25°C. Package dependent. Temp 25°C. Notes
COUT
Input voltage Input leakage Capacitive load pins input Capacitive load pins output
0.75
2.7V General Purpose Specifications
This table lists guaranteed maximum minimum specifications voltage temperature ranges: 2.4V 2.90V -40°C <85°C, respectively. Typical parameters apply 2.7V 25°C. These design guidance only. Parameter VOH1 VOH2 VOH3 VOH4 Description Pull resistor High output voltage Port pins High output voltage Port pins High output voltage Port pins High output voltage Port pins output voltage 0.75 Unit maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum source current IOs. maximum sink current even port pins sink current port pins. IOL=5 maximum sink current even port pins sink current port pins (2.4<VDD <2.9V 3.1<VDD <3.6V). 2.90V 3.10V 3.6V. 2.7V. 2.90V 3.10V 3.6V. Gross tested Page Notes
VOLP1
output voltage port pins
VIH1 VIH2
Input voltage Input high voltage Input high voltage Input hysteresis voltage Input leakage
0.75
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2.7V General Purpose Specifications (continued)
This table lists guaranteed maximum minimum specifications voltage temperature ranges: 2.4V 2.90V -40°C <85°C, respectively. Typical parameters apply 2.7V 25°C. These design guidance only. Parameter COUT Description Capacitive load pins input Capacitive load pins output Unit Notes Package dependent. Temp 25°C. Package dependent. Temp 25°C.
2.7V Spec Line with 1.8V External Pull-Up
This table lists guaranteed maximum minimum specifications voltage temperature ranges: 2.4V 2.9V 3.10V 3.60V, -40°C<TA <85°C, respectively. Typical parameters apply 2.7V 25°C. lines drive mode must open drain pulled 1.8V externally. Parameter VOLP1 Description output voltage port pins Unit Notes IOL=5 maximum sink current even port pins sink current port pins. 2.4<VDD <2.9V 3.1<VDD <3.6V. 2.90V 3.10V 3.6V. 2.7V. Package dependent. Temp 25°C. Package dependent. Temp 25°C.
COUT
Input voltage Input high voltage Capacitive load pins input Capacitive load pins output
0.75
Specifications
Parameter VPPOR0 VPPOR1 VLVD0 VLVD2 VLVD6 Description Value PPOR Trip VDD= 2.7V VDD= 3.3V, Value Trip VDD= 2.7V VDD= 3.3V VDD= 2.39 2.75 3.98 2.36 2.60 2.45 2.92 4.05 2.40 2.65 2.51 2.99 4.12 Unit Notes must greater than equal 2.5V during startup, reset from XRES pin, reset from watchdog.
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Programming Specifications
This table lists guaranteed maximum minimum specifications voltage temperature ranges: 4.75V 5.25V -40°C<TA<85°C, 3.10V 3.6V -40°C<TA<85°C, 2.4V 2.90V -40°C<TA<85°C, respectively. Typical parameters apply 3.3V, 2.7V 25°C. These design guidance only. Flash Endurance Retention specifications with EEPROM user module valid only within range: 25°C±20°C during Flash Write operation. Refer EEPROM user module data sheet instructions EEPROM Flash Write requirements outside 25°C±20°C temperature window. this User Module Flash Writes outside this range must occur known temperature (±20°C) requires designer configure temperature variable rather than default 25°C value hard coded into API. this outside range 25°C±20°C user's risk. This risk includes overwriting Flash cell (when above allowable temperature range) thereby reducing data sheet specified endurance performance underwriting Flash cell (when below allowable temperature range) thereby reducing data sheet specified retention. Symbol Description VddIWRITE Supply Voltage Flash Write Operations[2] IDDP Supply Current During Programming Verify VILP Input Voltage During Programming Verify VIHP Input High Voltage During Programming Verify IILP Input Current when Applying Vilp P1[0] P1[1] During Programming Verify IIHP Input Current when Applying Vihp P1[0] P1[1] During Programming Verify VOLV Output Voltage During Programming Verify VOHV Output High Voltage During Programming Verify FlashENPB Flash Endurance (per block) FlashENT Flash Endurance (total) FlashDR Flash Data Retention -1.0 50,000 1,800,0 0.75 Units Years Erase/write cycles block. Erase/write cycles. Driving internal pull down resistor. Driving internal pull down resistor. Notes
CapSense Electrical Characteristics
3.10 Typical 3.10 2.45 Conditions Supply Voltage <2.9V <2.45V <2.4V 5.25 3.10 4.75 >3.10V <4.73V 4.75V Result device automatically reconfigures itself work 2.7V mode operation. scanning CapSense parameters shuts down until voltage returns over 2.45V. device goes into reset. device automatically reconfigures itself work 3.3V mode operation. scanning CapSense parameters shuts down until voltage returns over 4.73V. This range supported CapSense Express. device will work, CapSense scanning enabled until voltage goes above 4.73V. This range supported CapSense Express.
3.1V
Note Commands involving Flash Writes (0x01, 0x02, 0x03) must executed only within same voltage range detected (power XRES, command 0x06) above 2.7V. register details, refer CY8C201xx Register Reference Guide. user powers device 2.4V-3.6V range, Flash writes must performed only range 2.7V 2.9V 3.10V 3.6V. user powers device 4.75V 5.25V range, Flash writes must performed that range only.
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Electrical Characteristics
3.3V General Purpose Specifications
Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload Port Rise time, strong mode, Cload Port Fall time, strong mode, Cload ports Unit Notes 3.10V 3.6V 4.75V 5.25V, 3.10V 3.6V, 3.10V 3.6V 4.75V 5.25V,
2.7V General Purpose Specifications
Parameter TRise0 TRise1 TFall Description Rise time, strong mode, Cload Port Rise time, strong mode, Cload Port Fall time, strong mode, Cload ports Unit Notes 2.4V 2.90V, 2.4V 2.90V, 2.4V 2.90V,
Specifications
Parameter FSCLI2C Description clock frequency Standard Mode Fast Mode Unit Notes Fast mode supported 3.0V
THDSTAI2C Hold time (repeated) START condition. After this period, first clock pulse generated TLOWI2C THIGHI2C TSUSTAI2C period clock HIGH period clock Setup time repeated START condition
THDDATI2C Data hold time TSUDATI2C Data setup time TSUSTOI2C Setup time STOP condition TBUFI2C TSPI2C free time between STOP START condition Pulse width spikes suppressed input filter
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CY8C20160
Figure Definition Timing Fast/Standard Mode
tSUDATI2C
tLOWI2C
tHDSTAI2C
tSPI2C
tBUFI2C
tHDSTAI2C
tHDDATI2C
tHIGHI2C
tSUSTAI2C
tSUSTOI2C
Ordering Information
Ordering Code CY8C20160-LDX2I CY8C20160-SX2I Package Diagram 001-09116 51-85068 Package Type COL[5] SOIC Operating Temperature Industrial Industrial
Thermal Impedances Package
Package COL[5] SOIC Typical JA[3] 79.96
Solder Reflow Peak Temperature
Package COL[5] SOIC Minimum Peak Temperature[4] Maximum Peak Temperature
Notes Power Higher temperatures required based solder melting point. Typical temperatures solder with Sn-Pb with Sn-Ag-Cu paste. Refer solder manufacturer specifications. Earlier termed package.
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Package Diagrams
Figure Chip Lead Package Outline (SAWN) 001-09116 (Pb-Free)
001-09116
Figure 16-Pin (150-Mil) SOIC (51-85068)
51-85068-*B
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Document History Page
Document Title: CY8C20160 CapSense Express- Configurable Document Number: 001-17347 Rev. 1341766 1494145 Orig. Change TUP/ SFVTMP TUP/AESA Submission Date Data Sheet Changed FINAL Datasheet Removed table 2.7V General Purpose Specifications Open Drain with pull 1.8V Updated Logic Block Diagram Removed table General Purpose Specifications Updated Logic Block Diagram Updated table Specifications Updated table Chip Level Specifications Updated table 3.3V General Purpose Specifications Updated table 2.7V General Purpose Specifications Updated table GPIO Specifications split into tables 5V/3.3V 2.7V Added section CapSense ExpressSoftware tool Updated 16-QFN Package Diagram Updated table-DC Chip Level Specifications Updated table-Pin Definitions Updated table-Pin Definitions SOIC Updated table-5V 3.3V General Purpose Specifications Updated table 2.7V General Purpose Specifications Changed definition Timing Fast/Standard Mode diagram Updated Logic Block Diagram Added Programming Specifications Table Updated Features Added CapSense Electrical Characteristics Table Different sleep modes explained Bi-Directional Sleep Control defined Table added "2.7V Spec Line with 1.8V External Pull-Up Included section Device Addressing Updated CapSense Electrical Specifications table Deleted VOH5, VOH6, VOH7, VOH8, VOH9, VOH10 parameters Description Change
1773608
TUP/AESA
2091026
DZU/MOHD /AESA
2404731
DZU/MOHD/PY
2544918
ZSK/AESA
2648811
DZU/PYRS
01/28/09
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Cypress Semiconductor Corporation, 2007-2009. information contained herein subject change without notice. Cypress Semiconductor Corporation assumes responsibility circuitry other than circuitry embodied Cypress product. does convey imply license under patent other rights. Cypress products warranted intended used medical, life support, life saving, critical control safety applications, unless pursuant express written agreement with Cypress. Furthermore, Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress products life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. Source Code (software and/or firmware) owned Cypress Semiconductor Corporation (Cypress) protected subject worldwide patent protection (United States foreign), United States copyright laws international treaty provisions. Cypress hereby grants licensee personal, non-exclusive, non-transferable license copy, use, modify, create derivative works compile Cypress Source Code derivative works sole purpose creating custom software firmware support licensee product used only conjunction with Cypress integrated circuit specified applicable agreement. reproduction, modification, translation, compilation, representation this Source Code except specified above prohibited without express written permission Cypress. Disclaimer: CYPRESS MAKES WARRANTY KIND, EXPRESS IMPLIED, WITH REGARD THIS MATERIAL, INCLUDING, LIMITED IMPLIED WARRANTIES MERCHANTABILITY FITNESS PARTICULAR PURPOSE. Cypress reserves right make changes without further notice materials described herein. Cypress does assume liability arising application product circuit described herein. Cypress does authorize products critical components life-support systems where malfunction failure reasonably expected result significant injury user. inclusion Cypress' product life-support systems application implies that manufacturer assumes risk such doing indemnifies Cypress against charges. limited subject applicable Cypress software license agreement.
Document Number:001-17347 Rev.
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CapSense ExpressTM, PSoC DesignerTM, Programmable System-on-ChipTM, PSoC Expressare trademarks PSoC® registered trademark Cypress Semiconductor Corp. other trademarks registered trademarks referenced herein property respective corporations. Purchase components from Cypress sublicensed Associated Companies conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. products company names mentioned this document trademarks their respective holders.
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CapSense Express- Configurable CapSense Expresscontroller allows

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