ATION EVALU ILABLE Multiprotocol Dual Smart Card Interface D
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8/08
ATION EVALU ILABLE
Multiprotocol Dual Smart Card Interface
DS8007 multiprotocol dual smart card interface low-cost, dual smart card reader interface supporting 7816, EMVTM, GSM11-11 requirements. Through 8-bit parallel dedicated address selects (AD3-AD0), DS8007 easily directly connect nonmultiplexed byte-wide Maxim secure microcontroller. Optionally, parallel multiplexed allow direct access multiplexed 80C51-compatible microcontroller through MOVX memory addressing. integrated 7816 UART multiplexed among interfaces allow high-speed automatic smart card processing with each card-possessing, independent, variable, baud-rate capability. card interface controlled internal sequencers that support automatic activation deactivation sequencing, handling actions required synchronous protocols. Emergency deactivation also supported case supply dropout. third card supported through auxiliary I/O. same optionally used additional serial interface UART. DS8007 provides electrical signals necessary interface with smart cards. integrated voltage converter ensures full cross-compatibility between 1.8V/ 3V/5V cards 1.8V/3V/5V environment, allows operation within 2.7V supply voltage range.
Features
Integrated 7816 UART Provides Complete Interface/Control Separate Smart Card Devices (min) Protection Card Interfaces Internal Card Supply Voltage Generation 5.0V ±5%, 65mA (max) 3.0V ±8%, 50mA (max) 1.8V ±10%, 30mA (max) Automatic Card Activation, Deactivation, Data Communication Controlled Dedicated Internal Sequencer Host Interface Through 8-Bit Parallel (UserSelectable Multiplexed Nonmultiplexed Modes) Chip Select Tri-State Allow Multiple Devices (Card Readers Memories) 8-Character Receive FIFO with Optional Programmable Depth/Threshold Interface External 7816 UART Auxiliary Interface Separate Card Clock Generation 10MHz) with Frequency Doubling Selectable Card Clock Stop High, Stop Low, Internally Generated 1.25MHz (for Card PowerDown) EMV-Certified Reference Design Evaluation Available (DS8007-KIT)
DS8007
Applications
Banking Applications (Point-of-Sale Terminals, Debit/Credit Payment Terminals, Pads, Automated Teller Machines) Telecommunications Television Access Control
Configuration
INTAUX DELAY XTAL1 XTAL2 CPA2 AGND
RSTOUT
Ordering Information
PART DS8007-ENG TEMP RANGE -40°C +85°C SMART PINCARDS PACKAGE SUPPORTED auxiliary LQFP LQFP
I/OAUX I/OA PRESA
GNDA CLKA VCCA RSTA I/OB
DS8007
auxiliary DS8007-ENG+ -40°C +85°C Denotes lead-free/RoHS-compliant device.
trademark owned EMVCo LLC. MAXQ registered trademark Maxim Integrated Products, Inc. Note: Some revisions this device incorporate deviations from published specifications known errata. Multiple revisions device simultaneously available through various sales channels. information about device errata, www.maxim-ic.com/errata.
Typical Operating Circuit appears data sheet.
Maxim Integrated Products
pricing, delivery, ordering information, please contact Maxim Direct 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
PRESB GNDB CLKB VCCB RSTB CPA1 CPB1 VDDA CPB2
LQFP
Multiprotocol Dual Smart Card Interface DS8007
ABSOLUTE MAXIMUM RATINGS
Voltage Range Relative Ground .-0.5V +6.5V Voltage Range VDDA Relative Ground .-0.5V +6.5V Voltage Range Relative Ground Pins CPA1, CPA2, CPB1, CPB2, .-0.5V +7.5V Other Pins.-0.5V (VDD 0.5V) Maximum Junction Temperature .+125°C Maximum Power Dissipation -25°C) .900mW Storage Temperature Range .-55°C +150°C Soldering Temperature .See IPC/JEDEC J-STD-020 Specification
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD +3.3V, VDDA +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Digital Supply Voltage Step-Up Converter Supply Voltage Power-Down Current Cards Inactive Cards Active SYMBOL VDDA ISTOP fXTAL 0MHz fXTAL 0MHz, fCLK 0MHz, VCCx fCLK 0MHz, step-up: ICCA ICCB 80mA, 2.7V, fXTAL 20MHz, fCLK 10MHz step-up: ICC1 ICC2 80mA, fXTAL 20MHz, fCLK 10MHz, 2.7V step-up: ICC1 ICC2 80mA, fXTAL 20MHz, fCLK 10MHz, VRST VHYS VDRST VDELAY VDELAY Threshold voltage (falling) Hysteresis 1.25 Output Voltage Delay Output Current Output Capacitance RSTOUT Output High Voltage Output Voltage Leakage Current VOHRSTO VOLRSTO -1mA -0.3 +0.4 CONDITIONS UNITS
Sleep Mode Current (Cards Active) Active Current Cards
Active Current Cards
Power-Fail Reset Voltage Reset Threshold
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3.3V, VDDA +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Alarm Pulse Width External Clock Frequency Internal Oscillator Voltage Voltage Detection VDDA Step-Up Shutdown Temperature Card Inactive Mode Output Voltage Output Current Output Voltage RSTx Pins Card Active Mode Output High Voltage Rise Time Fall Time Shutdown Current Current Limitation Card Inactive Mode Output Voltage Output Current Output Voltage CLKx Card Pins Active Mode Output High Voltage Rise Time Fall Time Current Limitation Clock Frequency Duty Factor SYMBOL fXTAL fINT VDET VOLRST IOLRST VOLRSTL VOHRSTH tRRST tFRST IRST(SD) IRST(LIMIT) VOLCLK IOLCLK VOLCLK VOHCLK tRCLK tFCLK ICLK(LIMIT) fCLK Idle configuration (1MHz) Operational 30pF IOLCLK VOLCLK IOLCLK +200µA IOHCLK -200µA 30pF (Note 30pF (Note IOLRST VOLRST IOLRST +200µA IOHRST -200µA 30pF 30pF 1.85 step-up step-up 3.35 CONDITIONS CDELAY 22nF External crystal External oscillator 3.50 +150 3.60 UNITS
DS8007
Multiprotocol Dual Smart Card Interface DS8007
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3.3V, VDDA +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Card Inactive Mode Output Voltage Output Current SYMBOL ICC(5V) 65mA ICC(3V) 50mA ICC(1.8V) 30mA Output Voltage VCCx Pins Card Active Mode Output Current Total Current (Two Cards) Shutdown Current Slew Rate Card Inactive Mode Output Voltage Output Current Internal Pullup Resistor Output Voltage Output High Voltage I/Ox Pins Card Active Mode Output Rise/Fall Time Input Voltage Input High Voltage Input Current Input High Current Input Rise/Fall Time Current Limitation card, current pulses 40nC with 200mA, 400ns, 20MHz card, current pulses 24nC with 200mA, 400ns, 20MHz 1.8V card, current pulses 12nC with 200mA, 400ns, 20MHz VCC(5V) VCC(3V) VCC(1.8V) 1.8V ICC(A+B) ICC(SD) VCCSR VOLIO IOLIO RPULLUP VOLIO VOHIO VILIO VIHIO IILIO IIHIO IIO(LIMIT) VILIO VIHIO 30pF Up/down, 300nF (Note IOLIO VOLIO VCCx IOLIO IOHIO -20µA IOHIO -40µA (3V/5V) 30pF -0.3 0.05 0.75 -100 0.16 0.05 +0.8 V/µs CONDITIONS 4.75 2.78 1.65 2.75 1.62 5.00 3.00 1.80 5.25 3.22 1.95 3.25 1.98 UNITS
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3.3V, VDDA +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Output Voltage Output Current Internal Pullup Resistor Output Voltage Output High Voltage Output Rise/Fall Time C4x, Pins Card Active Mode Input Voltage Input High Voltage Input Current Input High Current Input Rise/Fall Time Pullup Pulse Width Operating Frequency TIMING Activation Sequence Duration Deactivation Sequence Duration PRESA/PRESB PINS Input Voltage Input High Voltage Input Current Input High Current I/OAUX Internal Pullup Resistor Output Voltage Output High Voltage Output Rise/Fall Time RPULLUP VOLAUX VOHAUX Between I/OAUX IOLAUX IOHAUX 40µA (3V/5V) 30pF 0.75 VILPRES VIHPRES IILPRES IIHPRES VILPRES VIHPRES 0.25 tACT Figure Figure SYMBOL VOLC48 IOLC48 RPULLUP VOLC48 VOHC48 VILC48 VIHC48 IILC48 IIHC48 tWPU fMAX VILIO VIHIO 30pF Active pullup card contact pins IOLC48 VOLC48 Between VCCx IOLC48 IOHC48 -20µA IOHC48 -40µA (3V/5V) 30pF -0.3 CONDITIONS 0.75 +0.8 UNITS
DS8007
Card Inactive Mode
Multiprotocol Dual Smart Card Interface DS8007
ELECTRICAL CHARACTERISTICS (continued)
(VDD +3.3V, VDDA +3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Input Voltage Input High Voltage Input Current Input High Current Input Rise/Fall Time INTERRUPT Output Voltage Input High Leakage Current OTHER LOGIC PINS Output Voltage Output High Voltage Output Rise/Fall Time Input Voltage Input High Voltage Input Current Input High Current Load Capacitance VOLD VILD VIHD IILD IIHD IOLD +5mA IOHD -5mA 50pF VOLINT ILIHINT SYMBOL VILAUX VIHAUX IILAUX IIHAUX VILAUX VIHIO 30pF CONDITIONS -0.3 UNITS
Note Operation guaranteed -40°C +85°C tested. Note Parameters guaranteed meet 7816, GSM11-11, 2000 requirements. 1.8V card, maximum rise fall time 10ns. Note Parameter guaranteed meet 7816, GSM11-11, 2000 requirements. 1.8V card, minimum slew rate 0.05V/µs maximum slew rate 0.5V/µs.
Multiprotocol Dual Smart Card Interface
ELECTRICAL SPECIFICATIONS-TIMING PARAMETERS MULTIPLEXED PARALLEL
(VDD 3.3V, VDDA 3.3V, +25°C, unless otherwise noted.) (Figure
PARAMETER XTAL Cycle Time Pulse Width Address Valid Pulse Width Data Read Valid WR/RD High High Pulse Width Data Write Valid SYMBOL tCY(XTAL1) tW(ALE) tAVLL t(AL-RWL) tW(RD) t(RL-DV) t(RWH-AH) tW(WR) t(DV-WL) Register Other registers CONDITIONS tCY(XTAL1) UNITS
DS8007
tW(ALE)
tAVLL
t(AL-RWL)
D7-D0
ADDRESS
DATA (READ) t(RWH-AH)
ADDRESS
DATA (WRITE)
tW(RD)
t(DV-WL) tW(WR)
t(RWH-AH)
t(RL-DV)
Figure Multiplexed Parallel Timing
Multiprotocol Dual Smart Card Interface DS8007
ELECTRICAL SPECIFICATIONS-TIMING PARAMETERS NONMULTIPLEXED PARALLEL (READ WRITE)
(VDD 3.3V, VDDA 3.3V, +25°C, unless otherwise noted.) (See Figure
PARAMETER High Access Time Data Valid High Data High Impedance Data Valid Write Data Hold Time Address Stable High Address SYMBOL CONDITIONS UNITS
READ (EN)
(R/W) AD3-AD0 ADDRESS
D7-D0
DATA
WRITE (EN) WRITE RELEASE WITH
WRITE RELEASE WITH
(EN) (R/W) AD3-AD0 ADDRESS D7-D0 DATA
Figure Nonmultiplexed Parallel Timing (Read Write)
Multiprotocol Dual Smart Card Interface
ELECTRICAL SPECIFICATIONS-TIMING PARAMETERS CONSECUTIVE READ/WRITE URR/UTR/TOC
(VDD 3.3V, VDDA 3.3V, +25°C, unless otherwise noted.)
PARAMETER FIGURE Pulse Width CRED Time Time FIGURE WR/CS Pulse Width WR/CS FIGURE WR/CS Pulse Width WR/CS High CRED tW(WR) tW(TOC) (Notes tW(WR) tWR(UTR) (Note tW(WR) 2tCY(CLK) tW(WR) 3tCY(CLK) tW(RD) tRD(URR) tSB(FE) tSB(RBF) tW(RD) 2tCY(CLK) 10.5 10.5 tW(RD) 3tCY(CLK) SYMBOL CONDITIONS UNITS
DS8007
Note Depends leading edge (whichever deasserted first). Reference this specification rising edge CS/WR instead falling edge. Note programmed prescaler value 32).
I/Ox
tSB(FE)
tSB(RBF)
tW(RD)
CRED
tRD(URR)
Figure Timing Between Read Operations Register
Multiprotocol Dual Smart Card Interface DS8007
I/Ox
WR/CS
tW(WR)
CRED
tWR(UTR)
Figure Timing Between Write Operations Register
WR/CS
tW(WR)
CRED
tWR(TOC)
Figure Timing Between Write Operations Register
Multiprotocol Dual Smart Card Interface
Description
NAME RSTOUT I/OAUX I/OA PRESA GNDA CLKA VCCA RSTA I/OB PRESB GNDB CLKB VCCB RSTB FUNCTION Reset Output. This active-high output provided resetting external devices. RSTOUT driven high until DELAY reaches VDRST. Once DELAY reaches VDRST, RSTOUT tri-stated externally pulled down. SUPL each RSTOUT pulse. Auxiliary I/O. This allows connection auxiliary smart card interface. Smart Card Data Line. This data line associated with smart card This also referred contact. Smart Card Auxiliary I/O. This auxiliary associated with smart card This also referred contact. This associated with synchronous cards. Smart Card Presence Contact. This active-high presence contact associated with smart card Smart Card Auxiliary I/O. This auxiliary associated with smart card This also referred contact. This associated with synchronous cards. Smart Card Ground. This must connected GND. Smart Card Clock Output. This clock output associated with smart card This also referred contact. Smart Card Supply Voltage. This supply voltage output associated with smart card This also referred contact. Smart Card Reset. This reset output associated with smart card This also referred contact. Smart Card Data Line. This data line associated with smart card This also referred contact. Smart Card Auxiliary I/O. This auxiliary associated with smart card This also referred contact. This associated with synchronous cards. Smart Card Presence Contact. This active-high presence contact associated with smart card Smart Card Auxiliary I/O. This auxiliary associated with smart card This also referred contact. This associated with synchronous cards. Smart Card Ground. This must connected GND. Smart Card Clock Output. This clock output associated with smart card This also referred contact. Smart Card Supply Voltage. This supply voltage output associated with smart card This also referred contact. Smart Card Reset. This reset output associated with smart card This also referred contact. Ground Step-Up Converter Connection. Connect low-ESR capacitor 220nF between this ground.
DS8007
Multiprotocol Dual Smart Card Interface DS8007
Description (continued)
28-35 NAME CPA1 CPB1 VDDA CPB2 AGND CPA2 D0-D7 FUNCTION Step-Up Converter Contact Connect low-ESR capacitor 220nF between CPA1 CPA2. Step-Up Converter Contact Connect low-ESR capacitor 220nF between CPB1 CPB2. Analog Supply Voltage. Positive analog-supply voltage step-up converter; higher lower than VDD. This should decoupled AGND with good quality capacitor. Step-Up Converter Contact Connect low-ESR capacitor 220nF between CPB1 CPB2. Analog Ground Step-Up Converter Contact Connect low-ESR capacitor 220nF between CPA1 CPA2. Digital Supply Voltage. This should decoupled with good quality capacitor. 8-Bit Digital I/O. This port functions data address/data communication lines between host controller DS8007 nonmultiplexed multiplexed operating modes, respectively. Active-Low Parallel Read Strobe Input. multiplexed mode, this input indicates when host processor reading information from DS8007. nonmultiplexed mode, this signals current operation read write when low. Active-Low Parallel Write Strobe Input. multiplexed mode, this input indicates when host processor writing information DS8007. nonmultiplexed mode, this signals engaged read write operation. Active-Low Chip-Select Input. This input indicates when DS8007 active parallel bus. Address Latch Enable Input. This signal monitors signal when host processor operating multiplexed mode. Connect this signal when operating nonmultiplexed mode. Active-Low Interrupt. This output indicates interrupt active. Auxiliary Interrupt Input. This serves auxiliary interrupt. Register Selection Address Inputs. These pins function address input lines nonmultiplexed configuration should connected ground multiplexed configuration. Crystal Oscillators. Place crystal with appropriate load capacitors between these pins that desired clock source. XTAL1 also acts input there external clock source place crystal. External Delay Capacitor Connection. Connect capacitor from this ground power-on reset delay.
42-45
INTAUX AD3-AD0 XTAL2, XTAL1 DELAY
Multiprotocol Dual Smart Card Interface
Detailed Description
following describes major functional features device. this document requires reader have basic understanding 7816 terminology. edge (activity) detected pin. Once rising edge detected pin, DS8007 placed into multiplexed mode operation. Once multiplexed mode operation, reset/power cycle deassertion forces device nonmultiplexed mode. Connecting ground forces device into nonmultiplexed parallel mode. Figure shows that recognition dictates whether external address lines (AD3-AD0) used directly whether external data lines (D7-D0) must latched according input signal. multiplexed mode operation, address latched irrespective state
DS8007
Parallel Interface
device interfaces host computer/processor through multiplexed demultiplexed, parallel, 8-bit data (D0-D7). parallel interface monitors signal automatically detects whether multiplexed nonmultiplexed external interface intended. nonmultiplexed external interface default configuration maintained long
DS8007
GNDB I/OB PRESB RSTB CLKB VCCB GNDA I/OA PRESA RSTA CLKA VCCA RSTOUT DELAY INTAUX I/OAUX UART ANALOG INTERFACE DIGITAL INTERFACE
TIMEOUT COUNTER POWER-SUPPLY SUPERVISOR
CPA1 CPA2 CPB1 CPB2 VDDA AGND
CONTROL SEQUENCERS DC-DC CONVERTER CLOCK GENERATION XTAL1 XTAL2
Figure Block Diagram
Multiprotocol Dual Smart Card Interface DS8007
REGISTERS
AD3-AD0
D7-D0
LATCH D3-D0
LOGIC
CONTROL
Figure Parallel Interface
Multiplexed Mode
multiplexed mode operation, D7-D0 signals multiplexed between address data. falling edge address latch enable (ALE) signal from host microcontroller latches address (D3-D0), strobe input signals used enable read write operation, respectively, DS8007 selected (i.e., timing multiplexed parallel mode found earlier this data sheet.
Nomultiplexed Mode
nonmultiplexed mode operation, address always provided AD3-AD0 signals, data always transacted D7-D0 signals. input signal used read/write (R/W) operation select. input signals serve active-low enables, must asserted read write operation take place. timing nonmultiplexed parallel mode found earlier this data sheet.
Multiprotocol Dual Smart Card Interface
Control Registers
Special control registers that host computer/microcontroller accesses through parallel manage most DS8007 features. Many registers, although only mentioned once listing, duplicated each card interface. PDR, GTR, UCR1, UCR2, registers exist separately each three card interfaces. register provided only card interface card interface specific register accessed controlled current setting SC3-SC1 bits Card Select Register. example, there three instances UART Control Register (UCR1) address 06h. SC3-SC1 bits configured that card selected, then reads writes address only affect card SC3-SC1 changed select card then reads writes address only affect card etc. addition, some registers have different functions based whether register being read from written example this UART Receive (URR)/UART Transmit (UTR) registers located address 0Dh. Although they share same address, during read operations receive register read, write operations separate transmit register. This selection requires extra configuration software.
DS8007
Table Special Function Register
ADDRESS REGISTER (HEX) NAME UCR2 UCR1 TOR1 TOR2 TOR3 CSR7 GTR.7 FTE0 TOC7 TOL7 TOL15 TOL23 CLKSW CSR6 CSR5 CSR4 PDWN GTR.4 PROT TOC4 TOL4 TOL12 TOL20 CRED PEC0 SUPL GTR.3 TOC3 TOL3 TOL11 TOL19 FTE1 PRLB AUTOC GTR.2 RSTIN TOC2 TOL2 TOL10 TOL18 PRLA GTR.1 3V/5V TOC1 TOL1 TOL9 TOL17 INTAUX INTAUXL RESET
0011 0000 0011 0uuu 0000 0000 00uu uuuu 0000 0000 uuuu uuuu 0000 0000 uuuu uuuu
DISTBE/ DISAUX GTR.6 TOC6 TOL6 TOL14 TOL22 PEC2 PRTLB GTR.5 TOC5 TOL5 TOL13 TOL21 PEC1 PRTLA
GTR.0 0000 0000 uuuu uuuu CONV 0000 0000 0uuu 00uu START 0011 0000 0011 uuuu TOC0 0000 0000 0000 0000 TOL0 0000 0000 uuuu uuuu TOL8 0000 0000 uuuu uuuu TOL16 0000 0000 uuuu uuuu TBE/ TBE/ 0101 0000 u1u1 uuu0 0000 0000 0uuu 0uuu 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0001 0000 0uuu xxxu
unchanged, always reflects state external device pin, even when Note: Writes unimplemented bits have effect. Reads unimplemented bits return
Multiprotocol Dual Smart Card Interface DS8007
Card Select Register (CSR)
Address CSR7 CSR6 CSR5 CSR4 RW-0 RW-0 RW-0 RW-0
unrestricted read, unrestricted write, value after reset. This register reset 00110uuub
Bits Identification Bits (CSR7 CSR4). These bits provide method software identify device follows: 0011 DS8007 revision Reset UART (RIU). When this cleared (0), most UART registers reset their initial values. This must cleared least 10ns prior initiating activation sequence. This must software before action UART take place.
Bits Select Card Bits (SC3 SC1). These bits determine which card interface active shown below. Only should active time, card selected after reset (i.e., SC3-SC1 000b). Other combinations invalid. card selected. Card selected. Card selected. card interface selected.
Clock Configuration Register (CCR)
Address RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
unrestricted read, unrestricted write, value after reset. This register reset 00uuuuuub
Bits Reserved. Stop High (SHL). This determines card clock stops high state when active. forces clock stop state when high state when Clock Stop (CST). asynchronous card, this allows clock selected card stopped. When this (1), card clock stopped state determined bit. When this cleared (0), card clock operation defined bits AC2-AC0. Synchronous Clock (SC). synchronous card, card clock controlled software manipulation this contact copy value this bit. synchronous transmit mode, write results least significant (LSb) data written being driven I/Ox
pin. synchronous receive mode, state I/Ox read from URR. Bits Alternating Clock Select (AC2 AC0). These bits select frequency clock provided active card interface UART elementary time unit (ETU) generation shown below. frequency changes synchronous that there spikes unwanted pulse widths during transitions. fINT frequency internal oscillator. AC2-AC0 fXTAL fXTAL fXTAL fXTAL fINT
Multiprotocol Dual Smart Card Interface
Programmable Divider Register (PDR)
Address RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0 RW-0
DS8007
unrestricted read, unrestricted write, value after reset; bits unaffected
Bits Programmable Divider Register Bits (PD7 PD0). These bits, conjunction with defined UART input clock (based upon CKU, AC2-AC0) prescaler selection (PSC bit), used define UART when interfaced associated card interface. output prescaler block further divided according PD7-PD0 bits follows:
Prescaler output (PD7-PD0), when PD7-PD0 02h-FFh Prescaler output when PD7-PD0 00h-01h Prescaler output supported
UART Control Register (UCR2)
Address DISTBE/RBF RW-0 DISAUX RW-0 PDWN RW-0 RW-0 AUTOC RW-0 RW-0 RW-0
unrestricted read, unrestricted write, value after reset; bits unaffected
Reserved. Disable TBE/RBF Interrupt (DISTBE/RBF). This controls whether TBE/RBF flag generate interrupt pin. When this cleared interrupt signaled response TBE/RBF flag getting set. When DISTBE/RBF interrupts generated response TBE/RBF flag. Disabling TBE/RBF interrupt allow faster communication speed with card, requires that copy TBE/RBF register polled lose priority interrupts that occur register USR.
Disable Auxiliary Interrupt (DISAUX). This controls whether external INTAUX generate interrupt output pin. When this cleared change INTAUX input results assertion output pin. When DISAUX change INTAUX does result assertion output pin. INTAUXL change INTAUX independent DISAUX state. Since INTAUX independent DISAUX bit, advisable read (thus clearing INTAUX) prior clearing DISAUX avoid interrupt pin. avoid interrupt when selecting different card, DISAUX should UCR2 registers.
Multiprotocol Dual Smart Card Interface
Power-Down Mode Enable (PDWN). This controls entry into power-down mode. Power-down mode only entered SUPL been cleared. When PDWN XTAL1 XTAL2 crystal oscillator stopped, basic functions such sequencers supported internal ring oscillator. UART suspended state, clocks UART, unit, timeout counter gated off. During power-down mode, possible select card other than currently selected (advisory programmer, selecting another card during power-down mode recommended). There five ways exiting powerdown mode: Insertion card card (detected PRLA PRLB). Withdrawal card card (detected PRLA PRLB). Reassertion select DS8007 must deasserted after setting PDWN this event exit from power-down). INTAUXL change INTAUX (INTAUXL must cleared first). Clearing PDWN software always tied Except case read operation register HSR, remains asserted active-low state. host device read status registers after oscillator warmup time, signal returns high state. Synchronous/Asynchronous Card Select (SAN). This selects whether synchronous asynchronous card interface enabled. When this cleared asynchronous card interface expected. When this synchronous interface expected. synchronous mode, UART bypassed; controls CLK, transacted UTR/URR. Card interface cannot operate true synchronous mode since does have signal accompany I/OAUX. However, invokes same control I/OAUX through UTR/URR given card interfaces Auto Convention Disable (AUTOC). This activelow controls whether decoding convention should automatically detected during first received character answer-to-reset (ATR). AUTOC character decoding convention automatically detected (while UCR1.CONV written accordingly hardware. AUTOC UCR1.CONV must software assign character decoding convention. AUTOC must changed during card session. Clock UART Doubler Enable (CKU). This enables effective defined UART last half number clock cycles defined AC2-AC0 PD7-PD0 configuration (except case when AC2-AC0 000b, where XTAL). When cleared AC2-AC0 defined fCLK used timing generation. When clock frequency fCLK used generation. Prescaler Select (PSC). When prescaler value When prescaler value
DS8007
Guard Time Register (GTR)
Address GTR.7 RW-0 GTR.6 RW-0 GTR.5 RW-0 GTR.4 RW-0 GTR.3 RW-0 GTR.2 RW-0 GTR.1 RW-0 GTR.0 RW-0
unrestricted read, unrestricted write, value after reset; bits unaffected
Bits Guard Time Register Bits (GTR.7 GTR.0). These bits used storing number guard time units (ETU) requested during ATR. When
transmitting, DS8007 UART delays these numbers extra guard time before transmitting character written UTR.
Multiprotocol Dual Smart Card Interface
UART Control Register (UCR1)
Address FTE0 RW-0 PROT RW-0 RW-0 RW-0 RW-0 CONV RW-0
DS8007
unrestricted read, unrestricted write, value after reset. This register reset 0uuu00uub
FIFO Threshold Enable (FTE0). When this FTE1 (FCR.3) set, programmable FIFO threshold feature enabled. This always reads compatibility. Force Inverse Parity (FIP). When this configured correct parity transmitted with each character, receive characters checked correct parity. When inverse parity transmitted with each character correctly received characters NAK'd. Reserved. This must left Setting this causes improper device operation. Protocol Select (PROT). This software select asynchronous protocol cleared select protocol. Transmit/Receive (T/R). This should software operate UART transmit mode. When this changed from (UART changed from receive transmit mode), hardware sets USR.RBF/TBE bit, indicating empty transmit buffer. automatically cleared following successful transmission UCR1.LCT configured prior transmission. This cannot written when (holding reset).
Last Character Transmit (LCT). This optionally software prior writing last character transmitted UART transmit register (UTR). prior writing UTR, hardware resets LCT, T/R, TBE/RBF bits following successful transmission. Setting this allows automatic change reception mode after last character sent. This during before transmission. This cannot written when (holding reset). Software Convention Setting (SS). This should software prior allow automatic convention detection. Hardware automatically resets 10.5 after detection start first character ATR. Convention (CONV). This defines character decoding convention UART. CONV convention direct. CONV convention inverted. automatic convention detection enabled (AUTOC hardware detects character convention configures CONV appropriately 10.5 ETU. Otherwise (AUTOC software must configure CONV bit.
Multiprotocol Dual Smart Card Interface DS8007
Power Control Register (PCR)
Address RW-1 RW-1 RW-0 RSTIN RW-0 3V/5V RW-0 START RW-0
unrestricted read, unrestricted write, value after reset. This register reset 0011uuuub Note: card interface does have register PCR. external ports that internally pulled (10k VCCx), writing configures weak pullup. Reads made state different physical bit. Writing configures pulldown. bits written irrespective state bit.
Bits Reserved. Contact (C8). Writes this register output card interface. Reads this register reflect value pin. Contact (C4). Writes this register output card interface. Reads this register reflect value pin. 1.8V Card Select (1V8). this VCCx supplied card interface 1.8V. This overrides 3V/5V bit. Reset (RSTIN). When card interface activated, RSTx driven according value contained this register bit.
3V/5V Card Select (3V/5V). This determines VCCx level card interface. When this VCCx defined When this cleared VCCx defined When 3V/5V bits priority given 1V8. Start (START). This controls software activation/deactivation card interface. When this written activation sequence selected card performed. When this written deactivation sequence selected card performed. Hardware automatically resets START associated card interface when emergency deactivation occurs. This written regardless state bit.
Timeout Configuration Register (TOC)
Address TOC7 RW-0 TOC6 RW-0 TOC5 RW-0 TOC4 RW-0 TOC3 RW-0 TOC2 RW-0 TOC1 RW-0 TOC0 RW-0
unrestricted read, unrestricted write, value after reset. This register reset 00000000b
Bits Timeout Counter Configuration Register Bits (TOC7 TOC0). These register bits determine counting configuration three timeout counter registers. available configurations detailed
Timeout Counter Operation section. These registers written when before activation cannot written when
Multiprotocol Dual Smart Card Interface
Timeout Counter Register (TOR1)
Address TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0
DS8007
unrestricted read, unrestricted write, value after reset. This register unchanged
Bits Timeout Counter Register Bits (TOL7 TOL0). This register configured operate 8-bit counter lowest bits 24-bit counter. TOR1, TOR2, TOR3 concatenated form 24bit counter pair independent 8-bit
counters. These counters only used when card supplied active clock. Timeout Counter Operation section details configurable modes.
Timeout Counter Register (TOR2)
Address TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8
unrestricted read, unrestricted write, value after reset. This register unchanged
Bits Timeout Counter Register Bits (TOL15 TOL8). This register configured operate lower bits 16-bit counter middle
bits 24-bit counter. Timeout Counter Operation section details configurable modes.
Timeout Counter Register (TOR3)
Address TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16
unrestricted read, unrestricted write, value after reset. This register unchanged
Bits Timeout Counter Register Bits (TOL23 TOL16). This register configured operate high bits 16-bit counter high
bits 24-bit counter. Timeout Counter Operation section details configurable modes.
Multiprotocol Dual Smart Card Interface DS8007
Mixed Status Register (MSR)
Address CLKSW CRED INTAUX TBE/RBF
unrestricted read, unrestricted write, value after reset. This register reset u1u1uuu0b
Clock Switch (CLKSW). This status indicates clock (fXTAL fINT being sourced selected card interface thus used determine when requested clock switch occurred properly. When CLKSW clock switched from fXTAL fINT when CLKSW cleared clock switched from fINT fXTAL FIFO Empty Status (FE). This when receive FIFO empty. This cleared when least character remains receive FIFO. Block Guard Time Status (BGT). This status linked counter currently selected card interface, intended verifying that block guard time always being met. counter restarts every start stops only terminal count reached. terminal count dependent upon selected protocol This cleared every start bit. Control Ready (CRED). This signals host device that DS8007 ready handle next write operation next read operation URR. When CRED DS8007 still working previous operation cannot correctly process read/write request. When CRED DS8007 ready next read/write request. This "busy" allows DS8007 meet timing constraints high-speed host devices. CRED remains low: clock cycles after rising edge before reading URR. clock cycles after rising edge before writing UTR.
1/PSC (min) 2/PSC (max) after rising edge before writing CRED timing applies asynchronous mode only; this forced synchronous mode. Presence Card (PRB). This when card presence detected cleared when card present. Presence Card (PRA). This when card presence detected cleared when card present. INTAUX (INTAUX). This reflects state INTAUX pin. This when INTAUX high cleared when INTAUX low. Transmit Buffer Empty/Receive Buffer Full (TBE/RBF). This signals special conditions relating UART associated hardware. This when last character transmitted UART when This when: UCR1.T/R changed from (receive mode) (transmit mode). character transmitted UART. receive FIFO becomes full. This cleared when: UART reset character written UART transmit register (UTR) transmit mode. character read from receive FIFO receive mode. UCR1.T/R changed from (transmit mode) (receive mode).
Multiprotocol Dual Smart Card Interface
FIFO Control Register (FCR)
Address PEC2 PEC1 PEC0 FTE1
DS8007
unrestricted read, unrestricted write, value after reset. This register reset 0uuu0uuub
Reserved. Bits Parity Error Count (PEC2 PEC0). These bits used only protocol determine number retransmission attempts that occur transmit mode number parity errors that occur before indicate that parity error limit been reached. transmit mode, DS8007 attempts retransmit character (PEC2-PEC0) times (when NAK'd card) before set. Retransmission attempts automatically made from previous start bit. PEC2-PEC0 000b, retransmission attempt made, however, host device manually rewrite character which case, re-sent early 13.5 from previous start error character. receive mode, (PEC2-PEC0 parity errors have been detected, USR.PE example,
PEC2-PEC0 000b, only parity error needs detected set; PEC2-PEC0 111b, parity errors must detected, etc. character correctly received before allowed parity error count reached, parity counter reset. protocol, parity counter used. whenever parity error detected received character. FIFO Threshold Enable (FTE1). When this FTE0 (UCR1.7) set, programmable FIFO threshold feature enabled. This always reads compatibility. Bits FIFO Length (FL2 FL0). These bits determine depth receive FIFO. receive FIFO depth equal (FL2-FL0) (e.g., FIFO depth FL2-FL0 001b).
UART Receive Register (URR)/UART Transmit Register (UTR)
Address UR7/UT7 RW-0 UR6/UT6 RW-0 UR5/UT5 RW-0 UR4/UT4 RW-0 UR3/UT3 RW-0 UR2/UT2 RW-0 UR1/UT1 RW-0 UR0/UT0 RW-0
unrestricted read, unrestricted write, value after reset. This register reset 00000000b
Bits UART Receive Register (Read Operations)/UART Transmit Register (Write Operations) (UR7/UT7 UR0/UT0). This register used both UART transmit receive buffer host microcontroller. Received characters always read host microcontroller direct convention, meaning that CONV then characters received using inverse convention automatically translated hardware. When receive FIFO enabled, reads always access oldest available received data. synchronous mode operation, (URR.0) reflects state selected card I/Ox line. Writes host microcontroller this register transmit characters selected card. host microcontroller should write data direct convention
(inverse convention encoding handled hardware). register cannot loaded during transmission. transmission: Starts write operation (rising edge previous character been transmitted extra guard time been satisfied. Starts extra guard time that guard time been satisfied. Does start transmission previous character completed (e.g., during retransmission attempts transmit parity error occurs). synchronous mode operation, only (UTR.0) loaded data transferred I/Ox selected card.
Multiprotocol Dual Smart Card Interface DS8007
UART Status Register (USR)
Address TBE/RBF
unrestricted read, unrestricted write, value after reset. register bits reset 00000000b Note: bits TO3, TO2, TO1, OVR, set, then read operation clears bit, causing interrupt less than after rising edge strobe. same reception.
Bits Timeout Counter 3/2/1 Status (TO3 TO1). These bits whenever their respective timeout counter reaches terminal count. these bits causes asserted. Early Answer Detected (EA). This start detected line during between clock cycles 200-368 when RSTx low, during first clock cycles after RSTx high. When becomes set, asserted. card during ATR, this cleared when switched another card. During early answer detection period, 46-clock-cycles sampling period should used detect start bit; there undetected period clock cycles both cases (between clock cycles 200-368 when RSTx low, first clock cycles after RSTx high). Parity Error (PE). This status indicates when transmit receive parity error count been exceeded. protocol PEC2-PEC0 bits define allowable number transmit receive parity errors. protocol parity error results
setting bit. When set, asserted. protocol characters received with incorrect parity stored receive FIFO. protocol received characters with parity errors stored receive FIFO regardless parity bit. 10.5 reception mode 11.5 transmit mode applicable transmit Overrun FIFO (OVR). This status UART receives character when receive FIFO full. When FIFO overrun condition occurs, character received lost previous FIFO content remains undisturbed. When status set, asserted. 10.5 receive mode Framing Error (FER). This status line high state time 10.25 after start bit. 10.5 receive mode Transmit Buffer Empty/Receive Buffer Full (TBE/RBF). This duplicate same status contained Mixed Status Register (MSR).
Multiprotocol Dual Smart Card Interface
Hardware Status Register (HSR)
Address PRTLB PRTLA SUPL PRLB PRLA INTAUXL
DS8007
unrestricted read, unrestricted write, value after reset, always reflects state external device pin. This register reset 0uuuxxxub Note: minimum needed between successive reads allow hardware updates. addition, minimum needed between reads activation card card card.
Reserved. Protection Card Interface Status (PRTLB). This when fault been detected card reader interface fault defined detection short-circuit condition either RSTB VCCB given specs IRST(SD) ICC(SD). signal asserted logic (active) while this set. This returns after read, unless condition persists. Protection Card Interface Status (PRTLA). This when fault been detected card reader interface fault defined detection short-circuit condition either RSTA VCCA given specs IRST(SD) ICC(SD). signal asserted logic (active) while this set. This returns after read, unless condition persists. Supervisor Latch (SUPL). This when VRST when reset caused externally driving DELAY 1.25V. this time signal asserted logic (active). This returns only after read outside alarm pulse.
Presence Latch (PRLB). This when level change been detected PRESB card interface signal asserted logic (active) while this set. This returns after read. Presence Latch (PRLA). This when level change been detected PRESA card interface signal asserted logic (active) while this set. This returns after read. INTAUX Latch (INTAUXL). This when level change been detected INTAUX pin. This remains set, regardless further level changes INTAUX until cleared read. Protection Thermal Latch (PTL). This when excessive heating (approximately +150°C greater) detected. signal asserted logic (active) while this set. This returns after read, unless condition persists.
Multiprotocol Dual Smart Card Interface DS8007
Card Interface Voltage Regulation Step-Up Converter Operation
VDDA pins supply power DS8007. Voltage supervisor circuitry detects input voltage levels automatically engages step-up converter necessary generate appropriate voltages card interfaces according control register settings. conversion process transparent user usually only noticed changes voltage, which reflects operation internal charge pump. Table elaborates pin. VDDA pins must decoupled externally, extra care must taken decouple large current spikes that occur VDDA pins because noise generated cards internal voltage stepup circuitry.
Table Step-Up Converter Operation
VOLTAGE VDDA 2.4-3.5 3.5-5.5 5.5-6.0 2.4-3.5 2.4-6.0 SMART CARD VDDA VDDA VDDA VDDA
Voltage Supply Supervision
voltage supervisor circuitry monitors holds device reset until satisfactory level. DELAY external indicator state internal power also driven externally hold device reset state. external capacitor usually attached this pin, defining time constant power-on delay DS8007. When below voltage threshold VRST, charging path that exists between DELAY disconnected strong pulldown enabled DELAY pin. Once exceeds VRST, strong pulldown DELAY released pullup enabled, allowing external DELAY capacitor charged. RSTOUT alarm released (allowing pulled externally) whenever DELAY voltage less than VDRST, whether caused VRST result external hardware pulling DELAY
low. minimum duration RSTOUT pulse specification) defined capacitor connected DELAY typically 2nF. RSTOUT driven strongly once DELAY exceeds VDRST voltage threshold. SUPL initial power-up reset again when RSTOUT alarm pulse occurs. SUPL only cleared read register. Figure illustrates sequencing various signals involved. Short-circuit thermal-protection circuitry prevent damages done accidentally shorting VCCx pins when ambient temperature exceeding maximum operating temperature. When internal temperature approximately +150°C, voltage VCCx drivers CLKx, RSTx, I/Ox, C4x, signals both card interfaces turned off. interrupt generated. When short detected RSTx pin, device initiates normal deactivation sequence. short I/Ox, C4x, does cause deactivation.
Multiprotocol Dual Smart Card Interface DS8007
VRST 2.1V 2.5V RESULTING FROM VRST DELAY DRIVEN EXTERNALLY VDRST ~1.25V DELAY
RSTOUT
SUPL
SUPL CLEARED READ ONLY
Figure Voltage Supervisor
Multiprotocol Dual Smart Card Interface DS8007
Activation Sequencing
activation sequence only requested host device through parallel interface. host request activation sequence specific card (card card setting START PCRx register (where determined card select bits CSR). host software activate both cards same time, only card selected transmit/receive given time. activation sequence only occur given satisfactory operating conditions (e.g., card present supply voltage correct). These conditions ascertained through HSR, MSR, bits. microcontroller attempts write PCRx.START without having satisfied necessary conditions, card activated does change. activation time (from assertion START until clock output enabled) less than 130µs. activation sequence detailed Figure
ACTIVATION SEQUENCE
DEACTIVATION SEQUENCE
START RSTIN
ACTIVATION NEEDS OCCUR UNDER 130s
RSTx
VCCx VCCx NEEDS DECREASE LESS THAN 0.4V
CLKx
I/0x
UNDEFINED
C4x,
ACCORDING PCRx.C4, PCRx.C8 BITS
TIMING
tACT
ACTIVATION SEQUENCE PCRx.START SOFTWARE. CONDITIONS NEEDED HARDWARE) ARE: MSR.PRx (CARD PRESENT) HSR.PRTLx, SUPL, PRLx, STEP-UP CONVERTER ACTIVATED (MAY ALREADY ANOTHER CARD ACTIVE). VCCx ENABLED 1.8V, SELECTED PCRx.1V8 PCR.3V/5V BITS. VCCx RISES FROM 1.8V, WITH CONTROLLED RISE TIME 0.17V/s TYPICAL. I/Ox PULLED HIGH. C4x, ALSO PULLED HIGH PCRx.C4 PCRx.C8 (RESPECTIVELY). THESE PINS HAVE INTEGRATED PULLUPS (14k I/Ox C8x) VCCx. CLKx OUTPUT ENABLED OUTPUT ENABLED. (PCRx.RSTIN SHOULD ACTIVE-LOW RSTx.) PCRx.RSTIN WRITTEN SOFTWARE AFTER USING TIME SUFFICIENT DURATION RSTx ASSERTION.
DEACTIVATION SEQUENCE PCRx.START CLEARED SOFTWARE. ACTIVE-LOW RSTx SIGNAL ASSERTED SOFTWARE. CLKx SIGNAL STOPPED. I/Ox, C4x, FALL VCCx DISABLED FALLS WITH TYPICAL RATE 0.17V/s. STEP-UP CONVERTER DEACTIVATED ANOTHER CARD PINS CLKx, RSTx, I/Ox, VCCx BECOME IMPEDANCE GROUND.
Figure Card Activation, Deactivation Sequences
Multiprotocol Dual Smart Card Interface
Deactivation Sequencing
host device request deactivation sequence resetting START desired card interface. deactivation (from deassertion START bit, step deactivation sequence, VCCx decrease less than 0.4V) less than 150µs. VCCX shorted, sequencer executes deactivation sequence same START cleared
DS8007
Interrupt Generation
output signals host device that event occurred that require attention. assertion function following sources: fault been detected card interfaces dropped below acceptable level. reset caused externally driving DELAY less than 1.25V. Excessive heating detected (i.e., level change been detected PRESx INTAUX card interfaces AUX). parity and/or frame error detected. early answer (EA) during ATR. timeout counter(s) reach their terminal count(s). FIFO full status reached. FIFO overrun occurs. transmit buffer empty.
Emergency Deactivation
emergency deactivation occurs unsatisfactory operating conditions detected. emergency deactivation occurs activated cards response supply-voltage brownout condition reported HSR.SUPL bit) chip overheating reported HSR.PTL). Emergency deactivation individual card occur short-circuit condition detected associated RSTx reported HSR.PRTLx) case card takeoff reported HSR.PRLx). When emergency deactivation occurs, hardware automatically forces associated START bit(s) state. response device emergency deactivation varies according source. RSTx shorted device overheats, sequencer executes fast emergency deactivation sequence, which ramps down VCCX immediately.
HSR.PRTLA HSR.PRLA HSR.PRTLB HSR.PRLB HSR.SUPL HSR.PTL HSR.INTAUXL UCR2A.DISAUX UCR2B.DISAUX UCR2AUX.DISAUX SCA, SCB, SCAUX USR.TO3 USR.TO2 USR.TO1 USR.EA USR.PE USR.OVR USR.FER USR.TBE/RBF UCR2A.DISTBE/RBF UCR2B.DISTBE/RBF UCR2AUX.DISTBE/RBF SCA, SCB, SCAUX INTERRUPT GENERATION OUTPUT
Figure Interrupt Sources
Multiprotocol Dual Smart Card Interface DS8007
Timeout Counter Operation
timeout counter assists host device timing real-time events associated with communication protocols: Work Wait Time (WWT), Block Waiting Time (BWT), etc. timeout counter registers count ETUs, input clock timeout counter derived from output programmable divided clock (per card register). timeout counter requires card powered have active clock. timeout counter operate single 24-bit counter (TOR3-TOR1) separate 16-bit (TOR3-TOR2) 8-bit (TOR1) counters. timeout counters operated either software mode start mode. software mode supported 16-bit 24-bit counters. start-bit mode supported counter widths bit, bit, bit). Table possible stop start 16-bit software counter while leaving 8-bit counter enabled (e.g., 05h, 85h, etc.). compatible software mode command written register before terminal count reached (e.g., write register while command running vice versa), command ignored (still software mode), register updated with command, counter continues count until terminal count reached, respective timeout flag(s) set, interrupt generated.
Start-Bit Mode
When configured start-bit mode, counting starts (and restarts 16-bit 24-bit counters) when START detected active card interface I/Ox pin. When terminal count reached, 8-bit autoreload counter begins counting from previously programmed start value, while 16-bit counter 24-bit counter stops when terminal count reached. terminal count reached, timeout flag interrupt generated. 8-bit autoreload TOR1 register cannot modified during count. 16-bit 24-bit counter registers modified during count without affecting current count. register data used next START detection.
Software Mode
software mode, software configures counter starting value (while stopped) starts down counter writing configuration value register. When terminal count reached (0h), counter stops, timeout flag set, interrupt generated. software counter does reach terminal count, must stopped before loading value into associated TORx counter registers.
Table Timeout Counter Configurations
VALUE Stopped TOR3 TOR2 Stopped Start Bit/Autoreload TOR1 counters stopped. Counters stopped. Counter continues startbit/autoreload mode both transmission reception. Counter stopped. Counters form 16-bit counter operating software mode. counter stopped writing register, must stopped before reloading values TOR3 TOR2 registers. Counters form 16-bit counter operating software mode. Writing register before reloading values TOR2/TOR3 stops counters. Counter operated startbit/autoreload mode. TOR1 register change during count. 16-bit counters stopped setting 05h. Both counters stopped setting 00h. Counters form 24-bit counter operating software mode. counter starts after command written register, stopped setting 00h. TOR3, TOR2, TOR1 cannot changed without stopping counter first. DESCRIPTION
Software
Stopped
Software
Start Bit/Autoreload
Software
Multiprotocol Dual Smart Card Interface DS8007
Table Timeout Counter Configurations (continued)
VALUE TOR3 TOR2 TOR1 DESCRIPTION Counter stopped. Counters form 16-bit counter operating start mode both transmission reception. TOR3 TOR2 registers changed during count, current count affected, values taken into account next START detected I/Ox pin. Setting stops counters. Counter 8-bit counter start-bit/autoreload mode both transmission reception; counters form 16-bit counter operating start-bit mode both transmission reception. TOR1 register allowed change during count. TOR3, TOR2 registers changed during count, current count affected, values taken into account next START detected I/Ox pin. Setting stops counters. Counters 1/2/3 form 24-bit counter operating start-bit mode both transmission reception. TOR3, TOR2 TOR1 registers changed during count, current count affected, value taken into account next START detected I/Ox pin. Setting stops counter. Counters stopped. Counter operated startbit/autostop mode reception stopped 12th following first received START detected I/Ox unless terminal count reached first. Counter operates startbit/autoreload mode transmission. Counters form 16-bit counter operating software mode. counters stopped setting before reloading values TOR3 TOR2 registers. Counter operated autostop mode reception stopped 12th following first received START detected I/Ox unless terminal count reached first. Counter operated start-bit/autoreload mode transmission. Counter stopped. Counters form 16-bit counter. 16-bit counter operated start-bit/auto-stop mode reception stopped 12th following first received START detected I/Ox unless terminal count reached first; 16-bit counter operated start-bit mode transmission. Counter 8-bit counter operating start-bit/autostop mode reception stopped 12th following first received START detected I/Ox unless terminal count reached first; 8-bit counter operated startbit/autoreload mode transmission. Counters form 16-bit counter operating start-bit mode transmission operate start-bit/autostop mode reception. Counters stopped 12th following first received START detected I/Ox unless terminal count reached first; counters stopped setting 00h.
Start
Stopped
Start
Start Bit/Autoreload
Start
Stopped
Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT) Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT)
Software
Start Bit/Autostop (RCV); Start (XMT)
Stopped
Start Bit/Autostop (RCV); Start (XMT)
Start Bit/Autostop (RCV); Start Bit/Autoreload (XMT)
Multiprotocol Dual Smart Card Interface DS8007
UART Implementation
Reset Operation
HSR.RIU control resets UART. HSR.RIU must reset prior activation. HSR.RIU must returned software before UART action take place.
Asynchronous Mode
asynchronous mode operation reset default mode card interfaces selected when synchronous/asynchronous card select (for given card interface) configured logic I/Ox card interface signal used asynchronous half-duplex data communication between host-controlled UART external smart card. host device optionally stop CLKx signal high state while card active using CCRx.CST CCRx.SHL register bits.
Synchronous Mode
synchronous mode operation invoked setting synchronous/asynchronous card select (for given card interface) logic synchronous mode operation, associated I/Ox card interface data transferred UART transmit/receive registers (UTR URR). this mode, host device using CCRx.SC register manually controls CLKx selected card interface. Switching synchronous mode vice versa allowed time when card active. However, responsibility host software/firmware ensure that current transmission concluded before switching. software configures active card synchronous mode, then activates another card, previously active card goes high-impedance state with weak pullup (high). newly selected interface configured synchronous mode) takes UTR.0. card interface does have associated signal, CCRAUX.SC does control output signal when synchronous mode operation effect. handshake between host auxiliary smart card interface accomplished through auxiliary interrupt input (INTAUX) pins. MSR.INTAUX reflects state INTAUX pin. UCR2.DISAUX cleared change INTAUX input results assertion output pin. host software/firmware establishes communication protocol controls when transmit/receive data response interrupt. UCR2.DISAUX asserted, host software/firmware must examine INTAUX register responds accordingly.
Generation Timing
basic unit time asynchronous mode communication I/Ox signal elementary time unit (ETU). defined within UART function fCLK frequency that configured card interface (i.e., same fCLK that sourced CLKx associated card interface addition receiving fCLK from clock generation block, UART additionally receives fCLK frequency CCRx.AC2-AC0 000b. host device select whether fCLK fCLK used generation using clock UART (CKU) select bit. When fCLK used, while fCLK used when exception exists when CCRx.AC2-AC0 000b, which case, only fCLK sourced UART setting effect duration ETU. basic clock that selected generation further prescaled factor prescaler select control (PSC) makes this prescaler selection. When configured logic prescale setting When configured logic prescale setting output clock prescaler drives 8-bit autoreload down counter. autoreload value downcounter configured host device through Programmable Divider Register (PDR). interval provided this downcounter defines duration selected card. Figure shows diagram generation. asynchronous character transmit/receive operations defined terms (e.g., 10.5 ETU, 10.25 ETU, etc).
Multiprotocol Dual Smart Card Interface DS8007
CLOCK PRESCALER /31: /32:
PD7:PD0 COUNTERS TO3, TO2,
fCLK UCR2x.PSC fCLK
SOFTWARE MODE (ALIGNED GENERATOR)
UCR2x.CKU
CLOCK PRESCALER /31: /32: 0.5ETU PD7:PD0 0.25ETU FRACTIONAL COUNTERS 10.5
RSTx START GATE FRAME-ERRORDETECTED COUNTER 10.25
Figure Generation
Standard Clock Frequencies Baud Rates
DS8007 supports communication CLKx frequency generation compliant following standards: 7816, EMV2000, GSM11-11. Each these standards allowable CLKx frequency range defined relationship between CLKx frequency (baud rate) generation that supported initially after negotiation. 7816, relationship between (baud rate) timing CLKx frequency follows: fCLKX) minimum CLKx frequency fixed 1MHz. default maximum CLKx frequency 5MHz, however maximum CLKx frequency increased according parameter given card during
ATR. 7816-1997(3) specification recommends Section 4.3.4 that CLKx frequency switches made immediately after immediately after successful exchange. transmission parameters respectively clock-rate conversion baud-rate adjustment factors. notations used represent `d'efault values these parameters, which notation used represent values `i'ndicated card within TA(1) character ATR. TA(1) present, then Fi,Di default Fd,Dd values. notation represent values `n'egotiated during successful exchange, which should range Fd-Fi Dd-Di, respectively. During ATR, default values shall apply. card comes negotiable mode (i.e., TA(2) absent from ATR), then parameters con-
Multiprotocol Dual Smart Card Interface DS8007
tinue used until successful exchange completed. negotiated values then used after successful exchange. card comes specific mode (i.e., TA(2) present ATR), then indicated values apply immediately after successful TA(2) character TA(2) implicit values should used. TA(1) character ATR, present, contains values indicated card. Table demonstrates prescaler (PSC) programmable divider register (PDRx) configured generate requested ratios. settings assume that configured reset default logic state.
Table Parameter Possibilities
TA(1).FI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 1116 1488 1860 1024 1536 2048 CLKx (MHz) TA(1).DI 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111
Reserved future use.
Table PSC, Settings Support Parameters
TA(1).Fi 0000 0001 0010 0011 0100 0101 0110 1001 1010 1011 1100 1101 SETTING 0001 0010 0011 0100 0101 0110 1000 1001
Multiprotocol Dual Smart Card Interface
Character Encoding/ Decoding Convention
UART designed support possible character encoding/decoding formats: direct inverted. direct character coding convention transmits receives data first associates high logic level with logic level with inverse character coding convention transmits receives data most significant first associates high logic level with logic level with UCR1.CONV defines which character convention (CONV 0:inverse; CONV 1:direct) should used UART. UCR1.CONV configured host device software configured hardware automatic convention detection been enabled.
DS8007
CHARACTER (CONVEYS CODING CONVENTION)
DIRECT CONVENTION (BYTE 3Bh)
INVERSE CONVENTION (BYTE 3Fh)
Automatic Convention Detection
automatic convention detection relies upon recognition predefined pattern first character received character) establishing future character coding convention. enable automatic convention detection, UCR1.SS must logic UCR2.AUTOC should configured logic prior ATR. automatically cleared hardware 10.5 after character received. automatic convention detection enabled unrecognized character received, CONV written. neither direct inverse character detected, parity error occurs along with error signal generation protocol. AUTOC should modified during card session.
Figure Direct, Inverse Character Coding Conventions
UART I/OA I/OB I/OAUX fCLKx fCLKx START DETECT
PDR.PD[7:0] GTR.GTR.[7:0] UCR1 UCR2 CSR.RIU MSR.FER MSR.BGT MSR.TBE/RBF USR.EA USR.PE USR.OVR USR.FER
Framing Error Detection
DS8007 monitors selected card I/Ox signal 10.25 following each detected start bit. I/Ox signal high state this point time, USR.FER (framing error) 10.5 ETU. cleared whenever read.
FCR.PEC[2:0] FIFO(8) FCR.FL[2:0]
Figure UART Signal Interface
Multiprotocol Dual Smart Card Interface DS8007
Block Guard Time
block guard time asynchronous serial communication between smart card reader (DS8007) defined minimum delay between consecutive start bits sent opposite direction. DS8007 implements internal counter specifically help host device assess that this minimum block guard time being met. This internal counter loaded each start with value 16d, dependent upon protocol selected. counter loaded with value counter loaded with value 22d. counter reaches MSR.BGT status counter stops. start detected before counter reaches counter reloaded status cleared retransmission occurring), character translated according character coding convention (CONV bit) moved from transmit buffer serial shift register. TBE/RBF returns high that another character loaded into register.
Transmit Mode
UART transmit mode invoked setting associated UCR1.T/R logic When UART placed into transmit mode, TBE/RBF indicate that transmit buffer empty. When character written register, TBE/RBF cleared indicate that transmit buffer longer empty. transmit serial shift register available (which case unless character
Guard Time Some smart cards require extra time handle information received from interface device. allow this extra time, DS8007 implements Guard Time Register (GTR) card interface. This register programmed with number extra that should enforced between consecutive start bits transmitted DS8007 (discounting retransmissions request ICC). register defaults reset, indicating that extra guard time required (i.e., must enforced between transmission consecutive start bits). register programmed FFh, delay required between consecutive start bits dependent upon protocol selected (per UCR1.PROT).
protocol: 11.8 protocol: 10.8
BLOCK GUARD TIME (BGT) COUNTER STATUS COUNTER CLEAR RESTART COUNTER (e.g.,
COUNTER (STOPPED):
I/Ox
Figure Block Guard Time Counter Operation
Multiprotocol Dual Smart Card Interface
Last Character Transmit UART implements special control input that allows automatic switch from transmit mode (UCR1.T/R receive mode (UCR1.T/R upon successful character transmission. last character transmit (UCR1.LCT) must host software prior writing last character transmission UTR. Upon successful transmission character, UCR1.T/R cleared hardware. When used, TBE/RBF transmission. Receive Mode UART receive mode effect associated UCR1.T/R When UART changed receive mode, MSR.FE indicate that receive FIFO empty. When least unread receive character exists FIFO, cleared. When FIFO, with depth defined FL2-FL0, full, TBE/RBF indicate that receive buffer full. Once character read from full FIFO, RBF/TBE cleared indicate that FIFO longer full. controller ready
(CRED) should polled assess data readiness when reading from register high frequencies.
DS8007
Parity Check protocol selection checks receive parity. parity error count bits (PEC2-PEC0) have function USR.PE first parity error. protocol selection also checks receive parity, allows setting USR.PE parity error based upon detection parity errors. PEC2-PEC0 bits define number consecutive parity errors that should detected before setting USR.PE. UART implements special control input that allows testing inverse parity. UCR1.FIP configured during receive mode, UART tests correct parity each received character. UCR1.FIP configured inverse parity expected. This control useful testing that properly detects error signals generated DS8007 retransmits requested characters.
LAST CHARACTER TRANSMIT WRITTEN SOFTWARE, THEN LOAD UTR. LAST CHARACTER LAST CHARACTER REMAINS BITS BOTH CLEARED HARDWARE.
TBE/RBF
Figure Last Character Transmit
Multiprotocol Dual Smart Card Interface
Error-Signal Generation protocol does support error-signal generation. When configured receive using protocol (UCR1.PROT DS8007 supports errorsignal generation response parity. parity error count bits (PEC2-PEC0) FIFO control register (FCR) determine number allowed repetitions reception, therefore number times that error signal generated response received character with incorrect parity before USR.PE becomes set. When receiving character, DS8007 verifies even parity combination received 8-bit character parity bit. incorrect parity determined consecutive parity error counter reached terminal count (000b), DS8007 generates error signal I/Ox line starting 10.5 lasting ETU. parity error counter initialized through PEC2-PEC0 bits. Configure PEC2-PEC0 bits 000b means that repetition reception allowed that error signal generation occurs response character received with incorrect parity. Configuring PEC2-PEC0 bits 001b means repetition reception allowed that DS8007 generates error signal only once character receive attempt. When consecutive parity error counter reaches 000b character received with incor-
DS8007
rect parity, USR.PE parity error counter reached terminal count, reset originally programmed value upon reception character having correct parity. Once USR.PE signals parity count error, software must re-establish nonzero PEC2-PEC0 setting.
Receive FIFO DS8007 implements enhanced receive FIFO. FIFO threshold-enable bits FTE0 FTE1 FIFO functions standard FIFO that configurable depth characters. protocols allow FIFO depth determined FCR.FL2-FCR.FL0 bits. When configurable, FIFO depth equal (FL2-FL0) (e.g., FL2-FL0 001b configures FIFO depth RBF/TBE status bits report full empty FIFO conditions, respectively. receive FIFO full maximum depth FIFO Overrun (OVR) character received lost, previous FIFO contents remain undisturbed. received characters read from URR. When receive FIFO enabled, reads always access oldest available received data. FIFO initialized every time receive mode invoked (i.e., cleared
ERROR-SIGNAL GENERATION PROTOCOL ONLY) (INCORRECT PARITY 000b) HARDWARE ERROR SIGNAL 10.5 ETU-11.5 DECREMENT PARITY COUNTER. (CORRECT PARITY RESET PARITY ERROR COUNTER ORIGINAL PEC2-PEC0 PROGRAMMED VALUE.
PARITY DOES CHECK
CHARACTER TIME
CHARACTER (RETRANSMIT)
Figure Receive Mode-Error Signal Generation
Multiprotocol Dual Smart Card Interface
protocol, only received characters without parity errors stored receive FIFO. When UCR1.FIP during reception, only those characters with incorrect parity stored receive FIFO since DS8007 checking inverse parity. protocol, receive character stored FIFO matter whether parity checks correctly not. FIFO threshold enable bits FTE0 FTE1 FIFO implements programmable threshold assertion RBF/TBE bits interrupt line. this mode, internal FIFO length forced bytes, FL[2:0] (the programmable FIFO length bits) determines threshold value. Characters accumulated FIFO without setting RBF/TBE bits until FIFO depth greater than threshold value. long used depth greater than FL[2:0] value, RBF/TBE bits (USR MSR) interrupt asserted. Reading FIFO level less than equal threshold value resets RBF/TBE deasserts interrupt line. Writing zero eight into bits while programmable threshold mode enabled causes FIFO behave does nonprogrammable threshold mode. programmable FIFO depth maximum characters) RBF/TBE when eighth character received written into FIFO. another character received while FIFO full, overflow (OVR) status set, character overwrites previously received character. programmable FIFO depth zero, receipt single character sets RBF/TBE. Receiving another character this state sets overwrites character. FIFO empty status (FE) operates before. programmable threshold feature functions same modes.
DS8007
Table Early Answer Detection
WHEN START ASSERTED Between clock cycles when RSTx Between clock cycles when RSTx Between clock cycles when RSTx Within first clock cycles after RSTx high Between 4000 clock cycles after RSTx high STATUS CHARACTER RECEIVED
Early Answer (EA)
start detected line during between clock cycles 200-368 when RSTx during first clock cycles after RSTx high, recognized early answer (EA), USR.EA register. When set, asserted. During early answer detection period, clock cycles sampling periods should used detect start there undetected (uncertainty) period clock cycles both cases (between clock cycles 200-368 when RSTx low, first clock cycles after RSTx high). Table summarizes status early answer bit. answer line begins between 40,000 clock cycles after rising edge RSTx signal.
Development Technical Support
DS8007 evaluation kit) available assist development designs using DS8007 multiprotocol smart card interface. purchased directly from Maxim. technical support,
Package Information
latest package outline information land patterns, www.maxim-ic.com/packages. PACKAGE TYPE LQFP PACKAGE CODE C48L+1 DOCUMENT 21-0054
DS8007
Multiprotocol Dual Smart Card Interface
VBAT DVDD VCCO VBAT 0.1F AVDD 0.22F CPA2 CPB1 0.22F DS8007 0.22F CPB2 0.1F VDDA CPA1 VCC0 CE1N P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 DS5002FP P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 CARD SOCKET CCM01-2065LFT SOCKET I/0A GNDA CLKA RSTA VCCA PRESA CE3/A15 CE2/A16 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 14.7456MHz 22pF 22pF XTAL2 DELAY RSTOUT I/OAUX INTAUX XTAL1 I/OB GNDB CLKB RSTB VCCB PRESB AGND 0.1F 0.1F 0.1F PROG CCM03-3001LFT P3.0/RXD P3.1/TXD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/TI P3.6 P3.7 DELAY VRST PROG NC68 NC73 XTAL2 MSEL 22pF XTAL1 14.7456 22pF
VCCO
0.1F
CY62148BLL-70SXC
Typical Operating Circuit
Multiprotocol Dual Smart Card Interface
Revision History
REVISION NUMBER REVISION DATE 1/07 10/07 DESCRIPTION PAGES CHANGED
DS8007
Initial release. Features section, changed (min) (min); added bullet EMV-certified reference design availability. General Description, added "ISO 7816" "UART" clarification; Features section, added clarification about integrated 7816 UART.
8/08
EMVCo approval interface module (IFM) contained this Terminal shall mean only that been tested accordance sufficient conformance with Specifications, Version 3.1.1, date testing. EMVCo approval endorsement warranty regarding completeness approval process functionality, quality performance particular product service. EMVCo does warrant products services provided third parties, including, limited producer provider EMVCo approval does under circumstances include imply product warranties from EMVCo, including, without limitation, implied warranties merchantability, fitness purpose, noninfringement, which expressly disclaimed EMVCo. rights remedies regarding products services which have received EMVCo approval shall provided party providing such products services, EMVCo EMVCo accepts liability whatsoever connection therewith. Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600
2008 Maxim Integrated Products registered trademark Maxim Integrated Products, Inc.
registered trademark Dallas Semiconductor Corporation.
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