LTM®9003 12-bit digital pre-distortion receiver subsystem transmit pat

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LTM®9003 12-bit digital pre-distortion receiver subsystem transmit pat

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LTM9003 12-Bit Digital Pre-Distortion Receiver Subsystem FEATURES
LTM®9003 12-bit digital pre-distortion receiver subsystem transmit path cellular basestations. Utilizing integrated system package (SiP) tech-nology, includes downconverting mixer, wideband filter analog-to-digital converter (ADC). system tuned intermediate frequency (IF) 184MHz signal bandwidth 125MHz. 12-bit samples rates 250Msps. Contact Linear Technology regarding customization. high signal level downconverting active mixer optimized high linearity, wide dynamic range sampling applications. includes differential buffer amplifier driving double-balanced mixer. Broadband, integrated transformers inputs provide single ended interfaces. inputs internally matched from 1.1GHz 1.8GHz. input controls converter operation driven differentially single-ended. optional clock duty cycle stabilizer allows high performance full speed wide range clock duty cycles.
LTC, LTM, Linear Technology Linear logo registered trademarks Linear Technology Corporation. other trademarks property their respective owners. Protected U.S. Patents including 5481178, 6580258, 6304066, 6127815, 6498466, 6611131.
Fully Integrated Receiver Subsystem Digital Pre-Distortion Applications Down-Converting Mixer with Wide Frequency Range: 400MHz 3.8GHz 125MHz Wide Bandpass Filter, <0.5dB Passband Ripple Power with 12-Bit Resolution, 250Msps Sample Rate -145.5dBm/Hz Input Noise Floor, 25.8dBm IIP3 1.5W Total Power Consumption Single-Ended Ports Internal Bypass Capacitance, External Components Clock Duty Cycle Stabilizer 11.25mm 15mm package
APPLICATIONS
Transmit Observation Path Receivers Digital Pre-Distortion (DPD) Receivers Wideband Receiver Wideband Instrumentation
TYPICAL APPLICATION
3.3V 2.5V LTM9003 OVDD 2.5V
4-Channel WCDMA Input 1.95GHz
(dB) LVDS -100 -110
DGND ENC- ENC+
9003 TA01
FREQUENCY (MHz)
9003 TA01b
9003p
LTM9003 ABSOLUTE MAXIMUM RATINGS
(Notes
CONFIGURATION
VIEW OTHERS
Supply Voltage (VCC1) LTM9003-AA -0.3V 3.6V LTM9003-AB -0.3V 5.5V Supply Voltage (VCC2) -03V 5.5V Supply Voltage (VDD, OVDD) -0.3V 2.8V Digital Output Ground Voltage (OGND) -0.3V Input Power (380MHz 4.2GHz) .10dBm Input Voltage. VCC1 Input Power (400MHz 3.8GHz) .15dBm Input Voltage ±0.1V Mixer Enable Voltage .-0.3V VCC1 0.3V Enable Input Current. ±10mA Digital Input Voltage. -0.3V (VDD 0.3V) Digital Output Voltage -0.3V (OVDD 0.3V) Operating Ambient Temperature Range LTM9003CV 70°C LTM9003IV .-40 85°C Storage Temperature Range 125°C Maximum Junction Temperature 125°C CAUTION: inputs sensitive electrostatic discharge (ESD). very important that proper precautions observed when handling LTM9003.
OVDD
VCC1
ENC- ENC+
VCC2
AMP_EN MIX_EN
DATA, CONTROL 2.32mm)
PACKAGE 108-LEAD (15mm 11.25mm
TJMAX 125°C, 15°C/W, 6°C/W DERIVED FROM TBDmm TBDmm WITH LAYERS WEIGHT
ORDER INFORMATION
LEAD FREE FINISH LTM9003CV-AA#PBF LTM9003IV-AA#PBF LTM9003CV-AB#PBF LTM9003IV-AB#PBF TRAY LTM9003CV-AA#PBF LTM9003IV-AA#PBF LTM9003CV-AB#PBF LTM9003IV-AB#PBF PART MARKING* LTM9003V LTM9003V LTM9003V LTM9003V PACKAGE DESCRIPTION 108-Lead (11.25mm 15mm 2.3mm) 108-Lead (11.25mm 15mm 2.3mm) 108-Lead (11.25mm 15mm 2.3mm) 108-Lead (11.25mm 15mm 2.3mm) TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C
Consult Marketing parts specified with wider operating temperature ranges. *The temperature grade identified label shipping container. more information lead free part marking, http://www.linear.com/leadfree/ This product only offered trays. more information
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LTM9003 ELECTRICAL CHARACTERISTICS
PARAMETER Input Frequency Range CONDITIONS LTM9003-AA External Matching (Midband) With External Matching (Low Band High Band) LTM9003-AB External Matching (Midband) With External Matching (Low Band High Band) Input Frequency Range LTM9003-AA External Matching With External Matching LTM9003-AB External Matching With External Matching Input Return Loss 1100MHz 1800MHz External Matching) LTM9003-AA LTM9003-AB 900MHz 3500MHz External Matching) LTM9003-AA LTM9003-AB LTM9003-AA LTM9003-AB 1200MHz 4200MHz, LTM9003-AA 1200MHz 3500MHz, LTM9003-AB 380MHz 1200MHz LTM9003-AA 380MHz 1600MHz 1600MHz 4000MHz LTM9003-AB 400MHz 2100MHz 2100MHz 3200MHz Isolation LTM9003-AA 400MHz 1700MHz 1700MHz 3800MHz LTM9003-AB 400MHz 2200MHz 2200MHz 3700MHz
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
1100 1800 1100 1800 3500 3500 -1.8 -1.8 <-50 <-45 <-44 <-36 3700 3800 UNITS
Input Return Loss
Input Power -1dBFS Input Power
Leakage
CONVERTER CHARACTERISTICS
PARAMETER Resolution Missing Codes) Integral Linearity Error (Note Differential Linearity Error CONDITIONS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
UNITS Bits
184.32MHz 184.32MHz
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LTM9003 FILTER CHARACTERISTICS
PARAMETER Center Frequency Lower Bandedge Upper Bandedge Lower 20dB Stopband Upper 20dB Stopband Passband Flatness Group Delay Flatness Absolute Delay LTM9003-Ax LTM9003-Ax LTM9003-Ax LTM9003-Ax LTM9003-Ax 129MHz 239.6MHz, LTM9003-Ax 174MHz 194MHz, LTM9003-Ax 129MHz 239.6MHz, LTM9003-Ax 174MHz 194MHz, LTM9003-Ax LTM9003-Ax
denotes specifications which apply over full operating temperature
184.32 0.15 UNITS
range, otherwise specifications 25°C.
CONDITIONS
DYNAMIC ACCURACY
SYMBOL PARAMETER Signal-to-Noise Ratio -1dBFS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS 1950MHz, 1766MHz 1889MHz, 1766MHz 2011MHz, 1766MHz LTM9003-AA 1948MHz, 1952MHz, 1766MHz LTM9003-AB 1948MHz, 1952MHz, 1766MHz
143.7 143.7 25.8 26.5 52.4
UNITS dB/Hz dB/Hz dB/Hz
IIP3
Input Order Intercept, 2-Tone
IIP2
Input Order Intercept, 1-Tone
LTM9003-AA 1950MHz, 1766MHz LTM9003-AB 1950MHz, 1766MHz
SFDR
Spurious Free Dynamic Range Harmonic -1dBFS
LTM9003-AA 1889MHz, 1766MHz 1950MHz, 1766MHz 2011MHz, 1766MHz LTM9003-AB 1889MHz, 1766MHz 1950MHz, 1766MHz 2011MHz, 1766MHz
67.4 71.5
SFDR
Spurious Free Dynamic Range Higher -1dBFS
1950MHz, 1766MHz 1889MHz, 1766MHz 2011MHz, 1766MHz
S/(N+D)
Signal-to-Noise Plus Distortion Ratio -1dBFS 1950MHz, 1766MHz 1889MHz, 1766MHz 2011MHz, 1766MHz Intermodulation Distortion -7dBFS Tone Adjacent Channel Power Ratio 2.4dBm Carrier, Four Carriers Alternate Channel Power Ratio 2.4dBm Carrier, Four Carriers 1950MHz, 1766MHz
58.5 63.3
IMD3 ACPR ALTCPR
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LTM9003 DIGITAL INPUTS OUTPUTS
SYMBOL VICM Mixer Enable High Level Input Voltage Level Input Voltage Input Current Turn-On Time Turn-Off Time Amplifier Enable ISENSE IMODE ILVDS OVDD 2.5V Differential Output Voltage Output Common Mode Voltage Differential Load Differential Load
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
PARAMETER Differential Input Voltage Common Mode Input Voltage Input Resistance Input Capacitance High Level Input Voltage Level Input Voltage Input Current Input Capacitance 2.5V 2.5V (Note VCC1 3.3V, LTM9003-AA VCC1 LTM9003-AB VCC1 3.3V, LTM9003-AA VCC1 LTM9003-AB VCC1, LTM9003-AA VCC2 3.3V VCC2 3.3V VCC2 SENSE Descriptions Voltage Levels Descriptions Voltage Levels
CONDITIONS
UNITS
Encode Inputs (ENC-, ENC+) Internally Externally
Logic Inputs (OE, SHDN)
High Level Input Voltage Level Input Voltage Input Current SENSE Input Leakage MODE Pull-Down Current LVDS Pull-Down Current
Control Inputs (SENSE, MODE, LVDS)
Logic Outputs (LVDS Mode) 1.125 1.250 1.375
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LTM9003 POWER REQUIREMENTS
SYMBOL VCC1 VCC2 ICC1 ICC1(SHDN) ICC2 ICC2(SHDN) IDD(ADC) PD(SHDN) PD(NAP) OVDD IOVDD(ADC) PD(ADC) PD(TOTAL) PARAMETER Mixer Supply Range Amplifier Supply Range Analog Supply Voltage Mixer Supply Current Mixer Shutdown Supply Current Amplifier Supply Current Supply Current Shutdown Power Mode Power Digital Output Supply Voltage Digital Output Supply Current Power Dissipation Total Power Dissipation SHDN MIX_EN AMP_EN fSAMPLE (LTM9003-AA) (LTM9003-AB) SHDN SHDN
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
CONDITIONS LTM9003-AA LTM9003-AB 2.375 MIX_EN LTM9003-AA MIX_EN LTM9003-AB MIX_EN AMP_EN
5.25 5.25 2.625
UNITS
Amplifier Shutdown Supply Current AMP_EN
LVDS Output Mode 2.375 1472 1591 2.625
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LTM9003
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. (Note
SYMBOL tJITTER LVDS Output Mode DATA delay CLKOUT Delay DATA CLKOUT Skew Rise Time Fall Time Pipeline Latency Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note voltage values with respect ground with OGND wired together (unless otherwise noted). (Note (Note (Note
TIMING CHARACTERISTICS
PARAMETER Sampling Frequency Time High Time
CONDITIONS
UNITS fsRMS
Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note Duty Cycle Stabilizer (Note
Sample-and-Hold Acquisition Delay Time Jitter Sample-and-Hold Aperture Delay Output Enable Delay (Note
-0.6
Cycles
Note VCC1 VCC2 3.3V (LTM9003-AA) VCC1 VCC2 3.3V (LTM9003-AB), 2.5V, OVDD 2.5V, fSAMPLE 250MHz, input range -1dBFS, differential ENC+/ENC- 2VP-P sine wave, unless otherwise noted. Note Integral nonlinearity defined deviation code from "best straight line" transfer curve. deviation measured from center quantization band. Note Guaranteed design, subject test.
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LTM9003 TIMING DIAGRAM
ANALOG INPUT ENC- ENC+ D0-D11,
CLKOUT- CLKOUT+
9003 TD01
LVDS Output Mode Timing Outputs Differential Have LVDS Levels
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LTM9003 TYPICAL PERFORMANCE CHARACTERISTICS
Point FFT, LTM9003-AA
1950MHz -1dBFS SENSE AMPLITUDE (dBFS) -100 -110 -120 FREQUENCY (MHz)
9003
Point 2-Tone FFT, LTM9003-AA
1948MHz, 1952MHz -7dBFS TONE SENSE AMPLITUDE (dBFS) -100 -110 -120 FREQUENCY (MHz)
9003
Frequency, LTM9003-AA
(dBFS)
FREQUENCY (MHz)
9003
Frequency Response, LTM9003-AA
-0.5 AMPLITUDE (dBFS) -1.0 -1.5 -2.0 -2.5 -3.0 AMPLITUDE (dBFS)
9003
Frequency Response, LTM9003-AA
FREQUENCY (MHz)
FREQUENCY (MHz)
9003
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LTM9003 TYPICAL PERFORMANCE CHARACTERISTICS
Point FFT, LTM9003-AB
1950MHz -1dBFS SENSE AMPLITUDE (dBFS) AMPLITUDE (dBFS) -100 -110 -120 FREQUENCY (MHz)
9003
Point 2-Tone FFT, LTM9003-AB
1948MHz, 1952MHz -7dBFS TONE SENSE -100 -110 -120 FREQUENCY (MHz)
9003
Frequency, LTM9003-AB
(dBFS)
FREQUENCY (MHz)
9003
Frequency Response, LTM9003-AB
-0.5 AMPLITUDE (dBFS) -1.0 -1.5 -2.0 -2.5 -3.0 AMPLITUDE (dBFS)
9003
Frequency Response, LTM9003-AB
FREQUENCY (MHz)
FREQUENCY (MHz)
9003
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LTM9003 FUNCTIONS
VCC1 (Pins F2): 3.3V (LTM9003-AA) (LTM9003-AB) Supply Voltage Mixer. VCC1 internally bypassed GND. VCC2 (Pins B2): 3.3V Supply Voltage Amplifier. VCC2 internally bypassed GND. (Pins D11, E8): 2.5V Supply Voltage ADC. internally bypassed GND. OVDD (Pins G12, H11): Positive Supply Output Drivers. Bypass ground with 0.1F ceramic chip capacitor. OVDD 0.5V 2.6V. OVDD internally bypassed OGND. (See Table Locations): Module Ground. OGND (Pins F12, H10, H12, J12): Output Driver Ground. (Pin G1): Single-Ended Input Signal. This internally connected primary side input transformer, which resistance ground. source blocked, then series blocking capacitor must used. input internally matched from 1.1GHz 1.8GHz. Operation down 400MHz 3.8GHz possible with simple external matching. (Pin J2): Single-Ended Input Local Oscillator Signal. This internally connected primary side transformer, which internally blocked. external blocking capacitor required. input internally matched from 0.9GHz 3.5GHz. Operation down 380MHz possible with simple external matching. MIX_EN (Pin F4): Mixer Enable Pin. Connecting MIX_EN VCC1 results normal operation. Connecting MIX_EN disables mixer. MIX_EN should left floating. AMP_EN (Pin C3): Amplifier Enable Pin. This internally pulled high typically resistor VCC2. Connecting AMP_EN VCC2 results normal operation. Connecting AMP_EN disables amplifier. ENC+ (Pin D12): Encode Input. Conversion starts positive edge. ENC- (Pin E12): Encode Complement Input. Conversion starts negative edge. Bypass ground with 0.1F ceramic single-ended ENCODE signal.
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SHDN (Pin B11): Shutdown Mode Selection Pin. Connecting SHDN results normal operation with outputs enabled. Connecting SHDN results normal operation with outputs high impedance. Connecting SHDN results mode with outputs high impedance. Connecting SHDN results sleep mode with outputs high impedance. (Pin C11): Output Enable Pin. Refer SHDN function. MODE (Pin C7): Output Format Clock Duty Cycle Stabilizer Selection Pin. Connecting MODE selects offset binary output format turns clock duty cycle stabilizer off. selects offset binary output format turns clock duty cycle stabilizer selects complement output format turns clock duty cycle stabilizer selects complement output format turns clock duty cycle stabilizer off. SENSE (Pin G7): Reference Programming Pin. Connecting SENSE selects internal reference ±0.5V input range. selects internal reference input range. external reference greater than 0.5V less than applied SENSE selects input range ±VSENSE. largest valid input range. LVDS (Pin D7): Output Mode Selection Pin. Connect LVDS VDD. Digital Outputs D0-/D0+ D11-/D11+ (See Table Locations): LVDS Digital Outputs. LVDS outputs require differential termination resistors LVDS receiver. D11-/D11+ MSB. CLKOUT-/CLKOUT+ (Pins J10/J11): LVDS Data Valid Output. Latch data rising edge CLKOUT-, falling edge CLKOUT+. OF-/OF+ (Pins E5/F5): LVDS Over/Under Flow Output. High when over under flow occurred.
LTM9003 FUNCTIONS
Configuration
VCC1 VCC2 VCC1 VCC1 VCC2 AMP_EN MIX_EN D10- D10+ D11- D11+ SENSE LVDS MODE OGND OVDD CLKOUT+ OGND CLKOUT- OVDD SHDN OGND OGND OVDD OGND ENC- ENC+
View Package (Looking Through Component)
BLOCK DIAGRAM
VCC1 VCC2 MODE LVDS SHDN OVDD INPUT PIPELINED SECTIONS CONTROL LOGIC SHIFT REGISTER/ ERROR CORRECTION OGND INTERNAL CLOCK SIGNALS REFH REFL OUTPUT DRIVERS CLKOUT
1.25V REFERENCE RANGE SELECT
REFERENCE BUFFER
DIFFERENTIAL INPUT JITTER CLOCK DRIVER DIFFERENTIAL REFERENCE AMPLIFIER
ENC- ENC+
9003 BD01
MIX_EN
AMP_EN
SENSE
Figure Simplified Block Diagram
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LTM9003 OPERATION
DESCRIPTION LTM9003 integrated system package (SiP) that includes high-speed 12-bit converter, wideband filter active mixer. LTM9003 designed sampling, digital pre-distortion (DPD) applications, also known transmit observation path receivers, with input frequencies 3.8GHz. Typical applications include multicarrier base stations telecom test instrumentation. Digital pre-distortion technique often used thirdgeneration (3G) wireless base stations improve linearity power amplifiers (PA). Improved linearity allows lower power used therefore save significant amount power base station. receiver captures output, digitizes feeds back where distortion analyzed. complementary distortion then introduced transmit thereby pre-distorting signal. significant factor linearity distortion caused order intermodulation (IM) products. bandwidth digitized equivalent signal bandwidth multiplied order product canceled. example, four carrier WCDMA consumes 20MHz signal bandwidth; therefore, capture fifth order product requires 100MHz. Nyquist theory requires that sample rate least twice that frequency. However, simply doubling captured bandwidth sample rate best choice. Selecting exact sample rate intermediate frequency (IF) depends other factors within system. simplify filtering, sample rate often multiple chip rate. chip rate WCDMA 3.84MHz; selecting sample rate times chip rate gives 245.76Msps. Placing 3/4ths sample rate (fS) gives 184.32MHz allows entire bandwidth fall within second Nyquist zone. Many other frequency plans acceptable. following sections describe further detail operation each functional element LTM9003. technology allows LTM9003 customized this described Semi-Custom Options section. outline remaining sections follows basic functional elements shown Figure
MIXER FILTER AMPLIFIER FILTER
9003
Figure Basic Functional Elements
mixer dominates noise figure calculation would expected. overall gain optimized dynamic range relative input level allowed mixer. equivalent cascaded noise figure 9.1dB (LTM9003-AA) 9.9dB (LTM9003-AB). bandpass filter second order filter following mixer lowpass filter following amplifier provides anti-alias noise limiting. SEMI-CUSTOM OPTIONS Module construction affords level flexibility application-specific standard products. Standard amplifier components integrated regardless their process technology matched with passive components particular application. LTM9003-AA, first example, configured with 12-bit sampling rates 250Msps. total system gain approximately 10.8dB. fixed bandpass filter 184MHz with 125MHz bandwidth. range matched 1.1GHz 1.8GHz with side However, other options possible through Linear Technology's semi-custom development program. Linear Technology place program deliver other speed, resolution, range, gain filter configurations nearly specified application. These semi-custom designs based existing ADCs amplifiers with appropriately modified matching network. final subsystem then tested exact parameters defined application. final result fully integrated, accurately tested optimized solution same package. more details semi-custom receiver subsystem program, contact Linear Technology. Down-Converting Mixer mixer stage consists high linearity double-balanced mixer, buffer amplifier, high speed limiting buffer amplifier bias/enable circuits.
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LTM9003 OPERATION
inputs both single ended. side high side injection used. mixer's input consists integrated transformer high linearity differential amplifier. primary terminals transformer connected input (Pin ground. secondary side transformer internally connected amplifier's differential inputs. mixer's input consists integrated transformer high speed limiting differential amplifiers. amplifiers designed precisely drive mixer highest linearity lowest noise figure. Wideband Filter Most filtering done between mixer amplifier. This network order Chebychev bandpass section, designed 0.1dB passband ripple. bandwidth 220MHz, centered 184MHz, Figure Additional lowpass filtering done just before ADC. This filter serves bandlimit band noise entering converter, well isolate output amplifier from sampling action converter.
AMPLITUDE (dBFS) FREQUENCY (MHz)
9003
Analog Digital Converter shown Figure analog-to-digital converter (ADC) CMOS pipelined multistep converter. converter five pipelined stages; sampled analog input will result digitized value five cycles later (see Timing Diagram section). encode input differential improved common mode noise immunity. phases operation, determined state differential ENC+/ENC- input pins. brevity, text will refer ENC+ greater than ENC- high ENC+ less than ENC- low. Each pipelined stage shown Figure contains ADC, reconstruction interstage residue amplifier. operation, quantizes input stage quantized value subtracted from input produce residue. residue amplified output residue amplifier. Successive stages operate phase that when stages outputting their residue, even stages acquiring that residue visa versa. When low, analog input sampled differentially directly onto input sample-and-hold capacitors, inside "Input S/H" shown Block Diagram. instant that transitions from high, sampled input held. While high, held input voltage buffered amplifier which drives first pipelined stage. first stage acquires output during this high phase ENC. When goes back low, first stage produces residue which acquired second stage. same time, input goes back acquiring analog input. When goes back high, second stage produces residue which acquired third stage. identical process repeated third fourth stages, resulting fourth stage residue that sent fifth stage final evaluation. Each stage following first additional range accommodate flash amplifier offset errors. Results from stages digitally synchronized such that results properly combined correction logic before being sent output buffer.
Figure Filter Response
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LTM9003 APPLICATIONS INFORMATION
Input Port mixer's input shown Figure internally matched from 1.1GHz 1.8GHz, requiring external components over this frequency range. input return loss, shown Figure typically 12dB band edges. input match lower band edge optimized with shunt 3.3pF capacitor which improves 0.8GHz return loss greater than 25dB. Likewise, 2GHz match improved greater than 25dB with series 3.9nH inductor shunt capacitor. Measured input return losses these three cases plotted Figure
LOW-PASS MATCH 450MHz, 900MHz 3.6GHz RFIN (mm)
9003
This series transmission line/shunt capacitor matching topology allows LTM9003 used multiple frequency standards without circuit board layout modifications. series transmission line also replaced with series chip inductor more compact layout. input impedance versus frequency (with external matching) listed Table referenced data used with microwave circuit simulator design custom matching networks simulate board-level interfacing input filter.
Table Input Impedance Frequency (LTM9003-AA)
FREQUENCY (MHz) INPUT IMPEDANCE 20.3 23.6 j6.7 27.1 j6.1 30.8 j5.3 34.9 j4.2 39.4 j2.9 44.6 j1.4 50.1 61.5 j1.2 j0.3 68.7 j1.4 j3.2 67.5 j4.5 64.3 j4.7 60.8 j4.1 56.7 j2.8 52.7 j1.2 48.6 j0.6 44.7 j2.3 40.8 j5.3 33.1 j6.3 29.4 j6.9 22.9 j6.7 0.57 0.53 0.48 0.43 0.38 0.33 0.28 0.22 0.17 0.14 0.14 0.17 0.22 0.27 0.32 0.36 0.43 0.46 0.48 0.51 0.52 0.53 0.53 0.53 ANGLE 137.9 132.7 120.4 112.6 102.8 89.8 70.4 42.2 -21.5 -64.3 -72.2 -79.5 -85.8 -92.1 -104.3 -110.5 -117.2 -124.3 -131.7 -139.6
LTM9003
MIXER
1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000
RFIN
HIGH-PASS MATCH 2.6GHz WIDEBAND
Figure Input Schematic
2GHz MATCH (3.9nH 1pF)
PORT RETURN LOSS (dB)
MATCHING ELEMENTS 800MHz MATCH (3.3pF) 1000 FREQUENCY (MHz) 10000
9003
Figure Input Return Loss with without Matching
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LTM9003 APPLICATIONS INFORMATION
Table Input Impedance Frequency (LTM9003-AB)
FREQUENCY (MHz) 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 INPUT IMPEDANCE 19.8 j7.3 22.7 25.7 j6.6 28.8 j5.9 32.3 j5.1 36.1 j3.9 40.5 j2.6 45.4 j1.1 50.8 j0.2 56.3 j0.9 61.4 j0.7 65.3 j0.5 67.4 j2.4 67.3 j4.1 65.7 j5.1 63.2 j5.2 60.4 j4.7 57.6 j3.7 j2.6 52.4 j1.3 49.9 47.4 j1.4 44.8 j2.7 41.9 j3.9 35.7 j5.9 0.59 0.55 0.51 0.47 0.42 0.38 0.32 0.26 0.15 0.12 0.14 0.19 0.25 0.31 0.37 0.42 0.46 0.49 0.51 0.53 0.54 0.55 0.55 0.55 0.54 ANGLE 138.4 133.9 129.2 123.9 117.9 110.6 101.3 87.6 65.6 27.5 -13.1 -37.9 -52.4 -61.9 -68.9 -74.4 -79.1 -86.7 -90.1 -93.7 -97.3 -101.6 -106.3 -111.9
VCC2
9003
LTM9003 EXTERNAL MATCHING 1GHz LOIN REGULATOR LIMITER VREF
MIXER
Figure Input Schematic
Custom matching networks designed using port impedance data listed Table This data referenced with external matching.
Table Input Impedance Frequency (LTM9003-AA)
FREQUENCY (MHz) 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 INPUT IMPEDANCE 10.3 j6.1 j2.2 18.7 j8.2 j6.2 64.5 j9.9 109.7 j42.2 206.6 j35.9 183.8 115.4 j59.4 86.7 j35.2 70.7 j18.5 59.3 j7.4 50.2 j0.2 42.6 j4.5 35.9 j7.2 30.2 j8.3 25.6 j8.1 22.4 j6.7 20.8 j4.6 21.5 j2.1 24.2 28.9 j1.3 35.3 j1.5 42.6 j0.9 50.3 57.7 j0.6 0.73 0.68 0.64 0.59 0.63 0.66 0.68 0.71 0.68 0.66 0.63 0.59 0.54 0.48 0.42 0.35 0.28 0.21 0.16 0.12 ANGLE -159.1 172.4 141.8 108.4 72.7 38.3 -17.1 -37.3 -53.7 -67.4 -79.2 -89.7 -99.6 -109.2 -118.9 -129.2 -140.3 -152.3 -165.5 -179.8 163.9 145.1 121.1 88.6 45.8
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Input Port mixer's input, shown Figure internally matched from 0.9GHz 3.5GHz. input matching near 600MHz requires series inductor (L4)/shunt capacitor (C4) network shown Figure Likewise, 2GHz match improved using 2.7H, 0.5pF Measured input return losses these three cases plotted Figure optimum drive -3dBm frequencies above 1.2GHz, although amplifiers designed accommodate several input power variation without significant mixer performance variation. Below 1.2GHz, 0dBm drive recommended optimum noise figure, although -3dBm will still deliver good conversion gain linearity.
LTM9003 APPLICATIONS INFORMATION
Table Input Impedance Frequency (LTM9003-AB)
FREQUENCY (MHz) 1000 1100 1200 1300 1400 1500 1600 1700 1800 1900 2000 2100 2200 2300 2400 2500 2600 2700 2800 2900 3000 INPUT IMPEDANCE 14.3 j7.5 12.6 j2.4 15.8 j1.9 22.7 j4.1 32.5 j3.8 44.2 j1.3 56.3 j1.2 j1.3 70.7 69.9 j3.1 j3.7 61.8 j3.3 58.1 j2.4 54.9 j1.5 52.7 j0.8 50.7 j0.2 49.4 j0.2 47.8 j0.5 46.7 j0.7 45.7 j0.8 45.5 j0.7 46.4 j0.4 48.7 j0.1 50.9 j0.1 52.9 j0.3 54.6 j0.5 0.68 0.61 0.53 0.44 0.35 0.25 0.18 0.15 0.18 0.21 0.25 0.27 0.28 0.29 0.28 0.28 0.27 0.25 0.23 0.17 0.13 0.09 0.09 0.11 ANGLE -150.6 -170.4 170.8 151.5 130.2 104.9 70.3 26.4 -12.8 -37.8 -54.1 -65.5 -73.4 -79.8 -84.2 -88.5 -91.4 -95.5 -98.9 -103.3 -106.8 -107.1 -97.9 -84.2 -72.5 -66.7
Mixer Enable Interface voltage necessary turn mixer 2.7V. disable mixer, enable voltage must less than 0.3V. MIX_EN allowed float, mixer will tend remain last operating state. Thus recommended that enable function used this manner. shutdown function required, then MIX_EN should connected directly VCC1. Amplifier Enable Interface AMP_EN self-biases VCC2 through resistor. must pulled below 0.8V order disable amplifier. Driving Clock Input noise performance depend encode signal quality much analog input. ENC+/ENC- inputs intended driven differentially, primarily noise immunity from common mode noise sources. Each input biased through 4.8k resistor 1.5V bias. bias resistors operating point transformer coupled drive circuits logic threshold single-ended drive circuits. noise present encode signal will result additional aperture jitter that will summed with inherent aperture jitter. applications where jitter critical (high input frequencies) take following into consideration: Differential drive should used. large amplitude possible; transformer coupled higher turns ratio increase amplitude. clocked with sinusoidal signal, filter encode signal reduce wideband noise.
RETURN LOSS (dB) MATCHING ELEMENTS 2GHz MATCH (2.7nH 0.5pF) 1000 FREQUENCY (MHz) 10000
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600MHz MATCH (6.8nH 5.6pF)
Balance capacitance series resistance both encode inputs that coupled noise will appear both inputs common mode noise. encode inputs have common mode range 1.2V 2.0V. Each input driven from ground single-ended drive.
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Figure Input Return Loss with without Matching
LTM9003 APPLICATIONS INFORMATION
LTM9003 INTERNAL CIRCUITS MA/COM 0.1F ETC1-1-13 ENC+ 1.5V BIAS 4.8k
CLOCK INPUT
lower limit sample rate determined droop sample-and-hold circuits. pipelined architecture this relies storing analog signals small valued capacitors. Junction leakage will discharge capacitors. specified minimum operating frequency LTM9003 1Msps. Clock Duty Cycle Stabilizer optional clock duty cycle stabilizer circuit used input clock duty cycle. This circuit uses rising edge ENC+ sample analog input. falling edge ENC+ ignored internal falling edge generated phase-locked loop. input clock duty cycle vary from clock duty cycle stabilizer will maintain constant internal duty cycle. clock turned long period time, duty cycle stabilizer circuit will require hundred clock cycles lock onto input clock. clock duty cycle stabilizer, MODE should connected 1/3VDD 2/3VDD using external resistors. Clock Sources Undersampling Undersampling especially demanding clock source higher input frequency, greater sensitivity clock jitter phase noise. clock source that degrades full-scale signal 70MHz will degrade 140MHz, 4.5dB 190MHz. cases where absolute clock frequency accuracy relatively unimportant only single required, canned oscillator from vendors such Saronix Vectron placed close simply connected directly ADC. there distance ADC, some source termination reduce ringing that occur even over fraction inch advisable. must allow clock overshoot supplies performance will suffer. filter clock signal with narrow band filter unless have sinusoidal clock source, rise fall time artifacts present typical digital clock signals will translated into phase noise.
8.2pF ENC- 0.1F 1.5V BIAS 4.8k
0.1F
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Figure Transformer Driven ENC+/ENC-
VTHRESHOLD 1.5V
ENC+ 1.5V ENC- 0.1F
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LTM9003
Figure Single-Ended Driver, Recommended Jitter
0.1F LVDS CLOCK
ENC+ LTM9003
0.1F
ENC-
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Figure Drive Using LVDS
Maximum Minimum Conversion Rates maximum conversion rate 250Msps. operate properly, encode signal should have (±5%) duty cycle. Each half cycle must have least 1.9ns internal circuitry have enough settling time proper operation. Achieving precise duty cycle easy with differential sinusoidal drive using transformer using symmetric differential logic such PECL LVDS.
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LTM9003 APPLICATIONS INFORMATION
lowest phase noise oscillators have single-ended sinusoidal outputs, these devices filter close beneficial. This filter should close both reduce roundtrip reflection times, well reduce susceptibility traces between filter ADC. circuit sensitive closein phase noise, power supply oscillators buffers must very stable, propagation delay variation with supply will translate into phase noise. Even though these clock sources regarded digital devices, operate them digital supply. your clock also used drive digital devices such FPGA, should locate oscillator, clock fan-out devices close ADC, give routing precedence. clock signals FPGA should have series termination driver prevent high frequency noise from FPGA disturbing substrate clock fan-out device. FPGA programmable divider, must re-time signal using original oscillator, re-timing flip-flop well oscillator should close ADC, powered with very quiet supply. cases where there multiple ADCs, where clock source originates some distance away, differential clock distribution advisable. This advisable both from perspective EMI, also avoid receiving noise from digital sources both radiated, well propagated waveguides that exist between layers multilayer PCBs. differential pairs must close together distanced from other signals. differential pair should guarded both sides with copper distanced least distance between traces, grounded with vias more than inch apart. Digital Outputs Table shows relationship between analog input voltage, digital data bits, overflow bit.
Table Output Codes Input Voltage
INPUT (SENSE VDD) Overvoltage Maximum (OFFSET BINARY) 1111 1111 1111 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 0000 0000 0000 (2'S COMPLEMENT) 0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
0.000000V
Minimum Undervoltage
Digital Output Buffers Figure shows equivalent circuit differential output pair LVDS output mode. 3.5mA current steered from OUT+ OUT- vice versa which creates ±350mV differential voltage across termination resistor LVDS receiver. feedback loop regulates common mode output voltage 1.25V. proper operation each LVDS output pair needs external
LTM9003 OVDD 2.5V 0.1F
1.25V
OUT+ OUT- LVDS RECEIVER
3.5mA
OGND
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Figure Digital Output LVDS Mode
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LTM9003 APPLICATIONS INFORMATION
termination resistor, even signal used (such OF+/OF- CLKOUT+/CLKOUT-). minimize noise board traces each LVDS output pair should routed close together. minimize clock skew LVDS board traces should have about same length. Data Format LTM9003 parallel digital output selected offset binary complement format. format selected with MODE pin. Connecting MODE 1/3VDD selects offset binary output format. Connecting MODE 2/3VDD selects complement output format. external resistor divider used 1/3VDD 2/3VDD logic values. Table shows logic states MODE pin.
Table MODE Function
MODE 1/3VDD 2/3VDD OUTPUT FORMAT Straight Binary Straight Binary Complement Complement CLOCK DUTY CYCLE STABILIZER
Output Enable outputs disabled with output enable pin, LVDS output mode high disables data outputs including CLKOUT. data access relinquish times slow allow outputs enabled disabled during full speed operation. output Hi-Z state intended during long periods inactivity. Hi-Z state truly open circuit; output pins that make LVDS output pair have resistance between them. Sleep Modes converter placed shutdown modes conserve power. Connecting SHDN results normal operation. Connecting SHDN results sleep mode, which powers down circuitry including reference typically dissipates 1mW. When exiting sleep mode, will take milliseconds output data become valid because reference capacitors have recharge stabilize. Connecting SHDN results mode typically dissipates 30mW. mode, on-chip reference circuit kept that recovery from mode faster than that from sleep mode, typically taking clock cycles. both sleep modes, digital outputs disabled enter Hi-Z state. Supply Sequencing VCC1 VCC2 pins provide supply mixer amplifier, respectively, provides supply ADC. mixer, amplifier separate integrated circuits within LTM9003. Separate linear regulators used without additional supply sequencing circuitry they have common input supplies.
Overflow overflow output indicates when converter overranged underranged. differential logic high OF+/OF- pins indicates overflow underflow. Output Clock LTM9003 delayed version ENC+ input available digital output, CLKOUT. CLKOUT used synchronize converter data digital system. This necessary when using sinusoidal encode. Data will updated just after CLKOUT+/CLKOUT- rises latched falling edge CLKOUT+/CLKOUT-. Output Driver Power OVDD should connected 2.5V supply OGND should connected GND.
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LTM9003 APPLICATIONS INFORMATION
Grounding Bypassing LTM9003 requires printed circuit board with clean unbroken ground plane; multilayer board with internal ground plane recommended. pinout LTM9003 been optimized flow-through layout that interaction between inputs digital outputs minimized. Ample ground pads facilitate layout that ensures that digital analog signal lines separated much possible. LTM9003 internally bypassed with (VDD), amplifier (VCC2) mixer (VCC1) supplies returning common ground (GND). digital output supply (OVDD) returned OGND. Additional bypass capacitance optional required power supply noise significant. Heat Transfer Most heat generated LTM9003 transferred through bottom-side ground pads. good electrical thermal performance, critical that ground pins connected ground plane sufficient area with many vias possible. Recommended Layout high integration LTM9003 makes board layout very simple easy. However, optimize electrical thermal performance, some layout considerations still necessary. large copper areas ground. This helps dissipate heat package through board also helps shield sensitive on-board analog signals. Common ground (GND) output ground (OGND) electrically isolated LTM9003, connected underneath part provide common return path. multiple ground vias. Using many vias possible helps improve thermal performance board creates necessary barriers separating analog digital traces board high frequencies. Separate analog digital traces much possible, using vias create high-frequency barriers. This will reduce digital feedback that reduce signal-to-noise ratio (SNR) dynamic range LTM9003. Figures through give good example recommended layout. quality paste print important factor producing high yield assemblies. recommended type printing no-clean solder paste. solder stencil design should follow guidelines outlined Application Note 100. LTM9003 employs gold-finished pads with Pb-based tin-based solder paste. inherently Pb-free complies with JEDEC (e4) standard. materials declaration available online http://www.linear. com/leadfree/mat_dec.jsp.
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LTM9003 APPLICATIONS INFORMATION
Figure Layer Component Side
Figure Layer
Figure Layer
Figure Backside
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Package 108-Lead (15mm 11.25mm 2.32mm)
(Reference 05-08-1757
DETAIL MOLD SUBSTRATE 10.16 0.27 0.37 1.95 2.05 1.27 DETAIL PADS NOTES DETAIL 1.905 3.175 4.445 5.715 6.985 0.630 ±0.025 108x (0.635) 11.25 2.22 2.42 13.97
0.22 CHAMFER
PACKAGE
CORNER
PACKAGE VIEW
PACKAGE BOTTOM VIEW
6.985
5.715
4.445
3.175
1.905
5.080
3.810
2.540 DETAIL
1.270
0.000
0.635 0.000 0.635
1.270
NOTES: DIMENSIONING TOLERANCING ASME Y14.5M-1994 DIMENSIONS MILLIMETERS LAND DESIGNATION JESD MO-222, SPP-010 DETAILS IDENTIFIER OPTIONAL, MUST LOCATED WITHIN ZONE INDICATED. IDENTIFIER EITHER MOLD MARKED FEATURE
COMPONENT "A1"
2.540
LTMXXXXXX Module
3.810
5.080
Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
TRAY BEVEL
SUGGESTED LAYOUT VIEW
PRIMARY DATUM SEATING PLANE TOTAL NUMBER PADS: SYMBOL TOLERANCE 0.15 0.10 0.05
PACKAGE TRAY LOADING ORIENTATION
0707
LTM9003
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LTM9003 RELATED PARTS
PART NUMBER LTC2240-10 LTC2240-12 LTC2241-10 LTC2241-12 LTC2242-10 LTC2242-12 LTC6410 LT5527 LT5557 LTM9001 LTM9002 DESCRIPTION 10-Bit, 170Msps, 2.5V ADC, LVDS Outputs 12-Bit, 170Msps, 2.5V ADC, LVDS Outputs 10-Bit, 210Msps, 2.5V ADC, LVDS Outputs 12-Bit, 210Msps, 2.5V ADC, LVDS Outputs 10-Bit, 250Msps, 2.5V ADC, LVDS Outputs 12-Bit, 250Msps, 2.5V ADC, LVDS Outputs Differential Amplifier with Configurable Input Impedance 400MHz 3.7GHz, High Signal Level Downconverting Mixer 800MHz 2.7GHz High Linearity Direct Conversion Quadrature Demodulator 16-Bit, IF/Receiver Subsystem COMMENTS 445mW, 60.6dB SNR, 78dB SFDR, 64-Pin 445mW, 65.5dB SNR, 80dB SFDR, 64-Pin 585mW, 60.6dB SNR, 78dB SFDR, 64-Pin 585mW, 65.5dB SNR, 78dB SFDR, 64-Pin 740mW, 60.5dB SNR, 78dB SFDR, 64-Pin 740mW, 65.4dB SNR, 78dB SFDR, 64-Pin 1.4GHz, -3dB Fixed Voltage Gain System), 36dBm OIP3 23.5dBm IIP3 1.9GHz, 12.5dB, Single-Ended Ports 24.7dBm IIP3 1.9GHz, 11.7dB, Single-Ended Ports, 3.3V Supply 16-Bit, 130Msps ADC, 20dB Gain Amplifier, Anti-Alias Filter, Internal Bypass Capacitance
Dual 14-Bit, IF/Baseband Receiver Subsystem Dual 14-Bit, 125Msps ADC, dual 26dB Gain Amplifiers, Anti-Alias Filters, Auxiliary Gain Adjustment, Internal Bypass Capacitance
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
0709 PRINTED
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2009

LTM®9003 12-bit digital pre-distortion receiver subsystem transmit pat

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