serial input, 12-, 16-bit, voltage output SoftSpanDACs that operate fr

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LTC2704 Quad 12-, 16-Bit Voltage Output SoftSpan DACs with Readback FEATURES
serial input, 12-, 16-bit, voltage output SoftSpanDACs that operate from logic ±15V analog supplies. SoftSpan offers output spans-two unipolar four bipolar-fully programmable through 3-wire serial interface. accurate 1LSB (2LSB LTC2704-16). accurate 1LSB versions. Readback commands allow verification on-chip register just instruction cycle. other commands produce "rolling readback" response from LTC2704, dramatically reducing needed number instruction cycles. Sleep command allows combination DACs powered down. There also reset flag offset adjustment each channel.
Lare registered trademarks Linear Technology Corporation. SoftSpan trademark Linear Technology Corporation. other trademarks property their respective owners.
Programmable Output Ranges: Unipolar: Bipolar: ±5V, ±10V, ±2.5V, -2.5V 7.5V Serial Readback On-Chip Registers 1LSB Over Industrial Temperature Range (LTC2704-14/LTC2704-12) Force/Sense Outputs Enable Remote Sensing Glitch Impulse: 2nV-sec Outputs Drive ±5mA Compatible 12-, 16-Bit Parts Power-On Clear Zero Volts 44-Lead SSOP Package
APPLICATIONS
Process Control Industrial Automation Direct Digital Waveform Generation Software Controlled Gain Adjustment Automated Test Equipment
TYPICAL APPLICATION
AGND VOSB RFBB OUTB AGNDB VOSA RFBA OUTA AGNDA OUTD AGNDD CS/LD LDAC RFLAG
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REFM1 REFG1 REF1 REF2 REFG2 REFM2 1,8,15,22,31,36 VOSC AGNDC VOSD RFBD RFBC OUTC
LTC2704-16 Integral Nonlinearity (INL)
V+/V- ±15V VREF ±10V RANGE
DACS SUPERIMPOSED
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
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LTC2704 ABSOLUTE MAXIMUM RATINGS
(Note
CONFIGURATION
VIEW REFG1 AGNDA VOSA OUTA RFBA LDAC REFM1 REF1 AGNDB VOSB OUTB RFBB RFLAG AGND RFBC OUTC VOSC AGNDC REF2 REFM2
Total Supply Voltage V+1, -0.3V V+1, V+2, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx GND, AGND, AGNDx, C1x, REFG1, REFG2 .18V GND, AGND, AGNDx, C1x, REFG1, REFG2 V+1, V+2, REF1, REF2, REFM1, REFM2, OUTx, RFBx, VOSx .18V OUTA, RFBA, VOSA, OUTB, RFBB, VOSB, REF1, REFM1 GND, AGND 0.3V 0.3V OUTC, RFBC, VOSC, OUTD, RFBD, VOSD, REF2, REFM2 GND, AGND. 0.3V 0.3V VDD, Digital Inputs/Outputs -0.3V Digital Inputs/Outputs .0.3V GND, AGNDx, REFG1, REFG2 AGND .±0.3V AGNDx .±0.3V .0.3V Maximum Junction Temperature. 150°C Operating Temperature Range LTC2704C 70°C LTC2704I 40°C 85°C Storage Temperature Range.- 65°C 150°C Lead Temperature (Soldering, sec) 300°C
CS/LD
RFBD OUTD VOSD AGNDD REFG2
PACKAGE 44-LEAD PLASTIC SSOP TJMAX 125°C, 80°C/W
ORDER INFORMATION
LEAD FREE FINISH LTC2704CGW-16#PBF LTC2704IGW-16#PBF LTC2704CGW-14#PBF LTC2704IGW-14#PBF LTC2704CGW-12#PBF LTC2704IGW-12#PBF TAPE REEL LTC2704CGW-16#TRPBF LTC2704IGW-16#TRPBF LTC2704CGW-14#TRPBF LTC2704IGW-14#TRPBF LTC2704CGW-12#TRPBF LTC2704IGW-12#TRPBF PART MARKING LTC2704CGW-16 LTC2704IGW-16 LTC2704CGW-14 LTC2704IGW-14 LTC2704CGW-12 LTC2704IGW-12 PACKAGE DESCRIPTION 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP 44-Lead Plastic SSOP TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C
Consult Marketing parts specified with wider operating temperature ranges. Consult Marketing information non-standard lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
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LTC2704 ELECTRICAL CHARACTERISTICS
SYMBOL Accuracy Resolution Monotonicity Integral Nonlinearity Differential Nonlinearity Gain Error Gain Temperature Coefficient Unipolar Zero-Scale Error VREF VREF VREF Gain/Temperature Span 25°C Span 10V, 25°C Span Span Range Range Bipolar Ranges ±10% (Note ±10% (Note Range, Code V+/V- ±15V ±10% (Note V+/V- ±10%, VREF (Note Range, Step, ±1LSB Range, Step, ±1LSB ±10V Range, Step, ±1LSB V+/V- ±15V, VREF ±7.25V, Range, ILOAD ±3mA (Note V+/V- ±5V, VREF ±2.25V, Range, ILOAD ±3mA (Note Load Current V+/V- ±10.8V ±16.5V, VREF ±5V, Range, VOUT ±10V (Note V+/V- ±4.5V ±16.5V, VREF ±2V, Range, VOUT (Note Load Regulation
-14.5 -4.5
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C, 15V, -15V, REF1 REF2 AGND AGNDx REFG1 REFG2
PARAMETER CONDITIONS LTC2704-12 ±0.5 ±100 ±140 ±150 ±0.25 ±0.003 ±0.006
LTC2704-14
LTC2704-16
UNITS Bits Bits ppm/°C
±200 ±300 ±400 ±600
±100 ±140 ±150
±200 ±300 ±400 ±600
±100 ±140 ±150
±200 ±300 ±400 ±600
V/°C V/°C
Temperature Coefficient PSRR Bipolar Zero Error Power Supply Rejection Ratio
±0.5 ±0.013 ±0.025
±2.5
±0.05 ±0.1
LSB/V LSB/V LSB/V LSB/V
±0.001 ±0.06 ±0.002 ±0.05 14.5 -14.5 ±0.005 -4.5
±0.005 ±0.25 ±0.01 ±0.13 14.5 -14.5 ±0.01 -4.5
±0.02 ±0.1 ±0.04 ±0.5 14.5 ±0.04
Analog Outputs (Note Settling Time
Output Swing
LSB/mA
V+/V- ±15V, VREF Range, Code ±5mA Load (Note V+/V- ±5V, VREF Range, Code ±3mA Load (Note
±0.01
±0.013
±0.05
LSB/mA
Output Impedance Short-Circuit Current
VREF Range, Code ±5mA Load V+/V- ±16.5V, VREF ±10V Range Code VOUT Shorted (Note Code Full Scale, VOUT Shorted V+/V- ±5.5V, VREF ±10V Range Code VOUT Shorted (Note Code Full Scale, VOUT Shorted
0.015
0.006
0.006
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LTC2704
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C, 15V, -15V, REF1 REF2 AGND AGNDx REFG1 REFG2
SYMBOL PARAMETER Slew Rate Capacitive Load Driving CONDITIONS V+/V- ±15V (Note V+/V- (Note Within Maximum Load Current
ELECTRICAL CHARACTERISTICS
LTC2704-12 1000
LTC2704-14 1000
LTC2704-16 1000
UNITS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C, 15V, -15V, REF1 REF2 AGND AGNDx REFG1 REFG2
SYMBOL Reference Inputs REF1, REF2 Input Voltage Resistances RREF1, RREF2 RFBx RVOSX Reference Input Resistance Output Feedback Resistance Offset Adjust Input Resistance Glitch Impulse Crosstalk Range, Midscale Transition Step VOUTA Range, Full Scale Range, Full Scale ±10V Range, Midscale Range, VREF ±5V, 10kHz Sine Wave Span Full Scale Span 10V, Full Scale 10kHz Span Midscale Span 10V, Midscale 0.1Hz 10Hz Span Midscale Span 10V, Midscale Digital Inputs V+/V- ±15V ±10%; VREF VOUT (Note V+/V- ±5V, ±10%; VREF VOUT (Note Sleep Mode-All DACs (Note
PARAMETER
CONDITIONS V+/V- ±15V, Span (Note
-14.5
14.5
UNITS nV-s nV-s nV-s nV-s mVP-P V/Hz V/Hz VRMS VRMS
1000 0.35
Performance (Note
Digital Feedthrough Multiplying Feedthrough Error Multiplying Bandwidth Output Noise Voltage Density
Output Noise Voltage
Power Supply Supply Current, Supply Current, V+/V-
17.5 17.0 -16.5
16.5 -4.5
Logic Supply Voltage
Positive Analog Supply Voltage Negative Analog Supply Voltage Digital Input High Voltage Digital Input Voltage Digital Output High Voltage Digital Output Voltage 2.7V 5.5V 2.7V 3.3V 2.7V 5.5V 4.5V 5.5V 200A 200A
Digital Inputs/Outputs
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LTC2704
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C, 15V, -15V, REF1 REF2 AGND AGNDx REFG1 REFG2
SYMBOL PARAMETER Digital Input Current Digital Input Capacitance (Note CONDITIONS
ELECTRICAL CHARACTERISTICS
0.001
UNITS
TIMING CHARACTERISTICS
range, otherwise specifications 25°C.
SYMBOL 4.5V 5.5V 2.7V 3.3V Valid Setup Valid Hold High Time Time CS/LD Pulse Width High CS/LD High CS/LD Positive Edge CS/LD High Positive Edge Propagation Delay Pulse Width LDAC Pulse Width RFLAG CS/LD High RFLAG High Frequency Valid Setup Valid Hold High Time Time CS/LD Pulse Width High CS/LD High CS/LD Positive Edge CS/LD High Positive Edge Propagation Delay Pulse Width LDAC Pulse Width RFLAG CS/LD High RFLAG High Frequency PARAMETER
denotes specifications which apply over full operating temperature
CONDITIONS
UNITS
CLOAD 10pF
CLOAD 10pF (Note CLOAD 10pF (Note Duty Cycle (Note
CLOAD 10pF
CLOAD 10pF CLOAD 10pF Duty Cycle (Note
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Refer Operation Section proper power supply sequencing. Note notation used denote both when same voltage applied both pins.
Note Guaranteed design, subject test. Note Measured unipolar mode. Note When using SRO, maximum frequency fMAX limited propagation delay follows: fMAX
where setup time receiving device.
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LTC2704 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2704-16 Integral Nonlinearity (INL)
V+/V- ±15V VREF ±10V RANGE
(LSB) (LSB)
Differential Nonlinearity (DNL)
V+/V- ±15V
VREF
V+/V- ±15V RANGE
VREF ±10V RANGE
(LSB)
-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
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-0.2 -0.4 -0.6 -0.8 -1.0 16384 32768 CODE 49152 65535
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-0.2 -0.4 -0.6 -0.8 -1.0 VREF
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Temperature
V+/V- ±15V VREF ±10V RANGE
Temperature
V+/V- ±15V VREF ±10V RANGE
-200 -400
Offset Temperature
V+/V- ±15V VREF RANGE
(LSB)
(LSB)
-0.2 -0.4 -O.6 -0.8 -1.0 TEMPERATURE (°C)
-0.2 -0.4 -O.6 -0.8 -1.0
OFFSET
TEMPERATURE (°C)
-600
TEMPERATURE (°C)
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Bipolar Zero Temperature
V+/V- ±15V VREF ±10V RANGE
Gain Error Temperature
V+/V- ±15V VREF ±10V RANGE
GAIN ERROR (LSB)
TEMPERATURE (°C)
TEMPERATURE (°C)
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LTC2704 TYPICAL PERFORMANCE CHARACTERISTICS
LTC2704-16 Settling
VOUT 5V/DIV VOUT 5V/DIV VOUT 1mV/DIV
Settling
VOUT 10V/DIV
Settling ±10V
VOUT 1mV/DIV
VOUT 1mV/DIV
CS/LD 5V/DIV 2.5s/DIV
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CS/LD 5V/DIV 2.5s/DIV
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CS/LD 5V/DIV 2.5s/DIV
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LTC2704-14 Integral Nonlinearity (INL)
V+/V- ±15V VREF ±10V RANGE
Differential Nonlinearity (DNL)
V+/V- ±15V VREF ±10V RANGE -0.2 -0.4 -0.6 -0.8 -1.0
-0.2 -0.4 -0.6 -0.8 -1.0 4096 8192 CODE 12288 16383
2704
4096
8192 CODE
12288
16383
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LTC2704-12 Integral Nonlinearity (INL)
Differential Nonlinearity (DNL)
-0.2 -0.4 -0.6 -0.8 -1.0 V+/V- ±15V VREF ±10V RANGE
V+/V- ±15V VREF ±10V RANGE
-0.2 -0.4 -0.6 -0.8 -1.0 1536 1024 2048 2560 3072 3584 4095 CODE
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1536 1024 2048 2560 3072 3584 4095 CODE
2704
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LTC2704 TYPICAL PERFORMANCE CHARACTERISTICS
Positive Slew Negative Slew
CS/LD 5V/DIV
Midscale Glitch
5V/DIV
5V/DIV
VOUT 2mV/DIV
V+/V- ±15V VREF ±10V RANGE STEP
2.5s/DIV
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V+/V- ±15V VREF ±10V RANGE STEP
2.5s/DIV
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2.5s/DIV
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0.1Hz 10Hz Noise
(mA)
Supply Current Logic Voltage
SCK, SDI, CS/LD, LDAC TIED TOGETHER
1V/DIV
V+/V- ±15V VREF RANGE CODE
1s/DIV
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LOGIC VOLTAGE
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FUNCTIONS
(Pins 36): Analog Negative Supply, Typically -15V. -4.5V -16.5V Range. REFG1 (Pin Reference Ground. High impedance input, does carry supply currents. clean analog ground. AGNDA (Pin Signal Ground. High impedance input, does carry supply currents. clean analog ground. VOSA (Pin Offset Adjust Nominal input range ±5V. VOS(DAC V(VOSA) ±2.5V modes]. Operation section. (Pin Feedback Capacitor Connection Output. This provides direct access negative input channel output amplifier. OUTA (Pin Voltage Output Pin. best load regulation, this open-loop amplifier output connected RFBA close load possible. RFBA (Pin Output Feedback Resistor Pin. LDAC (Pin Asynchronous Load Input. When LDAC logic low, DACs updated.
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LTC2704 FUNCTIONS
CS/LD (Pin 10): Synchronous Chip Select Load Pin. (Pin 11): Serial Data Input. Data clocked rising edge serial clock when CS/LD low. (Pin 12): Serial Readback Data Output. Data clocked falling edge SCK. Readback data begins clocking after last address clocked (Pin 13): Serial Clock. (Pin 14): Asynchronous Clear Pin. When this low, code span registers cleared zero. outputs cleared zero volts. RFBD (Pin 16): Voltage Output Feedback Resistor Pin. OUTD (Pin 17): Voltage Output Pin. best load regulation, this open-loop amplifier output connected RFBD close load possible. (Pin 18): Feedback Capacitor Connection Output. This provides direct access negative input channel output amplifier. VOSD (Pin 19): Offset Adjust Nominal input range ±5V. VOS(DAC V(VOSD) ±2.5V modes]. Operation section. AGNDD (Pin 20): Signal Ground. High impedance input, does carry supply currents. clean analog ground. REFG2 (Pin 21): Reference Ground. High impedance input, does carry supply currents. clean analog ground. REFM2 (Pin 23): Reference Inverting Output. gain from REF2 REFM2 swing within 0.5V analog supplies V+/V-. REF2 (Pin 24): Reference Input. (Pin 25): Analog Positive Supply DACs Typically 15V. 4.5V 16.5V Range. different from V+1.
VOSC (Pin 27): Offset Adjust Nominal input range ±5V. VOS(DAC V(VOSC) ±2.5V modes]. Operation section. (Pin 28): Feedback Capacitor Connection Output. This provides direct access negative input channel output amplifier. OUTC (Pin 29): Voltage Output Pin. best load regulation, this open-loop amplifier output connected RFBC close load possible. RFBC (Pin 30): Output Feedback Resistor Pin. AGND (Pin 32): Analog Ground Pin. clean analog ground. (Pin 33): Ground Pin. clean analog ground. (Pin 34): Logic Supply. 2.7V 5.5V Range. RFLAG (Pin 35): Reset Flag Pin. active output asserted when there power reset clear event. Returns high when update command executed. RFBB (Pin 37): Output Feedback Resistor Pin. OUTB (Pin 38): Voltage Output Pin. best load regulation, this open-loop amplifier output connected RFBB close load possible. (Pin 39): Feedback Capacitor Connection Output. This provides direct access negative input channel output amplifier. VOSB (Pin 40): Offset Adjust Nominal input range ±5V. VOS(DAC -0.01 V(VOSB) ±2.5V modes]. Operation section. AGNDB (Pin 41): Signal Ground. High impedance input, does carry supply currents. clean analog ground. (Pin 42): Analog Positive Supply DACs Typically 15V. 4.5V 16.5V Range. different from V+2. REF1 (Pin 43): Reference Input. REFM1 (Pin 44): Reference Inverting Output. gain from REF1 REFM1 swing within 0.5V analog supplies V+/V-.
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AGNDC (Pin 26): Signal Ground. High impedance input, does carry supply currents. clean analog ground.
LTC2704 BLOCK DIAGRAM
RFBB OUTB RFBC OUTC REF1 VOSB 1,8,15,22,31,36 AGND REF2 VOSC
AGNDB
VOSA RFBA OUTA
AGNDA
REFM1 REFG1
COMMAND DECODE CS/LD
INPUT SHIFT REGS
BUFFERS
LDAC
TIMING DIAGRAM
CS/LD LDAC Hi-Z
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READBACK SHIFT REGS RFLAG
AGNDC
VOSD RFBD OUTD
AGNDD
REFM2 REFG2
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LTC2704 OPERATION
SERIAL INTERFACE When CS/LD taken low, data loaded into shift register rising edge clock signal (SCK pin). minimum (24-bit wide) loading sequence required LTC2704 4-bit command word C0), followed 4-bit address word data (span code) bits, first. Figure shows input word syntax when writing code span. 32-bit input sequence needed, first eight bits must zeros, followed same sequence 24-bit wide input. Figure shows input readback sequences both 24-bit 32-bit operations. When CS/LD low, Serial Readback Output (SRO) active output. readback data begins after command (C3-C0) address (A3-A0) words have been shifted into SDI. 24-bit load sequence, readback bits shifted falling edges clocks 8-23, suitable shifting into microprocessor rising edges clocks 9-24. 32-bit load sequence, these clock cycle counts; Figure When CS/LD high, presents high impedance (three-state) output. beginning load sequence, when CS/LD taken low, outputs logic until readback data begins. When asynchronous load pin, LDAC, taken low, DACs updated with code span data (data buffers copied into buffers). CS/LD must high during this operation. LDAC functionally identical "Update B1B2" commands. codes command word (C3-C0) defined Table Table defines codes address word (A3-A0). READBACK Each pairs double-buffered digital registers, pair code other output span (four buffers DAC). Each double-buffered pair comprises registers called buffer (B1) buffer (B2).
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holding buffer. When data shifted into write operation, outputs affected. contents only changed copying contents into update operation changed together, commands 0110-1001 Table contents (DAC code span) directly control output voltage output range. Additionally each readback register associated with When readback command issued DAC, contents four buffers copied into readback register serially shifted onto pin. Figure shows loading readback sequences. 16-bit data field (D15-D0 LTC2704-16, Figure write update command, readback (SRO) shifts contents buffer which specified preceding command. This "rolling readback" mode operation used reduce number operations, since command verified during succeeding commands with additional overhead. Table shows location (readback pointer) data which will output from during next instruction. readback commands, data shifted during readback instruction itself falling edges immediately after last address shifted SDI). When programming span DAC, span bits last four bits shifted when checking span using SRO, span bits likewise last four bits shifted out. Table shows span codes. When span information read back SRO, sleep status addressed also output. sleep status bit, occurs sequentially just before four span bits. sequence shown Figures Table codes. Note that output only; sleep programmed using command code 1110 along with desired address. update command, including LDAC, wakes addressed DAC(s).
LTC2704 OPERATION
OUTPUT RANGES LTC2704 quad with software-programmable output ranges. SoftSpan provides unipolar output ranges 10V), four bipolar ranges (±2.5V, ±5V, ±10V 2.5V 7.5V). These ranges obtained when external precision reference analog supplies ±12V ±15V used. When reference voltage analog supplies used,
Table Command Codes
CODE COMMAND Write Span Write Code Update B1B2 Update B1B2 DACs Write Span Update B1B2 Write Code Update B1B2 Write Span Update B1B2 DACs Write Code Update B1B2 DACs Read Span Read Code Read Span Read Code Sleep (Note Operation READBACK POINTRE- CURRENT INPUT WORD Previous Command Previous Command Previous Command Previous Command Previous Command Previous Command Previous Command Previous Command Span Code Span Code Previous Command Previous Command Span Code READBACK POINTRE- NEXT INPUT WORD Span Code Span Code Span Code Span Code
SoftSpan ranges become: ±1V, ±2V, output ranges linearly scaled references other than (appropriate analog supplies should used within range ±15V). Each four DACs programmed output ranges. outputs swing ±10V ±10.8V supplies (±12V supplies with ±10% tolerance) while sourcing sinking load current.
Codes shown reserved should used. Note Normal operation resumed issuing update B1B2 command sleeping DAC.
Table Address Codes
DACs READBACK POINTER
Table Span Codes
SPAN Unipolar Unipolar Bipolar Bipolar -10V Bipolar -2.5V 2.5V Bipolar -2.5V 7.5V
Codes shown reserved should used.
Codes shown reserved should used.
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OPERATION
ADDRESS WORD ADDRESS WORD ADDRESS WORD 12-BIT CODE 14-BIT CODE ZEROS 16-BIT CODE
LTC2704-16 (WRITE CODE)
CONTROL WORD
LTC2704-14 (WRITE CODE)
ZEROS
CONTROL WORD
LTC2704-12 (WRITE CODE)
CONTROL WORD
ZEROS
SPAN
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LTC2704-12 LTC2704-14 LTC2704-16 (WRITE SPAN) ADDRESS WORD
CONTROL WORD
Figure Input Words
LTC2704
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LTC2704
OPERATION
24-BIT DATA STREAM CODE SPAN ADDRESS WORD SLEEP STATUS SPAN
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CS/LD
CONTROL WORD
Hi-Z
READBACK CODE
Hi-Z
READBACK SPAN
Figure 24-Bit Load Sequence
32-BIT DATA STREAM
CS/LD ADDRESS WORD CONTROL WORD CODE SPAN
ZEROS
Hi-Z
READBACK CODE Hi-Z
SLEEP STATUS
SPAN
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READBACK SPAN
Figure 32-Bit Load Sequence
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LTC2704 OPERATION
Examples Using 24-bit loading sequence, load with unipolar range 10V, output zero volts other DACs with bipolar range ±10V, outputs zero volts. Note outputs should change same time. CS/LD Clock 0010 1111 0000 0000 0000 0011 CS/LD B1-Range DACs bipolar ±10V. CS/LD Clock 0010 0000 0000 0000 0000 0001 CS/LD B1-Range unipolar 10V. CS/LD Clock 0011 1111 1000 0000 0000 0000 CS/LD B1-Code DACs midscale. CS/LD Clock 0011 0000 0000 0000 0000 0000 CS/LD B1-Code zero code. CS/LD Clock 0100 1111 XXXX XXXX XXXX XXXX CS/LD Update DACs into both Code Range. Alternatively steps could replaced with LDAC Using 32-bit load sequence, load with bipolar 2.5V output zero volts. readback check contents before updating output (i.e., before copying contents into B2). CS/LD (Note that after power-on, Code zero) Clock 0000 0000 0011 0100 1000 0000 0000 0000 CS/LD B1-Code midscale setting. CS/LD Clock 0000 0000 0010 0100 0000 0000 0000 0100 Read Data 1000 0000 0000 0000 Verifies that B1-Code midscale setting. CS/LD B1-Range Bipolar ±2.5V range. CS/LD Clock 0000 0000 1010 0100 xxxx xxxx xxxx xxxx Data 0000 0000 0000 0100 Verifies that B1-Range Bipolar ±2.5V Range. CS/LD CS/LD Clock 0000 0000 0100 0100 xxxx xxxx xxxx xxxx CS/LD Update into both Code Range Alternatively steps could replaced with LDAC System Offset Adjustment Many systems require compensation overall system offset, which order magnitude more greater than excellent offset LTC2704. LTC2704 individual offset adjust pins each four DACs. VOSA, VOSB, VOSC VOSD referred their corresponding signal grounds, AGNDA, AGNDB, AGNDC AGNDD. noise immunity ease adjustment, control voltage attenuated output: -0.01 V(VOSx) ±2.5V spans] -0.02 V(VOSx) 10V, ±5V, -2.5V 7.5V spans] -0.04 V(VOSx) [±10V span] nominal input range these pins ±5V; other reference voltages ±15V used needed. VOSx pins have input impedance preserve settling performance LTC2704, these pins
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LTC2704 OPERATION
should driven with Thevenin-equivalent impedance less. used, they should shorted their respective signal grounds, AGNDx. POWER-ON RESET CLEAR When power first applied LTC2704, DACs power-up unipolar mode 0000). internal registers reset outputs zero volts. When taken low, system clear results. command address shift registers, code configuration buffers, reset outputs reset zero volts. buffers left intact, that subsequent "Update B1B2" command (including LDAC) restores addressed DACs their respective previous states. asserted during operation, i.e., when CS/LD low, operation aborted. Integrity relevant input (B1) buffers guaranteed under these conditions, therefore contents should checked using readback replaced. RFLAG used flag notify system loss data integrity. RFLAG output asserted power-up, system clear, logic supply dips below approximately stays asserted until valid update command executed. SLEEP MODE When sleep command 1110) issued, addressed DACs into power-down mode. DACs share reference inverting amplifier DACs either (similarly DACs powered down, shared reference inverting amplifier remains powered When both powered down together, their shared reference inverting amplifier also powered down (similarly DACs determine sleep status particular DAC, direct read span command performed addressing reading status readback SRO. fifth sleep status (see Figures 2b). Table shows sleep status bit's functionality.
Table Readback Sleep Status
STATUS Awake Sleep Mode
Supply Sequencing Proper initialization operation LTC2704 guaranteed supplies applied last, after needed, sequencing circuit such shown Figure used this purpose.
ADJ1 ZN7002 LTC2704
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MTD2955
LTC2909-5 ADJ2 215k 10.7k
Figure Supply Sequencing Circuit Ensures Supply Comes Only When 4.5V -10V.
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LTC2704 APPLICATIONS INFORMATION
Overview LTC2704 highly integrated device, greatly simplifying design layout compared design using multiple current output DACs separate amplifiers. similar design using four separate current output DACs would require precision amps, compensation capacitors, bypass capacitors each amplifier, several times much area more complicated serial interface. Still, important avoid some common mistakes order achieve full performance. DC752A evaluation board LTC2704. designed meet data sheet specifications, allow LTC2704 integrated into other prototype circuitry. force/sense lines available allow addition current booster stages other output circuits. DC752A design presented tutorial properly applying LTC2704. This board shows properly return digital analog ground currents, compensate small differences ground potential between banks DACs. There other ways ground LTC2704, requirement that analog digital grounds connected LTC2704 very impedance path. advisable split ground planes connect them with jumper inductor. When doubt, single solid ground plane rather than separate planes. LTC2704 does allow ground potential DACs vary ±300mV with respect analog ground, allowing compensation ground return resistance. Power Supply Grounding Noise LTC2704 pins supplies output amplifiers, ground sense amplifiers reference inversion amplifiers. These amplifiers have good power supply rejection, supplies must free from wideband noise. best scheme prefilter noise regulators such LT®1761 (positive) LT1964 (negative). Refer Linear Technology Application Note 101, Minimizing Switching Regulator Residue Linear Regulator Outputs. LTC2704 supply digital logic analog switches very sensitive noise. must treated analog supply. evaluation board uses LT1790 precision reference supply minimize noise. return digital currents AGND bias point internal analog circuitry. Both these pins must tied same point quiet ground plane. Each separate ground sense that used compensate small differences ground potential within system. Since DACs associated with REF1 DACs associated with REF2, grounds must grouped together follows: AGNDA, AGNDB REFG1 tied together ("GND1" DC752A) AGNDC, AGNDD REFG2 tied together ("GND2" DC752A) This scheme allows compensation ground return drops, long resistance shared both DACs group. This implies that ground return DACs must close possible, GND1 must connected this point through current, resistance trace. (Similar DACs Figure shows layer evaluation board. GND1 trace connects REFG1, AGNDA, AGNDB ground LT1236 precision reference (U4.) This point ground reference DACs GND2 trace connects REFG2, AGNDC, AGNDD ground other LT1236 precision reference (U5). This point ground reference DACs Voltage Reference high quality, noise reference such LT1236 LT1027 must used achieve full performance. ground terminal this reference must connected directly common ground point. GND1 GND2 separate, then references must used.
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LTC2704 APPLICATIONS INFORMATION
Voltage Output/Feedback Compensation LTC2704 provides separate voltage output feedback pins each DAC. This allows compensation resistance between output load, current boosting stage such LT1970 inserted without affecting accuracy. When OUTx connected directly RFBx
EXPOSED GROUND PLANE AROUND EDGE ALLOWS GROUNDING PROTOTYPE CIRCUITS
additional capacitance present, internal frequency compensation sufficient stability optimized fast settling time. bandwidth booster stage used, then compensation capacitor from OUTx required. Similarly, extra compensation required drive heavy capacitive load.
POWER LOAD RETURN CURRENTS FLOW THIS REGION VOUTA VOUTB LOAD RETURN CURRENTS FLOW THIS REGION WHEN "TIE" VOUTC VOUTD LOAD RETURN CURRENTS FLOW THIS REGION WHEN "TIE"
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GND1 TRACE, SEPARATED FROM AGND UNDER LTC2704
GND2 TRACE, SEPARATED FROM AGND UNDER LTC2704
DIGITAL RETURN CURRENTS FLOW THIS REGION
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Figure DC752 Layer
Figure DC752A Load Return, Power Return Digital Return
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CUTOUT PREVENTS DIGITAL RETURN CURRENTS FROM COUPLING INTO ANALOG GROUND PLANE. NOTE THAT THERE PLANE THIS REGION LAYER
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Figure DC752 Analog Ground Layer. Currents Returned this Plane, Used Reference Point Precise Voltage Measurements
SMALL GROUND POUR ALLOWS IMPEDANCE BYPASSING
Figure DC752A Routing, Bypass
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LTC2704 PACKAGE Package 44-Lead Plastic SSOP (Wide .300 Inch)
(Reference 05-08-1642)
1.40 ±0.127
17.73 17.93* (.698 .706)
10.804 7.75 8.258
10.11 10.55 (.398 .415)
0.520 ±0.0635 0.800
RECOMMENDED SOLDER LAYOUT
7.417 7.595** (.292 .299)
0.254 0.406 (.010 .016)
2.44 2.64 (.096 .104) 2.286 2.388 (.090 .094)
0.355
0.231 0.3175 (.0091 .0125)
0.40 1.27 (.015 .050)
NOTE: CONTROLLING DIMENSION: MILLIMETERS MILLIMETERS DIMENSIONS (INCHES)
0.800 (.0315)
0.28 0.51 (.011 .02)
(.004 .0118)
SSOP 0204
*DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.152mm (0.006") SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.254mm (0.010") SIDE
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC2704 TYPICAL APPLICATION
Evaluation Board Schematic. Force/Sense Lines Allow Remote Sensing Optimal Grounding
LDAC CS/LD INTERFACE LDAC CS/LD RFLAG VOSB REMOTE VOSx REFMx REF1 5VREF1 GND1 REFM1 REFG1 REF1 REFM1 LTC2704 OFFSET ADJUSTMENT VOSA, VOSB, VOSC, VOSC REMOTE REF2 5VREF2 BAT54S REGULATOR 0.1F LT1790ACS6-5 VOUT 4.7F 0.1F AGND VOSD RFBD OUTD AGNDD GND2 OUTD -15V BAV99LT1 REMOTE GND2 REFM2 REFG2 REF2 REFM2 VOSC RFBC OUTC AGNDC GND2 VOSD OUTSC OUTC OUTC BAV99LT1 VOSC RFBB OUTB AGNDB GND1 VOSA RFBA OUTA AGNDA GND1 VOSB VOSA OUTA BAV99LT1 REMOTE OUTSA OUTA OUTB BAV99LT1
RFLAG REFx
REMOTE
OUTSB OUTB
REMOTE
OUTSD OUTD
1,8,15,22,31,36
4.7F 4.7F -15V 0.1F
LT1236ACS8-5 VOUT TRIM
5VREF1
LT1236ACS8-5 VOUT TRIM
5VREF2 4.7F GND1 BAT54S
GND1
REMOTE
GND2 BAT54S
REMOTE
4.7F
0.1F
-15V
GND2
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GND1
GND2
RELATED PARTS
PART NUMBER 1019 LT1236 LTC1588/LTC1589 LTC1592 LTC1595 LTC1596 LTC1597 LTC1650 LTC1857/LTC1858 LTC1859 LT1970
DESCRIPTION Precision Reference Precision Reference
COMMENTS Ultralow Drift, 3ppm/°C, 0.05% Accuracy Ultralow Drift, 10ppm/°C, 0.05% Accuracy
12-/14-/16-Bit, Serial, SoftSpan IOUT DACs Software-Selectable Spans, ±1LSB INL/DNL 16-Bit Serial Multiplying IOUT SO-8 1LSB INL/DNL, Glitch, DAC8043 16-Bit Upgrade 16-Bit Serial Multiplying IOUT 16-Bit Parallel, Multiplying 16-Bit Serial VOUT 12-/14-/16-Bit, Serial 100ksps SoftSpan 500mA Power ±1LSB INL/DNL, Glitch, AD7543/DAC8143 16-Bit Upgrade ±1LSB INL/DNL, Glitch, Quadrant Resistors Power, Gritch, 4-Quadrant Multiplication Software-Selectable Spans, 40mW, Fault Protected ±25V Adjustable Sink/Source Current Limits
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2006

serial input, 12-, 16-bit, voltage output SoftSpanDACs that operate fr

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