LT®1720/LT1721 UltraFastdual/quad comparators optimized single supply

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LT®1720/LT1721 UltraFastdual/quad comparators optimized single supply

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LT1720/LT1721 Dual/Quad, 4.5ns, Single Supply 3V/5V Comparators with Rail-to-Rail Outputs DESCRIPTION
LT®1720/LT1721 UltraFastdual/quad comparators optimized single supply operation, with supply voltage range 2.7V input voltage range extends from 100mV below ground 1.2V below supply voltage. Internal hysteresis makes LT1720/LT1721 easy even with slow moving input signals. rail-to-rail outputs directly interface CMOS. Alternatively, symmetric output drive harnessed analog applications easy translation other single supply logic levels. LT1720 available three 8-pin packages; three pins comparator plus power ground. addition MSOP packages, profile (0.8mm) dual fine pitch leadless package (DFN) available space limited applications. LT1721 available 16-pin SSOP packages. pinouts LT1720/LT1721 minimize parasitic effects placing most sensitive inputs (inverting) away from outputs, shielded power rails. LT1720/LT1721 ideal systems where small size power paramount.
Lare registered trademarks Linear Technology Corporation. UltaFast trademark Linear Technology Corporation. other trademarks property their respective owners.
UltraFast: 4.5ns 20mV Overdrive Overdrive Power: Comparator Optimized Operation Pinout Optimized High Speed Ease Input Voltage Range Extends 100mV Below Negative Rail TTL/CMOS Compatible Rail-to-Rail Outputs Internal Hysteresis with Specified Limits Dynamic Current Drain; 15A/(V-MHz), Dominated Load Most Circuits Tiny 0.75mm Package (LT1720)
APPLICATIONS
High Speed Differential Line Receiver Crystal Oscillator Circuits Window Comparators Threshold Detectors/Discriminators Pulse Stretchers Zero-Crossing Detectors High Speed Sampling Circuits
TYPICAL APPLICATION
2.7V Crystal Oscillator with TTL/CMOS Output
2.7V DELAY (ns) 1MHz 10MHz CRYSTAL (AT-CUT)
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Propagation Delay Overdrive
25°C VSTEP 100mV CLOAD 10pF
RISING EDGE (tPDLH)
GROUND CASE OUTPUT
LT1720
FALLING EDGE (tPDHL)
OVERDRIVE (mV)
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0.1F
1.8k
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LT1720/LT1721 ABSOLUTE MAXIMUM RATINGS
(Note
Supply Voltage, Input Current. ±10mA Output Current (Continuous) ±20mA Junction Temperature 150°C Package) 125°C Lead Temperature (Soldering, sec) 300°C
Storage Temperature Range. -65°C 150°C Package) -65°C 125°C Operating Temperature Range Grade 70°C Grade -40°C 85°C
CONFIGURATION
VIEW VIEW
PACKAGE 8-LEAD (3mm 3mm) PLASTIC TJMAX 125°C, 160°C/W UNDERSIDE METAL INTERNALLY CONNECTED
PACKAGE 8-LEAD PLASTIC MSOP TJMAX 150°C, 230°C/W
VIEW VIEW
PACKAGE 8-LEAD PLASTIC TJMAX 150°C, 200°C/W
PACKAGE 16-LEAD NARROW PLASTIC SSOP
PACKAGE 16-LEAD PLASTIC
TJMAX 150°C, 135°C/W (GN) TJMAX 150°C, 115°C/W
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LT1720/LT1721 ORDER INFORMATION
LEAD FREE FINISH LT1720CDD#PBF LT1720IDD#PBF LT1720CMS8#PBF LT1720IMS8#PBF LT1720CS8#PBF LT1720IS8#PBF LT1721CGN#PBF LT1721IGN#PBF LT1721CS#PBF LT1721IS#PBF TAPE REEL LT1720CDD#TRPBF LT1720IDD#TRPBF LT1720CMS8#TRPBF LT1720IMS8#TRPBF LT1720CS8#TRPBF LT1720IS8#TRPBF LT1721CGN#TRPBF LT1721IGN#TRPBF LT1721CS#TRPBF LT1721IS#TRPBF PART MARKING* LAAV LAAV LTDS LTACW 1720 1720I 1721 1721I 1721 1721I PACKAGE DESCRIPTION 8-Lead (3mm 3mm) Plastic 8-Lead (3mm 3mm) Plastic 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic 8-Lead Plastic 16-Lead Narrow Plastic SSOP 16-Lead Narrow Plastic SSOP 16-Lead Plastic 16-Lead Plastic TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C 70°C -40°C 85°C
Consult Marketing parts specified with wider operating temperature ranges. *The temperature grade identified label shipping container. Consult Marketing information non-standard lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
denotes specifications that apply over full operating temperature range, otherwise specifications 25°C. COUT 10pF VOVERDRIVE 20mV, unless otherwise specified.
SYMBOL VCMR VTRIP+ VTRIP- VHYST VOS/T CMRR PSRR tPD20 tPD5 PARAMETER Supply Voltage Supply Current (Per Comparator) Common Mode Voltage Range Input Trip Points Input Trip Points Input Offset Voltage Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage Output Voltage Propagation Delay Propagation Delay (Note (Note (Note ISOURCE 4mA, VTRIP+ 10mV ISINK 10mA, VTRIP- 10mV VOVERDRIVE 20mV (Note VOVERDRIVE (Notes
ELECTRICAL CHARACTERISTICS
CONDITIONS
UNITS V/°C
(Note (Note (Note (Note (Note
-0.1 -2.0 -3.0 -5.5 -6.5
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LT1720/LT1721 ELECTRICAL CHARACTERISTICS
SYMBOL tSKEW tJITTER fMAX PARAMETER Differential Propagation Delay Propagation Delay Skew Output Rise Time Output Fall Time Output Timing Jitter Maximum Toggle Frequency
denotes specifications that apply over full operating temperature range, otherwise specifications 25°C. COUT 10pF VOVERDRIVE 20mV, unless otherwise specified.
CONDITIONS (Note Between Channels (Note Between tPDLH/tPDHL 1.2VP-P (6dBm), 20MHz VOVERDRIVE 50mV, VOVERDRIVE 50mV, tPDLH tPDHL 70.0 62.5 UNITS psRMS psRMS
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note input within these common mode limits, other input outside common mode limits output will valid. Note LT1720/LT1721 comparators include internal hysteresis. trip points input voltage needed change output state each direction. offset voltage defined average VTRIP+ VTRIP-, while hysteresis voltage difference these two. Note common mode rejection ratio measured with defined change offset voltage measured from -0.1V 3.8V, divided 3.9V. Note power supply rejection ratio measured with defined change offset voltage measured from 2.7V divided 3.3V.
Note Because internal hysteresis, there small-signal region which measure gain. Proper operation internal circuity ensured measuring with only 10mV overdrive. Note Propagation delay measurements made with 100mV steps. Overdrive measured relative VTRIP±. Note cannot measured automatic handling equipment with values overdrive. LT1720/LT1721 100% tested with 100mV step 20mV overdrive. Correlation tests have shown that limits guaranteed with this test, additional tests performed guarantee that internal bias conditions correct. Note Differential propagation delay defined larger two: tPDLH tPDLH(MAX) tPDLH(MIN) tPDHL tPDHL(MAX) tPDHL(MIN) where (MAX) (MIN) denote maximum minimum values given measurement across different comparator channels. Note Propagation Delay Skew defined tSKEW |tPDLH tPDHL|
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Trip Voltages Supply Voltage
TRIP POINT VOLTAGE (mV) TRIP POINT VOLTAGE (mV) VTRIP+ COMMON MODE INPUT VOLTAGE VTRIP
Input Offset Trip Voltages Temperature
-0.2
Input Common Mode Limits Temperature
VTRIP- 25°C SUPPLY VOLTAGE
VTRIP-
TEMPERATURE (°C)
-0.4
TEMPERATURE (°C)
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LT1720/LT1721 TYPICAL PERFORMANCE CHARACTERISTICS
QUIESCENT SUPPLY CURRENT COMPARATOR (mA)
Input Current Differential Input Voltage
INPUT CURRENT DIFFERENTIAL INPUT VOLTAGE 25°C
Quiescent Supply Current Temperature
TEMPERATURE (°C) SUPPLY CURRENT COMPARATOR (mA)
Quiescent Supply Current Supply Voltage
125°C
25°C -55°C
SUPPLY VOLTAGE
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Propagation Delay Load Capacitance
DELAY (ns) OUTPUT LOAD CAPACITANCE (pF) FALLING EDGE (tPDHL) 25°C VSTEP 100mV OVERDRIVE 20mV RISING EDGE (tPDLH) PROPAGATION DELAY (ns)
Propagation Delay Temperature
tPDLH VSTEP 100mV CLOAD 10pF DELAY (ns)
Propagation Delay Supply Voltage
25°C VSTEP 100mV OVERDRIVE 20mV CLOAD 10pF
OVERDRIVE
RISING EDGE (tPDLH)
OVERDRIVE 20mV TEMPERATURE (°C)
FALLING EDGE (tPDHL)
SUPPLY VOLTAGE
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Output Voltage Load Current
OUTPUT VOLTAGE RELATIVE -15mV OUTPUT VOLTAGE 125°C 2.7V 25°C -55°C 125°C
Output High Voltage Load Current
125°C 15mV -55°C -0.4 25°C SUPPLY CURRENT COMPARATOR (mA)
Supply Current Frequency
25°C
-0.2
CLOAD 20pF FREQUENCY (MHz)
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-0.6
LOAD
-0.8 25°C 2.7V -1.0 OUTPUT SOURCE CURRENT (mA)
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OUTPUT SINK CURRENT (mA)
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LT1720/LT1721 FUNCTIONS
LT1720 (Pin Noninverting Input Comparator (Pin Inverting Input Comparator (Pin Inverting Input Comparator (Pin Noninverting Input Comparator (Pin Ground. (Pin Output Comparator (Pin Output Comparator (Pin Positive Supply Voltage. LT1721 (Pin Inverting Input Comparator (Pin Noninverting Input Comparator (Pins Ground. (Pin Output Comparator (Pin Output Comparator (Pin Noninverting Input Comparator (Pin Inverting Input Comparator (Pin Inverting Input Comparator (Pin 10): Noninverting Input Comparator (Pins 14): Positive Supply Voltage. (Pin 12): Output Comparator (Pin 13): Output Comparator (Pin 15): Noninverting Input Comparator (Pin 16): Inverting Input Comparator
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LT1720/LT1721 TEST CIRCUITS
±VTRIP Test Circuit
15VP-P BANDWIDTH-LIMITED TRIANGLE WAVE ~1kHz 0.1F 10nF LT1112 1000 VHYST LTC203
1000 VTRIP+
200k
LT1720 LT1721
1000 LTC203
LT1638 100k 100k 2.4k
1000 VTRIP-
10nF
100k 100k
LT1638 0.15F
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LT1112
NOTES: LT1638, LT1112, LTC203s POWERED FROM 15V. 200kW PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN POWERED
Response Time Test Circuit
-100mV LT1720 LT1721 +VCC
0.01F SCOPE PROBE (CIN 10pF) 0.01F
0.1F PULSE
2N3866
1N5711
-VCM -1000 (OVERDRIVE VTRIP+) NOTE: RISING EDGE TEST SHOWN. FALLING EDGE, REVERSE LT1720 INPUTS
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LT1720/LT1721 APPLICATIONS INFORMATION
Input Voltage Considerations LT1720/LT1721 specified common mode range -100mV 3.8V when used with single supply. general common mode range 100mV below ground 1.2V below VCC. criterion this common mode limit that output still responds correctly small differential input signal. Also, input within common mode limit, other input signal outside common mode limits, absolute maximum limits diode drop past either rail 10mA input current) output will retain correct polarity. When either input signal falls below negative common mode limit, internal diode formed with substrate turn resulting significant current flow through die. external Schottky clamp diode between input negative rail speed recovery from negative overdrive preventing substrate diode from turning When both input signals below negative common mode limit, phase reversal protection circuitry prevents false output inversion least -400mV common mode. However, offset hysteresis this mode will increase dramatically, much 15mV each. input bias currents will also increase. When both input signals above positive common mode limit, input stage will become debiased output polarity will random. However, internal hysteresis will hold output valid logic level, because biasing each comparator completely independent, there will impact other comparator. When least inputs returns within common mode limits, recovery from this state will take long propagation delay does increase significantly when driven with large differential voltages. However, with levels overdrive, apparent increase seen with large source resistances delay caused typical input capacitance. Input Protection input stage protected against damage from large differential signals, beyond differential voltage equal supply voltage, limited only absolute maximum currents noted. External input protection circuitry only needed currents would otherwise exceed these absolute maximums. internal catch diodes conduct current these rated maximums without latchup, even when supply voltage absolute maximum rating. LT1720/LT1721 input stage general purpose internal protection human body model. line receiver, additional external protection required. with most integrated circuits, level immunity much greater when residing printed circuit board where power supply decoupling capacitance will limit voltage rise caused pulse. Unused Inputs inputs unused compartor should tied that defines output logic state. easiest this GND. Input Bias Current Input bias current measured with both inputs held with differential input stage, LT1720/LT1721 bias current flows device. With differential input voltage even just 100mV there will zero bias current into higher inputs, while current flowing lower input will twice measured bias current. With more than diode drops differential input voltage, LT1720/LT1721's input protection circuitry activates, current lower input will increase additional there will small bias current into higher input pins, less. Typical Performance curve "Input Current Differential Input Voltage."
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LT1720/LT1721 APPLICATIONS INFORMATION
High Speed Design Considerations Application high speed comparators often plagued oscillations. LT1720/LT1721 have internal hysteresis, which will prevent oscillations long parasitic output input feedback kept below 4mV. However, with 2V/ns slew rate LT1720/LT1721 outputs, step created input source with only 0.02pF output input coupling. pinouts LT1720/LT1721 have been arranged minimize problems placing most sensitive inputs (inverting) away from outputs, shielded power rails. input output traces circuit board should also separated, requisite level isolation readily achieved topside ground plane runs between outputs inputs. multilayer boards where ground plane internal, topside ground supply trace should between inputs outputs, illustrated Figure Although both pins electrically shorted internal LT1721, they must shorted together externally well order both function shields. same true pins. supply bypass should include adjacent 10nF ceramic capacitor 2.2F tantalum capacitor farther than away; more capacitance driving more than loads. prevent oscillations, helpful balance impedance inverting noninverting inputs; source impedances should kept low, preferably less. outputs LT1720/LT1721 capable very high slew rates. prevent overshoot, ringing other problems with transmission line effects, keep output traces shorter than 10cm, sure terminate lines maintain signal integrity. LT1720/LT1721 drive terminations more, lower characteristic impedance traces driven with series termination termination topologies. Hysteresis LT1720/LT1721 include internal hysteresis, which makes them easier than many other comparable speed comparators.
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Figure Typical Topside Metal Multilayer Layouts
Figure shows typical topside layout LT1720 such multilayer board. Shown topside metal etch including traces, escape vias, land pads SO-8 LT1720 adjacent 10nF bypass capacitor 1206 case. ground trace from runs under device bypass capacitor, shielding inputs from outputs. Note common LT1720 bypass capacitor, which minimizes interference from high frequency energy running around ground plane power distribution traces. Figure shows typical topside layout LT1721 multilayer board. this case, power ground traces have been extended bottom device solely high frequency shields between input output traces.
input-output transfer characteristic illustrated Figure showing definitions VHYST based upon measurable trip points. hysteresis band makes LT1720/LT1721 well behaved, even with slowly moving inputs.
VOUT VHYST VTRIP+ VTRIP-)
VHYST/2
VTRIP
TRIP
VIN+ VIN-
VTRIP+
TRIP
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Figure Hysteresis Characteristics
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LT1720/LT1721 APPLICATIONS INFORMATION
exact amount hysteresis will vary from part part indicated specifications table. hysteresis level will also vary slightly with changes supply voltage common mode voltage. advantage LT1720/ LT1721 significant reduction these effects, which important whenever LT1720/LT1721 used detect threshold crossing direction only. such case, relevant trip point will that matters, stable offset voltage with unpredictable level hysteresis, seen competing comparators, little value. LT1720/LT1721 many times better than prior comparators these regards. fact, CMRR PSRR tests performed checking changes either trip point limits indicated specifications table. Because offset voltage average trip points, CMRR PSRR offset voltage therefore guaranteed least good those limits. This more stringent test also puts limit common mode power supply dependence hysteresis voltage. Additional hysteresis added externally. rail-to-rail outputs LT1720/LT1721 make this more predictable than with output comparators LT1720/LT1721's small variability (output high voltage). additional hysteresis, positive feedback adding additional external resistor shown Figure Resistor adds portion output threshold resistor string. LT1720/LT1721 pulls outputs supply rail ground within 200mV rails with light loads, within 400mV with heavy loads. load most circuits, good model voltage right side 300mV 300mV, total voltage swing (VCC 300mV) 300mV 600mV. With this mind, calculation resistor values needed two-step process. First, calculate value based additional hysteresis desired, output voltage swing, impedance primary bias string: R2)(VCC 0.6V)/(additional hysteresis) Additional hysteresis desired overall hysteresis less internal 3.5mV hysteresis. second step recalculate same average threshold before. average threshold before (VREF)(R1)/(R1 R2). calculated based average output voltage (VCC/2) simplified circuit model Figure assure that comparator's noninverting input average, same before: (VREF VTH)/(VTH/R1 (VTH VCC/2)/R3) additional hysteresis 10mV less, uncommon same within resistor tolerances. This method will work additional hysteresis hundred millivolts. Beyond that, impedance enough effect bias string, adjustment also required. Note that currents through R1/R2 bias string should many times input currents LT1720/LT1721. accuracy, current must least 120A(6A 0.05); more higher accuracy.
VREF VREF VAVERAGE
LT1720
LT1720
INPUT
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Figure Additional External Hysteresis
Figure Model Additional Hysteresis Calculations
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LT1720/LT1721 APPLICATIONS INFORMATION
Interfacing LT1720/LT1721 LT1720/LT1721 comparators used high speed applications where Emitter-Coupled Logic (ECL) deployed. interface outputs LT1720/LT1721 logic inputs, standard TTL/CMOS level translators such 10H124, 10H424 100124 used. These components come cost nanoseconds additional delay well supply currents 50mA more, only available quads. faster, simpler lower power translator constructed with resistors shown Figure Figure shows standard Positive (PECL) resistive level translator. This translator cannot used LT1720/LT1721, with CMOS logic, because depends resistor limit output swing (VOH) all-NPN gate with so-called totem-pole output. LT1720/LT1721 fabricated complementary bipolar process their output stage driver that pulls output nearly supply rail, even when sourcing 10mA. Figure shows three resistor level translator interfacing LT1720/LT1721 running same supply rail. pull-down output LT1720/LT1721 needed, pull-down limits seen PECL gate. This needed because inputs have both minimum maximum specification proper operation. Resistor values given both interface types; both cases assumed that LT1720/LT1721 operates from same supply rail. Figure shows case translating PECL from LT1720/LT1721 powered supply rail. Again, resistor values given both interface types. This time four resistors needed, although with 10KH/E, needed. that case, circuit resembles standard translator Figure function resistor, much different. loads LT1720/LT1721 output when high that current flowing through doesn't forward bias LT1720/LT1721's internal clamp diode. Although this diode handle 20mA without damage, normal operation performance output stage impaired above 100A forward current. prevents this with minimum additional power dissipation. Finally, Figure shows case driving standard, negative-rail, with LT1720/LT1721. Resistor values given both interface types both LT1720/LT1721 supply rail. Again, fourth resistor, needed prevent state current from flowing LT1720/LT1721, turning internal ESD/substrate diodes. only output stage functionality speed suffer, this case substrate common comparators LT1720/LT1721, operation other comparator(s) same package could also affected. Resistor again prevents this with minimum additional power dissipation. dividers shown, output impedance about 110. This makes these fast, less than nanosecond, with most layouts. Avoid temptation speedup capacitors. only they foul operation gate because overshoots, they damage inputs, particularly during power-up separate supply configurations. level translator designs assume gate load. Multiple gates have significant loading, transmission line routing termination issues also make this case difficult. ECL, particularly PECL, valuable technology high speed system design, must used with care. With less than volt swing, noise margins need evaluated carefully. Note that there some degradation noise margin resistor selections shown. With 10KH/E, there temperature compensation logic levels, whereas LT1720/LT1721 circuits shown give levels that stable with temperature. This will degrade noise margin over temperature. some configurations possible compensation with diode transistor junctions series with resistors these networks. more information design, refer ECLiPS data book (DL140), 10KH system design handbook (HB205) PECL design (AN1406), from Semiconductor (www.onsemi.com).
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LT1720/LT1721 APPLICATIONS INFORMATION
LT1720/LT1721 LEVEL TRANSLATION. TEXT 10KH/E
LSTTL
STANDARD PECL TRANSLATOR
LT1720
10KH/E 100K/E 5.2V 4.5V
LT1720/LT1721 OUTPUT PECL TRANSLATOR 10KH/E 100K/E 5.2V OMIT 4.5V 1500 1000
LT1720
LT1720/LT1721 OUTPUT PECL TRANSLATOR
LT1720
FAMILY 10KH/E 100K/E
-5.2V -4.5V
1200 1500
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LT1720/LT1721 OUTPUT STANDARD TRANSLATOR
Figure
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LT1720/LT1721 APPLICATIONS INFORMATION
Circuit Description block diagram comparator LT1720/LT1721 shown Figure There differential inputs (+IN/-IN), output (OUT), single positive supply (VCC) ground (GND). comparators completely independent, sharing only power ground pins. circuit topology consists differential input stage, gain stage with hysteresis complementary common-emitter output stage. internal signal paths utilize voltage swings high speed power. input stage topology maximizes input dynamic range available without requiring power, complexity area complete input stages such found rail-to-rail input comparators. With 2.7V supply, LT1720/LT1721 still have respectable 1.6V input common mode range. differential input voltage range rail-to-rail, without large input currents found competing devices. input stage also features phase reversal protection prevent false outputs when inputs driven below -100mV common mode voltage limit. internal hysteresis implemented positive, nonlinear feedback around second gain stage. Until this point, signal path been entirely differential. signal path then split into drive signals upper lower output transistors. output transistors connected common emitter rail-to-rail output operation. Schottky clamps limit output voltages about 300mV from rail, quite 50mV 15mV Linear
NONLINEAR STAGE
Technology's rail-to-rail amplifiers other products. output comparator digital, this output stage drive CMOS directly. also drive ECL, described earlier, analog loads demonstrated applications follow. bias conditions signal swings output stages designed turn their respective output transistors faster than This nearly eliminates surge current from ground that occurs transitions, keeping power consumption even with high output-toggle frequencies. surge current what keeps power consumption high output-toggle frequencies. frequency dependence supply current shown Typical Performance Characteristics. Just 20pF capacitive load output more than triples frequency dependent rise. slope no-load curve just 32A/MHz. With supply, this current equivalent charging discharging just 6.5pF slope 20pF load curve 133A/MHz, addition 101A/MHz, 20A/MHz-V, units that equivalent picoFarads. LT1720/LT1721 dynamic current estimated adding external capacitive loading internal equivalent capacitance 15pF multiplied toggle frequency supply voltage. Because capacitance routing traces easily approach these values, dynamic current dominated load most circuits.
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Figure LT1720/LT1721 Block Diagram
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LT1720/LT1721 APPLICATIONS INFORMATION
Speed Limits LT1720/LT1721 comparators intended high speed applications, where important understand limitations. These limitations roughly divided into three categories: input speed limits, output speed limits, internal speed limits. There significant input speed limits except shunt capacitance input nodes. typical input nodes driven, LT1720/LT1721 will respond. output speed constrained mechanisms, first which slew currents available from output transistors. maintain power quiescent operation, LT1720/LT1721 output transistors sized deliver 25mA 45mA typical slew currents. This sufficient drive small capacitive loads logic gate inputs extremely high speeds. slew rate will slow dramatically with heavy capacitive loads. Because propagation delay (tPD) definition ends time output voltage halfway between supplies, fixed slew current actually makes LT1720/LT1721 faster than with 20mV input overdrive. Another manifestation this output speed limit skew, difference between tPDLH tPDHL. slew currents LT1720/LT1721 vary with process variations transistors, rising edges falling edges respectively. typical 0.5ns skew have either polarity, rising edge falling edge faster. Again, skew will increase dramatically with heavy capacitive loads. skews comparators single package correlated, identical. Besides some random variability, there small (100ps 200ps) systematic skew physical parasitics packages. LT1720 SO-8, comparator whose output adjacent pin, will have relatively faster rising edge than comparator Likewise, comparator virtue output adjacent ground will have relatively faster falling edge. Similar dependencies occur LT1721 S16, while systemic skews smaller MSOP SSOP packages half again small. course, capacitive loads comparators single package identical, differential timing will degrade further. second output speed limit clamp turnaround. LT1720/LT1721 output optimized fast initial response, with some loss turnaround speed, limiting toggle frequency. output transistors idled power state once reached detecting Schottky clamp action. only when output slewed from voltage voltage, clamp circuitry settled, that idle state reached output fully ready transition again. This clamp turnaround time typically each direction, resulting maximum toggle frequency 62.5MHz, 125MB data rate. With higher frequencies, dropout runt pulses occur. Increases capacitive load will increase time needed slewing limited slew currents maximum toggle frequency will decrease further. higher toggle frequency applications, refer LT1715, whose output stage toggle 150MHz typical. internal speed limits manifest themselves dispersion. comparators have some degree dispersion, defined change propagation delay versus input overdrive. propagation delay LT1720/LT1721 will vary with overdrive, from typical 4.5ns 20mV overdrive overdrive (typical). LT1720/ LT1721's primary source dispersion hysteresis stage. change polarity arrives gain stage, positive feedback hysteresis stage subtracts from overdrive available. Only when enough time elapsed signal propagate forward through gain stage, backwards through hysteresis stage forward through gain stage again, will output stage receive same level overdrive that would have received absence hysteresis. With overdrive, LT1720/LT1721 faster with supply than with supply, opposite what true with 20mV overdrive. This internal speed limit, because gain stage faster than primarily reduced junction capacitances with higher reverse voltage bias. many applications, shown following examples, there plenty input overdrive. Even applications providing levels overdrive, LT1720/LT1721 fast enough that absolute dispersion 2.5ns 4.5) often small enough ignore.
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LT1720/LT1721 APPLICATIONS INFORMATION
gain hysteresis stage LT1720/LT1721 simple, short high speed help prevent parasitic oscillations while adding minimum dispersion. This internal "self-latch" usefully exploited many applications because occurs early signal chain, power, fully differential stage. therefore highly immune disturbances from other parts circuit, either same comparator, supply lines, from other comparator(s) same package. Once high speed signal trips hysteresis, output will respond, after fixed propagation delay, without regard these external influences that cause trouble nonhysteretic comparators. ±VTRIP Test Circuit input trip points tested using circuit shown Test Circuits section that precedes this Applications Information section. test circuit uses 1kHz triangle wave repeatedly trip comparator being tested. LT1720/LT1721 output used trigger switched capacitor sampling triangle wave, with sampler each direction. Because triangle wave attenuated 1000:1 LT1720/LT1721's differential input, sampled voltages therefore 1000 times input trip voltages. hysteresis offset computed from trip points shown. Crystal Oscillators simple crystal oscillator using comparator LT1720/LT1721 shown first page this data sheet. 2k-620 resistor pair bias point comparator's noninverting input. 2k-1.8k-0.1F path sets inverting input node appropriate average level based output. crystal's path provides resonant positive feedback stable oscillation occurs. Although LT1720/LT1721 will give correct logic output when input outside common mode range, additional delays occur when operated, opening possibility spurious operating modes. Therefore, bias voltages inputs near center LT1720/LT1721's common mode range resistor attenuates feedback noninverting input. circuit will operate with AT-cut crystal from 1MHz 10MHz over 2.7V supply range. power applied, circuit remains until LT1720/LT1721 bias circuits activate, typical 2.2V (25°C), which point desired frequency output generated. output duty cycle this circuit roughly 50%, affected resistor tolerances and, lesser extent, comparator offsets timings. duty cycle required, circuit Figure creates pair complementary outputs with forced duty cycle. Crystals narrow-band elements, feedback noninverting input filtered analog version square wave output. Changing noninverting reference level therefore vary duty cycle. operates previous example, whereas creates complementary output comparing same nodes with opposite input polarity. compares band-limited versions outputs biases C1's negative input. C1's only degree freedom respond variation pulse width; hence outputs forced duty cycle. Again, circuit operates from 2.7V skew between edges outputs shown Figure There slight duty cycle dependence comparator loading, equal capacitive resistive loading should used critical applications. This circuit works well because matched delays rail-to-rail style outputs LT1720.
2.7V 1MHz 10MHz CRYSTAL (AT-CUT)
GROUND CASE OUTPUT 100k 0.1F 1.8k 0.1F
LT1720
LT1636 0.1F
LT1720
100k OUTPUT
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Figure Crystal Oscillator with Complementary Outputs Duty Cycle
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LT1720/LT1721 APPLICATIONS INFORMATION
1000 OUTPUT SKEW (ps)
optional feedback network shown used force identical output duty cycles. steady state duty cycles both outputs will 44%. Note, though, that addition this network only adjusts percentage time each output high same, which important switching circuits requiring identical settling times. cannot adjust relative phases between outputs exactly 180° apart, because signal input node driven crystal pure sinusoid.
SUPPLY VOLTAGE 2V/DIV
1720/21
Figure Timing Skew Figure Circuit
2V/DIV
circuit Figure shows crystal oscillator circuit that generates nonoverlapping clocks making full independent comparators LT1720. oscillates before, with lower reference level, C2's output will toggle different times. resistors degree separation between output's high pulses. With values shown, each output high duty cycle, sufficient allow between high pulses. Figure shows outputs.
2.7V 10MHz CRYSTAL (AT-CUT)
20ns/DIV
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Figure Nonoverlapping Outputs Figure Circuit
GROUND CASE OUTPUT OPTIONAL- TEXT 100k
LT1720
1.3k
LT1636 0.1F
0.1F
0.1F
2.2k
LT1720
100k OUTPUT
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Figure Crystal-Based Nonoverlapping 10MHz Clock Generator
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LT1720/LT1721 APPLICATIONS INFORMATION
Timing Skews number reasons, LT1720/LT1721's superior timing specifications make them excellent choice applications requiring accurate differential timing skew. comparators single package inherently well matched, with just 300ps typical. Monolithic construction keeps delays well matched supply voltage temperature. Crosstalk between comparators, usually disadvantage monolithic duals quads, minimal effect LT1720/LT1721 timing internal hysteresis, described Speed Limits section. circuits Figure show basic building blocks differential timing skews. 2.5k resistance interacts with typical input capacitance create least ±4ns delay, controlled potentiometer setting. differential single-ended version shown. differential configuration, output edges smoothly scrolled through with negligible interaction. Delay Detector often necessary measure comparative timing pulse edges order determine true synchronicity clock control signals, whether digital circuitry high speed instrumentation. circuit Figure delay detector which will output pulse when signals sync (specifically, when high low). Note that addition identical circuit detect opposite situation high) allows full skew detection. Comparators clean incoming signals render circuit less sensitive input levels slew rates. resistive divider network provides level shifting downstream comparator's common mode input range, well offset keep output except during decisive event. When upstream comparator's outputs overcome resistively generated offset (and hysteresis), comparator performs Boolean "X*_Y" function produces output pulse (see Figure 13). circuit will give full output response with input delays down partial output response with input delays down 1.8ns. Capacitor helps ensure that imbalance parasitic capacitances layout will cause common mode excursions result differential mode signal false outputs.1
Make sure input levels close 0.5V threshold R8-R9 divider. still getting false outputs, increasing 10pF more. also look problem impedance balance inputs U1C. Increasing offset lowering will help reject false outputs, should also lowered maintain impedance balance. ease design parasitic matching, replaced parallel resistors equal
LT1720
LT1720
INPUT 2.5k DIFFERENTIAL RELATIVE SKEW
INPUT
2.5k SINGLE-ENDED DELAY
VREF VREF
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Figure Building Blocks Timing Skew Generation with LT1720
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LT1720/LT1721 APPLICATIONS INFORMATION
DELAY DETECTOR 1.82k* 301* OPTIONAL LOGARITHMIC PULSE STRETCHER (SEE TEXT) CAPTURE
LT1721
301*
4.53k 0.1F 487*
301* 5.6pF LT1721
1N5711
499*
0.33F
LT1721 475*
LT1721 301*
540pF
261*
VOFF
DECAY
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METAL FILM RESISTOR 270pF REDUCED LEAD INDUCTANCE
RESULT
Figure Delay Detector with Logarithmic Pulse Stretcher
Figure Output Pulse Delay Input Pulse
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LT1720/LT1721 APPLICATIONS INFORMATION
Optional Logarithmic Pulse Stretcher fourth comparator quad LT1721 work logarithmic pulse stretcher. This simple circuit help tremendously don't have fast enough oscilloscope control circuit) easily capture pulse widths faster). When input pulse occurs, charged with 180ns capture2 time constant. hysteresis 10mV offset across overcome within first nanosecond3, switching comparator output high. When input pulse subsides, discharges with 540ns time constant, keeping comparator until decay overrides 10mV offset across minus hysteresis. Because this exponential decay, output pulse width will proportional logarithm input pulse width. important bypass circuit's well avoid coupling into resistive divider. keeps quiescent input voltage range where forward leakage diode 0.4V driving comparator problem. Neglecting some effects4, output pulse related input pulse tOUT {VCH (-tP/1)]/(VOFF VH/2)} [VCH/(VCH VOFF VH/2)] where input pulse width tOUT output pulse width VOFF 10mV 3.5mV VFDIODE R2/(R1 capture time constant decay time constant voltage drop across LT1721 hysteresis input pulse voltage after diode drop effective source voltage charge simplicity, with neglecting very slight delay turn-on offset hysteresis, equation approximated tOUT [(VCH tP/1)/(VOFF VH/2)] example, input pulse gives 1.67s output pulse. Doubling input pulse 16ns lengthens output pulse 0.37s. Doubling input pulse again 32ns adds another 0.37s output pulse, rate 0.37s octave falls above equation tOUT/octave ln(2) There ±0.01s jitter5 output pulse which gives uncertainty referred input pulse less than (60ps resolution pulse with 60MHz oscilloscope-not bad!). beauty this circuit that gives resolution precisely where it's hardest get. jitter combination slow decay last millivolts 4nV/Hz noise 400MHz bandwidth LT1721 input stage. Increasing offset across decreasing will decrease this jitter expense dynamic range. circuit topology itself extremely fast, limited theoretically only speed diode, capture time constant pulse source impedance. Figure shows results achieved with implementation shown, compared plot Equation (1). limited delivery time upstream comparators. input pulse width increased, function constrained asymptotic response but, rather than becoming clamped, becomes time linear. Thus, very long input pulses third term Equation dominates circuit becomes pulse stretcher.
called because very fast input pulse "captured," later examination, charge capacitor. Assuming input pulse slew rate diode infinite. This effective delay constant, about 0.4% 0.8ns, second term equation below. Driven 2.5ns slew-limited LT1721, this effective delay will 2ns. dependent LT1721 output voltage nonlinear diode characteristics. Also, Thevenin equivalent charge voltage seen boosted slightly being terminated above ground. Output jitter increases with inputs pulse widths below ~3ns.
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LT1720/LT1721 APPLICATIONS INFORMATION
tOUT STRETCHED MEASURED tPULSE (ns) 1000 10000
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EQUATION
output pulse widths per-octave response your circuit (see Equation (3)). Shorter cable length differences used plot circuit performance down 1.5ns any), which then later used lookup reference when have moved from quantifying circuit using circuit. (Note there slight aberration performance below 10ns. Figure 14.) final check, feed circuit with identical cable lengths check that producing output pulses. 10ns Triple Overlap Generator circuit Figure utilizes LT1721 generate three overlapping outputs whose pulse edges separated 10ns shown. time constant network output comparator Comparator trip fixed percentages exponential voltage decay across capacitor. 4.22k feed-forward comparator's inverting input keeps delay differences same each direction despite exponential nature network's voltage. There 15ns delay first edge both directions, 4.5ns delay LT1721 comparators, plus delay network. This starting delay shortened somewhat pulse shorter than 40ns because network will have fully settled; however, 10ns edge separations stay constant. values shown utilize only lowest supply voltage span, which allows work down 2.7V supply. delay differences grow couple nanoseconds from 2.7V supply fixed /VOH drops which grow percentage supply voltage. keep this effect minimum, pull-up comparator provides equal loading either state. Fast Waveform Sampler Figure uses diode-bridge-type switch clean, fast waveform sampling. diode bridge, because inherent symmetry, provides lower errors than other semiconductor-based switching technologies. This circuit features 20dB gain, 10MHz full power bandwidth 100V/°C baseline uncertainty. Switching delay less than 15ns minimum sampling window width full power response 30ns.
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Figure Pulse Stretcher Output Pulse Input Pulse
NANOSECOND INPUT RANGE MICROSECOND OUTPUT RANGE
FOOT CABLE CIRCUIT FIGURE FOOT CABLE SPLITTER
tOUT (SEE TEXT)
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Figure RG-58 Cable with Velocity Propogation 66%; Delay 1.54ns
don't need expensive equipment confirm actual overall performance this circuit. need respectable waveform generator (capable >~100kHz), splitter, variety cable lengths 20MHz 60MHz oscilloscope. Split single pulse source into different cable lengths then into delay detector, feeding longer cable into input (see Figure 15). foot cable length difference will create ~9.2ns delay (using propagation speed RG-58 cable), should result easily measured 1.70s output pulses. foot cable length difference will result ~18.4ns delay 2.07s output pulses. difference
LT1720/LT1721 APPLICATIONS INFORMATION
OUTPUTS
INPUT 100pF 1.37k LT1721
10ns
10ns
LT1721 VREF
LT1721
4.22k
10ns
10ns
LT1721
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Figure 10ns Triple Overlap Generator
2.2k 2.2k
INPUT 100mV FULL SCALE 1N5711 CA3039 DIODE ARRAY (SUBSTRATE -5V) 1.5k 3.6k 1.1k 0.1F BALANCE
LT1227 OUTPUT FULL SCALE
LT1720
1.1k
1.1k
SAMPLE COMMAND 10pF SKEW COMP 2.5k
1.1k MRF501 MRF501
BALANCE
LT1720
LM3045
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Figure Fast Waveform Sampler Using LT1720 Timing-Skew Compensation
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LT1720/LT1721 APPLICATIONS INFORMATION
input waveform presented diode bridge switch, output which feeds LT1227 wideband amplifier. LT1720 comparators, triggered sample command, generate phase-opposed outputs. These signals level shifted transistors, providing complementary bipolar drive switch bridge. skew compensation trim ensures bridge-drive signal simultaneity within 1ns. balance corrects parasitic capacitive bridge imbalances. balance adjustment trims bridge offset. trim sequence involves grounding input applying 100kHz sample command. balance adjusted minimal bridge variation output. skew compensation balance adjustments then optimized minimum disturbance output. Finally, unground input circuit ready use. Voltage-Controlled Clock Skew Generator sometimes necessary generate pairs identical clock signals that phase skewed time. Further, desirable able amount time skew tuning voltage. Figure 18's circuit does this utilizing LT1720 digitize phase information from varactor-tuned time domain bridge. control signal provides ±10ns output skew. This circuit operates from 2.7V supply.
CLOCK INPUT 2.7V
LT1720 2.5k FIXED OUTPUT
2.5k* 10ns TRIM "FIXED" "SKEWED" 12pF MV-209 VARACTOR DIODE 0.005F 36pF
2.5k
LT1720 SKEWED OUTPUT
0.1F
L1**
INPUT 10ns SKEW 1N4148 74HC04 FILM RESISTOR SUMIDA CD43-100 POLYSTYRENE,
LT1077
2.2F 6.2M*
LT1317 200pF
1.1M 100k
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1.82M*
Figure Voltage-Controlled Clock Skew
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LT1720/LT1721 APPLICATIONS INFORMATION
Coincidence Detector High speed comparators especially suited interfacing pulse-output transducers, such particle detectors, logic circuitry. matched delays monolithic dual well suited those cases where coincidence pulses needs detected. circuit Figure coincidence detector that uses LT1720 discrete components fast gate. reference level arbitrary threshold. Only when both input signals exceed this will coincidence detected. Schottky diodes from comparator outputs base MRF-501 form gate, while other Schottkys provide fast turn-off. logic gate could instead used, would considerably more delay than 300ps contributed this discrete stage. This circuit detect coincident pulses narrow 3ns. narrower pulses, output will degrade gracefully, responding, with narrow pulses that don't rise "high" before starting fall. decision delay 4.5ns with input signals 50mV more above reference level. This circuit creates compatible output typically drive CMOS well. more detailed description operation this circuit, Application Note pages
GROUND CASE LEAD
0.1F 3.9k LT1720
MRF501 OUTPUT
COINCIDENCE COMPARATORS
Figure Coincidence Detector
LT1720 1N5711
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300ps GATE
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LT1720/LT1721 SIMPLIFIED SCHEMATIC
OUTPUT
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LT1720/LT1721 PACKAGE DESCRIPTION
Package 8-Lead Plastic (3mm 3mm)
(Reference 05-08-1698)
0.115 0.675 0.05 0.38 0.10
0.05 2.15
1.65 0.05 0.05 SIDES) PACKAGE OUTLINE 0.25 0.05 0.50 2.38 0.05 SIDES) RECOMMENDED SOLDER PITCH DIMENSIONS MARK (NOTE
3.00 0.10 SIDES)
1.65 0.10 SIDES)
(DD) 1203
0.200
0.75
0.05
0.25
0.05 2.38 0.10 SIDES)
0.50
0.00 0.05
BOTTOM VIEW-EXPOSED NOTE: DRAWING MADE JEDEC PACKAGE OUTLINE M0-229 VARIATION (WEED-1) DRAWING SCALE DIMENSIONS MILLIMETERS DIMENSIONS EXPOSED BOTTOM PACKAGE INCLUDE MOLD FLASH. MOLD FLASH, PRESENT, SHALL EXCEED 0.15mm SIDE EXPOSED SHALL SOLDER PLATED SHADED AREA ONLY REFERENCE LOCATION BOTTOM PACKAGE
Package 8-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference 05-08-1610)
.189 .197 (4.801 5.004) NOTE
.045 .050
.005
.245
.160
.005 .228 .244 (5.791 6.197)
.150 .157 (3.810 3.988) NOTE
.030
.005 RECOMMENDED SOLDER LAYOUT .010 .020 (0.254 0.508) .008 .010 (0.203 0.254) .016 .050 (0.406 1.270) NOTE: DIMENSIONS
.053 .069 (1.346 1.752)
.004 .010 (0.101 0.254)
INCHES (MILLIMETERS) DRAWING SCALE THESE DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS. MOLD FLASH PROTRUSIONS SHALL EXCEED .006" (0.15mm)
.014 .019 (0.355 0.483)
.050 (1.270)
0303
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LT1720/LT1721 PACKAGE DESCRIPTION
Package 8-Lead Plastic MSOP
(Reference 05-08-1660)
0.889 (.035 0.127 .005)
5.23 (.206)
3.20 3.45 (.126 .136)
0.42 0.038 (.0165 .0015)
0.65 (.0256)
3.00 0.102 (.118 .004) (NOTE
0.52 (.0205)
RECOMMENDED SOLDER LAYOUT DETAIL
4.90 0.152 (.193 .006)
0.254 (.010) GAUGE PLANE
3.00 0.102 (.118 .004) (NOTE
0.53 0.152 (.021 .006) DETAIL 0.18 (.007) SEATING PLANE
1.10 (.043)
0.86 (.034)
0.22 0.38 (.009 .015)
NOTE: DIMENSIONS MILLIMETER/(INCH) DRAWING SCALE DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.152mm (.006") SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSIONS. INTERLEAD FLASH PROTRUSIONS SHALL EXCEED 0.152mm (.006") SIDE LEAD COPLANARITY (BOTTOM LEADS AFTER FORMING) SHALL 0.102mm (.004")
0.65 (.0256)
0.1016 (.004
0.0508 .002)
MSOP (MS8) 0307
Package 16-Lead Plastic Small Outline (Narrow .150 Inch)
(Reference 05-08-1610)
.045 .050
.386 .394 (9.804 10.008) NOTE
.005
.245
.160
.005
.228 .244 (5.791 6.197)
.030 .005
.150 .157 (3.810 3.988) NOTE
RECOMMENDED SOLDER LAYOUT
.010 .020 (0.254 0.508) .008 .010 (0.203 0.254)
.053 .069 (1.346 1.752)
.004 .010 (0.101 0.254)
.016 .050 (0.406 1.270) NOTE: DIMENSIONS
.014 .019 (0.355 0.483)
.050 (1.270)
0502
INCHES (MILLIMETERS) DRAWING SCALE THESE DIMENSIONS INCLUDE MOLD FLASH PROTRUSIONS. MOLD FLASH PROTRUSIONS SHALL EXCEED .006" (0.15mm)
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LT1720/LT1721 PACKAGE DESCRIPTION
Package 16-Lead Plastic SSOP (Narrow .150 Inch)
(Reference 05-08-1641)
.045 .005
.189 .196* (4.801 4.978)
.009 (0.229)
.254
.150 .165
.229 .244 (5.817 6.198)
.150 .157** (3.810 3.988)
.0165 .0015
.0250
RECOMMENDED SOLDER LAYOUT
.015 .004 (0.38 0.10) .007 .0098 (0.178 0.249) .016 .050 (0.406 1.270)
NOTE: CONTROLLING DIMENSION: INCHES INCHES DIMENSIONS (MILLIMETERS) DRAWING SCALE *DIMENSION DOES INCLUDE MOLD FLASH. MOLD FLASH SHALL EXCEED 0.006" (0.152mm) SIDE **DIMENSION DOES INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL EXCEED 0.010" (0.254mm) SIDE
.004 .0098 (0.102 0.249)
.0532 .0688 (1.35 1.75)
.008 .012 (0.203 0.305)
.0250 (0.635)
GN16 (SSOP) 0204
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LT1720/LT1721 TYPICAL APPLICATION
Pulse Stretcher detecting short pulses from single sensor, pulse stretcher often required. circuit Figure acts one-shot, stretching width incoming pulse consistent 100ns. Unlike logic one-shot, this LT1720-based circuit requires only 100pV-s stimulus trigger. circuit works follows: Comparator functions threshold detector, whereas comparator configured one-shot. first comparator prebiased with threshold overcome comparator system offsets establish output absence input signal. input pulse sends output high, which turn latches C2's output high. output back input first comparator, causing regeneration latching both outputs high. Timing
capacitor begins charging through and, 100ns, resets low. output also goes low, latching both outputs low. pulse input restart process. Timing capacitor increased without limit longer output pulses. This circuit ultimate sensitivity better than 14mV with 10ns input pulses. even detect avalanche generated test pulse just duration with sensitivity better than 100mV.6 detect short events better than coincidence detector Figure because one-shot configured catch just 100mV upward movement from C1's VOL, whereas coincidence detector's specification based full, legitimate logic high, without help regenerative one-shot.
Linear Technology Application Note Appendix This circuit detect output
pulse generator described after 40dB attenuation.
0.01F OUTPUT
6.8k 1N5711 100pF LT1720
Figure Pulse Stretcher
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1671 LT1715 LT1719 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground-Sensing Comparator 7ns, UltraFast, Single Supply Comparator 60ns, Power, Single Supply Comparator 4ns, 150MHz Dual Comparator 4.5ns Single Supply 3V/5V Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version LT1016 Single Supply Comparator 450A Single Supply Comparator Similar LT1720 with Independent Input/Output Supplies Single Comparator Similar LT1720/LT1721
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 1998
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PULSE SOURCE
LT1720
100ns

LT®1720/LT1721 UltraFastdual/quad comparators optimized single supply

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