LT®1715 UltraFastdual comparator optimized voltage operation. Separate
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LT1715 4ns, 150MHz Dual Comparator with Independent Input/Output Supplies DESCRIPTION
LT®1715 UltraFastdual comparator optimized voltage operation. Separate supplies allow independent analog input ranges output logic levels with loss performance. input voltage range extends from 100mV below 1.2V below VCC. Internal hysteresis makes LT1715 easy even with slow moving input signals. rail-to-rail outputs directly interface toTTL CMOS. symmetric output drive results similar rise fall times that harnessed analog applications easy translation other single supply logic levels. LT1715 available 10-pin MSOP package. pinout LT1715 minimizes parasitic effects placing most sensitive inputs away from outputs, shielded power rails. dual/quad single supply comparator with similar propagation delay, LT1720/LT1721. single comparator with similar propagation delay, LT1719.
Lare registered trademarks Linear Technology Corporation. UltraFast trademark Linear Technology Corporation.
UltraFast: 20mV Overdriven 150MHz Toggle Frequency Separate Input Output Power Supplies Power: 4.6mA Comparator Pinout Optimized High Speed Output Optimized Supplies TTL/CMOS Compatible Rail-to-Rail Output Input Voltage Range Extends 100mV Below Negative Rail Internal Hysteresis with Specified Limits Specified -40°C 125°C Temperature Range Available 10-pin MSOP Package
APPLICATIONS
High Speed Differential Line Receivers Level Translators Window Comparators Crystal Oscillator Circuits Threshold Detectors/Discriminators High Speed Sampling Circuits Delay Lines
TYPICAL APPLICATION
100MHz Dual Differential Line Receiver
Line Receiver Response 100MHz Clock, 50MHz Data Both with 25mVP-P Inputs
CLOCK
1V/DIV
DATA 5ns/DIV
1715 TA02
1V/DIV
1715 TA01
PROBES
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LT1715 ABSOLUTE MAXIMUM RATINGS
(Note
CONFIGURATION
VIEW
Supply Voltage .13.2V .13.2V -13.2V 0.3V Input Current (+IN, -IN) .±10mA Output Current (Continuous) .±20mA Operating Temperature Range (Note LT1715C. -40°C 85°C LT1715I -40°C 85°C LT1715H -40°C 125°C Specified Temperature Range (Note LT1715C. 70°C LT1715I -40°C 85°C LT1715H -40°C 125°C Junction Temperature 150°C Storage Temperature Range. -65°C 150°C Lead Temperature (Soldering, sec) 300°C
PACKAGE 10-LEAD PLASTIC MSOP TJMAX 150°C, 120°C/W (NOTE
ORDER INFORMATION
LEAD FREE FINISH LT1715CMS#PBF LT1715IMS#PBF LT1715HMS#PBF TAPE REEL LT1715CMS#TRPBF LT1715IMS#TRPBF LT1715HMS#TRPBF PART MARKING LTVQ LTVV LTVV PACKAGE DESCRIPTION 10-Lead Plastic MSOP 10-Lead Plastic MSOP 10-Lead Plastic MSOP SPECIFIED TEMPERATURE RANGE 70°C -40°C 85°C -40°C 125°C
Consult Marketing parts specified with wider operating temperature ranges. Consult Marketing information non-standard lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. -5V, COUT 10pF VOVERDRIVE 20mV, unless otherwise specified.
SYMBOL VCMR VTRIP+ VTRIP- PARAMETER Input Supply Voltage Output Supply Voltage Input Voltage Range Input Trip Points Input Trip Points (Note (Note (Note LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H CONDITIONS
ELECTRICAL CHARACTERISTICS
-1.5 -1.8 -5.5
UNITS
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LT1715 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Input Offset Voltage
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. -5V, COUT 10pF VOVERDRIVE 20mV, unless otherwise specified.
CONDITIONS (Note LT1715C, LT1715I LT1715H
UNITS V/°C
VHYST CMRR PSRR fMAX tPD20
Input Hysteresis Voltage Input Offset Voltage Drift Input Bias Current Input Offset Current Common Mode Rejection Ratio Power Supply Rejection Ratio Voltage Gain Output High Voltage Output Voltage Maximum Toggle Frequency Propagation Delay
(Note
LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H
-2.5
(Note (Note (Note
LT1715C, LT1715I LT1715H
ISOURCE 4mA, VTRIP+ 20mV ISINK 10mA, VTRIP- 20mV (Note VOVERDRIVE 20mV (Note 11), LT1715C, LT1715I LT1715H VOVERDRIVE 20mV, VOVERDRIVE 20mV, LT1715C, LT1715I LT1715H
psRMS psRMS
tPD5 tSKEW tJITTER
Propagation Delay Propagation Delay Skew Differential Propagation Delay Output Rise Time Output Fall Time Output Timing Jitter Positive Input Stage Supply Current (per Comparator)
VOVERDRIVE 5mV, (Notes (Note Between tPD+/tPD-, (Note Between Channels 1.2VP-P (6dBm), 20MHz (Note tPD+ tPD-
LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H
-4.8 -5.3 -3.8 -4.3 -2.9 -2.4
Negative Input Stage Supply Current (per Comparator)
LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H
Positive Output Stage Supply Current (per Comparator)
LT1715C, LT1715I LT1715H LT1715C, LT1715I LT1715H
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LT1715 ELECTRICAL CHARACTERISTICS
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note LT1715C guaranteed functional over operating range -40°C 85°C. Note LT1715C guaranteed meet specified performance from 70°C. LT1715°C designed, characterized expected meet specified performance from -40°C 85°C tested sampled these temperatures. LT1715I guaranteed meet specified performance from -40°C 85°C. LT1715H guaranteed meet specified performance from -40°C 125°C. Note Thermal resistances vary depending upon amount board metal attached device. specified 2500mm2 3/32" FR-4 board covered with copper both sides with 100mm2 copper attached Thermal performance improved beyond given specification using 4-layer board attaching more metal area Note input within these common mode limits, other input outside common mode limits output will valid. Note LT1715 comparator includes internal hysteresis. trip points input voltage needed change output state each direction. offset voltage defined average VTRIP+ VTRIP-, while hysteresis voltage difference these two. Note common mode rejection ratio measured with defined change offset voltage measured from -5.1V 3.8V, divided 8.9V. Note power supply rejection ratio measured with defined worst change offset voltage from 2.7V (with divided 3.3V change offset voltage from (with divided Note Because internal hysteresis, there small-signal region which measure gain. Proper operation internal circuity ensured measuring with only 20mV overdrive. Note Maximum toggle rate defined highest frequency which 100mV sinusoidal input results error free output toggling greater than when high less than when output supply. Note Propagation delay measurements made with 100mV steps. Overdrive measured relative VTRIP±. Note cannot measured automatic handling equipment with values overdrive. LT1715 100% tested with 100mV step 20mV overdrive. Correlation tests have shown that limits guaranteed with this test. Note Propagation Delay Skew defined tSKEW |tPDLH tPDHL| Note Differential propagation delay defined larger two: tPDLH |tPDLHA tPDLHB| tPDHL |tPDHLA tPDHLB| Note Package inductances combined with asynchronous activity other channel increase output jitter. Channel Interactions Applications Information. Specification above with channel active only.
TYPICAL PERFORMANCE CHARACTERISTICS
Input Offset Trip Voltages Supply Voltage
TRIP POINT VOLTAGE (mV) TRIP POINT VOLTAGE (mV) VTRIP+ 25°C SUPPLY VOLTAGE, VTRIP- TEMPERATURE (°C)
1715
Input Offset Trip Voltages Temperature
COMMON MODE INPUT VOLTAGE VTRIP+ -4.8 -5.0 -5.2
Input Common Mode Limits Temperature
VTRIP-
-5.4
TEMPERATURE (°C)
1715
1715
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LT1715 TYPICAL PERFORMANCE CHARACTERISTICS
Input Current Differential Input Voltage
SUPPLY CURRENT COMPARATOR (mA) INPUT BIAS DIFFERENTIAL INPUT VOLTAGE 25°C
Quiescent Supply Current Temperature
SUPPLY CURRENT COMPARATOR (mA)
Quiescent Supply Current Supply Voltage
25°C OUTPUT HIGH
OUTPUT
IEE, OUTPUT
IEE, OUTPUT HIGH SUPPLY VOLTAGE,
1715
TEMPERATURE (°C)
1715
1715
TOTAL SUPPLY CURRENT COMPARATOR (mA)
Output Voltage Load Current
OUTPUT VOLTAGE RELATIVE UNLESS 125°C OTHERWISE NOTED 2.7V -10mV 125°C -55°C 25°C -0.1
Output High Voltage Load Current
UNLESS OTHERWISE NOTED 10mV -55°C -0.3 25°C -0.4 125°C -0.5 125°C 2.7V -0.6 OUTPUT SOURCE CURRENT (mA)
1715
Supply Current Toggle Frequency
CLOAD 20pF CLOAD 25°C ±50mV SINUSOID TOGGLE FREQUENCY (MHz)
1715
VALID TOGGLING
INCOMPLETE OUTPUT TOGGLING
OUTPUT VOLTAGE
-0.2
CLOAD 10pF
OUTPUT SINK CURRENT (mA)
1715
Propagation Delay Overdrive
25°C VSTEP 100mV CLOAD 10pF PROPAGATION DELAY (ns)
Propagation Delay Temperature
tPDLH CLOAD 10pF VSTEP 100mV PROPAGATION DELAY (ns)
Propagation Delay Supply Voltage
25°C VSTEP 100mV OVERDRIVE 20mV CLOAD 10pF tPDLH tPDHL tPDLH tPDHL
PROPAGATION DELAY (ns)
OVERDRIVE
tPDLH tPDHL tPDLH OVERDRIVE (mV) tPDHL
1715
OVERDRIVE 20mV
TEMPERATURE (°C)
SUPPLY VOLTAGE,
1715
1715
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LT1715 TYPICAL PERFORMANCE CHARACTERISTICS
Maximum Toggle Rate Input Amplitude
25°C CLOAD 10pF INPUT SINUSOID AMPLITUDE (mV)
1715
Maximum Toggle Rate Temperature
25°C ±50mV SINUSOID CLOAD 10pF RLOAD TEMPERATURE (°C) TOGGLE FREQUENCY (MHz)
Maximum Toggle Rate Supply Voltage
TOGGLING FROM
TOGGLE FREQUENCY (MHz)
TOGGLE FREQUENCY (MHz)
TOGGLING FROM
25°C ±50mV SINUSOID CLOAD 10pF
SUPPLY VOLTAGE
1715
1715
Maximum Toggle Rate Load Capacitance
TOGGLE FREQUENCY (MHz) OUTPUT CAPACITANCE (pF)
1715
Propagation Delay Load Capacitance
25°C VSTEP 100mV OVERDRIVE 20mV RISING EDGE (tPDLH) FALLING EDGE (tPDHL) 25mVP-P
Response 150MHz 25mVP-P Sine Wave Driving 10pF
20mV/DIV
PROPAGATION DELAY (ns)
25°C ±50mV SINUSOID
1V/DIV
2.5ns/DIV
1715
PROBES
OUTPUT LOAD CAPACITANCE (pF)
1715
FUNCTIONS
(Pin Noninverting Input Comparator (Pin Inverting Input Comparator (Pin Inverting Input Comparator (Pin Noninverting Input Comparator (Pin Negative Supply Voltage Input Stage Substrate. (Pin Ground Output Stage. (Pin Output Comparator (Pin Output Comparator (Pin Positive Supply Voltage Output Stage. (Pin 10): Positive Supply Voltage Input Stage.
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TEST CIRCUITS
±VTRIP Test Circuit
BANDWIDTH-LIMITED TRIANGLE WAVE 1kHz, ±7.5V 0.1F 10nF 200k LT1112
LTC203
1000 VTRIP+
LT1715
1000 VHYST
1000 LTC203 1000 VTRIP- 100k 2.4k LT1112 0.15F
1715 TC01
LT1638 10nF
100k LT1638
NOTES: LT1638, LT1112, LTC203s POWERED FROM ±15V. 200k PULL-DOWN PROTECTS LTC203 LOGIC INPUTS WHEN POWERED
100k
100k
LT1715
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LT1715 TEST CIRCUITS
Response Time Test Circuit
-100mV 0.1F PULSE 2N3866 1N5711
0.01F
LT1715
0.01F -VCM
SCOPE PROBE (CIN 10pF)
-1000 (OVERDRIVE VTRIP+) NOTE: RISING EDGE TEST SHOWN. FALLING EDGE, REVERSE LT1719 INPUTS
1715 TC02
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LT1715 APPLICATIONS INFORMATION
Power Supply Configurations LT1715 separate supply pins input output stages that allow flexible operation, accommodating separate voltage ranges analog input output logic. course, single 3V/5V supply used tying together well VEE. minimum voltage requirement simply stated both output input stages need least 2.7V must equal less than ground. following rules must adhered configuration: 2.7V (VCC VEE) 2.7V (+VS GND) (+VS VEE)) Ground Although ground need tied system ground, most applications will that way. Figure shows three common configurations. final uncommon, will work useful level translator;
2.7V
input stage from -5.2V ground while output stage from ground. this case common mode input voltage range does include ground, helpful Conversely, also tied below ground, long above rules violated. Input Voltage Considerations LT1715 specified common mode range -100mV 3.8V when used with single supply. more general consideration that common mode range 100mV below 1.2V below VCC. criterion this common mode limit that output still responds correctly small differential input signal. input within common mode limit, other input signal outside common mode limits, absolute maximum limits, output will retain correct polarity. When either input signal falls below negative common mode limit, internal diode formed with substrate turn resulting significant current flow through die. external Schottky clamp diode between input negative rail speed uprecovery from negative overdrive preventing substrate diode from turning When both input signals below negative common mode limit, phase reversal protection circuitry prevents false output inversion least -400mV common mode. However, offset hysteresis this mode will increase dramatically, much 15mV each. input bias currents will also increase. When input signal goes above common mode range without exceeding diode drop above input supply rail, input stage will remain biased comparator will maintain correct output polarity. Above this voltage, input stage current source will saturate completely protection diode will forward conduct. Once aberrant input falls back into common mode range, comparator will respond correctly valid input signals within less than 10ns.
Single Supply
Input, Output Supplies
-5.2V
1715
Input, Output Supplies
Front Entirely Negative
Figure Variety Power Supply Configurations
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LT1715 APPLICATIONS INFORMATION
When both input signals above positive common mode limit, input stage will debiased output polarity will random. However, internal hysteresis will hold output valid logic level. When least inputs returns within common mode limits, recovery from this state will take long propagation delay does increase significantly when driven with large differential voltages, with levels overdrive, apparent increase seen with large source resistances delay caused typical input capacitance. Input Protection input stage protected against damage from large differential signals, beyond differential voltage equal supply voltage, limited only absolute maximum currents noted. External input protection circuitry only needed currents would otherwise exceed these absolute maximums. internal catch diodes conduct current these rated maximums without latchup, even when supply voltages absolute maximum ratings. LT1715 input stage general purpose internal protection human body model. line receiver, additional external protection required. with most integrated circuits, level immunity much greater when residing printed circuit board where power supply decoupling capacitance will limit voltage rise caused pulse. Input Bias Current Input bias current measured with both inputs held with differential input stage, LT1715 bias current flows device. will zero higher inputs double lower inputs. With more than diode drops differential input voltage, LT1715's input protection circuitry activates, current lower input will increase additional there will small bias current into higher input pins, less. Typical Performance curve "Input Current Differential Input Voltage." High Speed Design Considerations Application high speed comparators often plagued oscillations. LT1715 internal hysteresis, which will prevent oscillations long parasitic output input feedback kept below 4mV. However, with 2V/ns slew rate LT1715 outputs, step created input source with only 0.02pF output input coupling. LT1715's pinout been arranged minimize problems placing sensitive inputs away from outputs, shielded power rails. input output traces circuit board should also separated, requisite level isolation readily achieved topside ground plane runs between output inputs. multilayer boards where ground plane internal, topside ground supply trace should between inputs output. ground LT1715 disturb ground plane potential while toggling extremely fast times output stage. Therefore, using ground input termination filtering that separate from LT1715 ground highly beneficial. example, ground plane tied directly adjacent long input trace capacitively couple disturbance into input. this scenario, cutting ground plane between inputs will capacitance disturbance down substantially. Figure shows typical topside layout LT1715 such multilayer board. Shown topside metal etch including traces, escape vias, land pads MS10 LT1715 adjacent 10nF bypass capacitors 0805 case.
1715
Figure Typical Topside Metal Multilayer Layouts
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LT1715 APPLICATIONS INFORMATION
ground trace from runs under device bypass capacitor, shielding inputs from outputs. Note common LT1715 bypass capacitors, which minimizes interference from high frequency energy running around ground plane power distribution traces. supply bypass should include adjacent 10nF ceramic capacitor 2.2F tantalum capacitor farther than away; more capacitance driving more than loads. prevent oscillations, helpful balance impedance inverting noninverting inputs; source impedances should kept low, preferably less. outputs LT1715 capable very high slew rates. prevent overshoot, ringing other problems with transmission line effects, keep output traces shorter than 10cm, sure terminate lines maintain signal integrity. LT1715 drive terminations more, lower characteristic impedance traces used with series termination termination topologies. Channel Interactions LT1715's channels designed entirely independent. However, frequencies approaching exceeding 100MHz, bond wire inductance begins interfere with overlapping switching edges channels. Figure shows channel comparator toggling 100MHz with other channel driven with scope display infinite persistence. Jitter almost nonexistent. Figure displays same channel 100MHz with infinite persistence, other channel ofthe comparator toggling well frequencies swept from 60MHz 160MHz. Jitter will occur rising falling edges align harmonic fundamental frequency high frequency signal. frequencies well beyond 100MHz, toggling channel impaired toggling other. This rather complex interaction supply bypassing bond inductance, cannot entirely prevented. However, good bypassing board layout techniques will effectively minimize Power Supply Sequencing LT1715 designed tolerate power supply sequencing system turn-on power down. previously shown power supply configurations, various supplies activate order without excessive current drain LT1715. always, Absolute Maximum Ratings must exceeded, either power supply terminals input terminals. Power supply sequencing problems occur when input signals powered from supplies that independent LT1715's supplies. problems should occur input signals powered from same supplies LT1715.
1V/DIV
1V/DIV
5ns/DIV
1715
5ns/DIV
1715
Figure Clean 100MHz Toggling
Figure 100MHz Jitter with Both Channels Driven
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LT1715 APPLICATIONS INFORMATION
Unused Comparators comparator unused, output should left floatingto minimize load current. unused inputs tied rails power consumption further minimized inputs connected power rails induce output low. Connecting inverting input noninverting input will likely easiest method. Hysteresis LT1715 includes internal hysteresis, which makes easier than many other similar speed comparators. input-output transfer characteristic illustrated Figure showing definitions VHYST based upon measurable trip points. hysteresis band makes LT1715 well behaved, even with slowly moving inputs. exact amount hysteresis will vary from part part indicated specifications table. hysteresis level will also vary slightly with changes supply voltage common mode voltage. advantage LT1715 significant reduction these effects, which important whenever LT1715 used detect threshold crossing direction only. such case, relevant trip point will that matters, stable offset voltage with unpredictable level hysteresis, seen competing comparators, useless. LT1715 many
VOUT
times better than prior generation comparators these regards. fact, CMRR PSRR tests performed checking changes either trip point limits indicated specifications table. Because offset voltage average trip points, CMRR PSRR offset voltage therefore guaranteed least good those limits. This more stringent test also puts limit common mode power supply dependence hysteresis voltage. Additional hysteresis added externally. railto-rail outputs LT1715 make this more predictable than with output comparators LT1715's small variability (output high voltage). additional hysteresis, positive feedback adding additional external resistor shown Figure Resistor adds portion output threshold resistor string. LT1715 pulls outputs ground within 200mV rails with light loads, within 400mV with heavy loads. load most circuits, good model voltage right side 300mV 300mV, total voltage swing (+VS 300mV) (300mV) 600mV. With this mind, calculation resistor values needed two-step process. First, calculate value based additional hysteresis desired, output voltage swing impedance primary bias string: (R1||R2)(+VS 0.6V)/(additional hysteresis) Additional hysteresis desired overall hysteresis less internal hysteresis.
VHYST VTRIP+ VTRIP-)
VREF VHYST/2 VTRIP-
TRIP TRIP
VIN+ VIN- VTRIP+ INPUT
LT1715
1715 1715
Figure Hysteresis Characteristics
Figure Additional External Hysteresis
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LT1715 APPLICATIONS INFORMATION
VREF VAVERAGE
power translator constructed with resistors shown Figure Figure shows standard Positive (PECL) resistive level translator. This translator cannot used forthe LT1715, with CMOS logic, because depends resistor limit output swing (VOH) all-NPNTTL gate with so-called totem-pole output. LT1715is fabricated complementary bipolar process output stage driver that pulls output nearly supply rail, even when sourcing 10mA. Figure shows three resistor level translator interfacing LT1715 running same supply rail. pull-down output LT1715 needed, pull-down limits seen PECL gate. This needed because inputs have both minimum maximum specification proper operation. Resistor values given both interface types; both cases assumed that LT1715 operates from same supply rail. Figure shows case translating PECL from LT1715 powered supply rail. Again, resistor values given both interface types. This time four resistors needed, although with 10KH/E, needed. that case, circuit resembles standard translator Figure function resistor, much different. loads LT1715 output when high that current flowing through doesn't forward bias LT1715's internal clamp diode. Although this diode handle 20mA without damage, normal operation performance output stage impaired above 100A forward current. prevents this with minimum additional power dissipation. Finally, Figure shows case driving standard, negative-rail, with LT1715. Resistor values given both interface types both LT1715 supply rail. Again, fourth resistor, needed prevent state current from flowing LT1715, turning internal ESD/substrate diodes. Resistor again prevents this with minimum additional power dissipation.
LT1715
1715
Figure Model Additional Hysteresis Calculations
second step recalculate same average threshold before. average threshold before (VREF)(R1)/(R1 R2). calculated based average output voltage (+VS /2)and simplified circuit model Figure assure that comparator's noninverting input average, same before: (VREF VTH)/(VTH (VTH /2)/R3) additional hysteresis 10mV less, uncommon same within resistor tolerances. This method will work additional hysteresis hundred millivolts. Beyond that, impedance enough effect bias string, adjustment also required. Note that currents through R1/R2 bias string should many times input currents LT1715. accuracy, current must least times input current, more higher accuracy. Interfacing LT1715 LT1715's comparators used high speed applications where Emitter-Coupled Logic (ECL) deployed. interface output LT1715 logic inputs, standard TTL/CMOS level translators such 10H124, 10H424 100124 used. secomponents come cost nanoseconds additional delay well supply currents 50mA more, only available quads. faster, simpler lower
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LT1715 APPLICATIONS INFORMATION
course, LT1715 same negative supply, tied well grounded. Then output stage same powerrails circuits Figure used. dividers shown, output impedance about 110. This makes these fast, less than nanosecond,with most layouts. Avoid temptation speed capaci5V LT1715 LEVEL TRANSLATION. TEXT 10KH/E
tors. only they foul operation gate because overshoots, they damage inputs, particularly during power-up separate supply configurations. level translator designs assume gate load. Multiple gates have significant loading, transmission line routing termination issues also make this case difficult.
LSTTL
STANDARD PECL TRANSLATOR
LT1715
10KH/E 100K/E 5.2V 4.5V
LT1715 OUTPUT PECL TRANSLATOR VECL
LT1715
10KH/E 100K/E VECL 5.2V OMIT 4.5V 1500 1000
LT1715 OUTPUT PECL TRANSLATOR
LT1715
FAMILY 10KH/E 100K/E
VECL -5.2V -4.5V
1200 1500
1715
VECL
LT1715 OUTPUT STANDARD TRANSLATOR
Figure
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LT1715 APPLICATIONS INFORMATION
ECL, particularly PECL, valuable technology high speed system design, must used with care. With less than volt swing, noise margins need evaluated carefully. Note that there some degradation noise margin resistor selections shown. With 10KH/E, there temperature compensation logic levels, whereas LT1715 circuits shown give levels that stable with temperature. This will lower noise margin over temperature. some configurations possible compensation with diode transistor junctions series with resistors these networks. more information design, refer ECLiPS data book (DL140), 10KH system design handbook (HB205) PECL design (AN1406), from Motorola, Semiconductor. Circuit Description block diagram LT1715 shown Figure circuit topology consists differential input stage, again stage with hysteresis complementary common-emitter output stage. internal signal paths utilize voltage swings high speed power. input stage topology maximizes input dynamic range available without requiring power, complexity area complete input stages such found rail-to-rail input comparators. With single 2.7V supply, LT1715 still respectable 1.6V input common mode range. differential input voltage rangeis rail-to-rail, without large input currents found incompeting devices. input stage also features phase reversal protection prevent false outputs when inputs driven below -100mV common mode voltage limit. internal hysteresis implemented positive, nonlinear feedback around second gain stage. Until this point, signal path been entirely differential. signal path then split into drive signals upper lower output transistors. output transistors connected common emitter rail-to-rail output operation. Schottky clamps limit output voltages about 300mV from rail, quite 50mV 15mV Linear Technology's rail-to-rail amplifiers other products. output comparator digital, this output stage drive CMOS directly. also drive ECL, described earlier, analog loads.
NONLINEAR STAGE
1715
Figure LT1715 Block Diagram
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LT1715 APPLICATIONS INFORMATION
bias conditions signal swings output stage designed turn their respective output transistors faster than This helps minimize surge current from ground that occurs transitions, minimize frequency-dependent increase power consumption. frequency dependence supply current shown Typical Performance Characteristics. Speed Limits LT1715 comparator intended high speed applications, where important understand limitations. These limitations roughly divided into three categories: input speed limits, output speed limits, internal speed limits. There significant input speed limits except shunt capacitance input nodes. typical input nodes driven, LT1715 will respond. output speed constrained three mechanisms, first which slew currents available from output transistors. maintain power quiescent operation, LT1715 output transistors sized deliver 35mA 60mA typical slew currents. This sufficient drive small capacitive loads logic gate inputs extremely high speeds. slew rate will slow dramatically with heavy capacitive loads. Because propagation delay (tPD) definition ends time output voltage halfway between supplies, fixed slew current makes LT1715 faster than with large capacitive loads sufficient input overdrive. Another manifestation this output speed limit skew, difference between tPD+ tPD-. slew currents LT1715 vary with process variations transistors, rising edges falling edges respectively. typical 0.5ns skew have either polarity, rising edge falling edge faster. Again, skew will increase dramatically with heavy capacitive loads. final limit output speed turn-on turn-off time output devices. Each device substantial base charge that requires nanosecond more active charging discharging bias current Darlington driver stage. When toggle rates high enough that insufficient time allowed this turn-on turn-off, glitches occur leading dropout runt pulses. Furthermore, power consumption increase nonlinearly devices turned before opposing cycle. However, once toggle frequency increases decreases, part will easily leave this undesired operating mode worse wear provided there adequate heat sinking toprevent thermal overload. frequencies well beyond maximum toggle rate, part will toggle with limited output swing well controlled power consumption. internal speed limits manifest themselves dispersion. comparators have some degree dispersion, defined change propagation delay versus input overdrive. propagation delay LT1715 will vary with overdrive, from typical 20mV overdrive overdrive (typical). LT1715's primary source dispersion hysteresis stage. change polarity arrives gain stage, positive feedback hysteresis stage subtracts from overdrive available. Only when enough time elapsed signal propagate forward through gain stage, backwards through hysteresis path forward through gain stage again, will output stage receive same level overdrive that would have received absence hysteresis. LT1715 several hundred picoseconds faster when -5V, relative single supply operation. This internal speed limit; gain stage operates between +VS, faster with higher reverse voltage bias reduced silicon junction capacitances. many applications, shown following examples, there plenty input overdrive. Even applications providing levels overdrive, LT1715 fast enough that absolute dispersion often small enough ignore.
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LT1715 APPLICATIONS INFORMATION
gain hysteresis stage LT1715 simple, short high speed help prevent parasitic oscillations while adding minimum dispersion. This internal "self-latch" usefully exploited many applications because occurs early signal chain, power, fully differential stage. therefore highly immune disturbances from other parts circuit, such output, supply lines. Once high speed signal trips hysteresis, output will respond, after some propagation delay, without regard these external influences that cause trouble nonhysteretic comparators. ±VTRIP Test Circuit input trip points test circuit uses 1kHz triangle wave repeatedly trip comparator being tested. LT1715 output used trigger switched capacitor sampling triangle wave, with sampler each direction. Because triangle wave attenuated 1000:1 LT1715's differential input, sampled voltages therefore 1000 times input trip voltages. hysteresis offset computed from trip points shown.
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LT1715
SIMPLIFIED SCHEMATIC
OUTPUT
1715
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LT1715 PACKAGE DESCRIPTION
Package 10-Lead Plastic MSOP
(Reference 05-08-1661)
0.889 0.127 (.035 .005)
5.23 (.206)
3.20 3.45 (.126 .136) 3.00 0.102 (.118 .004) (NOTE
0.50 0.305 0.038 (.0197) (.0120 .0015) RECOMMENDED SOLDER LAYOUT
0.497 0.076 (.0196 .003)
0.254 (.010) GAUGE PLANE
DETAIL
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE
0.53 0.152 (.021 .006) DETAIL 0.18 (.007) SEATING PLANE 0.17 0.27 (.007 .011) 0.1016 0.0508 (.004 .002)
MSOP (MS) 0307
1.10 (.043)
0.86 (.034)
NOTE: DIMENSIONS MILLIMETER/(INCH) DRAWING SCALE DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.152mm (.006") SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSIONS. INTERLEAD FLASH PROTRUSIONS SHALL EXCEED 0.152mm (.006") SIDE LEAD COPLANARITY (BOTTOM LEADS AFTER FORMING) SHALL 0.102mm (.004")
0.50 (.0197)
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LT1715 TYPICAL APPLICATION
High Performance Sine Wave Square Wave Converter Propagation delay comparators typically specified fora 100mV step with some fraction that overdrive. many signal processing applications, such communications, goal convert sine wave, such carrier, square wave timing clock. desired behavior output timing dependent input timing only. phase shift should occur function input amplitude, which would result conversion. circuit Figure simple LT1715-based sine wave square wave converter. supplies input allow very large swing inputs, while logic supply keeps output swing small minimize crosstalk. Figure shows time delay input amplitude with 10MHz sine wave. LT1715 delay changes just 0.65ns over 26dB amplitude range; 2.33° 10MHz. delay particularly flat yielding excellent rejection from 0dBm 15dBm. transformer used drive input differentially, this exceptionally flat zone spans -5dBm 10dBm, common range signal levels.
SINE WAVE INPUT SQUARE WAVE OUTPUT 632mVP-P 2VP-P 6.32VP-P
1715 F12b
Similar delay performance achieved with input frequencies high 50MHz. There however, some additional encroachment into central flat zone both small amplitude large amplitude variations. With small input signals, hysteresis dispersion make LT1715 like comparator with 12mV hysteresis span. other words, 12mVP-P sine wave 10MHz will barely toggle LT1715, with phase lagor 25ns additional delay. Above 5VP-P 10MHz, LT1715 delay starts decrease internal capacitive feed-forward input stage. Unlike some comparators, LT1715 will falsely anticipate change input polarity, feed-forward enough make transition propagate through LT1715 faster once input polarity does change.
TIME DELAY (ns) 25°C 10MHz
LT1715
INPUT AMPLITUDE (dBm)
Figure 12a. LT1715-Based Sine Wave Square Wave Converter
RELATED PARTS
PART NUMBER LT1016 LT1116 LT1394 LT1711/LT1712 LT1713/LT1714 LT1719 LT1720/LT1721 DESCRIPTION UltraFast Precision Comparator 12ns Single Supply Ground-Sensing Comparator 7ns, UltraFast, Single Supply Comparator 4.5ns, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators 7ns, Power, 3V/5V/±5V Single/Dual Rail-to-Rail Comparators 4.5ns Single Supply 3V/5V Comparator Dual/Quad 4.5ns, Single Supply 3V/5V Comparator COMMENTS Industry Standard 10ns Comparator Single Supply Version LT1016 Single Supply Comparator UltraFast Rail-to-Rail Input Output Comparator Rail-to-Rail Input Output Comparator Single Comparator Similar LT1715 Dual/Quad Comparator Similar LT1715
Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2001
1715 F12a
Figure 12b. Time Delay Sine Wave Input Amplitude
1715fa 1008 PRINTED
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