LTC1669 10-bit voltage output with true buffered rail-to-rail output v

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LTC1669 10-bit voltage output with true buffered rail-to-rail output v

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LTC1669 10-Bit Rail-to-Rail Micropower with Interface DESCRIPTION
LTC1669 10-bit voltage output with true buffered rail-to-rail output voltage capability. operates from single supply with range 2.7V 5.5V. reference selectable between supply voltage internal bandgap reference. Selecting internal bandgap reference will full-scale output voltage range 2.5V. Selecting supply reference sets output voltage range supply voltage. part features simple 2-wire serial interface compatible with that allows communication between many devices. internal data registers double buffered allow simultaneous update several devices once. current power-down mode power conscious systems. Power-on reset ensures output when power initially applied, internal registers cleared. LTC1669 pin-for-pin compatible with LTC1663. SMBus-compatible designs, please refer LTC1663.
Lare registered trademarks Linear Technology Corporation. other trademarks property their respective owners.
Micropower 10-Bit SOT-23 Operating Current: Ultralow Power Shutdown Mode: 2-Wire Serial Interface Compatible with I2CSelectable Internal Reference Ratiometric Maximum Error: 0.75LSB User Selectable Addresses (MSOP Package) Single 2.7V 5.5V Operation Buffered True Rail-to-Rail Voltage Output Power-On Reset 1.5V 2.1V Small 5-Lead TSOT-23 8-Lead MSOP Packages
APPLICATIONS
Digital Calibration Offset/Gain Adjustment Industrial Process Control Automatic Test Equipment Arbitrary Function Generators Battery-Powered Data Conversion Products
BLOCK DIAGRAM
1.25V BANDGAP REFERENCE
Differential Nonlinearity (DNL)
VREF 25°C
REFERENCE SELECT ERROR (LSB) 10-BIT BUFFERED VOUT MSOP PACKAGE ONLY 2-WIRE INTERFACE
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-0.2 -0.4 -0.6 -0.8 -1.0 1024 CODE
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10-BIT LATCH VOUT
COMMAND LATCH
INPUT LATCH
NOTE: NUMBERS PARENTHESES REFER MSOP PACKAGE
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LTC1669 ABSOLUTE MAXIMUM RATINGS
(Note
0.3V 7.5V SDA, -0.3V 7.5V AD0, AD1, (MSOP Only) .-0.3V (VCC 0.3V) VOUT .-0.3V (VCC 0.3V)
Operating Temperature Range LTC1669C 70°C LTC1669I. -40°C 85°C Storage Temperature Range. -65°C 150°C Lead Temperature (Soldering, sec) 300°C
CONFIGURATION
VIEW VOUT VOUT VIEW
PACKAGE 8-LEAD PLASTIC MSOP TJMAX 125°C, 150°C/W
PACKAGE 5-LEAD PLASTIC SOT-23 TJMAX 125°C, 250°C/W
ORDER INFORMATION
LEAD FREE FINISH LTC1669CMS8#PBF LTC1669IMS8#PBF LTC1669-8CMS8#PBF LTC1669-8IMS8#PBF TAPE REEL (MINI) LTC1669CS5#TRMPBF LTC1669-1CS5#TRMPBF TAPE REEL LTC1669CMS8#TRPBF LTC1669IMS8#TRPBF LTC1669-8CMS8#TRPBF LTC1669-8IMS8#TRPBF TAPE REEL LTC1669CS5#TRPBF LTC1669-1CS5#TRPBF PART MARKING LTAHV LTAHX LTAHT LTAHU PART MARKING LTAHW LTAHR PACKAGE DESCRIPTION 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP 8-Lead Plastic MSOP PACKAGE DESCRIPTION 5-Lead Plastic TSOT-23 5-Lead Plastic TSOT-23 TEMPERATURE RANGE 70°C -40°C 85°C 70°C -40°C 85°C TEMPERATURE RANGE 70°C 70°C
pieces. Consult Marketing parts specified with wider operating temperature ranges. Consult Marketing information lead based finish parts. more information lead free part marking, http://www.linear.com/leadfree/ more information tape reel specifications,
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LTC1669 ELECTRICAL CHARACTERISTICS
SYMBOL Resolution Monotonicity VOSTC VOUT VFSTC PSRR Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Error Output Span Full-Scale Voltage Temperature Coefficient Power Supply Rejection Ratio Reference Reference Internal Bandgap Reference Reference Internal Bandgap Reference Reference Internal Bandgap Reference Internal Bandgap, Code 1023
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 2.7V 5.5V, reference, VOUT unloaded, unless otherwise noted.
PARAMETER CONDITIONS ±0.5 ±0.4 ±0.75 UNITS Bits Bits V/°C V/°C V/°C LSB/V
(Note Guaranteed Monotonic (Note (Note Measured Code
Power Supply Positive Supply Voltage Supply Current Supply Current Shutdown Mode Short-Circuit Current (Sourcing) Short-Circuit Current (Sinking) Output Impedance (Note (Note (Note VOUT Shorted GND, Input Code 1023 VOUT Shorted VCC, Input Code Input Code Input Code Shutdown Mode Input Code 1023, Input Code 1023, Rising (Notes Falling (Notes ±0.5LSB (Notes 1LSB Change Around Major Carry
0.75 0.25 0.75
Performance
Output Impedance Performance Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Digital-to-Analog Glitch Impulse Digital Inputs SCL, SDAs VLTH ILEAK High Level Input Voltage Level Input Voltage Logic Threshold Voltage Digital Input Leakage Digital Input Capacitance Digital Output Voltage
5.5V (Note IPULLUP
Digital Output
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LTC1669 ELECTRICAL CHARACTERISTICS
SYMBOL PARAMETER Address Pull-Up Current High Level Input Voltage Level Input Voltage Address Inputs AD0, AD1, (MSOP Only)
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 2.7V 5.5V, reference, VOUT unloaded, unless otherwise noted.
CONDITIONS UNITS
denotes specifications which apply over full operating temperature range, otherwise specifications 25°C. 2.7V 5.5V, reference, VOUT unloaded, unless otherwise noted.
SYMBOL fSCL tBUF tHD, tSU, tSU, tHD, (IN) tHD, (OUT) tSU, tLOW tHIGH PARAMETER Clock Operating Frequency Free Time Between Stop Start Condition Hold Time After (Repeated) Start Condition Repeated Start Condition Setup Time Stop Condition Setup Time Data Hold Time (Input) Data Hold Time (Output) Data Setup Time Clock Period Clock High Period Clock, Data Fall Time Clock, Data Rise Time
TIMING CHARACTERISTICS
Timing Characteristics (Notes
UNITS
1000 3450
Note Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. Exposure Absolute Maximum Rating condition extended periods affect device reliability lifetime. Note Nonlinearity monotonicity defined from code code 1003 (full scale). Applications Information.
Note Digital inputs VCC. Note Load parallel with 100pF Note VREF switched between 0.1VFS 0.9VFS, i.e., codes 922. Note values referenced levels. Note Guaranteed design subject test.
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LTC1669 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
ERROR (LSB) ERROR (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 1024 CODE
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Differential Nonlinearity (DNL)
VREF 25°C OUTPUT VOLTAGE 1024 CODE
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Source Sink Current Capability with
25°C CODE 1023
VREF 25°C
-0.2 -0.4 -0.6 -0.8 -1.0
CODE
OUTPUT CURRENT SOURCE/SINK (mA)
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Large-Signal Step Response
(VOLTS) VOUT (VOLTS) CODE 5s/DIV
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Midscale Glitch
CODE VOUT (LSB) -0.2 -0.4 -0.6 -0.8 -1.0
Load Regulation Output Current
VREF VOUT 2.5V CODE 25°C
CODE 4.7k 100pF 25°C
VOUT 10mV/DIV 4.7k 100pF 25°C 2s/DIV
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SOURCE
SINK
IOUT (mA)
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Load Regulation Output Current
VOUT (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 -1.0 -0.8 -0.6 -0.4 -0.2 IOUT (mA)
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Offset Error Voltage Temperature
2.510 2.508 2.506 OUTPUT VOLTAGE 2.504 2.502 2.500 2.498 2.496 2.494 2.492 OFFSET ERROR VOLTAGE (mV) TEMPERATURE (°C)
Full-Scale Output Voltage Temperature
REFERENCE INTERNAL BANDGAP
VREF VOUT 1.5V CODE 25°C
SOURCE
SINK
2.490 TEMPERATURE (°C)
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1669
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LTC1669 FUNCTIONS
(Pin SOT-23): Serial Data Bidirectional Pin. Data shifted into acknowledged pin. High impedance while data shifted Open-drain N-channel output during acknowledgment. Requires pull-up resistor current source VCC. (Pin Slave Address Select this either modify corresponding LTC1669's slave address. (Pin Slave Address Select this either modify corresponding LTC1669's slave address. (Pin SOT-23): Serial Clock Input Pin. Data shifted into rising edges clock. This high impedance requires pull-up resistor current source VCC. (Pin SOT-23): Power Supply. 2.7V 5.5V. Also used reference voltage input when part programmed reference. (Pin Slave Address Select this either modify corresponding LTC1669's slave address. (Pin SOT-23): System Ground. VOUT (Pin SOT-23): Voltage Output. Buffered rail-to-rail output.
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LTC1669 DEFINITIONS
Differential Nonlinearity (DNL): difference between measured change ideal 1LSB change adjacent codes. error between codes calculated follows: (VOUT LSB)/LSB Where VOUT measured voltage difference between adjacent codes. Digital Feedthrough: glitch that appears analog output caused coupling from digital inputs when they change state. area glitch specified (nV)(sec). Full-Scale Error (FSE): deviation actual full-scale voltage from ideal. includes effects offset gain errors (see Applications Information). Integral Nonlinearity (INL): deviation from straight line passing through endpoints transfer curve (Endpoint INL). Because output cannot below zero, linearity measured between full scale lowest code that guarantees output will greater than zero. error given input code calculated follows: [VOUT (VFS VOS)(code/1023)]/LSB Where VOUT output voltage measured given input code. Least Significant (LSB): ideal voltage difference between successive codes. VREF/1024 Resolution (n): Defines number output states (2n) that divide full-scale range. Resolution does imply linearity. Voltage Offset Error (VOS): Nominally, voltage output when loaded with zeros. single supply have true negative offset, output cannot below zero (see Applications Information). this reason, single supply offset measured lowest code that guarantees output will greater than zero.
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LTC1669
TIMING DIAGRAM
tSU, tLOW tHD,
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tSU, tHD, tBUF tSU,
tHIGH START CONDITION REPEATED START CONDITION STOP CONDITION START CONDITION
tHD,
Typical LTC1669 Input Waveform-Programming Output Full Scale (AD2 High)
ADDRESS
COMMAND
DATA
DATA STOP
START
FULL-SCALE VOLTAGE ZERO-SCALE VOLTAGE
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VOUT
NOTE: DON'T CARE
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LTC1669 APPLICATIONS INFORMATION
Write Word Protocol Used LTC1669
Slave Address Command Byte LSData Byte MSData Byte
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Start Condition, Write Acknowledge, Stop Condition
Serial Digital Interface LTC1669 communicates with host (master) using standard 2-wire interface. Timing Diagram shows timing relationship signals bus. lines, SCL, must high when use. External pull-up resistors current sources, such LTC1694 SMBus/I2C Accelerator, required these lines. LTC1669 receive-only (slave) device. master communicate with LTC1669 using Quick Command, Send Byte Write Word protocols explained later. START STOP Conditions When use, both must high. master signals beginning communication slave device transmitting START condition. START condition generated transitioning from high while high. When master finished communicating with slave, issues STOP condition. STOP condition generated transitioning from high while high. then free communication with another device. Acknowledge Acknowledge signal used handshaking between master slave. Acknowledge (active LOW) generated slave lets master know that latest byte information received. Acknowledge related clock pulse generated master. master releases line (HIGH) during Acknowledge clock pulse. slave-receiver must pull down line during Acknowledge clock pulse that remains stable during HIGH period this clock pulse.
Write Word Protocol master initiates communication with LTC1669 with START condition 7-bit address followed Write (Wr) LTC1669 acknowledges master delivers command byte. LTC1669 acknowledges latches command byte into command byte input register. master then delivers least significant data byte. Again LTC1669 acknowledges data latched into least significant data byte input register. master then delivers most significant data byte. LTC1669 acknowledges once more latches data into most significant data byte input register. Lastly, master terminates communication with STOP condition. reception STOP condition, LTC1669 transfers input register information output registers output updated. Slave Address (MSOP Package Only) LTC1669 respond eight 7-bit addresses. first bits (MSBs) have been factory programmed 0100. first bits LTC1669-8 have been factory programmed 0011. three address bits, AD2, programmed user determine LSBs slave address, shown table below:
LTC1669 0100 0100 0100 0100 0100 0100 0100 0100 0100 LTC-1669-8 0011 0011 0011 0011 0011 0011 0011 0011 0011
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LTC1669 APPLICATIONS INFORMATION
Slave Address (SOT-23 Package) slave address SOT-23 package been factory programmed "0100 000" (LTC1669) "0100 001" (LTC1669-1). another address required, please consult factory. Command Byte
Least Significant Data Byte Allows update Acknowledge SYNC Address only Update Stop condition only (Power-On Default) Puts device power-down mode Puts device standard operating mode (Power-On Default) Selects internal bandgap reference Selects supply reference (Power-On Default) Don't Care
Bandgap (BG) when selects supply voltage voltage reference. full-scale output with this setting equal supply voltage. When "1," internal bandgap reference (1.25V) selected DAC's reference. full-scale output voltage this setting 2.5V. Data Bytes
Most Significant Data Byte
Don't care
Send Byte Protocol stop condition normally initiates update DAC's output latches. Simultaneous update more than other devices achieved reissuing start bit, address, command data bytes before issuing final stop condition (which will update devices). alternate achieve simultaneous LTC1669 updates override stop condition update setting "SY" command byte. Setting this sets device update output latches only reception SYNC address quick command. actual update occurs rising edge during Acknowledge. this way, devices update reception SYNC address quick command instead STOP condition. Shutdown (SD) HIGH will device power state retain data latch information. Shutdown will occur reception STOP condition. This shutdown could synchronized other devices. output impedance will high impedance state 500k GND). Send Byte protocol used LTC1669 actually subset Write Word protocol described previously. Send Byte protocol only used send command byte information LTC1669.
Slave Address Command Byte
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Start Condition, Write Bit, Acknowledge, Stop Condition
Send Byte protocol also used whenever Write Word protocol interrupted reason. Reception START STOP condition after Acknowledge command byte, before Acknowledge last data byte, will cause both data bytes ignored command byte accepted. Reception START STOP condition before Acknowledge command byte will cause interrupted command byte ignored.
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LTC1669 APPLICATIONS INFORMATION
SYNC Address/Quick Command addition slave address, LTC1669 address that shared other devices that they updated synchronously. address called SYNC address uses quick command protocol. SYNC Address 1111
Start 1111 SYNC Address SY/CLR Stop
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Rail-to-Rail Output Considerations rail-to-rail device, output limited voltages within supply range. offset negative, output lowest codes limits shown Figure Similarly, limiting occur near full scale when used reference. VREF full-scale error (FSE) positive, output highest codes limits shown Figure full-scale limiting occur internal reference used. Offset linearity defined tested over region transfer function where output limiting occur. Internal Reference applications where predictable output required that independent supply voltage, LTC1669 user-selectable internal reference. Selecting internal reference will full-scale output voltage 2.5V. This useful applications where supply voltage poorly regulated. Using LT®1460 Micropower Series Reference Power Supply LTC1669 applications where advantages using internal reference required full-scale range needs greater than 2.5V, external series reference used. LT1460 ideal power supply LTC1669 provide 3.3V full-scale output voltage ranges. LT1460 provides accuracy, noise immunity extended supply range LTC1669 when LTC1669 operated ratiometric VCC. Since both parts available SOT-23 packages, board space this application extremely small. Figure
SY/CLR
Update output latches rising edge during Acknowledge SYNC Address Clear internal latches rising edge during Acknowledge SYNC Address
SY/CLR high only meaning when "SY" command byte previously HIGH. otherhand, SY/CLR will always clear part, independent state "SY" command byte. Voltage Output output amplifier contained LTC1669 source sink 5mA. output stage swings within millivolts either supply rail when unloaded equivalent output resistance when driving load rails. output amplifier stable driving capacitive loads 1000pF small resistor placed series with output used achieve stability load capacitance greater than 1000pF example, 0.1F load driven LTC1669 series resistance used. phase margin resulting circuit increases monotonically from this point larger values resistance, capacitance both substituted values given.
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LTC1669 APPLICATIONS INFORMATION
VREF
POSITIVE
OUTPUT VOLTAGE
INPUT CODE VREF
OUTPUT VOLTAGE
INPUT CODE
1023
OUTPUT VOLTAGE
NEGATIVE OFFSET INPUT CODE
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Figure Effects Rail-to-Rail Operation Transfer Curve. Overall Transfer Function Effect Negative Offset Codes Near Zero Scale Effect Positive Full-Scale Error Input Codes Near Full Scale When VREF
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LTC1669 APPLICATIONS INFORMATION
3.9V 0.1F
LT1460S3-3
0.01F
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LTC1669
VOUT
LTC1669 NUMBERS PARENTHESES REFER MSOP PACKAGE
Figure LT1460 Power Supply LTC1669
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LTC1669 PACKAGE DESCRIPTION
Package 5-Lead Plastic TSOT-23
(Reference 05-08-1635)
0.62 0.95 2.90 (NOTE
1.22
3.85 2.62
2.80
1.50 1.75 (NOTE
RECOMMENDED SOLDER LAYOUT CALCULATOR 0.30 0.45 PLCS (NOTE
0.95
0.80 0.90 0.20 DATUM 1.00 0.01 0.10
0.09 0.20 (NOTE NOTE: DIMENSIONS MILLIMETERS DRAWING SCALE DIMENSIONS INCLUSIVE PLATING DIMENSIONS EXCLUSIVE MOLD FLASH METAL BURR MOLD FLASH SHALL EXCEED 0.254mm JEDEC PACKAGE REFERENCE MO-193
0.30 0.50
1.90
TSOT-23 0302
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LTC1669 PACKAGE DESCRIPTION
Package 8-Lead Plastic MSOP
(Reference 05-08-1660)
3.00 0.102 (.118 .004) (NOTE
0.889 0.127 (.035 .005)
0.52 (.0205)
5.23 (.206)
3.20 3.45 (.126 .136)
0.254 (.010) GAUGE PLANE
DETAIL
4.90 0.152 (.193 .006)
3.00 0.102 (.118 .004) (NOTE
0.42 0.038 (.0165 .0015)
0.65 (.0256)
RECOMMENDED SOLDER LAYOUT DETAIL 0.18 (.007) NOTE: DIMENSIONS MILLIMETER/(INCH) DRAWING SCALE DIMENSION DOES INCLUDE MOLD FLASH, PROTRUSIONS GATE BURRS. MOLD FLASH, PROTRUSIONS GATE BURRS SHALL EXCEED 0.152mm (.006") SIDE DIMENSION DOES INCLUDE INTERLEAD FLASH PROTRUSIONS. INTERLEAD FLASH PROTRUSIONS SHALL EXCEED 0.152mm (.006") SIDE LEAD COPLANARITY (BOTTOM LEADS AFTER FORMING) SHALL 0.102mm (.004")
0.53 0.152 (.021 .006)
1.10 (.043)
0.86 (.034)
SEATING PLANE
0.22 0.38 (.009 .015)
0.65 (.0256)
0.127 0.076 (.005 .003)
MSOP (MS8) 0603
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Information furnished Linear Technology Corporation believed accurate reliable. However, responsibility assumed use. Linear Technology Corporation makes representation that interconnection circuits described herein will infringe existing patent rights.
LTC1669 TYPICAL APPLICATION
Program Control Outputs Place Them Where They Needed
2.7V 5.5V SMBus LTC1694 SMBus
0.1F
LTC1669CMS8 VOUT
0.1F CONTROL OUTPUT VOUT0
LTC1669CMS8 VOUT
0.1F CONTROL OUTPUT VOUT1
LTC1669-8CMS8 VOUT
OTHER DEVICES
0.1F CONTROL OUTPUT VOUT15
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RELATED PARTS
PART NUMBER LTC1694 LTC1694-1 DACs LTC1659 LTC1660/LTC1664 LTC1661 LTC1663 ADCs LTC1285/LTC1288 LTC1286/LTC1298 8-Pin Micropower ADCs 8-Pin Micropower ADCs 2-Channel, Autoshutdown 2-Channel, Autoshutdown Single Rail-to-Rail 12-Bit VOUT 8-Lead MSOP Package. 2.7V 5.5V Dual 10-Bit VOUT 8-Lead MSOP Package 10-Bit VOUT SOT-23, SMBUS Interface Power Multiplying VOUT DAC. Output Swings from Input Tied VCC. 3-Wire Interface. 2.7V 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface. Compatible with LTC1669 DESCRIPTION SMBus/I2C Accelerator SMBus/I2C Accelerator COMMENTS Dual SMBus Accelerator with Active Pull-Up Current Sources Dual SMBus Accelerator with Active Pull-Up Current Only
Octal/Quad 10-Bit VOUT DACs 16-Pin Narrow SSOP 2.7V 5.5V Micropower Rail-to-Rail Output. 3-Wire Interface.
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Linear Technology Corporation
(408) 432-1900 FAX: (408) 434-0507
1007 PRINTED
1630 McCarthy Blvd., Milpitas, 95035-7417
www.linear.com
LINEAR TECHNOLOGY CORPORATION 2007

LTC1669 10-bit voltage output with true buffered rail-to-rail output v

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