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TMXF28155 Supermapper155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
documentation package Supermapper system chip consists following documents:
Supermapper Family Register Description Supermapper Family System Design Guide. These documents available password-protected website. Supermapper Product Description (this document) Supermapper Hardware Design Guide. These documents available public website shown below.
contact Agere, please last page this document. access related documents, including documents mentioned above, please following public website, contact your Agere representative:
Telecom
additional Supermappers)
High Speed
TMUX STS3/ STM1/ STS1/ AU-3 SPEMPR
STS1/AU3/AU4
x28/x21 DS1/J1/E1
Interface
155.52 Mbits/s STS-3/STM-1 51.84 Mbits/s STS-1/AU-3
System Interfaces
(x1)
Clock/Sync
x28/x21 VT/TU VTMPR DS1/J1/E1
Multifunction System
Switching Modes:
8PSB x672 DS0/E0 4CHI x672 DS0/E0
Transport Modes:
155.52 Mbits/s STS-3/STM-1 51.84 Mbits/s STS-1/AU-3
TPG/TPM
Interface Control
4DS1/J1/E1 (X29) x28/x21 prot. 4DS2 prot.
x28/x21 DS1/E1
NSMI Modes:
4DS1/J1/E1 x28/x21 4DS3 4STS1
XClks
TOAC
LOPOH
POAC
10/17/03 Supermapper
Figure 1-1. Supermapper Functional Block Diagram
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
SONET/SDH compliant condition alarm reporting. Built-in diagnostic loopback modes. line frame sync output.
Features
Versatile supports SONET/SDH 155/51 Mbits/s interface solutions DS3, DS2, DS1/J1/E1, DS0/J0/E0 applications. Terminates DS1/J1 framed unframed signals. popular framing formats supported. Mates with other Supermappers provide full 84/84/63 DS1/J1/E1 termination. Loopbacks, manual error insertion, internal pattern generator/monitor, internal cross connects simplify debugging diagnostics. Supports full processing line/section/path overhead with inhibitable automatic generation AIS, RDI, REI, times filtering critical overhead. Low-power supply. industrial temperature range. 456-pin ball grid array (PBGA) package. Complies with appropriate Telcordia, ITU, ANSI, ETSI, Japanese standards.
Telecom Interface
Telecom interface mate devices including clock, data[8], parity, SPE-, J0-, J1-, timing indicator. Line path signals passed mate devices.
Synchronous Payload Envelop Mapper (SPEMPR) Features (x1)
mapper accepts/delivers TUG-2 data from/to mapper. TUG-2 data mapped/demapped either to/from AU-3/STS-1 signal North American digital systems to/from TUG-3 signal based systems. mapper accepts/delivers channelized data from/to MUX/deMUX. data mapped/ demapped either to/from AU-3/STS-1 signal North American digital systems to/from TUG-3 signal ITU-based systems. mapper accepts/delivers channelized unchannelized signals 44.736 Mbits/s rate from external I/O. signals mapped/demapped same signal described above. mapper loopback circuit placed demap remap signal. particularly useful cases where signal, mapped AU-3/STS-1 signal, requires remapping TUG-3 signal vice versa. mapper supports path overhead access channel (POAC). Seven path overhead bytes (J1, inserted/dropped through this channel. This channel works master, meaning provides clock both transmit receive directions data inserted transmit side dropped receive side. Path overhead byte (BIP error) generation/detection programmable BIP-8 error rate insertion. Capable detecting/inserting AIS, RDI, REI. Monitoring provided TUG-3/VC-3 path overhead bytes. tandem connection support provided.
TMUX Features (x1)
Multiplexes/demultiplexes three STS-1 signals to/from SONET STS-3 signal. Multiplexes/demultiplexes three VC-3 signals to/from STM-1 (AU-4) signal TUG-3 construction. Multiplexes/demultiplexes three VC-3 signals to/from STM-1 (3xAU-3) signal. Provides STS-3/STM-1/STS-1 pointer interpretation. Detects AIS-P LOP. Provides STS-3/STM-1/STS-1 selectable scrambler/ descrambler functions. Built-in clock data recovery circuit (can bypassed external clock recovery provided). Supports overhead processing transport path overhead bytes. Optional insertion extraction overhead bytes serial transport overhead access channel (TOAC). Configurable dedicated channels. Software controlled linear protection dedicated interface protection card.
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Virtual Tributary Mapper (VTMPR) Features (x1)
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Maps DS1/E1/J1 into VT/TU structures: into VT1.5/TU-11/TU-12. into VT1.5/TU-11/TU-12. into VT2/TU-12. Supports asynchronous, byte-synchronous, bit-synchronous mappings. Supports automatic generation microprocessor overwrite RDI-V enhanced RDI-V, RFI-V. Supports applications tributary loopback tributary pointer processing. Supports trace identifier monitoring/insertion. Automatic receive monitor functions include VT/TU RDI-V, REI-V, BIP-2 errors, AIS-V, LOP-V.
Pseudorandom sequence (PRBS, also known pseudonoise sequences) based maximallength feedback shift register sequences; codes selectable from following options: QRSS, PRBS15, PRBS20, PRBS23, ALT_01, ALL_ONES, USER pattern bits, repeating). test patterns transmitted either unframed payload framed signal defined ITU-T Recommendation O.150 (DS2 unframed only). Single errors framing errors injected into test pattern under register control. sink receiving channel replaced testpattern monitor, which detect count errors misconfigurations, and/or detect idle conditions AIS. Data link (DS1-ESF multiframe fields readable/writable.
Features (x1)
DS1/J1/E1 Framing Features (FRM) Features (1x28/21)
Configurable multiplexer/demultiplexer signals, signals, signals to/from signal. Operates either C-bit parity mode. Provisionable time-slot selection DS1, insertion drop. Automatic receive monitor that detects loss signal (LOS), bipolar violation (BPV), excessive zeros (EXZ), frame (OOF), severely errored frame (SEF), AIS, RAI, FEAC codes, P-bit parity errors, C-bit parity errors, FEBE indications. forced loopback DS2, DS1, forced loopback loopback request generation. multiplexer capable generating alarm indication signal (AIS), remote alarm indicator (RAI), idle, far-end alarm control (FEAC), far-end block error (FEBE) signals.
x28/x21 DS1/J1/E1 channels. Line coding: B8ZS, HDB3, ZCS, AMI. framing modes: ESF, SLC-96, DDS, only). framing: G.704 basic CRC-4 multiframe consistent with G.706. framing modes: JESF (Japan). Supports unframed transparent transmission format. signaling modes: transparent; register system access 2-state, 4-state, 16-state; 2-state, 4-state, 16-state; SLC-96 2-state, 4-state, 16state; J-ESF handling groups maintenance signaling; 2-state, 4-state, 16-state. signaling modes: transparent; register system access entire TS16 multiframe structure G.732. Signaling debounce change state interrupt. V5.2 processing. Alarm reporting performance monitoring AT&T, ANSI, ITU-T, ETSI standards.
Test Pattern Generator/Monitor (TPG/TPM) Features (x1)
Configurable test-pattern generator: DS1, DS2, formats.
Agere Systems Inc.
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Sources broadcast, looped back, routed from test-pattern generator monitor. channel routed through jitter attenuator. configured interconnect with SPE, external interconnect with SPE.
Facility data link features: HDLC transparent access either frame formats. Register/stack access SLC-96 transmit receive data. Extended superframe (ESF): automatic transmission performance report messages (PRM). Automatic transmission ANSIT1.403 performance report messages. Automatic detection transmission ANSI T1.403 bit-oriented codes. Register/stack access CEPT bits transmit receive data. HDLC features: HDLC transparent mode. Programmable logical channel assignment: time slot, ISDN D-channel, also inserts/extracts C-channels V5.1, V5.2 interfaces. logical channels both transmit receive direction (any framing format). Maximum channel data rate: kbits/s. Minimum channel data rate: kbits/s (DS1-FDL bit). 128-byte FIFO channel both transmit receive direction. loopback supported. System interfaces: Concentration highway interface: Single clock frame sync signals; programmable clock rates 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz; programmable data rates 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s; programmable clock edges bit/byte offsets. Parallel system interface 19.44 data signaling: single clock frame sync signals. Time-division multiplex data rate serial interface 1.544 2.048 MHz. Twenty-eight receive data, clock, frame sync signals. Twenty-eight transmit data signals with global clock frame sync. Network serial multiplexed interface minimal count serial interface 51.84 optimized data applications.
DS1/E1 Digital Jitter Attenuation (DJA) Features (1x28/21)
PLL-free receive operation using built-in digital jitter attenuator VT/VC mode mode). bandwidth, damping factor, sampling rates configurable meet jitter MTIE requirements.
2.10 Microprocessor Unit (MPU) Features (x1)
20-bit address/16-bit data microprocessor interface. Synchronous MHz)/asynchronous microprocessor interface modes. Microprocessor data parity monitoring. Summary interrupts from major functional blocks/ maskable. Separate device interrupt outputs automatic protection switch Supermapper global interrupt. Global configuration network performance monitoring counters operation. Global software resets. Global enabling powering down major functional blocks. Registers provisionable clear read clear write. Compatible with most industry-standard processors.
2.11 JTAG DS2/DS1/E1 Cross Connect (XC) Features (x1)
IEEE 1149.1 JTAG boundary scan.
Highly configurable interconnect signals to/from framer, external pins, M13, mappers. Supports seven signals to/from external pins M13.
Agere Systems Inc.
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Overview
SONET/SDH Supermapper device integrates SONET/SDH section, line, path, tributary termination functions with multiplex functions primary rate framing function. interfaces OC-3/STM-1 optical signal allow modular growth terminal add/drop applications. SONET/SDH Supermapper device provides versatile interface STS-3/STM-1 STS-1 termination applications point-to-point scenarios ring applications. Used tributary shelf applications, this chip enables DS1, interfaces, provide best possible mapping into SONET/SDH. Because flexibility mappings, software upgrades from mapped connections VT/TU mapped connections possible. device also accommodate DS3/DS2 applications. single Supermapper capable processing aggregate bandwidth STS-1 DS3. connecting other mate devices telecom interface, device capable terminating full STS-3/STM-1 signal.
Agere Systems Inc.
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Block Description
TMUX Block
TMUX block implements SONET/SDH-compliant, byteinterleave multiplexing/demultiplexing, overhead insertion termination, multiplex section protection (MSP) switch capability, serializer/deserializer 155.52 Mbits/s 51.84 Mbits/s traffic. TMUX provides three modes operation follows:
mapping mode, mapper functional block accepts/delivers structured data from/to functional block clear channel signal 44.736 Mbits/s rate maps/demaps asynchronously to/from STS-1 TU-3. mapper generates fixed pointer value 522. B3ZS encoding/decoding included. Additionally, this block built-in auxiliary channel known path overhead access channel (POAC). This channel mainly used insert/drop path overhead bytes into/from STS-1 VC-3.
STS-3 mode STM-1 mode STS-1 mode
VT/TU Mapper (VTMPR) Block
STS-3 mode, TMUX implements functions necessary multiplex demultiplex three STS-1 signals to/from SONET STS-3 signal. STM-1 (VC-4) mode, TMUX provides functionality multiplex demultiplex three TUG-3 signals to/from STM-1 (VC-4) signal. device also build/extract three AU-3 signals to/from STM-1 (VC-3) stream. STS-1 mode, TMUX implements functions necessary interface single STS-1 to/from external serial link. high-speed side line side, block configured either 155.52 Mbits/s (STS-3/STM-1) 51.84 Mbits/s (STS-1) serial data interface. lowspeed side tributary side, TMUX provides bytewide that communicate with three STS-1/TUG-3/ AU-3 devices 19.44 rate. single STS-1 mode used, rate will 6.48 MHz. TMUX therefore provides complete multiplexing/demultiplexing to/from STS-3/STM-1 signal DS1, signals. STS-1 mode, TMUX provides multiplexing/ demultiplexing DS1, streams. STS-3/STM-1 mode, TMUX from only Supermapper, operating master mode required. TMUX other slave Supermapper devices powered down reduce power consumption. This architecture allows flexible modular growth equipment capacity both 51.84 Mbits/s 155.52 Mbits/s links.
VT/TU mapper maps valid combination signals into stream rate 51.84 Mbits/s (STS-1 AU-3). mapping methods (VT1.5, VT2, group ANSI nomenclature; TU-11, TU-12, TUG-2 nomenclature) analogous. VT/VC mapper supports following mappings: asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. asynchronous, byte-, bit-synchronous signals mapped into seven groups TUG-2s. Maps into VT1.5/TU-11/TU-12, into VT1.5/TU11/TU-12, into VT2/TU-12.
applications supported tributary loopback, tributary pointer processing, low-order path overhead access channel. VT/TU mapper supports automatic generation microprocessor overwrite 1-bit RDI-V, enhanced RDI-V, 1-bit RFI-V, automatic downstream generation, five trace identifier modes. 4.3.1 Receive Direction receive direction, mapper terminates data stream receives from mapper. demultiplexes AU-3/TUG-3 into VTs/TUs checks multiframe alignment. pointer interpreter VTs/TUs detects LOP, AIS, NDF, NORM, INC, each channel. low-order path termination includes byte termination, path trace, Z6/N2 tandem connection, Z7/K4 enhanced RDI-V low-order monitoring, payload termination asynchronous, byte- bit-synchronous signals. byte termination performs BIP-2 check (bit block mode), REI-V count, RFI-V, RDI-V detection, signal label monitoring, automatic AIS-V insertion (which inhibited). Agere Systems Inc.
SPE/AU-3 Mapper (SPEMPR) Block
mapper highly configurable; operate different modes: AU-3/STS-1 mapper TUG-3 mapper. both modes, map/demap data from/to either mapper block, MUX/deMUX block, clear channel, loopback channel. mapper supports numerous automatic monitoring functions. provide interrupts control system, operated polled mode.
monitor supports following modes:
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Multiplexer (M13) Blocks
block highly configurable multiplexer/demultiplexer operation. operate C-bit parity mode, mixed M13/M23 mode. C-bit parity mode, provides far-end alarm control (FEAC) code generator receiver, HDLC transmitter receiver, automatic far-end block error (FEBE) generator. Each internal MUX/deMUX MUX/deMUX configured operate independent MUXes/deMUXes. inputs groups four) input signals groups three) feed into individual MUXes, while take signals from outputs MUXes, direct inputs, loopback deMUXed DS2s. supports numerous automatic monitoring functions. provide interrupt control system, operate polled mode. 4.4.1 Receive Direction receive monitored loss clock loss signal (LOS) according T1.231. B3ZS decoder accepts either unipolar clock data, unipolar clock positive negative data. also checks bipolar coding violations. transmit looped back into receive side after B3ZS decoding. demultiplexer checks valid framing finding frame alignment pattern (F-bits) then locating multiframe alignment signal (M-bits). During each M-frame, data stream checked presence (1010) idle (1100) pattern. Within demultiplexer, there four performance monitoring counters M-bit, P-bit, E-bit parity, FEBE errors. Each demultiplexer contains performance monitoring counters. 4.4.2 Transmit Direction incoming DS1/E1 clocks first checked activity loss-of-clock (LOC). data signals retimed checked activity. DS1/E1 loopback selectors allow individual DS1/E1 signals within received looped back toward DS2/DS3 input. This loopback performed automatically, user force loopback. four three signals each into single-bit, 16-word-deep FIFOs synchronize signals frame generation clock. fill level each FIFO determines need stuffing DS1/E1 input. handle DS1/E1 signals with nominal frequency offsets five unit intervals peak jitter.
Cyclic check SONET framing mode framing mode Single byte check
byte-synchronous mode, receive demapper generates frame synchronization signal indicate frame time slot Additionally, provides framer access received signaling bits. Output mapper DS1/J1/E1 signal with gapped clock. overwritten with automatically upon microprocessor request. 4.3.2 Transmit Direction transmit direction, mapper gets clock, data, frame synchronization signal from cross connect. input retimed checked digital loss clock (LOC), condition, zeros density. byte-synchronous mode, input signal additionally checked loss-of-frame (LOF). transmit elastic store synchronizes incoming DS1/J1/ signals local STS-1 clock. asynchronous bit-synchronous mode, works bit-oriented (64-bit) FIFO, byte-synchronous mode, byte-wide (8-byte) buffer using byte marker (8-bit). Overflow underflow conditions monitored reported. asynchronous bit-synchronous mode, fixed pointer (VT1.5/TU-11) (VT2/TU-12) generated payload mapped into container using positive/null/negative stuffing mechanism S-bits). bit-synchronous mode, stuffing mechanism disabled. byte-synchronous mode, dynamic pointer value generated using marker, implementing NORM, NDF, INC, pointers. generation comprises byte with BIP-2 generation, AIS-V, UNEQ-V insertion, automatic REI-V, RFI-V, RDI-V, enhanced RDI-V generation (Telcordia, ITU-T), path trace insertion microprocessor, Z6/N2 byte insertion, Z7/K4 byte insertion microprocessor low-order path overhead (LOPOH) access channel. data stream synchronized received internal synchronization pulse multiplexed form STS-1/AU-3 signal, which then output mapper. When operating byte-synchronous mode, phase signaling bits from framer stored inserted into mapped frame.
Agere Systems Inc.
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
DS2/DS3 transmit clock used derive clock source frame generation. multiplexer generates transmit frame, fills information bits frame with data from seven select blocks. transmit output either form unipolar clock data, unipolar clock positive negative data. data B3ZS-encoded looped back from receive input. 4.6.1 Line Decoder/Encoder
line decoder/encoder supports either single-rail dualrail transmission. dual-rail mode, line codes supported follows:
Alternate mark inversion (AMI). binary zero code suppression (B8ZS). ITU-CEPT high-density bipolar order three (HDB3).
Test Pattern Generator/Monitor (TPG/TPM) Block
test pattern generator/test pattern monitor functional block (TPG/TPM) consists configurable test pattern generators monitors local self-test, maintenance, troubleshooting operations. feeds more DS1/E1/DS2 test signals (via data, clock, (DS1/E1 only) signal paths) cross connect, which redistribute broadcast these signals valid channel framer, external I/O, MUX, mapper functional blocks. also generate unframed test signal. channel arriving cross connect routed test monitor. test monitor automatically detect/ count errors pseudorandom test sequence, loss frame (DS1/E1 only), loss synchronization situation. provide interrupt control system, operated polled mode. Simultaneous testing DS1, DS2, signals supported with channel each. Supported test patterns quasirandom signal (QRSS), pseudorandom sequence (PRBS23, PRBS20, PRBS15), alternating zeros/ones, all-ones pattern, 16-bit user-provisionable pattern. test patterns transmitted either unframed payload framed signal, defined ITU-T Recommendation O.150. patterns unframed only. Under register control, single bit-errors injected into test pattern.
single-rail mode, line interface unit (LIU) decodes/ encodes data. dual-rail mode, loss-of-signal monitored. case coded mark inversion (CMI) coding (Japanese standard JJ-20.11), decodes data, listing both coding rule violations (CRVs) line coding violations bipolar violations. mode, framer single-rail mode.) 4.6.2 Receive Frame Aligner/Transmit Frame Formatter receive frame aligner transmit frame formatter support following frame formats:
superframe. superframe: framing only. J-D4 superframe with Japanese remote alarm. DDS. SLC-96. ESF. J-ESF standard with different CRC-6 algorithm). Nonalign (193 bits-clear channel). CEPT basic frame (ITU G.706). CEPT CRC-4 multiframe with timer (ITU G.706). CEPT CRC-4 multiframe with timer (automatic CRC-4/non-CRC-4 equipment interworking; G.706 Annex Nonalign (256 bits-clear channel). 2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11).
Framer Block
DS1/J1/E1 framer block's internal components listed below. particular application will determine which components within framer used.
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4.6.3 Receive Performance Monitor receive performance monitor detects following alarms:
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
Associated signaling mode (ASM). Signaling inhibit. Signaling stomp.
Loss receive clock. Loss-of-signal. Loss-of-frame. Alarm indication signal (AIS). Remote frame alarms. Remote multiframe alarms.
Voice data channels programmable robbed-bit signaling modes. entire payload forced into data-only signaling channels) mode (i.e., transparent mode, achieved programming control bit). Signaling access occurs through on-chip signaling registers system interface. Data associated signaling information accessed through system either CEPT-E1 modes. 4.6.5 Facility Data Link (FDL) Processor receive facility data link processor monitors bit-oriented data-link messages defined ANSI T1.403. transmit facility data link unit overrides FDL-FIFO transmission bit-oriented data-link messages defined ANSI T1.403-1995. processor extracts stores data link bits from three different frame types follows:
These alarms detected defined appropriate ANSI, AT&T, ITU, ETSI standards. Performance monitoring, specified AT&T, ANSI, ITU, provided through counters monitoring following:
Bipolar violations. Frame errors. errors. Errored events. Errored seconds. Bursty errored seconds. Severely errored seconds.
D-bits delineator bits from SLC-96 multisuperframe. Data link bits from frames (bit time slot 24). multiframes Sa[4:8] bits from time slot CEPT basic CRC-4 multiframes.
In-band loopback activation deactivation codes transmitted line payload facility data link. In-band loopback activation deactivation codes payload facility data link detected. 4.6.4 Signaling Processor signaling processor supports following modes:
respective bits always extracted from framealigned frames stored stack. processor controls notification stack updates through interrupt (maskable) registers. transmit functional block performs transmission D-bits into SLC-96 Superframes, Sa-bits CEPT frames, D-bits frames.
Superframe (D4, SLC-96): 2-state, 4-state, 16-state. SPE: 2-state, 4-state, 16-state. Extended superframe: 2-state, 4-state, 16-state. CEPT: common channel signaling (CCS) (TS-16). Transparent (pass through) signaling. J-ESF handling groups. Signaling debounce. Signaling freeze. Signaling interrupt upon change state.
SLC-96 frames, delineator bits always sourced from this functional block when block enabled insertion. frames, data link bits always sourced from this functional block when this block enabled insertion. This functional block also provides capability transmit BOMs (bit-oriented messages) data link channel links. CEPT frames, bits sourced from either stack within this functional block from system interface. data link functional block only responds with valid data when selected source control bits.
Signaling features supported channel follows:
Agere Systems Inc.
TMXF28155 Supermapper 155/51 Mbits/s SONET/SDH xDS3/DS2/DS1/E1/DS0
4.6.6 HDLC Unit HDLC processor formats HDLC packets insertion into programmable channels. channel number bits from time slot. maximum number channels maximum channel rate kbits/s. minimum channel rate kbits/s. Each channel allocated bytes storage. HDLC processing data facility data link (PRMs, Sabits, otherwise) implemented assigning position logical HDLC channel.
DS1/E1 Digital Jitter Attenuation (DJA) Block
block contains copies digital jitter attenuator. These digital jitter attenuator functional blocks operate different modes, jitter attenuator. both modes, digital jitter attenuator provisioned operate second-order always, switch first-order during pointer adjustments help meet MTIE requirements. block will also insert proper signal primary block control input active. bandwidth over wide range accommodate number different system constraints.
DS2/DS1/E1 Cross Connect (XC) Block
cross connect (XC) functional block highly configurable crosspoint switch DS2/DS1/E1 signal connections Supermapper. cross connect allows flexible configuration Supermapper's internal blocks support variety applications. internal 28-channel framer, mapper, mapper, M13, digital jitter attenuator, test-pattern generator/monitor blocks external device pins interconnected with independent, nonblocking signal routing cross connect block. Multicast broadcast operation (one port many) also supported.
Agere Systems Inc.
Telcordia Telcordia Technologies trademarks Telcordia Technologies, Inc. ANSI registered trademark American National Standards Institute, Inc. AT&T registered trademark AT&T U.S.A. other countries. registered trademark Lucent Technologies Inc.
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere registered trademark Agere Systems Inc. Agere Systems, Agere logo, Ultramapper, Hypermapper, Supermapper trademarks Agere Systems Inc.
Copyright 2003 Agere Systems Inc. Rights Reserved
October 2003 DS03-213MPIC

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