Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226 DATA SHEET PRODUC
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EtherMapTM-3 Device
Ethernet into STS-3/STM-1 SONET/SDH Mapper TXC-04226 DATA SHEET PRODUCT PREVIEW FEATURES
Supports eight 10/100 Mbit/s Ethernet ports, each using SMII interface Supports single 1000 Mbit/s Ethernet port, using parallel GMII interface (lead shared with SMII interfaces) Supports Ethernet Management interface control configuration externally connected PHYs. Supports IEEE 802.3 flow control management statistics (RMON) 10/100/1000 Mbit/s Ethernet ports Supports Ethernet frame encapsulation/decapsulation protocols: ITU-T G.7041, Generic Framing Procedure (GFP) ITU-T X.86/X.85, Link Access Procedure (LAPS) ITU-T Q.922, Link Access Procedure Frame Mode (LAPF) Performs mapping/demapping encapsulated Ethernet frames into/from order (VT1.5 SPE/VC-12) high order (STS-1 SPE/VC-3) virtual concatenated payloads Performs mapping/demapping encapsulated Ethernet frames into/from single contiguous concatenated (STS-3c-SPE/VC-4) payload Supports optional LCAS processing (per ITU-T G.7042) high order virtual concatenated payloads Glueless memory interface external 64/128Mb SDRAMs Supports 84/63 VT/TU Order Pointer processing Supports High Order processing STS-1/VC-3/STS-3c/VC-4 Byte-wide parallel Drop Telecom interfaces Supports per-port Ethernet side SONET/SDH system side loopback system level diagnostics 16-bit wide microprocessor interface, selectable between Motorola Intel Boundary scan (IEEE 1149.1 standard) 3.3V +1.8V power supplies, tolerant leads 400-lead plastic ball grid array package
EtherMapTM-3 highly integrated device that provides mapping 10/100/1000 Mbit/s Ethernet into SONET/SDH STS-3/STM-1 Transport payloads. device supports connection eight 10/100 Mbit/s Ethernet ports, using SMII interfaces, single 1000 Mbit/s Ethernet port, using GMII interface. transmit direction, each port, received Ethernet frames encapsulated using either LAPS LAPF protocol. encapsulated Ethernet frames then mapped into configurable number virtual concatenated high order payloads, such VT1.5 SPE/VC-12/STS-1 SPE/VC-3, contiguous concatenated payload such STS-3c SPE/VC-4. both high order payloads, required SONET/SDH bytes encapsulated Ethernet payload generated output using byte-wide parallel interface TranSwitch Telecom format. EtherMap-3 supports Drop timing modes. receive direction, each Ethernet port, configurable number high order payloads terminated, with complete byte processing virtual contiguous concatenated payloads. Using external SDRAM, alignment differential delay compensation received high order virtual concatenated payloads performed. Ethernet frames then decapsulated using LAPS LAPF protocol forwarded each Ethernet port. both high order virtual concatenated payloads, optional standards based LCAS processing provided allow hitless dynamic bandwidth adjustments. addition support full-rate Ethernet transfer, over-subscribed Ethernet transfers also supported using back pressure mechanisms order prevents frame loss.
APPLICATIONS
SONET/SDH add/drop terminal multiplexers Multi-service access platforms Next generation Ethernet switches DSLAMS Integrated access devices
TELECOM SIDE
+1.8V +3.3V
HO/LO RING Ports
HO/LO Ports
Controls
CLOCKS (SONET/SDH Ref, System, Sec.)
ETHERNET LINE SIDE
DROP
EtherMap-3
Ethernet into STS-3/STM-1 SONET/SDH Mapper
10/100 Mbit/s SMII (Port 1000 Mbit/s GMII
TXC-04226
10/100 Mbit/s SMII (Port
Microprocessor SDRAM Interface Interface
Boundary Scan
Ethernet Management Interface
U.S. and/or foreign patents issued pending Copyright 2002 TranSwitch Corporation EtherMap trademark TranSwitch Corporation TranSwitch registered trademarks TranSwitch Corporation
Document Number: PRODUCT PREVIEW TXC-04226-MB 2002
TranSwitch Corporation Enterprise Drive Shelton, Connecticut 06484 Tel: 203-929-8810 Fax: 203-926-9453 www.transwitch.com
PRODUCT PREVIEW information documents contain information products their formative design phase development. Features, characteristic data other specifications subject change. Contact TranSwitch Applications Engineering current information this product.
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EtherMap-3 TXC-04226
DATA SHEET
PRODUCT PREVIEW
TABLE CONTENTS
Section Page
List Figures List Tables Features Mappings. Encapsulation Protocols:. Ethernet Ports 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block Sdram Interface. Telecom Timing Ring Port Interface Port Interface Microprocessor Interface. Jtag Interface Special Features Block Diagram Data Processing/flow Ethernet Ports 10/100/1000 Mbit/s Ethernet Media Access Controller (MAC) Block Mapper Block Demapper Block. Microprocessor Interface. Sdram Memory Interface. Parallel Telecom Interface High Order (Path Overhead Byte) Port Interface High Order Ring Port Interface. Alarms Performance Monitoring Block. Jtag Interface Application Example Lead Diagram Lead Descriptions. Absolute Maximum Ratings Environmental Limitations (Referenced VSS) Thermal Characteristics. Power Requirements Input, Output Input/Output Parameters Timing Characteristics Operation. SONET/SDH Processing Transmit High Order Path Termination (VC-3/VC-4/STS-1/STS-3c Generator) Receive High Order Path Termination (VC-3/VC-4/STS-1/STS-3c Monitor). High Order Port Interface High Order Ring Port Interface. TU-3 Pointer Generation TU-3 Pointer Tracking VC-3/STS-1/TUG-3 TimeSlot Interchange TU/VT Pointer Tracking. TU/VT Pointer Generation. Order TimeSlot InterchangE Transmit Order Path Termination (Low Order Generator) Receive Order Path Termination (Low Order Monitor) Order Port Interface Order Ring Port Interface Virtual Concatenation LCAS. Order Virtual Concatenation Without LCAS. High Order Virtual Concatenation Without LCAS.
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EtherMap-3 TXC-04226
High Order Virtual Concatenation with LCAS Ethernet Line Interfaces Ethernet Blocks Encapsulation Decapsulation. LAPS GFP. LAPF SDRAM Controller. SDRAM Memory Interface Telecom Operation General Drop Interface Drop Parity Selection Interface Timing Modes Parity Selection Indicator Invert Delay Force VC-3 VC-4 High Impedance Force TUG-3 High Impedance Force TUG-2 High Impedance Force TU-11/TU-12 High Impedance. Boundary Scan Memory Information Package Information Ordering Information Related Products. Standards Documentation Sources Documentation Update Registration Form*.
*Please note that TranSwitch provides documentation products. Current editions many documents available from Products page TranSwitch site www.transwitch.com. Customers using TranSwitch Product, planning should register with TranSwitch Marketing Department receive relevant updated supplemental documentation issued. They should also contact Applications Engineering Department ensure that they provided with latest available information about product, especially before undertaking development designs incorporating product.
PRODUCT PREVIEW TXC-04226-MB 2002
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LIST FIGURES
Figure
Page
Functional Block Diagram EtherMap-3 Order Virtual Concatenation Structure SONET High Order Virtual Concatenation Structure SONET. Typical Application using EtherMap-3 PHAST-3N Devices. EtherMap-3 TXC-04226 Lead Diagram Drop Timing (Only APAR, output). Drop Timing (all signals outputs) Timing (Timing signals inputs) Timing (Timing signals outputs). GMII Ethernet Interface GMII Ethernet Interface TX/RX SMII Ethernet InterfacE. Ethernet Management Interface SDRAM Interface Single Word Read SDRAM Interface Single Word Write. VC-3 Byte Interface. VC-3 Byte Interface Order Byte Interface Order Byte Interface VC-3 Ring Port Interface. VC-3 Ring Port Interface Order Ring Port Interface Order Ring Port Interface Asynchronous Microprocessor Interface: Intel 8xC196KD-type Write Cycle Timing Asynchronous Microprocessor Interface: Intel 8xC196KD-type Read Cycle Timing. Asynchronous Microprocessor Interface: Motorola 68360-type Write Cycle Timing Asynchronous Microprocessor Interface: Motorola 68360-type Read Cycle Timing Synchronous Microprocessor Interface: Motorola MPC860-type Read Cycle Timing Synchronous Microprocessor Interface: Motorola MPC860-type Write Cycle Timing Boundary Scan Timing Functional Block Diagram Mapper/Demapper. Functional Model Mapper/Demapper Mapper/Demapper bypass modes. VT1.5-Xv-SPE Structure. VC-11-Xv Structure. multiplexing structure supported EtherMap-3. multiplexing structure supported EtherMap-3. multiplexing structure supported EtherMap-3. SONET multiplexing structure supported EtherMap-3 STS-1-Xv-SPE structure. VC-3-Xv structure multiplexing structure supported EtherMap-3 SONET multiplexing structure supported EtherMap-3 EtherMap-3 Switch interconnection using GMII interface Format LAPS frame with Ethernet frame payload Format frame with Ethernet frame payload Format LAPF Bridged frame with Ethernet frame payload Boundary Scan Schematic EtherMap-3 TXC-04226 Package Diagram
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EtherMap-3 TXC-04226
Table
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MAC_Receive_Counters. MAC_Transmit_Counters. MAC_Configuration #1_Registers. MAC_Configuration #2_Registers. MAC_IPG IFG_Registers MAC_Half-Duplex_Registers MAC_Maximum Frame_Registers MAC_Reserved_Registers. MAC_Reserved_Registers. MAC_Test_Registers MAC_MII Mgmt Configuration_Registers. MAC_MII Mgmt Command_Registers. MAC_MII Mgmt Address_Registers MAC_MII Mgmt Control_Registers. MAC_MII Mgmt Status_Registers MAC_MII Mgmt Indicators_Registers. MAC_Interface Control_Registers. MAC_Interface Status_Registers MAC_Station Address_Registers. MAC_Station Address_Registers. record ENC0_GeneralConfig type T_ENC0_GeneralConfig (access record ENC0_LapsConfig type T_ENC0_LapsConfig (access record ENC0_LapfConfig type T_ENC0_LapfConfig (access RW). record ENC0_LapfStatus type T_ENC0_LapfStatus (access record ENC0_GfpConfig type T_ENC0_GfpConfig (access record ENC0_PerfCounters type T_ENC0_PerfCounters (access PASS) record ENC0_Alarm type T_ENC0_Alarm (access record ENC0_Alarm_Mask type T_ENC0_Alarm_Mask (access record ENC0_Interrupt type T_ENC0_Interrupt (access record ENC0_L1Alarm type T_ENC0_L1Alarm (access record ENC0_CountAlarm type T_ENC0_CountAlarm (access record ENC1_GeneralConfig type T_ENC1_GeneralConfig (access record ENC1_LapsConfig type T_ENC1_LapsConfig (access record ENC1_LapfConfig type T_ENC1_LapfConfig (access RW). record ENC1_LapfStatus type T_ENC1_LapfStatus (access record ENC1_GfpConfig type T_ENC1_GfpConfig (access record ENC1_PerfCounters type T_ENC1_PerfCounters (access PASS) record ENC1_Alarm type T_ENC1_Alarm (access record ENC1_Alarm_Mask type T_ENC1_Alarm_Mask (access record ENC1_Interrupt type T_ENC1_Interrupt (access record ENC1_L1Alarm type T_ENC1_L1Alarm (access record ENC1_CountAlarm type T_ENC1_CountAlarm (access record ENC2_GeneralConfig type T_ENC2_GeneralConfig (access record ENC2_LapsConfig type T_ENC2_LapsConfig (access record ENC2_LapfConfig type T_ENC2_LapfConfig (access RW). record ENC2_LapfStatus type T_ENC2_LapfStatus (access record ENC2_GfpConfig type T_ENC2_GfpConfig (access record ENC2_PerfCounters type T_ENC2_PerfCounters (access PASS) record ENC2_Alarm type T_ENC2_Alarm (access record ENC2_Alarm_Mask type T_ENC2_Alarm_Mask (access
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record ENC2_Interrupt type T_ENC2_Interrupt (access RO). record ENC2_L1Alarm type T_ENC2_L1Alarm (access record ENC2_CountAlarm type T_ENC2_CountAlarm (access record ENC3_GeneralConfig type T_ENC3_GeneralConfig (access RW). record ENC3_LapsConfig type T_ENC3_LapsConfig (access RW). record ENC3_LapfConfig type T_ENC3_LapfConfig (access record ENC3_LapfStatus type T_ENC3_LapfStatus (access RW). record ENC3_GfpConfig type T_ENC3_GfpConfig (access RW). record ENC3_PerfCounters type T_ENC3_PerfCounters (access PASS) record ENC3_Alarm type T_ENC3_Alarm (access RO). record ENC3_Alarm_Mask type T_ENC3_Alarm_Mask (access record ENC3_Interrupt type T_ENC3_Interrupt (access RO). record ENC3_L1Alarm type T_ENC3_L1Alarm (access record ENC3_CountAlarm type T_ENC3_CountAlarm (access record ENC4_GeneralConfig type T_ENC4_GeneralConfig (access RW). record ENC4_LapsConfig type T_ENC4_LapsConfig (access RW). record ENC4_LapfConfig type T_ENC4_LapfConfig (access record ENC4_LapfStatus type T_ENC4_LapfStatus (access RW). record ENC4_GfpConfig type T_ENC4_GfpConfig (access RW). record ENC4_PerfCounters type T_ENC4_PerfCounters (access PASS) record ENC4_Alarm type T_ENC4_Alarm (access RO). record ENC4_Alarm_Mask type T_ENC4_Alarm_Mask (access record ENC4_Interrupt type T_ENC4_Interrupt (access RO). record ENC4_L1Alarm type T_ENC4_L1Alarm (access record ENC4_CountAlarm type T_ENC4_CountAlarm (access record ENC5_GeneralConfig type T_ENC5_GeneralConfig (access RW). record ENC5_LapsConfig type T_ENC5_LapsConfig (access RW). record ENC5_LapfConfig type T_ENC5_LapfConfig (access record ENC5_LapfStatus type T_ENC5_LapfStatus (access RW). record ENC5_GfpConfig type T_ENC5_GfpConfig (access RW). record ENC5_PerfCounters type T_ENC5_PerfCounters (access PASS) record ENC5_Alarm type T_ENC5_Alarm (access RO). record ENC5_Alarm_Mask type T_ENC5_Alarm_Mask (access record ENC5_Interrupt type T_ENC5_Interrupt (access RO). record ENC5_L1Alarm type T_ENC5_L1Alarm (access record ENC5_CountAlarm type T_ENC5_CountAlarm (access record ENC6_GeneralConfig type T_ENC6_GeneralConfig (access RW). record ENC6_LapsConfig type T_ENC6_LapsConfig (access RW). record ENC6_LapfConfig type T_ENC6_LapfConfig (access record ENC6_LapfStatus type T_ENC6_LapfStatus (access RW). record ENC6_GfpConfig type T_ENC6_GfpConfig (access RW). record ENC6_PerfCounters type T_ENC6_PerfCounters (access PASS) record ENC6_Alarm type T_ENC6_Alarm (access RO). record ENC6_Alarm_Mask type T_ENC6_Alarm_Mask (access record ENC6_Interrupt type T_ENC6_Interrupt (access RO). record ENC6_L1Alarm type T_ENC6_L1Alarm (access record ENC6_CountAlarm type T_ENC6_CountAlarm (access record ENC7_GeneralConfig type T_ENC7_GeneralConfig (access RW). record ENC7_LapsConfig type T_ENC7_LapsConfig (access RW). record ENC7_LapfConfig type T_ENC7_LapfConfig (access record ENC7_LapfStatus type T_ENC7_LapfStatus (access RW). record ENC7_GfpConfig type T_ENC7_GfpConfig (access RW). record ENC7_PerfCounters type T_ENC7_PerfCounters (access PASS) record ENC7_Alarm type T_ENC7_Alarm (access RO). record ENC7_Alarm_Mask type T_ENC7_Alarm_Mask (access
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record ENC7_Interrupt type T_ENC7_Interrupt (access record ENC7_L1Alarm type T_ENC7_L1Alarm (access record ENC7_CountAlarm type T_ENC7_CountAlarm (access record EGEN0_GeneralConfig type T_EGEN0_GeneralConfig (access RW). record EGEN0_LapsConfig type T_EGEN0_LapsConfig (access RW). record EGEN0_LapfConfig type T_EGEN0_LapfConfig (access record EGEN0_RlmiBufStatus type T_EGEN0_RlmiBufStatus (access RW). record EGEN0_LinkStatus type T_EGEN0_LinkStatus (access record EGEN0_GfpConfig type T_EGEN0_GfpConfig (access RW). record EGEN0_LmiBuffer type T_EGEN0_LmiBuffer (access record EGEN0_Alarms type T_EGEN0_Alarms (access record EGEN0_Alarms_Masks type T_EGEN0_Alarms_Masks (access record EGEN0_L1Alarms type T_EGEN0_L1Alarms (access RR). record EGEN0_Interrupt type T_EGEN0_Interrupt (access record EGEN0_PerfCounters type T_EGEN0_PerfCounters (access PASS) record EGEN0_CountAlarm type T_EGEN0_CountAlarm (access record EGEN1_GeneralConfig type T_EGEN1_GeneralConfig (access RW). record EGEN1_LapsConfig type T_EGEN1_LapsConfig (access RW). record EGEN1_LapfConfig type T_EGEN1_LapfConfig (access record EGEN1_RlmiBufStatus type T_EGEN1_RlmiBufStatus (access RW). record EGEN1_LinkStatus type T_EGEN1_LinkStatus (access record EGEN1_GfpConfig type T_EGEN1_GfpConfig (access RW). record EGEN1_LmiBuffer type T_EGEN1_LmiBuffer (access record EGEN1_Alarms type T_EGEN1_Alarms (access record EGEN1_Alarms_Masks type T_EGEN1_Alarms_Masks (access record EGEN1_L1Alarms type T_EGEN1_L1Alarms (access RR). record EGEN1_Interrupt type T_EGEN1_Interrupt (access record EGEN1_PerfCounters type T_EGEN1_PerfCounters (access PASS) record EGEN1_CountAlarm type T_EGEN1_CountAlarm (access record EGEN2_GeneralConfig type T_EGEN2_GeneralConfig (access RW). record EGEN2_LapsConfig type T_EGEN2_LapsConfig (access RW). record EGEN2_LapfConfig type T_EGEN2_LapfConfig (access record EGEN2_RlmiBufStatus type T_EGEN2_RlmiBufStatus (access RW). record EGEN2_LinkStatus type T_EGEN2_LinkStatus (access record EGEN2_GfpConfig type T_EGEN2_GfpConfig (access RW). record EGEN2_LmiBuffer type T_EGEN2_LmiBuffer (access record EGEN2_Alarms type T_EGEN2_Alarms (access record EGEN2_Alarms_Masks type T_EGEN2_Alarms_Masks (access record EGEN2_L1Alarms type T_EGEN2_L1Alarms (access RR). record EGEN2_Interrupt type T_EGEN2_Interrupt (access record EGEN2_PerfCounters type T_EGEN2_PerfCounters (access PASS) record EGEN2_CountAlarm type T_EGEN2_CountAlarm (access record EGEN3_GeneralConfig type T_EGEN3_GeneralConfig (access RW). record EGEN3_LapsConfig type T_EGEN3_LapsConfig (access RW). record EGEN3_LapfConfig type T_EGEN3_LapfConfig (access record EGEN3_RlmiBufStatus type T_EGEN3_RlmiBufStatus (access RW). record EGEN3_LinkStatus type T_EGEN3_LinkStatus (access record EGEN3_GfpConfig type T_EGEN3_GfpConfig (access RW). record EGEN3_LmiBuffer type T_EGEN3_LmiBuffer (access record EGEN3_Alarms type T_EGEN3_Alarms (access record EGEN3_Alarms_Masks type T_EGEN3_Alarms_Masks (access record EGEN3_L1Alarms type T_EGEN3_L1Alarms (access RR). record EGEN3_Interrupt type T_EGEN3_Interrupt (access record EGEN3_PerfCounters type T_EGEN3_PerfCounters (access PASS) record EGEN3_CountAlarm type T_EGEN3_CountAlarm (access
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record EGEN4_GeneralConfig type T_EGEN4_GeneralConfig (access record EGEN4_LapsConfig type T_EGEN4_LapsConfig (access record EGEN4_LapfConfig type T_EGEN4_LapfConfig (access record EGEN4_RlmiBufStatus type T_EGEN4_RlmiBufStatus (access record EGEN4_LinkStatus type T_EGEN4_LinkStatus (access RO). record EGEN4_GfpConfig type T_EGEN4_GfpConfig (access record EGEN4_LmiBuffer type T_EGEN4_LmiBuffer (access RO). record EGEN4_Alarms type T_EGEN4_Alarms (access record EGEN4_Alarms_Masks type T_EGEN4_Alarms_Masks (access RW). record EGEN4_L1Alarms type T_EGEN4_L1Alarms (access record EGEN4_Interrupt type T_EGEN4_Interrupt (access RO). record EGEN4_PerfCounters type T_EGEN4_PerfCounters (access PASS). record EGEN4_CountAlarm type T_EGEN4_CountAlarm (access RW). record EGEN5_GeneralConfig type T_EGEN5_GeneralConfig (access record EGEN5_LapsConfig type T_EGEN5_LapsConfig (access record EGEN5_LapfConfig type T_EGEN5_LapfConfig (access record EGEN5_RlmiBufStatus type T_EGEN5_RlmiBufStatus (access record EGEN5_LinkStatus type T_EGEN5_LinkStatus (access RO). record EGEN5_GfpConfig type T_EGEN5_GfpConfig (access record EGEN5_LmiBuffer type T_EGEN5_LmiBuffer (access RO). record EGEN5_Alarms type T_EGEN5_Alarms (access record EGEN5_Alarms_Masks type T_EGEN5_Alarms_Masks (access RW). record EGEN5_L1Alarms type T_EGEN5_L1Alarms (access record EGEN5_Interrupt type T_EGEN5_Interrupt (access RO). record EGEN5_PerfCounters type T_EGEN5_PerfCounters (access PASS). record EGEN5_CountAlarm type T_EGEN5_CountAlarm (access RW). record EGEN6_GeneralConfig type T_EGEN6_GeneralConfig (access record EGEN6_LapsConfig type T_EGEN6_LapsConfig (access record EGEN6_LapfConfig type T_EGEN6_LapfConfig (access record EGEN6_RlmiBufStatus type T_EGEN6_RlmiBufStatus (access record EGEN6_LinkStatus type T_EGEN6_LinkStatus (access RO). record EGEN6_GfpConfig type T_EGEN6_GfpConfig (access record EGEN6_LmiBuffer type T_EGEN6_LmiBuffer (access RO). record EGEN6_Alarms type T_EGEN6_Alarms (access record EGEN6_Alarms_Masks type T_EGEN6_Alarms_Masks (access RW). record EGEN6_L1Alarms type T_EGEN6_L1Alarms (access record EGEN6_Interrupt type T_EGEN6_Interrupt (access RO). record EGEN6_PerfCounters type T_EGEN6_PerfCounters (access PASS). record EGEN6_CountAlarm type T_EGEN6_CountAlarm (access RW). record EGEN7_GeneralConfig type T_EGEN7_GeneralConfig (access record EGEN7_LapsConfig type T_EGEN7_LapsConfig (access record EGEN7_LapfConfig type T_EGEN7_LapfConfig (access record EGEN7_RlmiBufStatus type T_EGEN7_RlmiBufStatus (access record EGEN7_LinkStatus type T_EGEN7_LinkStatus (access RO). record EGEN7_GfpConfig type T_EGEN7_GfpConfig (access record EGEN7_LmiBuffer type T_EGEN7_LmiBuffer (access RO). record EGEN7_Alarms type T_EGEN7_Alarms (access record EGEN7_Alarms_Masks type T_EGEN7_Alarms_Masks (access RW). record EGEN7_L1Alarms type T_EGEN7_L1Alarms (access record EGEN7_Interrupt type T_EGEN7_Interrupt (access RO). record EGEN7_PerfCounters type T_EGEN7_PerfCounters (access PASS). record EGEN7_CountAlarm type T_EGEN7_CountAlarm (access RW). record RAMC_GeneralConfig type T_RAMC_GeneralConfig (access RW). record RAMC_RWTestSDRAM type T_RAMC_RWTestSDRAM (access record RAMC_ROTestSDRAM type T_RAMC_ROTestSDRAM (access
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record VCT_GeneralConfig type T_VCT_GeneralConfig (access RW). record VCT_HoLoAlarm type T_VCT_HoLoAlarm (access RO). record VCT_HoLoAlarm_Mask type T_VCT_HoLoAlarm_Mask (access record VCT_HoLoL1Alarm type T_VCT_HoLoL1Alarm (access record VCT_HoLoInterrupt type T_VCT_HoLoInterrupt (access RO). record VCT_LoTribConfig type T_VCT_LoTribConfig (access record VCT_HoTribConfig type T_VCT_HoTribConfig (access RW). record VCT_LcasGeneralConfig type T_VCT_LcasGeneralConfig (access RW). record VCT_LcasPrd1Config type T_VCT_LcasPrd1Config (access record VCT_LcasPrd2Config type T_VCT_LcasPrd2Config (access record VCT_LcasPrd3Config type T_VCT_LcasPrd3Config (access record VCT_HoLoStatus type T_VCT_HoLoStatus (access record VCR_GeneralConfig type T_VCR_GeneralConfig (access record VCR_Alarm type T_VCR_Alarm (access record VCR_Alarm_Mask type T_VCR_Alarm_Mask (access record VCR_L1Alarm type T_VCR_L1Alarm (access record VCR_Interrupt type T_VCR_Interrupt (access record VCR_LoTribConfig type T_VCR_LoTribConfig (access record VCR_HoTribConfig type T_VCR_HoTribConfig (access record VCR_HoLoStatus type T_VCR_HoLoStatus (access record VCR_HoLoStatusFc type T_VCR_HoLoStatusFc (access record VCR_HoLoStatusSq type T_VCR_HoLoStatusSq (access RO). record ETTC_GeneralConfig type T_ETTC_GeneralConfig (access record CKRST_GeneralConfig type T_CKRST_GeneralConfig (access record CKRST_Control type T_CKRST_Control (access RO). record ESA_GeneralConfig type T_ESA_GeneralConfig (access RW). record ESA_Alarms type T_ESA_Alarms (access record ESA_Alarms_Masks type T_ESA_Alarms_Masks (access record ESA_L1Alarms type T_ESA_L1Alarms (access RR). record ESA_Interrupts type T_ESA_Interrupts (access record SHTC_GeneralConfig type T_SHTC_GeneralConfig (access RW). record SHTC_Alarms type T_SHTC_Alarms (access record SHTC_Alarms_Masks type T_SHTC_Alarms_Masks (access record SHTC_L1Alarms type T_SHTC_L1Alarms (access record SHTC_Interrupts type T_SHTC_Interrupts (access record SHTC_PerfCounters type T_SHTC_PerfCounters (access PASS) record SHTC_CountAlarm type T_SHTC_CountAlarm (access record MAPDEMAP_ExternalConfig type T_MAPDEMAP_ExternalConfig (access record MAPDEMAP_Interrupt type T_MAPDEMAP_Interrupt (access record MAPDEMAP_Mask type T_MAPDEMAP_Mask (access record MAPDEMAP_Init type T_MAPDEMAP_Init (access record MAC_GeneralConfig type T_MAC_GeneralConfig (access record MAC_Alarms type T_MAC_Alarms (access RO). record MAC_Alarms_Masks type T_MAC_Alarms_Masks (access record MAC_L1Alarms type T_MAC_L1Alarms (access record MAC_Interrupts type T_MAC_Interrupts (access RO). record VTMAP_TxTG_GeneralConfig type T_TxTG_General_Config_record (access array VTMAP_TxTG_VC3_Config type T_TxTG_VC3_Config_record (access array VTMAP_TxTG_TUG2_Config type T_TxTG_TUG2_Config_record (access array VTMAP_TxTG_TU1x_Config type T_TxTG_TU1x_Config_record (access record LOMP_GeneralConfig type T_LOMP_GeneralConfig (access RW). array LOMP_TUG2_Config type T_LOMP_TUG2_Config (access array LOMP_VTTU_Config type T_LOMP_VTTU_Config (access RW). array LOMP_MAPRAM type T_LOMP_VTTU_MAPRAM (access PASS).
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array LOMP_V4Byte type T_LOMP_PTR_V4Byte (access array LOMP_POH_RAM type T_LOMP_POH_RAM_record (access PASS) array LOMP_POH_Bypass type T_LOMP_AU3_Config (access RW). array LOMP_PTR_Bypass type T_LOMP_AU3_Config (access array LOMP_XCON_Bypass type T_LOMP_AU3_Config (access record LODMP_GeneralConfig type T_LODMP_GeneralConfig (access array LODMP_ByPass_XConnect_array type T_LODMP_ByPass (access array LODMP_ByPass_PtrProcessor_array type T_LODMP_ByPass (access array LODMP_TUG2_Config type T_LODMP_TUG2_Config (access RW). array LODMP_Ptr_JustCounters_array type T_LODMP_Ptr_JustCounters (access record LODMP_Ptr_IntCtrlConfig type T_LODMP_Ptr_InterruptConfig (access RW). record LODMP_Ptr_Interrupt type T_LODMP_Ptr_Interrupt (access array LODMP_Ptr_DefectCorrelations_UL type T_LODMP_Ptr_Defects (access array LODMP_Ptr_DefectCorrelations_LI type T_LODMP_Ptr_Defects (access PASS) array type T_LODMP_Ptr_Defects_Mask (access array LODMP_Ptr_DefectCorrelations_LP type T_LODMP_Ptr_Defects (access PASS) array LODMP_Ptr_DefectCorrelations_PM type T_LODMP_Ptr_Defects (access array LODMP_Ptr_DefectCorrelations_FM type T_LODMP_Ptr_Defects (access RO). array LODMP_V1RAM_Data_Status type T_LODMP_VRAM_Data (access PASS) array LODMP_V2RAM_Data_Status type T_LODMP_VRAM_Data (access PASS) array LODMP_V4RAM_Data_Status type T_LODMP_VRAM_Data (access PASS). array LODMP_MAPRAM_Data_Config type T_LODMP_MAPRAM_Data (access PASS) array LODMP_ByPass_PohProcessor_array type T_LODMP_ByPass (access array LODMP_POHRAM_ReportReceived type T_LODMP_POHRAM_J2_Byte (access PASS) array LODMP_POHRAM_ReportAccepted type T_LODMP_POHRAM_J2_Byte (access PASS) array LODMP_POHRAM_J2_Expected type T_LODMP_POHRAM_J2_Byte (access PASS) array LODMP_POHRAM_ReceivedData type T_LODMP_POHRAM_ReceivedData (access PASS) array LODMP_POHRAM_AcceptedData type T_LODMP_POHRAM_AcceptedData (access PASS) array LODMP_POHRAM_ExpectedData type T_LODMP_POHRAM_ExpectedData (access PASS) record LODMP_POHMONITOR_CommonConfig type T_LODMP_POHMONITOR_CommonConfig (access RW). array LODMP_POHMONITOR_ChannelConfig type (access PASS) array LODMP_POHMONITOR_ChannelStatus type (access RO). record LODMP_POHMONITOR_ChannelReport type (access array LODMP_POHMONITOR_ChannelDefects type (access PASS) array type (access PASS) array type (access PASS) array type (access PASS)
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EtherMap-3 TXC-04226
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array type (access PASS). array type (access PASS). array type (access PASS) record type (access array type (access array type (access record type (access array type (access PASS) array type (access PASS) array type (access PASS) record LODMP_POHMONITOR_ResetCounters type (access PASS) record LODMP_POHMONITOR_IntCtrlConfig type (access array VTMAP_TxAP_TU_Config type T_VTMAP_TxAP_TU_Config_record (access RW). record VTMAP_TxAP_GeneralConfig type (access record VTMAP_TxAP_IntCtrlConfig type (access record VTMAP_TxAP_EventLatchForInt type (access PASS) record VTMAP_TxAP_EventPerfCount type (access PASS) record type (access PASS) record VTMAP_TxAP_Defects type T_VTMAP_TxAP_Defects_record (access PASS) record VTMAP_TxAP_EventInterruptMask type (access record VTMAP_TxAP_DefectInterruptMask type (access RW). record type (access RO). record type (access RO). record VTMAP_RxAP_Config type T_VTMAP_RxAP_Config_record (access record Interrupts type T_VCI_VTMPR_IC_Interrupt_record (access record Interrupts_Mask type T_VCI_VTMPR_IC_Interrupt_record (access record Interrupts_GroupSummary type (access record S34_RxAP_Config type T_S34_RxAP_Config_Record (access array S34_TxAP_VC_Config type T_S34_TxAP_VC_Config_Record (access RW). record S34_TxAP_GeneralConfig type T_S34_TxAP_GeneralConfig_Record (access RW). record S34_TxAP_IntCtrlConfig type T_S34_TxAP_IntCtrlConfig_record (access record S34_TxAP_EventLatchForInt type (access PASS). record S34_TxAP_EventPerfCount type (access PASS). record S34_TxAP_EventPerfCount_Shadow type
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(access PASS). record S34_TxAP_Defects type T_S34_TxAP_Defects_record (access PASS). record S34_TxAP_EventInterruptMask type (access RW). record S34_TxAP_DefectInterruptMask type (access record S34_TxAP_GeneralEventInterrupt type (access record S34_TxAP_GeneralDefectInterrupt type (access array Reporting_Received_TTI_64_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Reporting_Received_TTI_16_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Reporting_Accepted_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Expected_J1_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Expected_C2_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Received_POH_Bytes type (access PASS) array Accepted_POH_Bytes type (access PASS) record Common_Config type (access array Channel_Config type (access array Channel_Status type (access RO). array Channel_Defects type (access RO). record Channel_Report type (access array type (access array type (access PASS) array type (access array type (access PASS) array Channel_Defect_Correlations_PM type (access array Channel_Defect_Correlations_FM type (access array type (access array type (access RO). array type (access RW). record type (access array Channel_Event_Unlatched type (access RO). array Channel_Event_Latch type (access PASS).
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EtherMap-3 TXC-04226
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array Channel_Event_Mask type (access RW). record Channel_Event_GroupSummary type (access RO). array type (access PASS) array type (access array type (access array type (access RW). record ResetCounters type (access PASS) record IntCtrlConfig type (access array Reporting_Received_TTI_64_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Reporting_Received_TTI_16_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Reporting_Accepted_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS) array Expected_J1_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS). array Expected_C2_Bytes type T_VCI_RX_VCX_POH_Byte_record (access PASS). array Received_POH_Bytes type (access PASS) array Accepted_POH_Bytes type (access PASS). record Common_Config type (access record LoopBack_Config type (access RW). array Channel_Config type (access RW). array Channel_Status type (access array Channel_Defects type (access record Channel_Report type (access RO). array type (access RO). array type (access PASS) array type (access array type (access PASS) array Channel_Defect_Correlations_PM type (access RO). array Channel_Defect_Correlations_FM type (access RO). array type (access RW). array type (access array type (access record type (access array Channel_Event_Unlatched type (access array Channel_Event_Latch type (access PASS)
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array Channel_Event_Mask type (access record Channel_Event_GroupSummary type (access array type (access PASS). array type (access RO). array type (access array type (access record ResetCounters type (access PASS) record IntCtrlConfig type (access RW). record GeneralConfig type T_RX_TU3_Ptr_Config (access array PerChannelConfig type T_RX_TU3_Ptr_ChannelConfig (access RW). array CorrDefects_Unlatched type T_RX_TU3_Ptr_CorrDefects (access RO). array CorrDefects_LatchForInt type T_RX_TU3_Ptr_CorrDefects (access PASS). array CorrDefects_LatchForPMFM type T_RX_TU3_Ptr_CorrDefects (access PASS) array CorrDefects_PM type T_RX_TU3_Ptr_CorrDefects (access RO). array CorrDefects_FM type T_RX_TU3_Ptr_CorrDefects (access array CorrDefects_Mask type T_RX_TU3_Ptr_CorrDefects (access record CorrDefects_Summary type (access RO). record CorrDefects_SummaryMask type (access record CorrDefects_GroupSummary type (access RO). array PerfCounters type T_RX_TU3_Ptr_PerfCounters (access array ShadowPerfCounters type T_RX_TU3_Ptr_PerfCounters (access array Output_0 type T_VCI_L3XCON_Control_record (access array Output_1 type T_VCI_L3XCON_Control_record (access record GeneralConfig type T_TX_TU3_Ptr_Config (access RW). array PerChannelConfig type T_TX_TU3_Ptr_ChannelConfig (access array CorrDefects_Unlatched type T_TX_TU3_Ptr_CorrDefects (access array CorrDefects_LatchForInt type T_TX_TU3_Ptr_CorrDefects (access PASS) array CorrDefects_LatchForPMFM type T_TX_TU3_Ptr_CorrDefects (access PASS) array CorrDefects_PM type T_TX_TU3_Ptr_CorrDefects (access array CorrDefects_FM type T_TX_TU3_Ptr_CorrDefects (access array CorrDefects_Mask type T_TX_TU3_Ptr_CorrDefects (access record CorrDefects_Summary type (access RO). record CorrDefects_SummaryMask type (access RW). record CorrDefects_GroupSummary type (access array PerfCounters type T_TX_TU3_Ptr_PerfCounters (access array ShadowPerfCounters type T_TX_TU3_Ptr_PerfCounters (access record ConcatIndication type T_VCI_ConcatIndication_record (access array POH_Mode type T_VCI_TX_VCX_POH_Mode_record (access array POH_Control type T_VCI_TX_VCX_POH_Control_record (access array uP_J1MessageBytes type T_VCI_J1MessageByte (access PASS) array uP_POHBytes type T_VCIPOH_RAMBytes (access PASS). array PP_POHBytes type T_VCIPOH_PPBytes (access PASS) record ConcatIndication type T_VCI_ConcatIndication_record (access
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EtherMap-3 TXC-04226
array POH_Mode type T_VCI_TX_VCX_POH_Mode_record (access array POH_Control type T_VCI_TX_VCX_POH_Control_record (access array uP_J1MessageBytes type T_VCI_J1MessageByte (access PASS) array uP_POHBytes type T_VCIPOH_RAMBytes (access PASS) array PP_POHBytes type T_VCIPOH_PPBytes (access PASS) record GeneralConfig type T_L3RTM_Config (access RW). array PerChannelConfig type T_L3RTM_ChannelConfig (access array CorrDefects_Unlatched type T_L3RTM_CorrDefects (access array CorrDefects_LatchForInt type T_L3RTM_CorrDefects (access PASS) array CorrDefects_Mask type T_L3RTM_CorrDefects (access record CorrDefects_GroupSummary type (access RO). array Sequencer_Constants_A type T_L3RTM_Sequencer_Constant (access array Sequencer_Constants_B type T_L3RTM_Sequencer_Constant (access array Sequencer_Program type T_L3RTM_Sequencer_Instruction (access PASS) array Sequencer_Data type T_L3RTM_Sequencer_Data (access PASS). record GeneralConfig type T_AURTM_Config (access RW). array PerChannelConfig type T_AURTM_ChannelConfig (access array CorrDefects_Unlatched type T_AURTM_CorrDefects (access array CorrDefects_LatchForInt type T_AURTM_CorrDefects (access PASS) array CorrDefects_Mask type T_AURTM_CorrDefects (access record CorrDefects_GroupSummary type (access RO). array PtrLeakResetValueConfig type T_AURTM_PtrLeakResetValue (access array JustCounters type T_AURTM_JustCount (access record Interrupts type (access record Interrupts_Mask type (access record Interrupts_GroupSummary type (access record GeneralConfig type T_RX_COMBUS_Config (access RW). array PerChannelConfig type T_RX_COMBUS_PerChannel_Config (access RW). array PerChannelStatus type T_RX_COMBUS_PerChannel_Status (access RO). record Global_CorrDefects_Unlatched type T_RX_COMBUS_Global_CorrDefects (access record Global_CorrDefects_LatchForInt type T_RX_COMBUS_Global_CorrDefects (access PASS) record Global_CorrDefects_LatchForPMFM type T_RX_COMBUS_Global_CorrDefects (access PASS) record Global_CorrDefects_PM type T_RX_COMBUS_Global_CorrDefects (access record Global_CorrDefects_FM type T_RX_COMBUS_Global_CorrDefects (access record Global_CorrDefects_Mask type T_RX_COMBUS_Global_CorrDefects (access RW). record Global_CorrDefects_GroupSummary type (access array type (access RO). array type (access PASS) array type (access PASS) array PerChannel_CorrDefects_PM type (access RO). array PerChannel_CorrDefects_FM type (access RO). array PerChannel_CorrDefects_Mask type (access
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record PerChannel_CorrDefects_Summary type (access record type (access record type (access record Global_Config type T_VCI_TXCB_Global_Config_record (access RW). array AUG1_Config type T_VCI_TXCB_AUG1_Config_record (access array AU3_Config type T_VCI_TXCB_AU3_Config_record (access RW). array TUG2_Config type T_VCI_TXCB_TUG2_Config_record (access array TU1X_Config type T_VCI_TXCB_TU1X_Config_record (access record Global_CorrDefects_Unlatched type (access record Global_CorrDefects_LatchForInt type (access PASS) record Global_CorrDefects_Mask type (access RW). record Global_CorrDefects_LatchForPMFM type (access PASS) record Global_CorrDefects_PM type (access record Global_CorrDefects_FM type (access record Global_CorrDefects_GroupSummary type (access array type (access RO). array type (access PASS). array PerChannel_CorrDefects_Mask type (access array type (access PASS). array PerChannel_CorrDefects_PM type (access RO). array PerChannel_CorrDefects_FM type (access RO). record PerChannel_CorrDefects_Summary type (access record type (access record type (access array PerChannel_CorrDefects_Config type (access RW). record Interrupts type (access RO). record Interrupts_Mask type (access record Interrupts_GroupSummary type (access record Interrupts type (access record Interrupts_Mask type (access RW). record Interrupts_GroupSummary type (access RO).
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EtherMap-3 TXC-04226
EtherMap-3 supports following features. Please note that convention used here transmit add) direction from Ethernet line signal (SMII/GMII) SDH/SONET format (Telecom Bus), while receive drop) direction from SDH/SONET format Ethernet line. MAPPINGS EtherMap-3 provides following mapping features: 10/100/1000 Mbit/s Ethernet Traffic mapped into SONET/SDH High Order Order Virtual Concatenation Supported STM-1/AU-4/VC-4/C-4 STS-3/STS-1-SPE/VT-1.5 STS-3/STS-1-SPE STS-3c/STS-3c-SPE VC-12s virtually concatenated Mbit/s traffic ports). VT1.5-SPEs virtually concatenated Mbit/s traffic ports). VC-12s VC-3s virtually concatenated single VC-4 used Mbit/s traffic. VT1.5-SPEs STS-1-SPEs virtually concatenated single STS-3c-SPE used Mbit/s traffic. VC-3s virtually concatenated single VC-4 used 1000 Mbit/s traffic (only port supported). STS-1-SPEs virtually concatenated single STS-3c-SPE used 1000 Mbit/s traffic (only port supported). Mbit/s Mbit/s traffic supported ports).
ENCAPSULATION PROTOCOLS:
selection three encapsulation protocols supported: LAPS (Link Access Procedure SDH) LAPF (Link Access Procedure Framed Mode service) (Generic Framing Procedure) ETHERNET PORTS EtherMap-3 provides following Ethernet Port features:
Eight independent SMII (Serial Medial Independent Interfaces) 10/100 Mbit/s Ethernet Global reference clock Global Synchronization signal Lead selects Switch connection external client Single GMII (Gigabit MII) 1000 Mbit/s Ethernet Lead shared with SMII ports Selection GMII SMII selected through lead Ethernet Management Interface
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FEATURES
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10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK
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Compliant IEEE 802.3, 802.3u, 802.3x, 802.3z, 802.3ac Full Duplex Operation control layer provides support control frames including PAUSE frames Provides support statistics gathering based RMON Group RMON Group RMON Group RMON Group RMON Ethernet MIB.
SDRAM INTERFACE Glueless interface external Mbits, Mbits, Mbits SDRAM devices Data, Address, Chip Select, Clock, Clock Enable, Address Strobe, Column Address Strobe, Write Enable Strobe, Data Mask, Bank Address leads Buffers TX/RX data transfers Clock frequency Programmable Refresh Period Standard SDRAM commands supported: Single/Burst Mode Read Write Operation Active Precharge Auto-Refresh Load Mode Register Programmable Burst Lengths: latency supported Refresh operation transparent user
Drop timing timing derived from Drop timing input signals Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs. C1J1, SPE, Optional clock optionally disabled. timing (two modes) timing derived from timing input signals Drop bus: C1J1, SPE, Optional Data, Clock, Parity signal leads inputs bus: C1J1, Clock, Optional signal leads inputs; Data, Parity Indication signal leads outputs timing derived from external reference clock Drop bus: C1J1, SPE, Optional Data, Clock Parity signal leads inputs bus: C1J1, SPE, Optional Data, Clock, Parity Indication signal leads outputs
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single Telecom interface provided interfacing SONET/SDH line through TranSwitch's TOH/POH Terminator devices such PHAST-3N PHAST12E/POP-12 chip set. Timing adding tributaries derived from either Drop bus. EtherMap-3 provides following timing modes:
TELECOM TIMING
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EtherMap-3 TXC-04226
High Order Ring Port support ring applications Order Ring Port support ring applications PORT INTERFACE High Order Port access bytes Order Port access bytes MICROPROCESSOR INTERFACE 16-bit Address Data Motorola Intel style split supported Interrupt request lead Interrupt mask bits controlling generation hardware interrupt requests
JTAG INTERFACE
IEEE 1149.1 compliant provided board level testing.
SPECIAL FEATURES LCAS support
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RING PORT INTERFACE
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BLOCK DIAGRAM
SONET/SDH TERMINAL SIDE
Telecom DROP Telecom High order port order port High order Ring port order Ring port
High order port order port High order Ring port order Ring port
Mapper Block SONET/SDH (VT1.5/VC-12/VC3/VC-4)
Demapper Block SONET/SDH (VT1.5/VC-12/VC-3 /VC-4)
Transmit SONET/SDH Side LAPS, LAPF Encapsulation Block
Receive SONET/SDH Virtual Concatenation LCAS Processing Block SDRAM Interface Block
Transmit SONET/SDH Virtual Concatenation LCAS Processing Block
Performance Statistics Counters Block
Alarm Processing Block
SDRAM Controller Block
Transmit Ethernet Side LAPS, LAPF Decapsulation Block
Clock Generator Block
10/100/1000 Mbit/s Ethernet Media Access Controllers (MACs); RMON statistics counters; Ethernet Line Side loopbacks 10/100 Mbit/s Ethernet SMII i/fs; 1000 Mbit/s Ethernet GMII (shared)
JTAG Block
ETHERNET LINE SIDE
Figure Functional Block Diagram EtherMap-3
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Clocks
Address
MicroProcessor Interface
Data
Recieve Ethernet Side Frame Format Block
Transmit Ethernet Side Frame Deinterleave Logic Block
Operation Control Block
external SDRAM memory
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EtherMap-3 TXC-04226
general, EtherMap-3 provides functionality mapping demapping ethernet frames from SONET/SDH virtual concatenated tributary structures both LCAS/non-LCAS mode. figures below represent virtual tributary structures that supported EtherMap-3 device. figure below shows VT1.5-Xv structure. VT1.5-Xv provides payload area VT1.5 payload capacity shown. Ethernet payload mapped into individual VT1.5 SPEs which form VT1.5-Xv SPE. Each VT1.5 sent throughout SONET network individually then reassembled destination.
VT1.5-Xv payload capacity
500µs
500µs
VT1.5-Xv
VT1.5
500µs VT1.5
Figure Order Virtual Concatenation Structure SONET
figure below shows STS-1-Xv structure. This structure provides contiguous payload area STS-1 with payload capacity X*48384 kbit/s shown. payload capacity (i.e., encapsulated Ethernet frames) mapped into individual STS-1 SPEs which form STS-1-Xv SPE. Each STS-1 POH. Just like VT1.5-SPE case above, STS-1-SPEs travel through SONET network independently reassembled their destination recover Ethernet data. While these cases only show SONET examples, same principle applies payloads concatenating VC-3s VC-12s.
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DATA PROCESSING/FLOW
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Xx84
STS-1-Xv payload capacity
fixed stuff
125µs
STS-1-Xv
125µs STS-1 125µs STS-1
SONET/SDH side, EtherMap-3 supports STM-1/STS-3/STS-3c like structure using single TranSwitch defined Telecom operating 19.44 MHz. Ethernet Line side, EtherMap-3 supports EIGHT 10/100 Mbit/s ethernet ports 1000 Mbit/s (Gigabit) ethernet port. eight 10/100 Mbit/s ethernet ports each support industry standard SMII interface. single Gigabit ethernet port supports industry standard GMII interface lead shared with SMII interfaces. transmit direction (Ethernet-to-SONET/SDH), EtherMap-3 terminates 10/100/1000 Mbit/s ethernet traffic. ethernet frames from configured port(s) extracted buffered external SDRAM memory. external SDRAM primarily used implementing flow control when ethernet line side bandwidth greater than allocated bandwidth SONET/SDH side (i.e., over-subscription situation). Based system configuration, ethernet frames from each ethernet ports encapsulated using supported link layer protocols: LAPS, LAPF independently. encapsulated ethernet
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Figure High Order Virtual Concatenation Structure SONET
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EtherMap-3 TXC-04226
receive direction (SONET/SDH-to-Ethernet), EtherMap-3 terminates parallel telecom with SONET/SDH containers carrying encapsulated (LAPS, LAPF, GFP) ethernet frames. EtherMap-3 provides complete High order path overhead processing SONET/SDH tributaries. SONET/SDH containers then extracted buffered using external SDRAM memory. This memory primarily used providing alignment differential delay compensation select SONET/SDH containers which form part virtual concatenation group. Once alignment delay compensation been achieved, ethernet frames byte deinterleaved from SONET/SDH containers form their original frame structure port basis. ethernet frames then extracted from encapsulations (LAPS, LAPF) used transmit side passed onto ethernet port transmission external client(s).
ETHERNET PORTS
EtherMap-3 provides eight independent full-duplex Serial Media Independent Interfaces (SMII) support 10/100 Mbit/s Ethernet traffic single GMII port support 1000 Mbit/s Ethernet traffic. Please note, SMII interfaces lead-shared with GMII interface they cannot used together. power-up, package signal lead used allow selection between SMII GMII interfaces. SMII ports allow EtherMap-3 connected external 10/100 Mbit/s Ethernet client (PHY/Switch). configuration choice (PHY/Switch) made power-up/initialization through package signal lead. SMII interface comprised signals port Data Data), global synchronization signal global reference clock. eight Mbit/s Ethernet signals, Mbit/s Ethernet signals, combination both interfaced with these port. Gigabit Media Independent Interface (GMII) used allow mapper connect external 1000 Mbit/s ethernet client (PHY/Switch). EtherMap-3 device supports SINGLE GMII interface. Please note, GMII interface lead-shared with SMII interfaces configuration choice made powerup/initialization. GMII interface comprised independent 8-bit data paths, transmit enable signal, receive data valid signal. Status outputs report when coding violations detected. Network status inputs provided reporting errored frames frame received error. signals synchronous clock. single Ethernet Management interface provided EtherMap-3 connect external ethernet order configure control operation. This interface used both eight 10/100 Mbit/s ports single 1000 Mbit/s port. comprised output Management Data clock signal bidirectional Management Data signal that allows serial data clocked external device. data transfers synchronous clock signal provides support PHYs.
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frames then byte interleaved over preselected SONET/SDH containers transported using virtual concatenation. EtherMap-3 provides complete High order path overhead generation SONET/SDH containers. bandwidth SONET/SDH containers using virtual concatenation, allowed increase decrease hitless fashion through integrated link capacity adjustment scheme (LCAS). SONET/SDH containers carrying ethernet frames then transmitted upstream SONET/SDH Overhead Terminator device such TranSwitch's PHAST-3N, using parallel telecom bus.
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EtherMap-3 TXC-04226
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10/100/1000 MBIT/S ETHERNET MEDIA ACCESS CONTROLLER (MAC) BLOCK
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interface 10/100 Mbit/s ethernet ports 1000 Mbit/s ethernet port supported integrated Ethernet block. This block supports eight 10/100 Mbit/s ports single 1000 Mbit/s port. 10/100/1000 Mbit/s Ethernet block IEEE 802.3, 802.3x, 802.3z 802.3ac compliant supports Full-Duplex (MAC implements IEEE 802.3 Control layer PAUSE operation flow control) mode operation. main features which supported this block follows: Connection external 10/100/1000 Mbit/s Ethernet PHYs 10/100/1000 Mbit/s Ethernet Switch devices either SMII interfaces single GMII interface Line side loopbacks diagnostic capability Verify frame integrity (FCS Length checks) Errored frames configured passed discarded Egress Ethernet frame encapsulation, such padding achieve minimum length generation Programmable Minimum frame size bytes, maximum frame size: 9.6k bytes Transparent IEEE 802.3-1998 VLAN (Virtual LAN) byte Supports IEEE 802.3 mandatory Control Management Registers Over Subscription support Device Configuration Flow Control Option support IEEE 802.3-1998 Flow Control each ethernet port Programmable watermarks FIFO full conditions Automatic generation Pause frames based FIFO fill levels Upper layer device flow control Ethernet ports using side band host signaling cause generation PAUSE frame Provides port side-band PAUSE state indication upstream devices Control disable acting received PAUSE frames, that enables transparent transmission Ethernet PAUSE frame Control Statistics IEEE 802.3z-1998) that includes among others: Detection device, initialization, Device Standard Control Status Registers grouped function: Receive Transmit Control Registers, Receive Transmit Status Registers, RMON registers (for Network Management), Flow Control Registers, Management Registers, Ethernet Interface Control Status Registers Performance counters ensure roll-over compliance with standards Provides statistic counters support RMON implementations (minimum support Ethernet Statistics Group, Ethernet History Group, Alarm Group, Event Group). Auto Negotiation: provides Auto Detect adjusts 10/100 Mbit/s Ethernet interface.
MAPPER BLOCK This block provides mapping multiplexing order High order tributaries (carrying Ethernet framed data) into STS-3/STS-3c/STM-1 structures transmitted side telecom bus. vast assemblage SONET/SDH rates format mappings supported indicated below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s)
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EtherMap-3 TXC-04226
STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s order VC/VT tributaries formatted into STS-3 STM-1 structure. pointer value carried bytes transmitted with fixed value VT1.5 TU-12. microprocessor writes signal label, value message 16-byte message. device provides either single-bit extended using bytes. Local alarms, microprocessor, generate remote payload, server, connectivity defect indications. Remote Error Indication (REI) inserted from BIP-2 errors detected receive side, BIP-2 parity generated byte. Control bits provided generating unequipped status, generating TU/VT AIS, inserting BIP-2 errors byte. Control bits also provided that enable microprocessor insert overhead byte test values, including byte. list VT/TU Overhead byte generation functions listed below:
Byte Byte Microprocessor written message Forced ZERO option (Z7) Byte Signal label insertion Insertion (from receive side) Insertion Host Processor control BIP-2 calculation Insertion Insertion (from receive side) Enable bits alarms Host Processor control Single extended (bit byte bits byte) Generate least superframes Mask Alarm Bits from sending Microprocessor control Control spare bits byte bits single Bits through (Z7) byte (Z6) Byte: Tandem connection support Unequipped Channel Generation Supervisory Equipped Generation TU/VT Generation order VT/TU Pointer generation Fixed TU-12 Asynchronous Format Fixed VT1.5 Asynchronous Format High order VC-3/STS-1 Overhead byte generation Insertion bytes into STS-1s VC-3s that being mapped with asynchronous line signals byte 16-byte message insertion ETSI Applications
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64-byte message insertion ANSI Applications byte ability generate sequence lower order tributaries should provided when higher order virtual concatenation mode byte Signal Label Insertion byte BIP-8 Calculation Insertion Mask byte Single-bit (ETSI) extended generation (ANSI) (path FEBE) insertion insertion byte: tandem connection support Transmit Path Generation STS-1/AU-3/TUG-3 Overrides Unequipped generation Transmit Unequipped Generation STS-1/AU-3/TUG-3 Supervisory Unequipped generation option High order TU-3 (VC-3)/STS-1 Pointer generation: Drop timing mode pointer bytes follow drop C1J1 pulses Timing Mode pointer bytes follow C1J1 pulses Timing Mode pointer bytes fixed High order VC-4/STS-3c Overhead byte generation generated PHAST-3N EtherMap-3 High order VC-4/STS-3 Pointer generation pointer generation handled external Overhead Terminator device such PHAST-3N POP-12
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EtherMap-3 TXC-04226
Demapper Block provides demapping demultiplexing order High order tributaries from STS-3/STS-3c/STM-1 structures received Drop side telecom bus. same vast assemblage formats that supported Mapper Block also supported Demapper Block shown below: STS-3 STS-1 SPEs (19.44 Mbit/s) STS-3 STS-1s VT1.5s (19.44 Mbit/s) STS-3c (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TU-3s VC-3s (19.44 Mbit/s) STM-1 AU-4 VC-4 TUG-3s TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-3s VC-3 TUG-2s TU-12s VC-12s (19.44 Mbit/s) STM-1 AU-4 VC-4 (19.44 Mbit/s) SONET Order: supports VT1.5s SONET High Order: supports STS-1 SPEs Order: supports VC-12s High Order: supports VC-3s
EtherMap-3 device provides processing SONET/SDH overhead bytes follows:
Microprocessor Access VT/TU overhead bytes, V1/V2 pointer bytes, byte each channel available microprocessor read cycle, well V5/K4 Bytes. Byte Multiframe Detectors pulse (C1J1V1) reference input Determines Location V1/V2 Pointer Bytes Pointer Tracking V1/V2 Pointer Bytes ETSI/ITU/ANSI State Machine Wrong Size Bits Detection Positive/Negative Justification 8-bit Counters order tributaries, this Demapper block performs pointer processing based location bytes. pointer bytes monitored loss pointer Alarm Indication Signal (AIS). pointer tracking process based ETSI/ITU-T standards, which also meets ANSI requirements. Pointer increments decrements also counted, size bits monitored correct value. This block also processes monitors various alarms found four overhead bytes. These operations including signal label mismatch detection, unequipped status detection, BIP-2 parity error detection bit/block error counter, error counting, detector, single-bit extended Remote Defect Indications (RDI). DeMapper performs 16-byte trail trace comparison channels selected. byte processing supported. Below bullet list High order VC-3/STS-1 Overhead byte processing that performed DeMapper block: received bytes applicable alarm indications made accessible micro-processor. byte trace mismatch detection 16-byte trail trace alignment (MFAS pattern) comparison ETSI Applications 64-byte message alignment (Multiframe Alignment MFAS pattern CR/LF alignment) byte ability detect generate pulse from byte sequence lower order tributaries supported.
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DEMAPPER BLOCK
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byte Signal label mismatch Unequipped detection generation detection byte Single-bit (ETSI) extended detection (ANSI) (path FEBE) calculation with 16-bit Block error count access host processor access byte: supported Demapper provides complete TU-3 pointer tracking state machines including applicable alarm indications. Other higher order processing done external device such PHAST-3N POP-12 device; high order pointer processing must done external device such PHAST-3N POP-12. MICROPROCESSOR INTERFACE
EtherMap-3 supports single telecom architecture which consists single Drop single bus. This same architecture supported other TranSwitch Mappers (e.g., TL3M) SONET/SDH Overhead Terminators (e.g., PHAST-3N, PHAST-12E, POP-12) products. Telecom operates 19.44 rate. telecom interface consists byte wide data, 19.44 (STM-1/STS-3) clock, indication, C1J1(V1) pulses, even parity indication, active indicator. EtherMap-3 supports either Drop timing modes. package lead used provide this selection. This approach prevents contention upon power device reset. Drop timing mode: this mode, timing derived from Drop timing input signals. When Drop timing mode selected, interface output leads byte-wide data, parity indicator, add-to-bus indicator. clock, C1J1V1 signals, which derived from Drop bus, output disabled. selection performed package lead.
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Telecom interface enables EtherMap-3 connect upstream SONET/SDH Line Overhead Terminator such TranSwitch's PHAST-3N OC-3/STM-1 applications. OC-12/STM-4 applications, EtherMap-3 would connect TranSwitch's POP-12/PHAST-12E chip set. Telecom interface collectively comprised single Drop (RX) single (TX) bus.
PARALLEL TELECOM INTERFACE
Virtually concatenated realigned differential delay accommodated SDRAM during reconstruction process received frame.
This interface used allow mapper connect external SDRAM memory device. external SDRAM memory device used buffering ethernet traffic both directions provides "glueless" interface Mbits Mbits external SDRAM memory devices.
SDRAM MEMORY INTERFACE
EtherMap-3's microprocessor interface provides support either standard Motorola, Intel split address/data interface which allows access EtherMap-3's memory register locations through 16-bit data bus. mode operation configurable external package signal leads. interrupt request lead provided allow maskable interrupt bits generate interrupts external microprocessor, thus reducing required bandwidth.
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EtherMap-3 TXC-04226
SONET (STS-3 STS-1-SPEs) mode, high order virtual concatenation supported. SONET (STS-3 STS-1 SPEs VT1.5s) mode, selection order tributaries (VT1.5s) virtual concatenation group restricted same STS-1 SPE. Note that this means that virtual concatenation group this mode limited maximum VT1.5s. (STM-1 AU-3 VC-3 TUG-2s TU-12s VC-12s) mode, selection order tributaries (VC-12s) virtual concatenation group restricted same VC-3. Note that this means that virtual concatenation group this mode limited maximum VC-12s.
timing mode(s): these modes, interface timing independent Drop interface timing above restrictions apply. Using control bit, interface timing signals configured follows:
timing mode
Byte Clock, 19.44 (input); indicator (input); C1J1V1 indicator (input); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, external timing source must ensure three pointers pulses) when operating STS-3/AU-3 mode, synchronized fixed relative each other (i.e., there must pointer movements relative each other). same principle applies when operating STM-1 STS-3c mode; pointer adjustments allowed Bus. TranSwitch PHAST-3N overhead terminator device provide external timing required this mode.
timing mode interface signals follows: Byte Clock, 19.44 (output), derived from input clock lead; indicator (output); C1J1V1 indicator (output); Byte-wide Data (output); Parity indicator (output); Add-to-bus indicator (output);
Note: this timing mode, EtherMap-3 sources timing signals.
Drop parity configured checked over data only over signals, check even parity. Drop clock monitored stuck high stuck conditions. parity generated even generated over data only over signals. indicator goes active indicate when VT/TU/VC/SPE data being added Telecom Bus. When data being added telecom bus, data parity Tristated. HIGH ORDER (PATH OVERHEAD BYTE) PORT INTERFACE byte interface provides alternative access SONET/SDH Order High Order tributary bytes external processing. There interfaces. interface VT1.5/VC-12 second interface STS-1/VC-3 STS-3c/VC-4 POH. Individual byes except J1/J2, C2/V5/K4 Signal label BIP-2/BIP-8 fields inserted into from transmit byte interface. PRODUCT PREVIEW TXC-04226-MB 2002
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Note following restrictions apply when using Drop timing mode:
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bytes provided their respective receive byte interface external processing.
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HIGH ORDER RING PORT INTERFACE Ring port provided transport remote information signal from mate monitor generator. remote information includes REI, various extended indications. There separate Ring ports; VT1.5/VC-12 STS-1/VC-3 STS-3c/VC-4 ALARMS PERFORMANCE MONITORING BLOCK This block maintains updates statistics/performance counters LAPS, LAPF, (for ethernet ports) accessible host. following types statistics/performance counters provided this block:
Mapper/Demapper statistics/performance counters (for tributaries) grouped within part Mapper/Demapper block. JTAG INTERFACE
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This interface provides five signal Boundary Scan capability that conforms IEEE 1149.1 standard. This standard provides external boundary scan functions read write external Input/Output leads from board component test. addition lead provided place output buffers high impedance state systems that support IEEE 1149.1 standard.
Flag error counters Payload size violation counters error counters Control Field mismatch counters Total payload frames/octets transmitted counters Total payload frames/octets received counters
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EtherMap-3 TXC-04226
EtherMap-3 used broad array telecommunications applications, such SONET/SDH add/drop terminal multiplexers Multi-service access platforms Next generation Ethernet switches DSLAMS Integrated access devices
Multi-service Ethernet Aggregation with OC-3/STM-1 Uplink
SDRAM
Drop
10/100 Mbit/s SMII interfaces
10/100 Mbit/s SMII interfaces
OC-3/STM-1
PHAST-3N
EtherMap-3 TXC-04226
Ethernet Switch Ports)
TEMx28
28xDS1 21xE1
EtherMap-3 TXC-04226
Gigabit Ethernet
1000 Mbit/s Line
1000 Mbit/s GMII interface
SDRAM
Figure Typical Application using EtherMap-3 PHAST-3N Devices
Figure shows Multiservice STM-1/STS-3 application using EtherMap-3. TEMx28 device provides access 28xDS1 channels STS-3/STM-1 signal. EtherMap-3 devices used Gigabit Ethernet into STS-1-SPE/VC-3 container 10/100 Mbit/s Ethernet Traffic into VT1.5-SPE/VC-12. demonstrated this application, very small number TranSwitch components enables board developed which used simultaneously support mixture 10/100/1000 Mbit/s Ethernet Traffic T1/E1 Traffic. adding TranSwitch's TL3M device Telecom Bus, also supported.
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APPLICATION EXAMPLE
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LEAD DIAGRAM
BOTTOM VIEW
Notes: This bottom view. leads solder balls. Figure package information. This view rotated relative bottom view Figure Power supply leads shown solid black circles, ground leads cross-hatched circles.
Figure EtherMap-3 TXC-04226 Lead Diagram
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EtherMap-3 TXC-04226
POWER SUPPLY, GROUND, CONNECT LEADS Symbol VDD3 Lead E12, E14, G16, J16, M16, P16, T12, E10, E11, E13, E15, F16, H16, K16, L16, N16, R16, T10, T11, T13, I/O/P* Name/Function VDD3: +3.3 volt power supply, ±5%.
VDD18
VDD18: +1.8 volt power supply, ±5%.
A20, B19, C18, D17, E16, F10, F11, F12, F13, F14, F15, G10, G11, G12, G13, G14, G15, H10, H11, H12, H13, H14, H15, J10, J11, J12, J13, J14, J15, K10, K11, K12, K13, K14, K15, L10, L11, L12, L13, L14, L15, M10, M11, M12, M13, M14, M15, N10, N11, N12, N13, N14, N15, P10, P11, P12, P13, P14, P15, R10, R11, R12, R13, R14, R15, T16, U17, V18, W19,
Ground: (zero) Volts reference.
VDDP18 VDDPA18 VSSP18 VSSPA18
VDDP18: +1.8 volt digital power supply PLL, ±5%. VDDPA18: +1.8 volt analog power supply PLL, ±5%. VSSP18: digital ground PLL. VSSPA18: analog ground PLL.
A10, A11, A19, B11, B15, B18, B20, C14, C17, C19, D13, D16, D18, U18, V17, V19, W10, W14, W18, W20, Y10, Y15,
Connect: These leads connected, even another connect lead, must left floating. Connection lead impair performance cause damage device. leads that currently unused assigned functions future version device, affecting usability applications which have left them floating.
Note: Input; Output; Power; Tristate:
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LEAD DESCRIPTIONS
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DROP SIDE ORDER TRIBUTARY TELECOM INTERFACE
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Symbol DD(7-0)
Lead D10, C10, A12,
I/O/P
Type
Name/Function
LVTTL-5 Drop Data Byte wide data corresponding STM-1/STS-3c/STS-3 signal from Drop bus. first received (dropped) corresponds LVTTL-5 Drop Clock: This clock operates 19.44 STM1/STS-3c/STS-3 operation used clock data other signals into EtherMap-3. Drop byte wide data, parity bit, indication, C1J1(V1) signals clocked into EtherMap-3 core negative transitions this clock. This clock also used timing used derive like named byte wide data, add, TU/VT indications, parity bits. LVTTL-5 Drop Indicator/Multiframe Pulse: active high timing signal that carries frame information. high during bytes STM1/STS-3c/STS-3 payload. Three pulses present STS-3 operation pulse present STM-1/STS-3c operation. pulse optional C1J1 signal. When pulse provided, EtherMap-3 core provides detectors determine location V1/V2 bytes place using pulse. When pulses provided, there will three pulses STS-3 operation pulse STM-1/STS-3c operation. DC1J1V1 signal works conjunction with DSPE signal. pulse identifies location byte STM-1/STS-c/STS-3 signals, when DSPE signal low. pulses identify starting location bytes STM-1/STS-3c/STS-3 signal when DSPE high. pulses occur every four frames (after frame where byte 00H) following pulse(s).
DCLK
DC1J1V1
SIDE ORDER TRIBUTARY TELECOM INTERFACE Symbol AD(7-0) Lead I/O/P O(T) Type Name/Function
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LVCMOS Data Byte Byte wide data that corresponds selected TU/VT/VC.
DPAR
LVTTL-5 Drop Parity Bit: Parity input signal that represents parity calculation each data byte, SPE, C1J1V1 signal from bus. Even parity detected, option checking parity over DD(7-0) only over drop signals provided. parity error reported otherwise effect operation EtherMap-3 core.
DSPE
LVTTL-5 Drop Indicator: signal that active high during each byte STM-1/STS-3c/STS-3 payload bytes, during Transport Overhead byte times.
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EtherMap-3 TXC-04226
ACLK
LVTTL-5/ Clock: This clock operates 19.44 MHz. LVCMOS When timing selected cTBADD=0, clock this input must provided timing. this case AC1J1V1 ASPE clocked negative transitions this clock while AD(7-0), APAR, clocked positive transitions this clock. When timing selected cTBADD=1, clock output this lead. AC1J1V1, ASPE, AD(7-0), APAR, clocked positive transitions this clock. When drop timing selected, option (ABTE low) provided outputting this clock along with other signals, which derived from DCLK, otherwise this lead disabled.
AC1J1V1
LVTTL-5/ Indicator/Multiframe Pulse: When LVCMOS timing selected cTBADD=0, this signal input must provided timing. When timing selected cTBADD=1, this signal output device timing. Composite active high input timing signal that carries STM-1, STS-3c, STS-3 starting frame byte location information. This timing signal functions conjunction with ASPE signal. (J0) pulse identifies location first (J0) byte SONET/SDH frame when ASPE low. pulse identifies starting location byte VC-4 signal STS-3c-SPE three pulses identify starting location three bytes STS-1-SPE signals when ASPE high. more pulses present asynchronous VT/TU mappings determine starting location byte. When drop timing selected, option (ABTE low) provided outputting this signal, otherwise this lead disabled.
ASPE
LVTTL-5/ Indicator: When timing selected LVCMOS cTBADD=0, this signal input must provided timing. When timing selected cTBADD=1, this signal output device timing. This signal active high during each byte STS-3/STM-1/STS-1 payload, during Transport Overhead times. When drop timing selected, option (ABTE low) provided outputting this signal, otherwise this lead disabled. LVCMOS Parity Bit: even parity output signal which calculated over byte wide data. This 3-state lead only active when there data being added bus. control provided that allows even parity calculated. LVCMOS Data Present Indicator: This normally active signal present when output data valid. identifies location TU/VT/VC time slots being added bus. control provided that allows this active high.
APAR
O(T)
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Symbol
Lead
I/O/P
Type
Name/Function
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ETHERNET GMII/ 8xSMII INTERFACES
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control lead GMII/SMII selects when low, group eight SMII Ethernet interfaces, when high, selects single GMII interface. GMII interface described section below, also leads shared with SMII interface leads. Each SMII interface comprises Serial Data Transmit Output (SMII_DOn) Serial Data Receive Input (SMII_DIn); where 1-8. SMII data interface serial streaming standard Mbit/s (Fast Ethernet) interface (Media Independent Interface). Symbol GTX_CLK Lead I/O/P* Type Name/Function
LVCMOS Gigabit Ethernet Transmit Clock Output: GTX_CLK used drive TXD(7-0), TX_EN, TX_ER signals; runs MHz.
TX_CLK TX_EN /(SMII_ GSYNC)
LVTTL-5/ Transmit Enable: This output signal asserted LVCMOS indicate that valid data (octets) being presented Reconciliation Sublayer (RS) should transmitted PHY. When GMII/SMII control lead low, operates 12.5 SMII_GSYNC.
TX_ER
LVCMOS Transmit Error: This output signal asserted indicate that coding violation received input data stream. LVCMOS Transmit Data Out: Data output transmitted group eight data signals, PHY. When GMII/SMII control lead low, these leads operate eight SMII interface Data signals SMII_DOn correspond (i.e., TXD7 corresponds SMIIDO8).
TXD(7-0) U12, Y14, V13, /(SMII_ U13, W15, Y16, DO(8-1) V14,
RXD(7-0) /(SMII_ DI(8-1)
Y11, U10, V10,
LVTTL-5 Receive Data Data received passed group eight data signals DTE. When GMII/SMII control lead low, these leads operate eight SMII interface Data signals SMII_DIn correspond (i.e., RXD7 corresponds SMIIDI8).
RX_DV
LVTTL-5 Receive Data Valid: This signal asserted indicate that valid data (octets) being presented inputs. LVTTL-5 Receive Data Error: This signal asserted indicate frame received error. LVTTL Receive Clock: clock recovered from incoming data stream, passed onto DTE. RX_CLK runs either Mbit/s Ethernet Mbit/s operation. When GMII/SMII control lead low, operates SMII_GCLK.
RX_ER RX_CLK /(SMII_ GCLK)
MDIO
LVTTL-5/ Management Data I/O: Data input/output IEEE LVCMOS 802.3u compliant Management Status interface.
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LVTTL-5 Transmit Clock: Operates 10/100 Ethernet/ Fast Ethernet operation used GMII mode.
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EtherMap-3 TXC-04226
Symbol
Lead
I/O/P*
Type
Name/Function
LVCMOS Management Data Interface Clock: management data (MDIO) clocked into EtherMap-3 rising edge this clock. frequency this clock TBD.
SDRAM INTERFACE following table shows standard wide Data, SDRAM interface. There thirteen address bits, that include bank Selection needed; input mask bits (byte-wise); write enable, RAS/CAS, clock clock enable. Symbol DATA(31-0) Lead I/O/P* I/O(T) Type Name/Function
N18, R20, P18, T20, R18, U20, T18, V20, T17, U19, R17, T19, P17, R19, N17, P19, E17, D19, F17, E19, G17, F19, H17, G19, H18, F20, G18, E20, F18, D20, E18,
LVTTL/ SDRAM Controller External Data I/O: bits wide data LV3CMOS bus; byte wise tristateable. least significant bit.
ADDR(12-0)
K18, K19, N20, J20, K20, L19, L18, L17, M18, M17, P20, N19, M20,
LV3CMOS Address Bus: bits wide. least significant bit.
BA(1-0)
LV3CMOS Bank Select: These signals used select Banks standard SDRAM.
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Symbol
Lead
I/O/P*
Type
Name/Function
LV3CMOS Address Strobe: control external SDRAM. This signal along with define command being given external SDRAM.
Function NOP: operation
ACTIVE: Used activate particular bank. BA(1-0) selects bank, ADDR(12-0) selects row. READ: Used initialize SDRAM burst read. WRITE: Used initialize SDRAM burst write. PRECHARGE: Deactivate open bank banks. AUTO REFRESH: This command issued once every TBD, ensure that SDRAM rows refreshed.
MASK
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LV3CMOS Column Address Strobe: control external SDRAM. signal along with define command being given external SDRAM. Refer table lead description. LV3CMOS Write Enable: control external SDRAM. This signal along with define command being given external SDRAM. Refer table lead description. LV3CMOS Chip Select: control external SDRAM. Used select deselect external SDRAM. LV3CMOS Mask Bits: This control output used mask standard wide SDRAM memory interface. used tristate SDRAM data during READ cycle mask SDRAM data during WRITE cycle.
LOAD MODE REGISTER: This command issued during TBD, configure internal mode register SDRAM.
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EtherMap-3 TXC-04226
Symbol
Lead
I/O/P*
Type
Name/Function
LV3CMOS Interface Clock: control external SDRAM. SDRAM interface signals sampled/output rising edge this clock, which runs MHz. LV3CMOS Interface Clock Enable: control external SDRAM. High intended activate clock, intended deactivate clock.
CLKE
RECEIVE PATH OVERHEAD (VC3POH) BYTE INTERFACE Symbol RPCLK Lead I/O/P Type Name/Function
LVCMOS Receive VC3POH Interface Clock: receive VC3POH address (RPADD), address latch enable (RPALE), data (RPDAT), data latch enable (RPDLE) signals clocked falling edges this clock (2.43 MHz).
RPALE
LVCMOS Receive VC3POH Interface Address Latch Enable: positive (RPCLK) clock cycle-wide pulse that indicates valid address (eight consecutive bits) present RPADD. LVCMOS Receive VC3POH Interface Address: states present these leads during address latch enable time indicate output VC3POH byte SDH/SONET format. Eight consecutive bits make valid address.
RPADD
RPDLE
LVCMOS Receive VC3POH Interface Data Latch Enable: positive (RPCLK) clock cycle-wide pulse that indicates valid data present RPDAT. LVCMOS Receive VC3POH Interface Data: states present these leads over eight consecutive bits, during data latch enable time constitute output byte data selected address.
RPDAT
TRANSMIT PATH OVERHEAD (VC3POH) BYTE INTERFACE Symbol TPCLK Lead I/O/P Type
Name/Function
LVCMOS Transmit VC3POH Interface Clock: transmit address (TPADD), address latch enable (TPALE), data latch enable (RPDLE) signals clocked falling edge TPCLK (2.43 MHz). Data (TPDAT), clocked rising edge this clock. LVCMOS Transmit VC3POH Interface Address Latch Enable: positive (TPCLK) clock cycle-wide pulse that indicates valid address (eight consecutive bits) present TPADD. LVCMOS Transmit VC3POH Interface Address: states present this lead during address latch enable time indicate output byte SDH/SONET format. Eight consecutive bits make valid address.
TPALE
TPADD
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Symbol TPDLE
Lead
I/O/P
Type
Name/Function
LVCMOS Transmit VC3POH Interface Data Latch Enable: positive (TPCLK) clock cycle-wide pulse that indicates valid data present TPDAT. LVTTL-5 Transmit VC3POH Interface Data: states present these leads over eight consecutive bits, during data latch enable time, constitute input byte data selected address.
TPDAT
RECEIVE LOWER ORDER PATH OVERHEAD (LOPOH) BYTE INTERFACE Symbol RPCLK1 Lead I/O/P Type Name/Function
RPALE1
LVCMOS Receive LOPOH Interface Address Latch Enable: positive (RPCLK1) clock cycle-wide pulse that indicates valid address (twelve consecutive bits) present RPADD1.
RPDLE1
LVCMOS Receive LOPOH Interface Data Latch Enable: positive (RPCLK1) clock cycle-wide pulse that indicates valid data present RPDAT1.
Symbol TPCLK1
Lead
I/O/P
Type
TRANSMIT LOWER ORDER PATH OVERHEAD (LOPOH) BYTE INTERFACE Name/Function
TPALE1
TPADD1
TPDLE1
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LVCMOS Transmit LOPOH Interface Clock: transmit LOPOH address (TPADD1), address latch enable (TPALE1), data latch enable (RPDLE1) signals clocked falling edge TPCLK1 (19.44 MHz). Data (TPDAT1), clocked rising edge this clock.
LVCMOS Transmit LOPOH Interface Address Latch Enable: positive (TPCLK1) clock cycle-wide pulse that indicates valid address (twelve consecutive bits) present TPADD1. LVCMOS Transmit LOPOH Interface Address: states present this lead during address latch enable time indicate output LOPOH byte SDH/SONET format. Twelve consecutive bits make valid address. LVCMOS Transmit LOPOH Interface Data Latch Enable: positive (TPCLK1) clock cycle-wide pulse that indicates valid data present TPDAT1.
RPDAT1
LVCMOS Receive LOPOH Interface Data: states present these leads over eight consecutive bits, during data latch enable time constitute output byte data selected address.
RPADD1
LVCMOS Receive LOPOH Interface Address: states present these leads during address latch enable time indicate output LOPOH byte SDH/SONET format. Twelve consecutive bits make valid address.
LVCMOS Receive LOPOH Interface Clock: receive LOPOH address (RPADD1), address latch enable (RPALE1), data (RPDAT1), data latch enable (RPDLE1) signals clocked falling edges this clock (19.44 MHz).
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EtherMap-3 TXC-04226
TPDAT1
LVTTL-5
Transmit LOPOH Interface Data: states present these leads over eight consecutive bits, during data latch enable time, constitute input byte data selected address.
RECEIVE (VC3) HIGH ORDER RING PORT Symbol RAIPF Lead I/O/P Type Name/Function
LVCMOS Receive Ring Port Frame Pulse: active high (RAIPC) clock cycle-wide frame pulse that identifies data stream.
RAIPC
LVCMOS Receive Ring Port Clock: 19.44 output clock used clocking frame pulse (RAIPF) serial data (RAIPD) into mate device. LVCMOS Receive Ring Port Data: serial frame that contains count alarm states TU3_VC3s. multiplexing cannot implemented, individual ring ports required. count should converted four count. byte channel channels) should needed.
RAIPD
TRANSMIT (VC3) High Order RING PORT Symbol TAIPF Lead I/O/P Type
Name/Function
LVTTL-5 Transmit Ring Port Frame Pulse: active high (TAIPC) clock cycle-wide frame pulse that identifies data stream. Connected RAIPF mate device. LVTTL-5 Transmit Ring Port Clock: 19.44 output clock used clocking frame pulse (TAIPF1) serial data (TAIPD1). Connected RAIPC mate device. LVTTL-5 Transmit Ring Port Data: serial frame that contains count, alarm states, Tandem Connection monitoring alarm states individual TU-3 Paths. Connected RAIPD mate device.
TAIPC
TAIPD
RECEIVE ORDER RING PORT Symbol RAIPF1 Lead I/O/P Type Name/Function
LVCMOS Receive Ring Port Frame Pulse: active high (RAIPC) clock cycle-wide frame pulse that identifies data stream. LVCMOS Receive Ring Port Clock: 19.44 output clock used clocking frame pulse (RAIPF1) serial data (RAIPD1) into mate device. LVCMOS Receive Ring Port Data: serial frame that contains count alarm states VT/TUs.
RAIPC1
RAIPD1
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Symbol
Lead
I/O/P
Type
Name/Function
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TRANSMIT ORDER RING PORT
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Symbol TAIPF1
Lead
I/O/P
Type LVTTL-5
Name/Function Transmit Ring Port Frame Pulse: active high (TAIPC) clock cycle-wide frame pulse that identifies data stream. Connected RAIPF1 mate device. Transmit Ring Port Clock: 19.44 output clock used clocking frame pulse (TAIPF1) serial data (TAIPD1). Connected RAIPC1 mate device.
TAIPC1
LVTTL-5
TAIPD1
CONTROLS Symbol GMII/SMII Lead I/O/P Type
HIGHZ
RESET
ABUST
PHY/MAC
PRODUCT PREVIEW TXC-04226-MB 2002
LVTTL-5p Timing Selection: selects timing mode. When timing selected, ACLK, ASPE, AC1J1V1, programmed inputs used source AD(7-0), APAR, signal, they generated internally provided output signals. high selects drop timing. signals direction derived from drop bus. This lead internal pull resistor. LVTTL-5p PHY/MAC Interface Select: selects interconnection type Ethernet side. This lead internal pull-up resistor.
ABTE
LVTTL-5p Timing Signals Enabled: active signal enables ACLK, ASPE, AC1J1V1 outputs when drop timing selected. This lead internal pull resistor. high this lead causes those signals tristated.
LVTTL-5p Reset: active signal used resetting internal cores performance counters within EtherMap-3 preset values. reset must applied only after power applied stable, clocks also stable. reset must present minimum Internal processor also reset, requiring software download afterwards. This lead internal pull-up resistor.
LVTTL-5p High Impedance Select: forces output leads, except boundary scan data output TDO, high impedance state testing purposes. This lead internal pull-up resistor.
LVTTL-5p GMII/SMII Interface Select: selects SMII Ethernet interfaces place single GMII. This lead internal pull-up resistor.
Name/Function
LVTTL-5 Transmit Ring Port Data: serial frame that contains count, alarm states, Tandem Connection monitoring alarm states individual VT/TU Paths. Connected RAIPD1 mate device.
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SYNC_DIR
LVTTL-5p SMII Global SYNC Direction Select: SMII mode when low, SMII_GSYNC signal input. SMII mode when high, SMII_GSYNC signal output. GMII mode, this lead used. This lead internal pull-up resistor.
CLOCK INTERFACES Symbol RTCLK SYSCLK Lead I/O/P Type Name/Function
LVTTL-5d Reference Mapper/Demapper clock: This clock 19.44 clock used Mapper/Demapper blocks.
LVTTL-5 System Reference Clock: input clock. This clock internally doubled used system clock other functions except Mapper/Demapper block.
ONESEC
LVTTL-5d Second Performance Measurement Clock: This clock input used second shadow counters, PM/FM alarm registers. This clock should clock, with high time pulse.
HOST PROCESSOR INTERFACE Symbol MICCLK Lead I/O/P
Type
Name/Function
LVTTL-5 Microprocessor Clock: This clock should come from microprocessor being interfaced this device. Intel Motorola 68360 modes this clock asynchronous microprocessor clock cannot lower frequency microprocessor clock. Motorola MPC860 mode, this clock must synchronous microprocessor clock. LVTTL-5 Address Bus: These leads active high address line inputs that used host processor accessing EtherMap-3 read/write cycle. most significant location's address.
A(15-0)
D(15-0)
I/O(T)
LVTTL-5/ Data Bus: Bidirectional data lines used transferring data LVCMOS between EtherMap-3 host processor. most significant bit.
LVTTL-5p Select: enables data transfers between host processor EtherMap-3 read/write cycle. This lead internal pull-up resistor. PRODUCT PREVIEW TXC-04226-MB 2002
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Symbol
Lead
I/O/P
Type
Name/Function
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Symbol DS/TS
Lead
I/O/P
Type
Name/Function
LVTTL-5 Write Enable (Intel Mode) /Data Strobe (Motorola Mode)/Transfer Start (Motorola Mode): active signal. Intel Mode: Asserted initiate write cycle. Motorola 68360 Mode: This data strobe signal which indicates that host processor ready accept data during read cycle valid data during write cycle. Motorola MPC860 Mode: Indicates start cycle when becomes asserted. LVTTL-5 Read (Intel Mode) Read/Write (Both Motorola Modes): active signal that asserted initiate Read cycle Intel Mode. either Motorola Modes, high this lead initiates Read, initiates Write.
(RD/WR)
READY/ DTACK/TA
INT/IRQ
LVCMOS Interrupt: Intel Mode: high this output lead signals interrupt request host processor. Both Motorola Modes: this output lead signals interrupt request host processor.
MOTO(1-0)
LVTTL-5 Intel/Motorola: Selector lead selecting Intel/Motorola interface:
MOTO1
LVCMOS Ready (Intel Mode)/Data Transfer Acknowledge (Motorola Mode)/Transfer Acknowledge (Motorola Mode): Intel Mode: high indicates that transfer to/from memory accomplished. Motorola 68360 Mode: This lead active low, indicates either that data valid during Read operation, indicates data acceptance during Write operation. Motorola MPC860 Mode: This lead active low, indicates either that data valid during Read operation, indicates data acceptance during Write operation. synchronous MICCLK MICCLK cycle wide.
PRODUCT PREVIEW TXC-04226-MB 2002
MOTO0 Interface
use.
Intel 8xC196KD Processor Interface Motorola 68360 Processor Interface Motorola MPC860 Processor Interface
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EtherMap-3 TXC-04226
Symbol
Lead
I/O/P
Type
Name/Function
LVTTL-5 Test Boundary Scan Clock: This signal used shift data into rising edge falling edge. maximum clock frequency MHz. LVTTL-5p Test Boundary Scan Data Input: Serial test instructions data clocked into this lead rising edge TCK. This lead internal pull-up resistor. LVCMOS Test Boundary Scan Data Output: Serial data test instructions data clocked this lead falling edge TCK. When inactive, this lead goes high impedance state. LVTTL-5p Test Boundary Scan Mode Select: This input lead sampled rising edge TCK. used place Test Access Port controller into various states, defined IEEE 1149.1. internal pull-up holds this lead high during normal operation. This lead internal pull-up resistor.
LVTTL-5p Test Boundary Scan Reset: active signal that asynchronously resets Test Access Port controller. reset must present minimum This lead internal pull-up resistor.
SCAN_EN MBIST_MODE PLL_BYPASS
LVTTL-5d Scan Enable: high enables SCAN mode. This lead internal pull-down resistor. LVTTL-5d Memory Bist: high enables Bist mode. This lead internal pull-down resistor.
LVTTL-5d Bypass: high enables bypassed (see lead PLLOUT below). This lead internal pull-down resistor. LVCMOS Output: output divided after Bypass active (see lead PLL_BYPASS above).
PLLOUT SCAN_MODE
LVTTL-5d Scan Mode: high enables SCAN mode. This lead internal pull-down resistor.
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BOUNDARY SCAN (IEEE STANDARD 1149.1) TEST
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ABSOLUTE MAXIMUM RATINGS ENVIRONMENTAL LIMITATIONS (REFERENCED VSS)
Parameter Supply voltage (3.3V) Core Supply voltage (1.8V) input voltage LVTTL input voltage LVTTL-5 input voltage Storage temperature range Ambient Operating Temperature Moisture Exposure Level Relative Humidity, during assembly Relative Humidity, in-circuit Classification Symbol VDD3 VDD18 -0.5 +150
-0.3 -0.3
Unit
Conditions Note Note Note
Note ft/min linear airflow EIA/JEDEC JESD22-A112-A Note non-condensing Note
Parameter
THERMAL CHARACTERISTICS
Notes: Conditions exceeding values cause permanent failure. Exposure conditions near values extended periods impair device reliability. Pre-assembly storage non-drypack conditions recommended. Please refer instructions "CAUTION" label drypack which devices supplied. Test method MIL-STD-883D, Method 3015.7. Notice Spec 2001V latch Over/undershoot: +/150mA, 125°C Device core only. input signals leads accept signals except SMII/GMII SDRAM memory interface signals which accept only 3.3V signals.
POWER REQUIREMENTS
Parameter VDD3 IDD3 VDD18 IDD18 Power Dissipation,
Note: This approximate value.
Thermal resistance: junction ambient
14.7
3.15 1.62
3.30 1.80
PRODUCT PREVIEW TXC-04226-MB 2002
Unit
oC/W
Level
Test Conditions Test performed with package assembled JEDEC standard Multilayer test board with ft/min linear airflow.
3.45 1.89
Unit
Test Conditions
Note
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EtherMap-3 TXC-04226
INPUT PARAMETERS LVTTL-5 VOLT TOLERANT) Parameter Input leakage current Input capacitance Unit Test Conditions 3.15 VDD3 3.45 3.15 VDD3 3.45 VDD3 3.45,
INPUT PARAMETERS LVTTL-5p VOLT TOLERANT,with PULL-UP RESISTOR)
Parameter
Unit
Test Conditions
3.15 VDD3 3.45
3.15 VDD3 3.45
Input leakage current Input capacitance
VDD3 =3.45; Input volts
INPUT PARAMETERS LVTTL-5d VOLT TOLERANT, with PULL-DOWN RESISTOR) Parameter Input leakage current Input capacitance Unit Test Conditions
3.15 VDD3 3.45 3.15 VDD3 3.45 VDD3 3.45; Input 3.45 volts
INPUT PARAMETERS LVTTL (3.3 VOLT TOLERANT) Parameter Input leakage current Input capacitance
Unit
Test Conditions 3.15 VDD3 3.45 3.15 VDD3 3.45 VDD3 3.45,
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INPUT, OUTPUT INPUT/OUTPUT PARAMETERS
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OUTPUT PARAMETERS LVCMOS Parameter Output capacitance tRISE tFALL Leakage tristate 1.78 1.65 3.38 3.22 Unit CLOAD CLOAD input VDD3 3.15; -1.0 VDD3 3.15; Test Conditions
OUTPUT PARAMETERS LVCMOS Parameter tRISE tFALL Leakage tristate Output capacitance 2.97 2.95
tRISE tFALL Leakage tristate
Output capacitance
Parameter
OUTPUT PARAMETERS LV3CMOS pullups more than 3.3V with these outputs) Unit 3.39 3.36 CLOAD CLOAD input VDD3 3.15; -1.0 VDD3 3.15; Test Conditions
1.80 1.78
PRODUCT PREVIEW TXC-04226-MB 2002
Unit 5.54 5.56
Test Conditions
VDD3 3.15; -1.0 VDD3 3.15;
CLOAD CLOAD
input
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EtherMap-3 TXC-04226
Parameter Input leakage current Input capacitance tRISE tFALL
Unit
Test Conditions 3.15 VDD3 3.45 3.15 VDD3 3.45 input; Note VDD3 3.15; -1.0 VDD3 3.15;
-8.0 3.40 3.24
1.79 1.67
CLOAD CLOAD
INPUT/OUTPUT PARAMETERS LVTTL INPUT LV3CMOS OUTPUT (3.3V VOLT TOLERANT Input)
Parameter Input leakage current Input capacitance tRISE tFALL
Unit
Test Conditions
3.15 VDD3 3.45 3.15 VDD3 3.45
input; Note VDD3 3.15; -1.0 VDD3 3.15;
-8.0
1.80 1.78
3.39 3.36
CLOAD CLOAD
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INPUT/OUTPUT PARAMETERS LVTTL-5 INPUT LVCMOS OUTPUT VOLT TOLERANT Input)
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TIMING CHARACTERISTICS
This section presents detailed timing characteristics EtherMap-3 Figures through load capacitances output times indicated each Figure applicable. Unless otherwise indicated, timing parameters measured specific signal voltage levels: Inputs (except SDRAM) Outputs (except SDRAM) Inputs (SDRAM) Outputs (SDRAM) 0.80V 2.00V 0.80V 2.00V 0.25V 2.75V 0.25V 2.75V
specifications given this section cover following environmental condition: +125
DD(7-0) DPAR (INPUTS) DSPE (INPUT)
tSU(1)
DCLK (INPUT)
tCYC
Figure Drop Timing (Only APAR, output)
DATA
FIXED STUFF
DATA
DATA
tSU(3)
tH(2)
tSU(2)
tH(1)
FIXED STUFF
H1(1) TUG-3
H1(2) TUG-3
DC1J1V1 (INPUT)
tD(1) tD(3)
DATA
FIXED STUFF
(OUTPUT)
AD(7-0) APAR (OUTPUTS)
tH(3)
tD(2)
tD(4)
tD(5)
Load Notes: STM-1 mode with TUG-3 mapping shown. STS-3 mode used there would three pulses that would asynchronous with respect each other. However timing (i.e, setup hold, propagation delays) change.
parameter table next page.
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DCLK clock period DCLK duty cycle tPWH/tCYC DD(7-0)/DPAR setup time DCLK DD(7-0)/DPAR hold time after DCLK ASPE setup time DCLK ASPE hold time after DCLK AC1J1V1 setup time DCLK AC1J1V1 hold time after DCLK AD(7-0)/APAR stable from DCLK
tCYC tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(4) tD(3) tD(5)
51.44
AD(7-0)/APAR tristated from DCLK AD(7-0)/APAR turn from DCLK AD(7-0)/APAR valid from DCLK delay after DCLK
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Parameter
Symbol
Unit
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Figure Drop Timing (all signals outputs)
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tCYC DCLK (Input) DD(7-0) DPAR (Input) DSPE (Input) DC1J1V1 (Input) ACLK (Output) tD(2) AC1J1V1 (Output) ASPE (Output) AD(7-0) APAR (Output) (Output)
C1(1)
tPWH
tSU(1)
C1(1)
tH(1)
C1(2) C1(3) Data
TU/VT Selected Byte STS-1
STS-1
STS-1
Data STS-1
tSU(2)
tH(2)
Occurs every four frames when provided place byte STS-1 STS-1 STS-1 STS-1
tSU(3)
C1(1)
tH(3)
tD(1)
tD(3)
Load
Notes:
Parameter
STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e, setup hold, propagation delays) change.
single shown illustration purposes.
STS-1 STS-1
STS-1
tD(4) tD(6) tD(5)
Selected
Symbol tCYC
51.44
Unit
DCLK clock period
DCLK duty cycle tPWH/tCYC
tSU(1) tH(1) tSU(2) tH(2) tSU(3) tH(3) tD(1) tD(2) tD(3) tD(4) tD(5) tD(6)
DSPE setup time before DCLK DSPE hold time after DCLK
DC1J1V1 setup time before DCLK DC1J1V1 hold time after DCLK ACLK delay from DCLK AC1J1V1 delay from ACLK ASPE delay from ACLK AD(7-0)/APAR turn from ACLK delay from ACLK AD(7-0)/APAR valid delay from ACLK
DD(7-0)/DPAR hold time after DCLK
DD(7-0)/DPAR setup time before DCLK
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EtherMap-3 TXC-04226
tCYC ACLK (Input) ASPE (Input)
tSU(1) tH(1)
C1(1) STS-1 STS-1 STS-1
tPWH tSU(2)
tH(2)
Occurs every four frames
AC1J1V1
(Input)
STS-1
STS-1
STS-1
tD(2) AD(7-0) APAR (Output)
Selected
tD(3)
tD(4) tD(1)
(Output)
Load Notes:
single shown illustration purposes.
STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e, setup hold, propagation delays) change.
Parameter ACLK clock period ACLK duty cycle, tPWH/tCYC AC1J1V1 setup time before ACLK AC1J1V1 hold time after ACLK ASPE setup time before ACLK ASPE hold time after ACLK
Symbol tCYC
Unit
51.44
tSU(1) tH(1) tH(2) tD(2) tD(3) tD(1) tD(4) tSU(2)
AD(7-0)/APAR valid delay from ACLK
AD(7-0)/APAR tristate delay from ACLK indicator delayed from ACLK AD(7-0)/APAR tristate driven delay from ACLK
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Figure Timing (Timing signals inputs)
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Figure Timing (Timing signals outputs)
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tCYC ACLK (Output) ASPE (Output)
AC1J1V1
tPWH
tD(6) tD(5)
Occurs every four frames
(Output) AD(7-0) APAR (Output) (Output)
C1(1)
STS-1
STS-1
STS-1
STS-1
STS-1
STS-1
tD(2)
Selected
tD(3)
tD(4) tD(1)
Load
single shown illustration purposes.
Notes:
Parameter
STS-3 mode shown. STM-1 mode used there would pulse three TUG-3s, three pulses three AU-3s. However timing (i.e, setup hold, propagation delays) change.
Symbol tCYC tD(5) tD(6) tD(2) tD(3) tD(1) tD(4) 51.44
Unit
ACLK clock period
AD(7-0)/APAR tristate driven delay from ACLK
indicator delayed from ACLK
AD(7-0)/APAR tristate delay from ACLK
AD(7-0)/APAR valid delay from ACLK
ASPE valid delay from ACLK
AC1J1V1out valid delay from ACLK
ACLK duty cycle, tPWH/tCYC
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EtherMap-3 TXC-04226
tCYC GTX_CLK (Output)
tPWH
TX_EN (Output)
tD(1)
TXD(7-0)
(Output)
tD(2)
tD(3)
TX_ER (Output)
Load
Parameter GTX_CLK clock period
Symbol tCYC tD(1) tD(2) tD(3)
Unit
GTX_CLK duty cycle, tPWH/tCYC
tPWH
TX_EN valid delay from GTX_CLK
TXD(7-0) valid delay from GTX_CLK TX_ER valid delay from GTX_CLK
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Figure GMII Ethernet Interface
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Figure GMII Ethernet Interface
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tCYC RX_CLK (Input) tS(1) RX_DV (Input)
tPWH
tH(1)
tS(2)
RXD(7-0)
(Input)
RX_ER (Output)
Load
Parameter RX_CLK clock period
tS(3)
tH(2)
tH(3)
Symbol tCYC tS(1)
Unit
RX_CLK duty cycle, tPWH/tCYC RX_DV hold time after RX_CLK
tPWH tH(1) tS(2) tH(2) tS(3) tH(3)
RX_DV setup time before RX_CLK
RX_ER setup time before RX_CLK
RX_ER hold time after RX_CLK
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RXD(7-0) hold time after RX_CLK
RXD(7-0) setup time before RX_CLK
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EtherMap-3 TXC-04226
tCYC SMII_GCLK (Input)
tPWH
SMII_GSYNC (Output) tD(1)
SMII_DOn
(Output)
TXD6
TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
TXD3
TXD4 TXD5
TXD6 TXD7 TX_ER TX_EN TXD0
TXD1 TXD2
tD(2) SMII_DIn (Input)
RXD6 RXD7
RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7
RX_DV RXD0
RX_DV RXD0
RXD1 RXD2
n=1-8
Load
Parameter SMII_GCLK clock period
Symbol tCYC tD(1) tD(2)
Unit
SMII_GCLK duty cycle, tPWH/tCYC
tPWH
SMII_GSYNC valid delay from SMII_GCLK SMII_DOn valid delay from SMII_GCLK SMII_DIn setup time before SMII_GCLK SMII_DIn hold time after SMII_GCLK
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Figure TX/RX SMII Ethernet InterfacE
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Figure Ethernet Management Interface
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tCYC (Input)
tPWH
WRITE OPERATION MDIO
(Output)
READ OPERATION MDIO
Load
Parameter clock period duty cycle, tPWH/tCYC MDIO valid delay from MDIO setup time before
Symbol tCYC tPWH
(Intput)
Unit
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MDIO hold time after
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EtherMap-3 TXC-04226
tCYC
tPWH tD(1)
CLKE
ACTIVE
ACTIVE
READ
ACTIVE tD(2)
READ
ACTIVE
READ
READ
tD(3)
tD(4)
tD(5)
MASK
tD(7)
BA(1-0)
tD(8)
ADDR(12-0)
DATA(31-0)
Latency
Load
Parameter clock period duty cycle, tPWH/tCYC CLKE valid delay from valid delay from valid delay from valid delay from valid delay from BA(1-0) valid delay from ADDR(12-0) valid delay from DATA(31-0) setup time DATA(31-0) hold time from
Symbol tCYC tD(1) tD(2) tD(3) tD(4) tD(5) tD(7) tD(8)
Unit
tPWH
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Figure SDRAM Interface Single Word Read
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Figure SDRAM Interface Single Word Write
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tCYC
tPWH tD(1)
CLKE
ACTIVE
ACTIVE
WRITE
ACTIVE
WRITE
tD(2)
ACTIVE
WRITE
WRITE
tD(3)
tD(4)
tD(5)
MASK
tD(7)
BA(1-0)
ADDR(12-0)
tD(9)
tD(8)
tD(10)
DATA(31-0)
tD(11)
tD(12)
clock period
Parameter
Symbol
tCYC tPWH tD(1) tD(2) tD(3) tD(4) tD(5) tD(6) tD(7) tD(8) tD(9) tD(10) tD(11) tD(12)
Load
Unit
valid delay from
valid delay from valid delay from valid delay from MASK valid delay from BA(1-0) valid delay from ADDR(12-0) valid delay from DATA(31-0) tristate driven from DATA(31-0) valid delay from DATA(31-0) valid hold from DATA(31-0) driven tristate from
Note: burst accesses tD(10) tD(11) apply delay parameters between successive data bytes.
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CLKE valid delay from
duty cycle, tPWH/tCYC
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tCYC RPCLK (Output) RPALE (Output) tD(1)
RPADD
ADDRESS
tPWH
(Output) tD(2)
RPDLE (Output)
RPDAT (Output)
DATA
Load
Parameter RPCLK clock period RPCLK clock pulse width
Symbol tCYC tD(1) tD(2)
Unit
tPWH
RPALE/RPADD valid delay from RPCLK
RPDLE/RPDAT valid delay from RPCLK
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Figure VC-3 Byte Interface
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Figure VC-3 Byte Interface
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tCYC TPCLK (Output) TPALE (Output) tD(1)
TPADD
ADDRESS (8-bits)
tPWH
(Output) tD(2)
TPDAT (Input)
Load
Parameter TPCLK clock period TPCLK clock pulse width
TPDLE (Output)
DATA (8-bits)
Symbol tCYC tD(1)
Unit
tPWH tD(2)
TPDLE valid delay from TPCLK TPDAT setup time before TPCLK
TPDAT hold time after TPCLK
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TPALE/TPADD valid delay from TPCLK
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EtherMap-3 TXC-04226
tCYC RPCLKL (Output) RPALEL (Output) tD(1)
RPADDL
ADDRESS (12-bits)
tPWH
(Output) tD(2)
RPDLEL (Output)
RPDATL (Output)
DATA (8-bits)
Load
Parameter RPCLKL clock period RPCLKL clock pulse width
Symbol tCYC tD(1) tD(2)
Unit
tPWH
RPALEL/RPADDL valid delay from RPCLKL
RPDLEL/RPDATL valid delay from RPCLKL
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Figure Order Byte Interface
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EtherMap-3 TXC-04226
DATA SHEET
Figure Order Byte Interface
PRODUCT PREVIEW
tCYC TPCLKL (Output) TPALEL (Output) tD(1)
TPADDL
ADDRESS (12-bits)
tPWH
(Output) tD(2)
TPDATL (Input)
Load
Parameter TPCLKL clock period TPCLKL clock pulse width
TPDLEL (Output)
DATA (8-bits)
Symbol tCYC tD(1)
Unit
tPWH tD(2)
TPDLEL valid delay from TPCLKL TPDATL setup time before TPCLKL
TPDATL hold time after TPCLKL
PRODUCT PREVIEW TXC-04226-MB 2002
TPALEL/TPADDL valid delay from TPCLKL
Proprietary TranSwitch Corporation Information Solely Customers
DATA SHEET
EtherMap-3 TXC-04226
tCYC RAIPC (Output) tPWH
RAIPF
(Output)
RAIPD (Output)
Last
Load
Parameter
Symbol tCYC
Unit
RAIPC clock period RAIPC clock pulse width
tPWH
RAIPF/RAIPD valid delay from RPCLK
PRODUCT PREVIEW TXC-04226-MB 2002
PRODUCT PREVIEW
Figure VC-3 Ring Port Interface
Proprietary TranSwitch Corporation Information Solely Customers
EtherMap-3 TXC-04226
DATA SHEET
Figure VC-3 Ring Port Interface
PRODUCT PREVIEW
tCYC TAIPC (Input) tPWH
TAIPF
(Input) TAIPD (Input)
Load
Parameter TAIPC clock period TAIPC clock pulse width TAIPF/TAIPD setup time before TAIPC
Symbol tCYC tPWH
Last
Unit
TAIPF/TAIPD hold time after TAIPC
PRODUCT PREVIEW TXC-04226-MB 2002
Proprietary TranSwitch Corporation Information Solely Cus
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