documentation package TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system

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documentation package TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system

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TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
documentation package TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system chip consists following documents:
Supermapper Family Register Description Supermapper Family System Design Guide. These documents available password-protected website. Superframer Product Description (this document) Superframer Hardware Design Guide. These documents available public website shown below.
contact Agere, please last page this document. access related documents, including documents mentioned above, please following public website, contact your Agere representative:
x28/x21 DS1/J1/E1
Interface
System Interfaces
(x1)
DS1/J1/E1
Multifunction System
Switching Modes:
4CHI x672 DS0/E0
8PSB x672 DS0/E0
Transport Modes: TPG/TPM
Interface Control x28/x21 DS1/E1
4DS1/J1/E1 (X29) x28/x21 prot. 4DS2 prot.
NSMI Mode:
4DS1/J1/E1 x28/x21
XClks 10/22/03 Superframer
Figure 1-1. Superframer Functional Block Diagram
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
Features
Versatile supports DS1/J1/E1/DS0 applications. Terminates DS1/J1 framed unframed signals. popular framing formats supported. Loopbacks, manual error insertion, internal pattern generator/monitor, internal cross connects simplify debugging diagnostics. Low-power supply. industrial temperature range. 456-pin ball grid array (PBGA) package. Complies with appropriate Telcordia, ITU, ANSI, ETSI, Japanese standards.
test patterns transmitted either unframed payload framed signal defined ITU-T Recommendation O.150 (DS2 unframed only). Single bit-errors framing errors injected into test pattern, under register control. sink receiving channel replaced testpattern monitor, which detect count errors misconfigurations, and/or detect idle conditions AIS. Data link (DS1-ESF multiframe fields readable/writable.
DS1/J1/E1 Framing Features (FRM) Features (1x28/21)
x28/x21 DS1/J1/E1 channels. Line coding: B8ZS, HDB3, ZCS, AMI. framing modes: ESF, SLC-96, DDS, only). framing: G.704 basic CRC-4 multiframe consistent with G.706. framing modes: JESF (Japan). Supports unframed transparent transmission format. signaling modes: transparent; register system access 2-state, 4-state, 16-state; 2-state, 4-state, 16-state; SLC-96 2-state, 4-state, 16state; J-ESF handling groups maintenance signaling. signaling modes: transparent; register system access entire TS16 multiframe structure G.732. Signaling debounce change state interrupt. V5.2 processing. Alarm reporting performance monitoring AT&T, ANSI, ITU-T, ETSI standards. Facility data link features: HDLC transparent access either frame formats. Register/stack access SLC-96 transmit receive data. Extended superframe (ESF): automatic transmission performance report messages (PRM). Automatic transmission ANSIT1.403 performance report messages. Automatic detection transmission ANSIT1.403 bit-oriented codes. Register/stack access CEPT bits transmit receive data. Agere Systems Inc.
Features (x1)
Configurable multiplexer/demultiplexer signals, signals, signals to/from signal. Operates either C-bit parity mode. Provisionable time-slot selection DS1, insertion drop. Automatic receive monitor that detects loss-of-signal (LOS), bipolar violation (BPV), excessive zeros (EXZ), frame (OOF), severely errored frame (SEF), AIS, RAI, FEAC codes, P-bit parity errors, C-bit parity errors, FEBE indications. forced loopback DS2, DS1, forced loopback loopback request generation. multiplexer capable generating alarm indication signal (AIS), remote alarm indicator (RAI), idle, far-end alarm control (FEAC), far-end block error (FEBE) signals.
Test Pattern Generator/Monitor (TPG/TPM) Features (x1)
Configurable test-pattern generator: DS1, formats. Pseudorandom sequence (PRBS, also known pseudonoise sequences) based maximallength feedback shift register sequences; codes selectable from following options: QRSS, PRBS15, PRBS20, PRBS23, ALT_01, ALL_ONES, USER pattern bits, repeating).
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
DS1/E1 Digital Jitter Attenuation (DJA) Features (1x28/21)
HDLC features: HDLC transparent mode. Programmable logical channel assignment: time slot, ISDN D-channel, also inserts/extracts C-channels V5.1, V5.2 interfaces. logical channels both transmit receive direction (any framing format). Maximum channel data rate: kbits/s. Minimum channel data rate: kbits/s (DS1-FDL bit). 128-byte FIFO channel both transmit receive direction. loopback supported. System interfaces: Concentration highway interface: Single clock frame sync signals; programmable clock rates 2.048 MHz, 4.096 MHz, 8.192 MHz, 16.384 MHz; programmable data rates 2.048 Mbits/s, 4.096 Mbits/s, 8.192 Mbits/s; programmable clock edges bit/byte offsets. Parallel system interface 19.44 data signaling: single clock frame sync signals. Time-division multiplex data rate serial interface 1.544 2.048 MHz. Twenty-eight receive data, clock, frame sync signals. Twenty-eight transmit data signals with global clock frame sync. Network serial multiplexed interface minimal count serial interface 51.84 optimized data applications.
PLL-free receive operation using built-in digital jitter attenuator. bandwidth, damping factor, sampling rates configurable meet jitter MTIE requirements.
Microprocessor Unit (MPU) Features (x1)
20-bit address/16-bit data microprocessor interface. Synchronous MHz)/asynchronous microprocessor interface modes. Microprocessor data parity monitoring. Summary interrupts from major functional blocks/ maskable. Separate device interrupt outputs Superframer global interrupt. Global configuration network performance monitoring counters operation. Global software resets. Global enabling powering down major functional blocks. Registers provisionable clear read clear write. Compatible with most industry-standard processors.
DS2/DS1/E1 Cross Connect (XC) Features (x1)
Highly configurable interconnect signals to/from framer, external pins M13. Supports seven signals to/from external pins M13. Sources broadcast, looped back, routed from test-pattern generator monitor. channel routed through jitter attenuator.
JTAG
IEEE 1149.1 JTAG boundary scan.
Agere Systems Inc.
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
Overview
Superframer provides versatile interface DS1/J1/E1 applications. This device used full termination DS1s, J1s, E1s. Typical application this device would DS1/E1/DS0 DS1/E1 DS0. Each interface consists fully integrated, full-featured, primary rate framer with HDLC formatter facility data link access. also provides alarm reporting bidirectional performance monitoring. TFRA28J13 provides glueless interconnection analog line interface units.
Agere Systems Inc.
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
Block Description
Multiplexer (M13) Blocks
block highly configurable multiplexer/ demultiplexer operation. operate C-bit parity mode, mixed M13/M23 mode. C-bit parity mode, provides far-end alarm control (FEAC) code generator receiver, HDLC transmitter receiver, automatic far-end block error (FEBE) generator. Each internal MUX/deMUX MUX/ deMUX configured operate independent MUXes/deMUXes. inputs groups four) input signals groups three) feed into individual MUXes, while take signals from outputs MUXes, direct inputs, loopback deMUXed DS2s. supports numerous automatic monitoring functions. provide interrupt control system, operate polled mode.
four three signals each into single-bit, 16-word-deep FIFOs synchronize signals frame generation clock. fill level each FIFO determines need stuffing DS1/E1 input. handle DS1/E1 signals with nominal frequency offsets five unit intervals peak jitter. DS2/DS3 transmit clock used derive clock source frame generation. multiplexer generates transmit frame, fills information bits frame with data from seven select blocks. transmit output either form unipolar clock data, unipolar clock positive negative data. data B3ZS-encoded looped back from receive input.
Test Pattern Generator/Monitor (TPG/TPM) Block
4.1.1 Receive Direction
test pattern generator/test pattern monitor functional block (TPG/TPM) consists configurable test pattern generators monitors local self-test, maintenance, troubleshooting operations. feeds more DS1/E1/DS2 test signals (via data, clock, (DS1/E1 only) signal paths) cross connect, which redistribute broadcast these signals valid channel framer, external I/O, functional blocks. channel arriving cross connect routed test monitor. test monitor automatically detect/count errors pseudorandom test sequence, loss frame (DS1/E1 only), loss synchronization situation. provide interrupt control system, operated polled mode. Simultaneous testing DS1, signals supported with channel each. Supported test patterns quasirandom signal (QRSS), pseudorandom sequence (PRBS23, PRBS20, PRBS15), alternating zeros/ones, all-ones pattern, 16-bit user-provisionable pattern. test patterns transmitted either unframed payload framed signal, defined ITU-T Recommendation O.150. pattern unframed only. Under register control, single bit-errors injected into test pattern.
receive monitored loss clock lossof-signal (LOS) according T1.231. B3ZS decoder accepts either unipolar clock data, unipolar clock positive negative data. also checks bipolar coding violations. transmit looped back into receive side after B3ZS decoding. demultiplexer checks valid framing finding frame alignment pattern (F-bits) then locating multiframe alignment signal (M-bits). During each frame, data stream checked presence (1010) idle (1100) pattern. Within demultiplexer, there four performance monitoring counters M-bit, P-bit, E-bit parity, FEBE errors. Each demultiplexer contains performance monitoring counters.
4.1.2 Transmit Direction
incoming DS1/E1 clocks first checked activity loss-of-clock (LOC). data signals retimed checked activity. DS1/E1 loopback selectors allow individual DS1/E1 signals within received looped back toward DS2/DS3 input. This loopback performed automatically, user force loopback.
Agere Systems Inc.
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
Framer Block
4.3.3 Receive Performance Monitor
DS1/J1/E1 framer block's internal components listed below. particular application will determine which components within framer used.
4.3.1 Line Decoder/Encoder
line decoder/encoder supports either single-rail dual-rail transmission. dual-rail mode, line codes supported follows: Alternate mark inversion (AMI) binary zero code suppression (B8ZS) ITU-CEPT high-density bipolar order three (HDB3) single-rail mode, line interface unit (LIU) decodes/encodes data. dual-rail mode, loss-ofsignal monitored. case coded mark inversion (CMI) coding (Japanese standard JJ-20.11), decodes data, listing both coding rule violations (CRVs) line coding violations bipolar violations. mode, framer single-rail mode.)
receive performance monitor detects following alarms: Loss receive clock Loss-of-signal Loss-of-frame Alarm indication signal (AIS) Remote frame alarms Remote multiframe alarms These alarms detected defined appropriate ANSI, AT&T, ITU, ETSI standards. Performance monitoring, specified AT&T, ANSI, ITU, provided through counters monitoring following: Bipolar violations Frame errors errors Errored events Errored seconds Bursty errored seconds Severely errored seconds In-band loopback activation deactivation codes transmitted line payload facility data link. In-band loopback activation deactivation codes payload facility data link detected.
4.3.2 Receive Frame Aligner/Transmit Frame Formatter
receive frame aligner transmit frame formatter support following frame formats: superframe superframe: framing only J-D4 superframe with Japanese remote alarm SLC-96 J-ESF standard with different CRC-6 algorithm) Nonalign (193 bits-clear channel) CEPT basic frame (ITU G.706) CEPT CRC-4 multiframe with timer (ITU G.706) CEPT CRC-4 multiframe with timer (automatic CRC-4/non-CRC-4 equipment interworking) (ITU G.706 Annex Nonalign (256 bits-clear channel) 2.048 coded mark inversion (CMI) coded interface (TTC standards JJ-20.11)
4.3.4 Signaling Processor
signaling processor supports following modes: Superframe (D4, SLC-96): 2-state, 4-state, 16-state Extended superframe: 2-state, 4-state, 16-state CEPT: common channel signaling (CCS) (TS-16) Transparent (pass through) signaling J-ESF handling groups Signaling features supported channel follows: Signaling debounce Signaling freeze Signaling interrupt upon change state Associated signaling mode (ASM) Signaling inhibit Signaling stomp Voice data channels programmable robbed-bit signaling modes. entire payload forced into data-only signaling channels) mode (i.e., transparent mode, achieved programming control bit).
Agere Systems Inc.
TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0
4.3.6 HDLC Unit
Signaling access occurs through on-chip signaling registers system interface. Data associated signaling information accessed through system either CEPT-E1 modes.
HDLC processor formats HDLC packets insertion into programmable channels. channel number bits from time-slot. maximum number channels maximum channel rate kbits/s. minimum channel rate kbits/s. Each channel allocated bytes storage. HDLC processing data facility data link (PRMs, Sa-bits, otherwise) implemented assigning position logical HDLC channel.
4.3.5 Facility Data Link (FDL) Processor
receive facility data link processor monitors bitoriented data-link messages defined ANSI T1.403. transmit facility data link unit overrides FDL-FIFO transmission bit-oriented data-link messages defined ANSI T1.403-1995. processor extracts stores data link bits from three different frame types follows: D-bits delineator bits from SLC-96 multisuperframe. Data link bits from frames (bit time slot 24). multiframes Sa[4:8] bits from timeslot CEPT basic CRC-4 multiframes. respective bits always extracted from framealigned frames stored stack. processor controls notification stack updates through interrupt (maskable) registers. transmit functional block performs transmission D-bits into SLC-96 superframes, Sa-bits CEPT frames, D-bits frames. SLC-96 frames, delineator bits always sourced from this functional block when block enabled insertion. frames, data link bits always sourced from this functional block when this block enabled insertion. This functional block also provides capability transmit BOMs (bit-oriented messages) data link channel links. CEPT frames, bits sourced from either stack within this functional block from system interface. data link functional block only responds with valid data when selected source control bits.
DS2/DS1/E1 Cross Connect (XC) Block
cross connect (XC) functional block highly configurable crosspoint switch DS2/DS1/E1 signal connections Superframer. cross connect allows flexible configuration Superframer's internal blocks support variety applications. internal 28-channel framer, M13, digital jitter attenuator, test-pattern generator/monitor blocks external device pins interconnected with independent, nonblocking signal routing cross connect block. Multicast broadcast operation (one port many) also supported.
DS1/E1 Digital Jitter Attenuation (DJA) Block
block contains copies digital jitter attenuator. These digital jitter attenuator functional blocks operate different modes: jitter attenuator. both modes, digital jitter attenuator provisioned operate second-order always, switch first-order help meet MTIE requirements. block will also insert proper signal primary block control input active. bandwidth over wide range accommodate number different system constraints.
Agere Systems Inc.
additional information, contact your Agere Systems Account Manager following: INTERNET: http://www.agere.com E-MAIL: docmaster@agere.com AMERICA: Agere Systems Inc., Lehigh Valley Central Campus, Room 10A-301C, 1110 American Parkway Allentown, 18109-9138 1-800-372-2447, 610-712-4106 CANADA: 1-800-553-2448, 610-712-4106) ASIA: Agere Systems Hong Kong Ltd., Suites 3201 3210-12, 32/F, Tower Gateway, Harbour City, Kowloon Tel. (852) 3129-2000, (852) 3129-2020 CHINA: (86) 21-5047-1212 (Shanghai), (86) 25881122 (Shenzhen) JAPAN: (81) 3-5421-1600 (Tokyo), KOREA: (82) 2-767-1850 (Seoul), SINGAPORE: (65) 778-8833, TAIWAN: (886) 2-2725-5858 (Taipei) EUROPE: Tel. (44) 1344
Agere Systems Inc. reserves right make changes product(s) information contained herein without notice. liability assumed result their application. Agere registered trademark Agere Systems Inc. Agere Systems, Agere logo, Ultramapper, Hypermapper, Supermapper trademarks Agere Systems Inc.
Copyright 2003 Agere Systems Inc. Rights Reserved
October 2003 DS03-220MPIC

documentation package TFRA28J13 Superframer DS3/DS2/DS1/E1/DS0 system

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