PM73122 AAL1GATOR-32 LINK CES/DBCES AAL1 PROCESSOR PM73122
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
PM73122
AAL1GATOR-32
AADAPTATION LAYER SEGMENTATION REASSEMBLY PROCESSOR-32
DATASHEET
PROPRIETARY CONFIDENTIAL RELEASED ISSUE JUNE 2001
PMC-SIERRA, INC. PROPRIETARY CONFIDENTIAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
REVISION HISTORY Issue
Issue Date
1998 Sept 1999 1999 2000
Details Change
Document created. Significant design details added. Further design details pinout added. Updated reflect functional details based latest design. Clarified added further descriptive text. Finalized pinout.
2000
Added description floating nibble capability. (SHIFT_CAS). Added more functional detail.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Issue
Issue Date
2001
Details Change
Added section: Changes from Added "BUSMASTER" SBI_BUS_CFG_REG, along with description. Clarified NODROP_IN_START DROPPED_CELL counter functionality that NODROP_IN_START effect ROBUST Processing UDF-HS mode. LIN_STR_MODE added cross reference Operations section Dual mode. Corrected "Out Band Signaling Idle Detection" section with respect CAS. Fixed Robust processing Figure. Added note PROCESSING register clarify that only ROBUST_SN_EN DISABLE_SN set, both. Only mapping pages control RAM. Sometimes An_SW_RESET needs used with high speed queue. Updated Operations section An_SW_RESET description. Added times when OFFSET needs FRAMES_PER_CELL OFFSET description. Clarified MVIP-90 configuration Operations section Changed DC_INT from link tributary. Flipped HIZDATA HIZIO. Characteristics, made operating current typical, added margin C1FP hold Also applied C1FP timing C1FP_ADD also. Default value corrected MIN_DEPTH Register. Clarified and/or corrected "INSBI/EXSBI Programming Steps" section, "SBI Operation" section, tributary mapping sequences "Programming Sequence SBI" section lack depth check support Synchronous Mode. Added statements describing that UDF_HS Loopback Mode requires that High Speed Queue reset, that Activation Must Occur After Tributaries Enabled, that Activation must occur after tributaries enabled. Updated applications section with devices: PM8316 TEMUX-84, PM7341 S/UNI-IMA84.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Issue
Issue Date
June 2001
Details Change
Changed DC_INT_EN SYNC_INT_EN operations section. Characteristics, corrected IDDOP(2.7) mode. Operations section, clarified function Parity Error Detection recommended setting BUSMASTER device. Added note beginning Characteristics recommending that transition times clock inputs less than Corrected Interface Timing Memory Mapped Register Section added CSD_BYTES_LEFT register definition T_QUEUE_TABLE. Added hidden bits QUE_CREDITS word added R_DBCES_BM_IN_NEXT R_TOT_LEFT memory register changed R_DBCES_BM_IN_NEXT R_DBCES_BM_INACT R_STATE_0 memory register. Clarified C1FP signal definition Signal Definition section. Changed "Out Band" idle detection mode "Processor Controlled" idle detection mode Idle Detection section Functional Description. Updated section Functional Description Added SRTS patent legal note footer last page Corrected T1/E1 Link Rate Table (reversed polarity C1FP) Corrected cross reference QUEUE FIFO section Removed equations from partial cell section replaced with summary table. Added reference RL_CLK that clock gapped must have jitter less than using SRTS. Added minor clarifications, including: R_LINE_STATE location used UDF-HS mode, explanation UDF-ML, removed references over SBI, added recommendation unused TL_CLK pins high UDF-HS modes, renamed RPHY_ADD_RSX RPHY_ADD[4]/RSX match side, removed `sampled rising edge' from ADETECT description, added that PAGE don't care when accessing Control RAM's, clarified RSTB timing SYSCLK rd/wr timing, clarified T1/E1 granularity mode(at DA1SP level), E1_w_T1_sig mode supported over SBI, clarified that state machines freeze during underruns.
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
CONTENTS CHANGES FROM REV. REV. CHANGES FROM FEATURES APPLICATIONS REFERENCES. APPLICATION EXAMPLES AMULTI-SERVICE SWITCH PASSIVE OPTICAL NETWORK (PON) SYSTEM. DIGITAL ACCESS CROSS-CONNECT SYSTEM (DACS) WITH AINTERFACE.
BLOCK DIAGRAM DESCRIPTION DIAGRAM DESCRIPTION. 10.1 10.2 10.3 10.4 10.5 10.6 10.7 10.8 UTOPIA INTERFACE SIGNALS (52) MICROPROCESSOR INTERFACE SIGNALS (43). INTERFACE SIGNALS(41) LINE INTERFACE SIGNALS(DIRECT SPEED)(132) LINE INTERFACE SIGNALS(H-MVIP)(37) INTERFACE SIGNALS (ONLY USED MODE)(64). LINE INTERFACE SIGNALS(HIGH SPEED)(10). INTERFACE SIGNALS (ONLY USED H-MVIP, MODES)(41).
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
10.9
SUMMARY LINE INTERFACE SIGNALS.
10.10 CLOCK GENERATION CONTROL INTERFACE(18). 10.11 JTAG/TEST SIGNALS(5) 10.12 GENERAL SIGNALS(3+POWER/GND). FUNCTIONAL DESCRIPTION. 11.1 UTOPIA INTERFACE BLOCK (UI) 11.1.1 UTOPIA SOURCE INTERFACE (SRC_INTF) 11.1.2 UTOPIA SINK INTERFACE (SNK_INTF) 11.1.3 UTOPIA BLOCK (UMUX). 11.2 AAL1 PROCESSING BLOCK (A1SP). 11.2.1 AAL1 TRANSMIT SIDE (TXA1SP). 11.2.2 AAL1 RECEIVE SIDE (RXA1SP). 11.3 AAL1 CLOCK GENERATION CONTROL 11.3.1 DESCRIPTION 11.3.2 BLOCK DIAGRAM. 11.3.3 FUNCTIONAL DESCRIPTION 11.4 PROCESSOR INTERFACE BLOCK (PROCI) 11.4.1 INTERRUPT DRIVEN ERROR/STATUS REPORTING. 11.4.2 QUEUE FIFO 11.5 11.6 INTERFACE BLOCK (RAMI). LINE INTERFACE BLOCK (AAL1_LI) 11.6.1 CONVENTIONS 11.6.2 FUNCTIONAL DESCRIPTION 11.6.3 TRANSMIT DIRECTION.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
11.7
JTAG TEST ACCESS PORT.
MEMORY MAPPED REGISTER DESCRIPTION 12.1 12.2 INITIALIZATION A1SP LINE CONFIGURATION STRUCTURES. 12.2.1 HS_LIN_REG 12.3 TRANSMIT STRUCTURES SUMMARY 12.3.1 P_FILL_CHAR. 12.3.2 T_SEQNUM_TBL 12.3.3 T_COND_SIG. 12.3.4 T_COND_DATA. 12.3.5 RESERVED (TRANSMIT SIGNALING BUFFER). 12.3.6 T_OAM_QUEUE 12.3.7 T_QUEUE_TBL 12.3.8 RESERVED (TRANSMIT DATA BUFFER) 12.4 RECEIVE DATA STRUCTURES SUMMARY 12.4.1 R_OAM_QUEUE_TBL 12.4.2 R_OAM_CELL_CNT 12.4.3 R_DROP_OAM_CELL. 12.4.4 R_SRTS_CONFIG. 12.4.5 R_CRC_SYNDROME. 12.4.6 R_CH_TO_QUEUE_TBL. 12.4.7 R_COND_SIG 12.4.8 R_COND_DATA 12.4.9 RESERVED (RECEIVE SRTS QUEUE).
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
12.4.10 RESERVED (RECEIVE SIGNALING BUFFER). 12.4.11 R_QUEUE_TBL 12.4.12 R_OAM_QUEUE 12.4.13 RESERVED (RECEIVE DATA BUFFER) NORMAL MODE REGISTER DESCRIPTION 13.1 13.2 13.3 13.4 13.5 13.6 COMMAND REGISTERS. INTERFACE REGISTERS. UTOPIA INTERFACE REGISTERS LINE INTERFACE REGISTERS DIRECT SPEED MODE REGISTERS MODE REGISTERS 13.6.1 GENERAL REGISTERS 13.6.2 EXSBI REGISTERS 13.6.3 INSBI REGISTERS 13.7 13.8 13.9 INTERRUPT STATUS REGISTERS IDLE CHANNEL DETECTION CONFIGURATION STATUS REGISTERS. CONTROL STATUS REGISTERS.
OPERATION 14.1 14.2 HARDWARE CONFIGURATION. START-UP. 14.2.1 LINE CONFIGURATION. 14.2.2 QUEUE CONFIGURATION 14.2.3 ADDING QUEUES.
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
14.2.4 LINE CONFIGURATION DETAILS 14.3 UTOPIA INTERFACE CONFIGURATION 14.3.1 LOOPBACK SETUP EXAMPLE MULTI-ADDRESS MODE. 14.4 SPECIAL QUEUE CONFIGURATION MODES. 14.4.1 AAL0. 14.5 JTAG SUPPORT 14.5.1 CONTROLLER FUNCTIONAL TIMING. 15.1 15.2 15.3 15.4 SOURCE UTOPIA. SINK UTOPIA. PROCESSOR EXTERNAL CLOCK GENERATION CONTROL (CGC) 15.4.1 SRTS DATA OUTPUT 15.4.2 CHANNEL UNDERRUN STATUS OUTPUT. 15.4.3 ADAPTIVE STATUS OUTPUT 15.5 15.6 FREQ SELECT INTERFACE LINE INTERFACE TIMING. 15.6.1 LINE MODE. 15.6.2 H-MVIP TIMING. 15.6.3 INTERFACE. 15.6.4 DS3/E3 TIMING. ABSOLUTE MAXIMUM RATINGS D.C. CHARACTERISTICS
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
A.C. TIMING CHARACTERISTICS. 18.1 18.2 18.3 18.4 18.5 18.6 18.7 18.8 RESET TIMING SYS_CLK TIMING. NCLK TIMING MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS EXTERNAL CLOCK GENERATION CONTROL INTERFACE INTERFACE UTOPIA INTERFACE LINE TIMING. 18.8.1 DIRECT SPEED TIMING 18.8.2 TIMING 18.8.3 H-MVIP TIMING. 18.8.4 HIGH SPEED TIMING 18.9 JTAG TIMING.
ORDERING THERMAL INFORMATION. MECHANICAL INFORMATION. DEFINITIONS
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
LIST REGISTERS REGISTER 0X80000: RESET DEVICE REGISTER (DEV_ID_REG)253 REGISTER 0X80010, A1SPN COMMAND REGISTER (AN_CMD_REG) REGISTER 0X80020, A1SPN QUEUE FIFO REGISTER (AN_ADDQ_FIFO) REGISTER 0X80030, A1SPN CLOCK CONFIGURATION REGISTER (AN_CLK_CFG) REGISTER 0X80100: CONFIGURATION REGISTER (RAM_CFG_REG) REGISTER 0X80120: COMMON CONFIGURATION REGISTER (UI_COMN_CFG). REGISTER 0X80121: SOURCE CONFIG (UI_SRC_CFG) REGISTER 0X80122: SINK CONFIG (UI_SNK_CFG). REGISTER 0X80123: SLAVE SOURCE ADDRESS CONFIG REGISTER (UI_SRC_ADD_CFG) REGISTER 0X80124: SLAVE SINK ADDRESS CONFIG REGISTER (UI_SNK_ADD_CFG). REGISTER 0X80125: LOOPBACK (U2U_LOOP_VCI). REGISTER 0X80126: SOURCE POLLING PRIORITY LIST REGISTER (UI_SRC_POLL_LIST). REGISTER 0X80200H, 0FH: SPEED LINE CONFIGURATION REGISTERS(LS_LN_CFG_REG). REGISTER 0X80210H: LINE MODE REGISTER(LINE_MODE_REG). REGISTER 0X80300H: CONFIGURATION REGISTER(SBI_BUS_CFG_REG). REGISTER 0X80301H: LINK CONFIGURATION REGISTER(SBI_LNK_CFG_REG)
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
REGISTER 0X80302H: LINK DISABLE REGISTER LOW(SBI_LINK_DIS_REGL). REGISTER 0X80304H: SYNC LINK REGISTER LOW(SBI_SYNC_LINK_REGL). REGISTER 0X80305H: SYNC LINK HIGH REGISTER(SBI_SYNC LINKH_REG) REGISTER 0X80309H: EXTRACT ALARM INTERRUPT REGISTER HIGH (EXT_ALRM_INTH) REGISTER 0X8030AH: EXTRACT ALARM STATUS REGISTER (EXT_ALRM_STAT_REGL) REGISTER 0X8030CH: INSERT ALARM INSERT REGISTER (INS_ALRM_REGL) REGISTER 0X8030DH: INSERT ALARM INSERT REGISTER HIGH (INS_ALRM_REGH) REGISTER 0X80400H: EXTRACT CONTROL REGISTER (EXT_CTL) REGISTER 0X80401H: EXTRACT FIFO UNDER INTERRUPT STATUS REGISTER (EXT_FI_URI) REGISTER 0X80403H: EXTRACT TRIBUTARY INDIRECT ACCESS ADDRESS REGISTER (EXT_TRIAD) REGISTER 0X80404H: EXTRACT TRIBUTARY INDIRECT ACCESS CONTROL REGISTER (EXT_TRIAC) REGISTER 0X80405H: EXTRACT TRIBUTARY MAPPING INDIRECT ACCESS DATA REGISTER (EXT_TRIB_MAP). REGISTER 0X80406H: EXTRACT TRIBUTARY CONTROL INDIRECT ACCESS DATA REGISTER (EXT_TRIB_CTL). REGISTER 0X80407H: PARITY ERROR INTERRUPT STATUS REGISTER (SBI_PERR). REGISTER 0X80409H: MIN_DEPTH REGISTER REGISTER 0X8040AH: THRESHOLD REGISTER. REGISTER 0X8040CH: THRESHOLD REGISTER.311
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
REGISTER 0X8040EH: EXTRACT DEPTH CHECK INTERRUPT STATUS REGISTER (EXT_DCR_INT). REGISTER 0X80500H: INSERT CONTROL REGISTER (INS_CTL). REGISTER 0X80501H: INSERT FIFO UNDERRUN INTERRUPT STATUS REGISTER (INS_FI_URI) REGISTER 0X80503H: INSERT TRIBUTARY REGISTER INDIRECT ACCESS ADDRESS REGISTER(INS_TRIAD) REGISTER 0X80504H: INSERT TRIBUTARY REGISTER INDIRECT ACCESS CONTROL REGISTER (INS_TRIAC) REGISTER 0X80505H: INSERT TRIBUTARY MAPPING INDIRECT ACCESS DATA REGISTER (INS_TRIB_MAP. REGISTER 0X80506H: INSERT TRIBUTARY CONTROL INDIRECT ACCESS DATA REGISTER (INS_TRIB_CTL) REGISTER 0X80507H: MIN_DEPTH REGISTER REGISTER 0X80509H: MIN_THR MAX_THR REGISTER REGISTER 0X8050BH: MIN_THR MAX_THR REGISTER REGISTER 0X80511H: INSERT DEPTH CHECK INTERRUPT STATUS REGISTER (INS_DVR_INT) REGISTER 0X81000: MASTER INTERRUPT REGISTER (MSTR_INTR_REG) REGISTER 0X81010, A1SPN INTERRUPT REGISTER (A1SPN_INTR_REG). REGISTER 0X81020, A1SPN STATUS REGISTER (A1SPN_STAT_REG)347 REGISTER 0X81030, A1SPN TRANSMIT IDLE STATE FIFO (A1SPN_TIDLE_FIFO). REGISTER 0X81040, A1SPN RECEIVE STATUS FIFO (A1SPN_RSTAT_FIFO) REGISTER 0X81100: MASTER INTERRUPT ENABLE REGISTER (MSTR_INTR_EN_REG)
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RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
REGISTER 0X81110, A1SPN INTERRUPT ENABLE REGISTER (A1SPN_EN_REG) REGISTER 0X81150, RECEIVE(N) QUEUE ERROR ENABLE (RCV_Q_ERR_EN). REGISTER 0X82000-0X8200F 0X400*N (N=0-3): A1SP CHANNEL ACTIVE TABLE REGISTER 0X82010-0X8201F 0X400*N (N=0-3): A1SP PENDING TABLE. REGISTER 0X82100-0X821FF 0X400*N (N=0-3): A1SP CHANGE POINTER TABLE (RX_CHG_PTR). REGISTER 0X82200-0X8220F 0X400*N (N=0-3): A1SP CHANNEL ACTIVE TABLE REGISTER 0X82210-0X82217 0X400*N (N=0-3): A1SP PATTERN MATCHING LINE CONFIGURATION (PAT_MTCH_CFG0 REGISTER 0X82220 0X400*N (N=0-3): A1SP IDLE DETECTION CONFIGURATION TABLE REGISTER 0X82300-0X823FF 0X400*N (N=0-3): A1SP CAS/PATTERN MATCHING CONFIGURATION TABLE REGISTER 0X84000H: CONFIGURATION REGISTER (DLL_CFG_REG) REGISTER 0X84002H: RESET REGISTER (DLL_SW_RST_REG) REGISTER 0X84003H: CONTROL STATUS REGISTER (DLL_STAT_REG)376
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
LIST FIGURES FIGURE MULTI-SERVICE SWITCH APPLICATION FIGURE USING AAL1GATOR-32 APASSIVE OPTICAL NETWORK. FIGURE USING AAL1GATOR-32 DACS APPLICATION. FIGURE AAL1GATOR-32 INTERNAL BLOCK DIAGRAM. FIGURE DATA FLOW BUFFERING DUAL A1SP BLOCKS FIGURE BLOCK DIAGRAM. FIGURE SOURCE PRIORITY SERVICING EXAMPLE. FIGURE CELL HEADER INTERPRETATION. FIGURE A1SP BLOCK DIAGRAM FIGURE CAPTURE SIGNALING BITS (SHIFT_CAS=0) FIGURE CAPTURE SIGNALING BITS (SHIFT_CAS=0) FIGURE TRANSMIT FRAME TRANSFER CONTROLLER. FIGURE SDF-MF FORMAT T_DATA_BUFFER FIGURE SF-SDF-MF FORMAT T_DATA_BUFFER FIGURE SDF-FR FORMAT T_DATA_BUFFER. FIGURE SDF-MF FORMAT T_DATA_BUFFER FIGURE SDF-MF WITH SIGNALING FORMAT T_DATA_BUFFER FIGURE SDF-FR FORMAT T_DATA_BUFFER FIGURE UNSTRUCTURED FORMAT T_DATA_BUFFER FIGURE SDF-MF FORMAT T_SIGNALING_BUFFER. FIGURE SDF-MF FORMAT T_SIGNALING BUFFER
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE SDF-MF FORMAT T_SIGNALING_BUFFER. FIGURE SDF-MF WITH SIGNALING FORMAT T_SIGNALING_BUFFER. FIGURE TRANSMIT SIDE SRTS FUNCTION. FIGURE IDLE DETECTION CONFIGURATION REGISTER STRUCTURE. FIGURE IDLE DETECTION INTERRUPT WORD FIGURE PROCESSOR CONTROLLED IDLE DETECTION INTERRUPT WORD FIGURE PROCESSOR CONTROLLED CONFIGURATION REGISTER STRUCTURE. FIGURE CHANNEL ACTIVE/IDLE TABLE STRUCTURE FIGURE PAT_MTCH_CFG REGISTER STRUCTURE FIGURE PATTERN MATCH IDLE DETECTION REGISTER STRUCTURE86 FIGURE PATTERN MATCH IDLE DETECTION INTERRUPT WORD. FIGURE FRAME ADVANCE FIFO OPERATION. FIGURE PAYLOAD GENERATION FIGURE LOCAL LOOPBACK. FIGURE CELL HEADER INTERPRETATION. FIGURE FAST ALGORITHM FIGURE RECEIVE CELL PROCESSING FAST FIGURE ROBUST ALGORITHM FIGURE CELL RECEPTION .113 FIGURE SDF-MF FORMAT R_DATA_BUFFER.114 FIGURE SDF-MF FORMAT R_DATA_BUFFER .114 FIGURE SDF-FR FORMAT R_DATA_BUFFER .115
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE SDF-MF FORMAT R_DATA_BUFFER.115 FIGURE SDF-MF WITH SIGNALING FORMAT R_DATA_BUFFER.116 FIGURE SDF-FR FORMAT R_DATA_BUFFER .116 FIGURE UNSTRUCTURED FORMAT R_DATA_BUFFER.117 FIGURE SDF-MF FORMAT R_SIG_BUFFER.117 FIGURE SDF-MF FORMAT R_SIG_BUFFER .118 FIGURE SDF-MF FORMAT R_SIG_BUFFER .118 FIGURE SDF-MF WITH SIGNALING FORMAT R_SIG_BUFFER.119 FIGURE POINTER/STRUCTURE STATE MACHINE. FIGURE OVERRUN DETECTION. FIGURE DBCES RECEIVE SIDE BUFFERING FIGURE OUTPUT SIGNALING BITS (SHIFT_CAS=0). FIGURE OUTPUT SIGNALING BITS (SHIFT_CAS=0) FIGURE CHANNEL-TO-QUEUE TABLE OPERATION FIGURE RECEIVE SIDE SRTS SUPPORT FIGURE SRTS DATA. FIGURE CHANNEL STATUS FUNCTIONAL TIMING FIGURE ADAPTIVE DATA FUNCTIONAL TIMING. FIGURE FREQ SELECT FUNCTIONAL TIMING FIGURE RECEIVE SIDE SRTS SUPPORT FIGURE DIRECT ADAPTIVE CLOCK OPERATION FIGURE MEMORY MAP. FIGURE A1SP SRAM MEMORY
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE CONTROL REGISTERS MEMORY FIGURE TRANSMIT DATA STRUCTURES MEMORY FIGURE RECEIVE DATA STRUCTURES FIGURE NORMAL MODE REGISTERS MEMORY FIGURE INTERRUPT HIERARCHY. FIGURE ADDQ_FIFO WORD STRUCTURE FIGURE LINE INTERFACE BLOCK ARCHITECTURE FIGURE LINE INTERFACE
INTERFACE
FIGURE CAPTURE SIGNALING BITS FIGURE CAPTURE SIGNALING BITS FIGURE OUTPUT SIGNALING BITS FIGURE OUTPUT SIGNALING BITS. FIGURE T1/E1 LINK RATE INFORMATION. FIGURE MULTI-PHY MULTI-LINK LAYER DEVICE INTERFACE FIGURE BLOCK ARCHITECTURE FIGURE SDF-MF FORMAT T_SIGNALING BUFFER FIGURE R_CRC_SYNDROME MASK TABLE LEGEND. FIGURE UTOPIA-2 MULTI-ADDRESS MODE WITH BASED LOOPBACK FIGURE BOUNDARY SCAN ARCHITECTURE FIGURE CONTROLLER FINITE STATE MACHINE FIGURE INPUT OBSERVATION CELL (IN_CELL) FIGURE OUTPUT CELL (OUT_CELL). FIGURE BIDIRECTIONAL CELL (IO_CELL)
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE LAYOUT OUTPUT ENABLE BIDIRECTIONAL CELLS400 FIGURE PIPELINED SINGLE-CYCLE DESELECT SSRAM. FIGURE PIPELINED SSRAM FIGURE SRC_INTF START TRANSFER TIMING (UTOPIA AMODE) FIGURE SRC_INTF END-OF-TRANSFER TIMING (UTOPIA AMODE) FIGURE UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER (UTOPIA MODE). FIGURE UI_SRC_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE UI_SRC_INTF START-OF-TRANSFER TIMING (ANY-PHY MODE) FIGURE UI_SRC_INTF END-OF-TRANSFER TIMING (ANY-PHY MODE) FIGURE SNK_INTF START-OF-TRANSFER TIMING (UTOPIA AMODE) FIGURE SNK_INTF END-OF-TRANSFER TIMING (UTOPIA AMODE) FIGURE SNK_INTF START-OF-TRANSFER TIMING (UTOPIA MODE) FIGURE SNK_INTF START-OF-TRANSFER UTOPIA (SINGLE ADDRESS MODE) FIGURE SNK_INTF CLAV DISABLE UTOPIA (SINGLE-ADDRESS MODE) FIGURE SNK_INTF END-OF-TRANSFER UTOPIA (SINGLE ADDRESS MODE).
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE SNK_INTF START-OF-TRANSFER UTOPIA (MULTI-ADDRESS MODE).411 FIGURE SNK_INTF END-OF-TRANSFER UTOPIA (MULTI-ADDRESS MODE).411 FIGURE SNK_INTF START-OF-TRANSFER (ANY-PHY MODE) FIGURE SNK_INTF END-OF-TRANSFER (ANY-PHY MODE) FIGURE MICROPROCESSOR WRITE ACCESS. FIGURE MICROPROCESSOR READ ACCESS FIGURE MICROPROCESSOR WRITE ACCESS WITH ALE. FIGURE MICROPROCESSOR READ ACCESS WITH FIGURE SRTS DATA. FIGURE CHANNEL STATUS FUNCTIONAL TIMING. FIGURE ADAPTIVE DATA FUNCTIONAL TIMING. FIGURE FREQ SELECT FUNCTIONAL TIMING. FIGURE RECEIVE LINE SIDE TIMING(RL_CLK 1.544 MHZ) FIGURE RECEIVE LINE SIDE TIMING(RL_CLK 2.048 MHZ). FIGURE MVIP-90 RECEIVE FUNCTIONAL TIMING FIGURE TRANSMIT LINE SIDE TIMING(TL_CLK 1.544 MHZ). FIGURE TRANSMIT LINE SIDE TIMING(TL_CLK 2.048 MHZ) FIGURE MVIP-90 TRANSMIT FUNCTIONAL TIMING FIGURE RECEIVE H-MVIP TIMING, CLOSE-UP VIEW FIGURE RECEIVE H-MVIP TIMING, EXPANDED VIEW FIGURE TRANSMIT H-MVIP TIMING, CLOSE-UP VIEW FIGURE TRANSMIT H-MVIP TIMING, EXPANDED VIEW FIGURE DROP T1/E1 FUNCTIONAL TIMING
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE DROP FUNCTIONAL TIMING. FIGURE ADJUSTMENT REQUEST FUNCTIONAL TIMING FIGURE RECEIVE HIGH-SPEED FUNCTIONAL TIMING FIGURE TRANSMIT HIGH-SPEED FUNCTIONAL TIMING. FIGURE RSTB TIMING FIGURE SYS_CLK TIMING. FIGURE NCLK TIMING FIGURE MICROPROCESSOR INTERFACE READ TIMING FIGURE MICROPROCESSOR INTERFACE WRITE TIMING FIGURE EXTERNAL CLOCK GENERATION CONTROL INTERFACE TIMING FIGURE INTERFACE TIMING. FIGURE SINK UTOPIA INTERFACE TIMING FIGURE SOURCE UTOPIA INTERFACE TIMING FIGURE TRANSMIT SPEED INTERFACE TIMING FIGURE RECEIVE SPEED INTERFACE TIMING FIGURE FRAME PULSE TIMING. FIGURE DROP TIMING FIGURE TIMING FIGURE COLLISION AVOIDANCE TIMING. FIGURE H-MVIP SINK DATA FRAME PULSE TIMING FIGURE H-MVIP INGRESS DATA TIMING FIGURE TRANSMIT HIGH SPEED TIMING FIGURE RECEIVE HIGH SPEED INTERFACE TIMING.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
FIGURE JTAG PORT INTERFACE TIMING FIGURE ENHANCED BALL GRID ARRAY (SBGA).
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
LIST TABLES TABLE LINE INTERFACE SIGNAL TABLE SELECTION TABLE LINE INTERFACE SUMMARY TABLE CFG_ADDR PHY_ADDR USAGE DIRECTION TABLE CFG_ADDR PHY_ADDR USAGE DIRECTION TABLE MINIMUM PARTIAL CELL SIZE PERMITTED CONNECTIONS ACTIVE. TABLE CHANNEL STATUS TABLE BUFFER DEPTH TABLE FREQUENCY SELECT MODE TABLE FREQUENCY SELECT MODE TABLE LINE_MODE ENCODING. TABLE T1/E1 CLOCK RATE ENCODING TABLE SUPPORTED LINKS TABLE STRUCTURE CARRYING MULTIPLEXED LINKS TABLE TRIBUTARY COLUMN NUMBERING TABLE TRIBUTARY COLUMN NUMBERING TABLE DESYNCHRONIZER E1/T1 CLOCK GENERATION ALGORITHM TABLE AAL1GATOR-32 MEMORY MAP. TABLE A1SP LINE CONFIGURATION STRUCTURES SUMMARY TABLE TRANSMIT STRUCTURES SUMMARY. TABLE R_CRC_SYNDROME MASK TABLE TABLE 21R_QUEUE_TBL FORMAT
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LINK CES/DBCES AAL1 PROCESSOR
TABLE REGISTER MEMORY MAP. TABLE COMMAND REGISTER MEMORY MAP. TABLE INTERFACE REGISTERS MEMORY TABLE UTOPIA INTERFACE REGISTERS MEMORY TABLE CFG_ADDR PHY_ADDR USAGE DIRECTION267 TABLE CFG_ADDR PHY_ADDR USAGE DIRECTION268 TABLE LINE INTERFACE REGISTER MEMORY SUMMARY TABLE DIRECT SPEED MODE REGISTER MEMORY TABLE GENERAL REGISTER MEMORY MAP. TABLE EXSBI BLOCK REGISTER MEMORY TABLE TRIB_TYP ENCODING TABLE INSBI BLOCK REGISTER MEMORY TABLE TRIB_TYP ENCODING TABLE INTERRUPT STATUS REGISTERS MEMORY MAP. TABLE IDLE CHANNEL DETECTION CONFIGURATION STATUS REGISTERS MEMORY TABLE CONTROL STATUS REGISTERS MEMORY TABLE CHANNEL STATUS TABLE FRAME DIFFERENCE TABLE ABSOLUTE MAXIMUM RATINGS. TABLE AAL1GATOR-32 D.C. CHARACTERISTICS TABLE RTSB TIMING. TABLE SYS_CLK TIMING TABLE NCLK TIMING.
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TABLE MICROPROCESSOR INTERFACE READ ACCESS TABLE MICROPROCESSOR INTERFACE WRITE ACCESS TABLE EXTERNAL CLOCK GENERATION CONTROL INTERFACE. TABLE INTERFACE. TABLE UTOPIA SOURCE SINK INTERFACE TABLE TRANSMIT SPEED INTERFACE TIMING TABLE RECEIVE SPEED INTERFACE TIMING. TABLE CLOCKS FRAME PULSE (FIGURE 145). TABLE DROP (FIGURE 146) TABLE (FIGURE FIGURE 148). TABLE H-MVIP SINK TIMING TABLE H-MVIP SOURCE TIMING TABLE TRANSMIT HIGH SPEED INTERFACE TIMING. TABLE RECEIVE HIGH SPEED INTERFACE TIMING TABLE JTAG PORT INTERFACE. TABLE AAL1GATOR-32 (PM73122) ORDERING INFORMATION. TABLE AAL1GATOR-32 (PM73122) THERMAL INFORMATION
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CHANGES FROM REV. REV. There four main changes when transitioning from Rev. Rev. DEV_ID changed from 0000 0001. JTAG version number changed from SHIFT_CAS feature which allows signaling aligned with first nibble data been added. This feature enabled setting SHIFT_CAS LIN_STR_MODE register. capability have separate C1FP DROP side been added. Rev. there only C1FP pin, Rev. option support separate C1FP pins. original C1FP becomes C1FP drop side pin, C1FP_ADD, C1FP side bus. Rev. defaults using C1FP which makes backwards compatible with Rev. C1FP capability enabled setting TWO_C1FP_EN SBI_BUS_CFG_REG register.
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LINK CES/DBCES AAL1 PROCESSOR
CHANGES FROM There three main changes when transitioning from Rev. Rev. DEV_ID changed from 0001 0010. JTAG version number changed from BUSMASTER been added (bit SBI_BUS_CFG_REG). When set, AAL1gator32 will drive bytes that driven other devices. will prevent parity errors from being detected floating bytes.
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FEATURES AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-32) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-32 device. Compliant with AForum's Circuit Emulation Services (CES) specification (AF-VTOA-0078), ITU-T I.363.1 Supports Dynamic Bandwidth Circuit Emulation Services (DBCES). Compliant with AForum's DBCES specification (AF-VTOA-0085). Supports idle channel detection processor intervention, signaling, data pattern detection. Provides idle channel indication channel basis. Supports non-DBCES idle channel detection activating queue when constituent time slots active, deactivating queue when constituent time slots inactive. Provides AAL1 segmentation reassembly individual lines, H-MVIP lines MHz, STS-1 unstructured lines. Using optional Scalable Bandwidth Interconnect (SBI) Interface, provides AAL1 segmentation reassembly links. mode tributary AAL1 links. Supports floating locked tributaries well unframed, framed without framed with tributaries. only supported Synchronous tributaries. Provides standard UTOPIA level Interface which optionally supports parity runs MHz. Only Cell Level Handshaking supported. MPHY mode, like single port port device. following modes supported: 8/16-bit Level Multi-Phy Mode (MPHY) 8/16-bit Level SPHY 8-bit Level AMaster
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Provides optional 8/16-bit Any-PHY slave interface. Supports 1024 Virtual Channels (VC). Supports (consecutive channels) (non-consecutive channels) structured data format. Provides transparent transmission Common Channel Signaling (CCS) Channel Associated Signaling (CAS). Provides termination signaling. Allows nibble coincident with either first second nibble data. Provides per-VC data signaling conditioning transmit cell direction data signaling conditioning transmit line direction. Data signaling conditioning individually enabled. Includes conditioning support both directions. Transmit line conditioning options include programmable byte pattern, pseudo-random pattern data. Conditioning automatically occurs underruns. Cell Transmit direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, data signaling conditioning, ACell header definition. Generates AAL1 sequence numbers, pointers SRTS values accordance with ITU-T I.363.1. Multicast connections supported. Cell Transmit direction provides counters for: Conditioned cells transmitted each queue Cells which were suppressed each queue Total number cells transmitted each queue
Cell Receive direction, provides per-VC configuration time slots allocated, signaling support, partial cell size, sequence number processing options, cell delay variation tolerance buffer depth, maximum buffer depth. Processes AAL1 headers accordance with ITU-T I.363.1. Cell Receive direction, supports Fast Sequence Number processing algorithm types connections Robust Sequence Number processing Unstructured Data Format (UDF) connections. Cells inserted/dropped maintain integrity lost misinserted cells. integrity maintained through single errored cell lost cells.
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integrity also optionally maintained even underrun occurs. Pointer bytes, signaling bytes, bitmask bytes taken into account. Cell insertion options include programmable single byte pattern, pseudo-random data, data Cell Receive direction provides counters following events which include counters required AForum's CES-IS MIB: Incorrect sequence numbers queue Incorrect sequence number protection fields queue Total number received cells queue Total number dropped cells queue Total number underruns queue Total number lost cells queue Total number overruns queue Total number reframes queue Total number pointer parity errors queue Total number misinserted cells queue Total number non-data cells received Total number non-data cells dropped.
each receive queue following sticky bits maintained: Cell received Structured pointer rule error detected DBCES bitmask parity error Cell dropped blank allocation table Cells dropped pointer search Cell dropped forced underrun
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Cell dropped sequence number processing algorithm Valid pointer received Pointer parity error detected SRTS resume from underrun condition SRTS underrun occurred Resume occurred from underrun condition Pointer reframe occurred Overrun condition detected Cell received while underrun
Supports AAL0 mode, selectable basis. Provides system side loopback support. When enabled incoming matches programmable loopback VCI, cell received Receive UTOPIA interface looped back Transmit UTOPIA interface. Alternatively UTOPIA interface into remote loopback mode where incoming cells looped back out. Provides line side loopback, enabled queue basis, which loop single channel group channels which mapped single queue. Provides patented frame based calendar queue service algorithm with anticlumping add-queue mechanism that produces minimal Cell Delay Variation (CDV). mode uses non-frame based scheduling optimize CDV. addition, four internal cell generation engines work parallel further insure CDV. Queues added making entries into add-queue FIFO minimize queue activation overhead. offset configured when queue added distribute cell build times minimize clumping. Provides single maskable, open-collector interrupt with master interrupt register facilitate interrupt processing. master interrupt register indicates following conditions each which masked: Error/status condition with four AAL1 blocks parity error
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UTOPIA parity error Transmit UTOPIA FIFO full Transmit UTOPIA transfer error UTOPIA loopback FIFO full UTOPIA runt cell detected error detected
each AAL1 block following conditions cause interrupt, each which masked. Separate entry FIFOs AAL1 block used track receive transmit status. receive queue sticky just (individual mask sticky bit) Receive queue entered underrun state Receive queue exited underrun state DBCES bitmask changed. Receive Status FIFO overflow Transmit Frame Advance FIFO full Reception cells Change idle state channel enabled idle channel detection Transmit Channel Idle State change FIFO overflow Line frame resync event Transmit ALayer Processor (TALP) FIFO full
logic following conditions cause interrupt, each which masked: FIFO overflow underrun C1FP resync
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depth check error Drop FIFO overflow underrun Drop parity error Drop depth check error Drop C1FP resync Alarm detected
Provides 16-bit microprocessor interface internal registers, external 256K 16(18) Pipelined Single-Cycle Deselect Synchronous SRAMs, Synchronous SRAMs. Provides transmit buffer which used Operations, Administration Maintenance (OAM) cells well other user-generated cells such AAL5 cells Asignaling. corresponding receive buffer exists reception cells non-AAL1 data cells. Includes internal E1/T1 clock synthesizer each line which generate nominal E1/T1 clock controlled Synchronous Residual Time Stamp (SRTS) clock recovery method Unstructured Data Format (UDF) mode programmable weighted moving average adaptive clocking algorithm. SRTS adaptive clocking supported using external clock synthesizer clock control port. clock synthesizers also controlled externally provide customization SRTS adaptive algorithms. SRTS also disabled hardware input. Adaptive SRTS information output port external processing both speed high speed mode, needed. Buffer depth provided units bytes. synthesizer discrete frequencies between either +/-100 +/-200 Low-power Volt CMOS technology with Volt, Volt tolerant I/O. 352-pin super ball grid array (SBGA) package.
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APPLICATIONS Multi-service ASwitch AAccess Concentrator Digital Cross Connect Computer Telephony Chassis with Ainfrastructure Wireless Local Loop Back Haul APassive Optical Network Equipment
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REFERENCES Applicable Recommendations Standards. ANSI Recommendation T1.403, Network-to-Customer Installation Metallic Interface, 1995. ANSI Recommendation T1.630, Broadband ISDN-AAdaptation Layer Constant Rate Services, Functionality Specification, 1993. AForum, AUser Network Interface (UNI) Specification, 3.1, Foster City, USA, September 1994. AForum, Circuit Emulation Service Interoperability Specification (CESIS), 2.0, Foster City, USA, August 1996. AForum, Specifications (DBCES) Dynamic Bandwidth Utilization 64Kbps Time Slot Trunking Over Using CES, Foster City, USA, (AF-VTOA-0085) July 1997. AForum, UTOPIA, ATM-PHY Layer Specification, Level 2.01, Foster City, USA, March 1994. AForum, UTOPIA, ATM-PHY Layer Specification, Level 1.0, Foster City, USA, June 1995. ITU-T Recommendation G.703, Physical/Electrical Characteristics Hierarchical Digital Interfaces, April 1991. ITU-T Recommendation I.363.1, B-ISDN AAdaptation Layer (AAL) Specification, July 1995. ITU-T Recommendation G.823, Control Jitter Wander within Digital Networks Which Based 2048 kbit/s Hierarchy, March 1993. ITU-T Recommendation G.824 Control Jitter Wander within Digital Networks Which Based 1544 kbit/s Hierarchy, March 1993. PMC-971268, "High density T1/E1 framer with integrated VT/TU mapper multiplexer" (TEMUX), 2000, Issue GO-MVIP, "MVIP-90 Standard" Release 1.1, October 1994. GO-MVIP, "H-MVIP Standard" Release 1.1a, January 1997.
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APPLICATION EXAMPLES essential function Anetworks emulate existing Time Division Multiplexing (TDM) circuits. Since most voice data services currently provided circuits, seamless interworking between Ahas become system requirement. AForum standardized internetworking function that satisfies this requirement Circuit Emulation Service (CES) Specification. AAL1gator-32 direct implementation that service specification silicon, including complex Nx64 channelized service support CAS.
AMulti-service Switch AMulti-service Switch, located edge wide area network, interfaces Frame Relay, well services consolidates these different services Acells transport over single high-bandwidth Acore network. With AAL1gator-32 support SBIbus, high density Service Port linecards ASwitches designed with PMC-Sierra's SPECTRATM, TEMUXTM, AAL1gator, S/UNI -IMA, FREEDMTM, S/UNI -APEXand S/UNI -ATLASproducts. design shown Figure supports broad spectrum existing emerging services including Frame Relay (FR), multilink Frame Relay, multi-link PPP, Internet Protocol (IP), Dedicated Private Line Integrated Voice Data.
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Figure Multi-service Switch Application
Telecom T1/J1/E1 Framer TU/VT Mapper PM8316 TEMUX-84 Packet Processor PM7389 FREEDM-84 PM7341 S/UNI-IMA-84 PM7326 S/UNI-APEX AAL1 Circuit Emulation Service PM8316 TEMUX-84 PM73122 AAL1gator-32 Circuit Emulation Service PM7324 S/UNI-ATLAS Any-PHY Packet/Cell Internetworking Function APPI UTOPIA Any-PHY UTOPIA
ML-PPP ML-Frame Relay Traffic Manager
STS-12 SONET/SDH Framer PM5313 SPECTRA622
PM8316 TEMUX-84
OC-12
PM8316 TEMUX-84
H-MVIP
Voice Processor VoAVoice Processing
Policing
RM7000 MIPS Processor
With dramatic reduction board space power, optimized AAL1gator32 TEMUX-84 solution enables generation OC-3 OC-12 Circuit Emulation Service Service Port linecards. Passive Optical Network (PON) System general architecture Passive Optical Network (PON) access network consists elements: Optical Line Termination (OLT) Optical Network Unit (ONU). connected through point-tomultipoint Passive Optical Network that consists fiber, splitters other passive components. Typically, ONUs connected single OLT, depending splitting factor. OLTs typically located local exchanges ONUs street locations, buildings even homes. Figure shows AAL1gator-32 application supporting functions. Note that PM73123 AAL1gator-8 PM73124 AAL1gator-4 used ONUs provide reciprocal functions OLT.
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PM73122 AAL1GATOR-32
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Figure Using AAL1gator-32 APassive Optical Network.
Interface Function
APHY (e.g. S/UNIQUAD)
Interface Function
Transmission Mux/Demux
ACross Connect Function
AAL1gator-32
TEMUX
Interface Function AAL1gator-32 TEMUX
Optical Line Termination Equipment
Digital Access Cross-connect System (DACS) with AInterface Digital Access Cross-connect systems (DACS) with Auplink core Aswitch more AAL1gator-32s emulate service over ATM. DACs with capabilities allow service providers consolidate legacy private line services onto high speed Abackbone network reduce number network elements physical connections that need managed. Figure shows AAL1gator-32 DACS application. Figure Using AAL1gator-32 DACS application.
UTOPIA Any-PHY UTOPIA
H-MVIP
H-MVIP
PM73122 AAL1gator-32
PM8316 TEMUX-84
Switch PM73122 AAL1gator-32
PM7326 S/UNI-APEX
PM5349 S/UNI-QUAD
Cell FIFO
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BLOCK DIAGRAM AAL1gator-32 contains four AAL1 Processors (A1SP) which work parallel. A1SP blocks interface common UTOPIA interface side Line Interface block other side which configured support several different line protocols. A1SP blocks share interface other A1SP blocks share other interface. processor Interface block which also contains external clock control interface shared blocks. Figure AAL1gator-32 Internal Block Diagram
RAM2_ADSCB RAM2_A[17:0] RAM2_D[15:0] RAM2_PAR[1:0] RAM2_WEB[1:0] RAM2_CSB RAM2_OEB
SYSCLK NCLK TL_CLK_OE TL_CLK[15:0] RL_CLK[15:0] CRL_CLK CTL_CLK
Line Interface Clock
RSTB SCAN_ENB SCAN_MODEB TATM_DATA[15:0] TATM_PAR TATM_ENB TATM_SOC TATM_CLAV TATM_CLK RPHY_ADD[4:0] RATM_DATA[15:0] RATM_PAR RATM_ENB RATM_SOC RATM_CLAV RATM_CLK TPHY_ADD[4:0]
RAM2 Interface
A1SP
LINE_MODE[1:0] ADETECT AACTIVE REFCLK C1FP DDATA[7:0] ADATA[7:0] AJUST_REQ
A1SP
UTOPIA Interface
H-MVIP Speed High Speed
TL_DATA[15:0] TL_SYNC[15:0] TL_SIG[15:0] RL_DATA[15:0] RL_SYNC[15:0] RL_SIG[15:0]
A1SP
A1SP
JTAG
Interface
Processor Interface
External Clock Interface
RAM1_ADSCB RAM1_A[17:0] RAM1_D[15:0] RAM1_PAR[1:0] RAM1_WEB[1:0] RAM1_CSB RAM1_OEB
CGC_DOUT[3:0] CGC_LINE[4:0] ADAP_STB SRTS_STB CGC_VALID CGC_SER_D
A[19:0] D[15:0] ACKB INTB
TRST
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PM73122 AAL1GATOR-32
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DESCRIPTION AAL1 Segmentation Reassembly (SAR) Processor (AAL1gator-32) monolithic single chip device that provides DS1, line interface access AAdaptation Layer (AAL1) Constant Rate (CBR) Anetwork. arbitrates access external SRAM storage configuration, user data, statistics. device provides microprocessor interface configuration, management, statistics gathering. PMC-Sierra also offers software device control package AAL1gator-32 device.
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DIAGRAM AAL1gator-32 manufactured enhanced ball grid array (SBGA) package.
vss5
vss4
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RL_CLK
TL_CLK
vss3
vss2
RAM1_D
RAM1_D
TL_DATA
RAM1_OE
RAM1_D
RAM1_D
TL_SYNC
TL_SYNC
RL_SIG
vss1
vss0
vss9
vdd10
vss8
SYS_CLK
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_PA
RAM1_W
RL_CLK
RAM1_D
RAM1_D
RAM1_D
RL_SYNC
TL_SYNC
RAM1_D
RAM1_D
CRL_CLK
RL_DATA
LINE_MO
TL_DATA
vss7
vdd9
vss6
TATM_DA
vss11
vdd12
RAM1_AD
RAM1_AD
RAM1_AD
RAM1_CS
RAM1_AD
RAM1_AD
RAM1_PA
TL_CLK
RAM1_D
RAM1_D
SCAN_EN
RL_DATA
RAM1_D
RAM1_D
CTL_CLK
RL_SYNC
TL_DATA
TL_SIG
RL_SYNC
vdd11
vss10
TL_CLK
TATM_DA
TATM_DA
TATM_DA
vdd17
TCLK
RAM1_AD
RAM1_AD
RAM1_AD
vdd16
RAM1_AD
RAM1_W
RAM1_D
vdd15
RAM1_D
RL_SIG
TL_SIG
RAM1_D
vdd14
RL_SIG
TL_SIG
TL_CLK
RL_CLK
vdd13
RL_DATA
TL_SIG
RL_CLK
TATM_PA
TATM_DA
RPHY_AD
TATM_DA
TL_SYNC
TL_DATA
RL_SYNC
TL_CLK
TATM_CL
RPHY_AD
TATM_DA
TATM_DA
RL_SIG
RL_DATA
TL_SIG
RL_CLK
TATM_SO
RPHY_AD
RPHY_AD
TL_SYNC
TL_DATA
RL_SYNC
TL_SYNC
TL_CLK
RL_CLK
TATM_EN
RPHY_AD
RL_SIG
RL_DATA
TL_CLK
RL_SIG
TL_DATA
TL_CLK
TL_CLK
vdd18
vdd19
TL_SIG
RL_CLK
RL_DATA
TATM_DA
TATM_DA
TL_SYNC
RL_CLK
TL_DATA
RL_SYNC
TL_CLK
TL_DATA
TATM_DA
TATM_DA
TL_SIG
TL_SYNC
TL_SIG
TL_SIG
RL_CLK
TATM_DA
TATM_DA
TATM_DA
TATM_CL
TL_DATA
RL_SIG
RL_SYNC
RL_DATA
Vss13
TL_CLK
RL_SYNC
RL_CLK
vss15
RL_CLK
vdd21
RATM_DA
TL_CLK
RL_CLK
RL_CLK
Bottom View SBGA Package
vdd20
TL_SYNC
TL_SIG
vss12
RL_SIG
TL_DATA
vss14
TL_SIG
TL_SYNC
RL_DATA
RL_SYNC
TL_CLK
RATM_DA
RATM_DA
RATM_DA
RL_DATA
RL_CLK
TL_DATA
TL_CLK
RATM_DA
RATM_EN
RATM_DA
RATM_CL
RL_SIG
TL_CLK
RL_SYNC
RL_SIG
RATM_DA
RATM_DA
TPHY_AD
vdd23
vdd22
RL_CLK
TL_SIG
TL_SYNC
RATM_SO
TPHY_AD
TPHY_AD
TPHY_AD
TL_SYNC
RL_SYNC
TL_DATA
RATM_CL
RATM_PA
RATM_DA
RATM_DA
RL_SYNC
RL_DATA
TL_CLK
RL_DATA
RATM_DA
TPHY_AD
RATM_DA
TL_SIG
RL_DATA
RL_SIG
TL_SYNC
RATM_DA
RATM_DA
RATM_DA
[17]
RL_SYNC
TL_DATA
RL_SIG
RL_SYNC
RATM_DA
[19]
SCAN_MO
vdd4
[15]
[15]
[11]
[11]
vdd3
TL_SYNC
TL_SIG
vdd2
TL_SYNC
RL_SIG
vdd1
CGC_DOU CGC_SER
CGC_LINE
TRSTB
vdd0
RL_DATA
RL_SIG
LINE_MO
[18]
vss17
vdd6
[16]
[12]
[12]
RL_DATA
RL_DATA
ACKB
TL_SIG
TL_DATA
CGC_DOU
NCLK
CGC_LINE
CGC_LINE
RSTB
vdd5
vss16
RL_CLK
vss21
vdd8
vss19
[13]
[13]
[10]
RL_SIG
RL_SYNC
INTB
RL_DATA
TL_SIG
CGC_DOU TL_CLK_O CGC_LINE ADAP_ST
vss20
vdd7
vss18
vss27
vss26
[14]
[14]
[10]
TL_DATA
RL_SIG
vss25
vss24
CGC_DOU
TL_DATA
RL_SYNC
TL_SYNC
CGC_VALI CGC_LINE
SRTS_ST
vss23
vss22
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DESCRIPTION
10.1 UTOPIA Interface Signals (52) Name Type Function
Note signals have different meanings depending whether UTOPIA Amaster mode, mode Any-PHY mode. mode controlled UTOP_MODE ANY-PHY_EN fields UI_SRC_CFG UI_SNK_CFG registers. outputs tri-state when chip reset when UI_EN disabled UI_COMN_CFG register. outputs have maximum output current (IMAX) TATM_CLK/RPHY_CLK Input ATM: Transmit UTOPIA ALayer Clock synchronization clock input TAinterface. PHY: Receive UTOPIA/Any-PHY Layer Clock synchronization clock input RPHY interface Maximum frequency MHz. TATM_SOC/RPHY_SOC /RSOP Output ATM: Transmit UTOPIA ALayer Start-Of-Cell active high signal asserted AAL1gator-32 when TATM_D contains first valid byte cell. PHY: Receive Any-PHY/UTOPIA Layer Start-Of-Cell active high signal asserted AAL1gator-32 when RPHY_D[15:0] contains first valid word cell. AAL1gator-32 drives this signal only when Alayer selected cell transfer. Any-PHY: This Receive Start Packet (RSOP) signal which functions just like RPHY_SOC.
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Name TATM_D[15]/RPHY_D[15] TATM_D[14]/RPHY_D[14] TATM_D[13]/RPHY_D[13] TATM_D[12]/RPHY_D[12] TATM_D[11]/RPHY_D[11] TATM_D[10]/RPHY_D[10] TATM_D[9]/RPHY_D[9] TATM_D[8]/RPHY_D[8] TATM_D[7]/RPHY_D[7] TATM_D[6]/RPHY_D[6] TATM_D[5]/RPHY_D[5] TATM_D[4]/RPHY_D[4] TATM_D[3]/RPHY_D[3] TATM_D[2]/RPHY_D[2] TATM_D[1]/RPHY_D[1] TATM_D[0]/RPHY_D[0]
Type Output
Function ATM: Transmit UTOPIA ALayer Data Bits form byte-wide data driven layer. Least Significant (LSB). Most Significant (MSB) first received cell from serial line. Note that only lower used Amaster mode. PHY: Receive UTOPIA/Any-PHY Layer Data Bits form word-wide data driven Alayer. This only driven when Alayer selected UI_SRC_INTF cell transfer. upper byte only used 16_BIT_MODE UI_SRC_CFG register. Otherwise upper byte driven 0's. LSB. first byte first received cell from serial line. ATM: Transmit UTOPIA ALayer Parity byte parity covering TATM_D(7:0). PHY: Receive UTOPIA/Any-PHY Layer Parity either byte parity covering RPHY_D(7:0) word parity covering RPHY_D(15:0) depending value 16_BIT_MODE.
TATM_PAR/ RPHY_PAR
Output
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TATM_ENB/RPHY_ENB /RENB
Type Bidi
Function ATM: Transmit UTOPIA ALayer Enable active signal asserted AAL1gator-32 during cycles when TATM_D contains valid data. asserted until AAL1gator-32 ready send full cell. PHY: Receive UTOPIA/Any-PHY Layer Enable active signal asserted Alayer indicate RPHY_D RPHY_SOC will sampled next cycle. UTOP_MODE UI_SRC_CFG UTOPIA Level Mode then AAL1gator32 will drive data only RPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register cycle before RPHY_ENB goes low. Any-PHY: This RENB input signal, which functions same RPHY_ENB. only difference that data driven cycles after selection instead just cycle.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TATM_CLAV/RPHY_CLAV /RPA
Type Bidi
Function ATM: Transmit UTOPIA ALayer Cell Available active high signal from layer device indicate that there sufficient room accept cell. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-32 indicate ready deliver complete cell. Utopia Level mode, this signal driven only when MPHY_ADD matches CFG_ADDR UI_SRC_ADD_CFG register previous cycle. pulldown resistor recommended. Any-PHY: This Receive Packet Available (RPA) signal which functions same RPHY_CLAV except activated cycles after matching address instead one.
RPHY_ADD[4]/RSX RPHY_ADD[3]/RCSB RPHY_ADD[2] RPHY_ADD[1] RPHY_ADD[0]
Input Input Input Input
ATM: These signals used Amode. PHY: Receive UTOPIA Layer Address (Bits which selects UTOPIA receiver. These inputs used output enable RPHY_CLAV validate activation RPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[4:0] UI_SRC_CFG_ADDR register. ANY-PHY: Receive Start Transfer(RSX) active high output which indicates start Any-PHY packet which identifies location prepended address. ANY-PHY_EN
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name
Type
Function UI_SRC_CFG register needs this function. Receive Chip Select (RCSB) active input which used select AAL1gator-32 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than RPHY_ADD[2]. This input goes cycle after Any-PHY address valid. ANY-PHY_EN CS_MODE_EN UI_SRC_CFG register needs this function. Otherwise this functions RPHY_ADD[3]. RPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SRC_CFG_ADDR register. Note these pins must tied ground when used.
RATM_CLK/ TPHY_CLK
Input
ATM: Receive UTOPIA ALayer Clock synchronization clock input synchronizing RAinterface. PHY: Transmit UTOPIA/Any-PHY Layer Clock synchronization clock input synchronizing TPHY interface. Maximum frequency MHz.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RATM_SOC/ TPHY_SOC /TSOP
Type Input
Function This signal definitions depending whether UTOPIA Amode mode. ATM: Receive UTOPIA ALayer Start-Of-Cell active high signal asserted layer when RATM_D contains first valid byte cell. PHY: Transmit UTOPIA/Any-PHY Layer Start-Of-Cell active high signal asserted Alayer when TPHY_D contains first valid byte cell. Any-PHY: This Transmit Start Packet (TSOP) signal which functions just like TPHY_SOC. This signal optional this mode. unused, low.
RATM_D[15]/TPHY_D[15] RATM_D[14]/TPHY_D[14] RATM_D[13]/TPHY_D[13] RATM_D[12]/TPHY_D[12] RATM_D[11]/TPHY_D[11] RATM_D[10]/TPHY_D[10] RATM_D[9]/TPHY_D[9] RATM_D[8]/TPHY_D[8] RATM_D[7]/TPHY_D[7] RATM_D[6]/TPHY_D[6] RATM_D[5]/TPHY_D[5] RATM_D[4]/TPHY_D[4] RATM_D[3]/TPHY_D[3] RATM_D[2]/TPHY_D[2] RATM_D[1]/TPHY_D[1] RATM_D[0]/TPHY_D[0]
Input
AB24 AA23 AC26 AB25 AB26 AA25
ATM: Receive UTOPIA ALayer Data Bits form byte-wide data from layer device. LSB. MSB. This first cell, which will transmitted serial line. upper byte used Amode. PHY: Transmit UTOPIA/Any-PHY Layer Data Bits form word-wide data from Alayer device. LSB. first byte. This first cell, which will transmitted serial line. upper byte only used 16_BIT_MODE UI_SNK_CFG register.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RATM_PAR/ TPHY_PAR
Type Input
Function ATM: Receive UTOPIA ALayer Parity byte parity covering RATM_D(7:0) word parity covering RATM_D(15:0) depending value 16_BIT_MODE. PHY: Transmit UTOPIA/Any-PHY Layer Parity either byte parity covering TPHY_D(7:0) word parity covering TPHY_D(15:0) depending value 16_BIT_MODE.
RATM_ENB/TPHY_ENB
Bidi
ATM: Receive UTOPIA ALayer Enable active signal asserted AAL1gator-32 indicate RATM_D RATM_SOC will sampled next cycle. will asserted until AAL1gator-32 ready receive full cell. PHY: Transmit UTOPIA/Any-PHY Layer Enable active signal asserted Alayer device during cycles when TPHY_D[15:0] contain valid data. AAL1gator-32 will accept data only TPHY_ADD matches CFG_ADDR UI_SNK_CFG register cycle before TPHY_ENB goes Any-PHY: This TENB input signal, which functions same TPHY_ENB.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RATM_CLAV/TPHY_CLAV
Type Bidi
Function ATM: Receive UTOPIA ALayer Cell Available active high signal asserted layer indicate that there cell available send. PHY: Receive UTOPIA/Any-PHY Layer Cell Available active high signal asserted AAL1gator-32 indicate there cell-space available. AAL1gator-32 drives this signal only when TPHY_ADD matches CFG_ADDR UI_SNK_CFG register previous cycle. pulldown resistor recommended. Any-PHY: This Transmit Packet Available (TPA) signal which functions same TPHY_CLAV except activated cycles after matching address instead one.
TPHY_ADD[4]/TSX TPHY_ADD[3]/TCSB TPHY_ADD[2] TPHY_ADD[1] TPHY_ADD[0]
Input
AA24
ATM: These signals used Amode. PHY: Transmit UTOPIA Layer Address (Bits which selects UTOPIA transmitter. These inputs used output enable TPHY_CLAV validate activation TPHY_ENB. There internal pull-up resistors. These pins compared with CFG_ADDR[4:0] UI_SNK_CFG_ADDR register. ANY-PHY: Transmit Start Transfer(TSX) active high input which indicates start AnyPHY packet which identifies location prepended address. ANY-PHY_EN UI_SNK_CFG register needs this
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name
Type
Function function. Transmit Chip Select (TCSB) active input which used select AAL1gator-32 when polling Any-PHY mode. This input used decode Any-PHY address bits greater than TPHY_ADD[2]. This input goes cycle after Any-PHY address valid. ANY-PHY_EN CS_MODE_EN UI_SNK_CFG register needs this function. Otherwise this functions TPHY_ADD[3]. TPHY_ADD[2:0] bottom three bits Any-PHY address used select device when polling. These pins compared with CFG_ADDR[2:0] UI_SNK_CFG_ADDR register. Note these pins must tied ground when used.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
10.2 Microprocessor Interface Signals (43) Name D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] A[19] A[18] A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] Type AC22 AF24 AE23 AD22 AC20 AF22 AE21 AD20 AE19 AD18 AC17 AF19 AE17 AF21 AD14 AE14 AC25 AD26 AB23 AD23 AC21 AF23 AE22 AD21 AC19 AE20 AD19 AF20 AE18 AD17 AF18 AC16 AE13 AD13 AF12 AE12 Function bi-directional data signals (D[15:0]) provide data allow AAL1gator-32 device interface external micro-processor. Both read write transactions supported. microprocessor interface used configure monitor AAL1gator-32 device. Maximum output current (IMAX)
Input
address signals (A[19:0]) provide address allow AAL1gator-32 device interface external micro-processor.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name
Type Input
AD12
Function address latch enable signal (ALE) latches A[19:0] signals during address phase transaction. When high, address latches transparent. When low, address latches hold address provided A[19:0]. internal pull-up resistor. write strobe signal (WRB) qualifies write accesses AAL1gator-32 device. When low, D[15:0] contents clocked into addressed register rising edge WRB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
Input
AF11
Input
AC12
read strobe signal (RDB) qualifies read accesses AAL1gator-32 device. When low, AAL1gator-32 device drives D[15:0] with contents addressed register falling edge RDB. Note that CSB, low, chip outputs tristated. Therefore should never active same time during functional operation.
Input
AE11
chip select signal (CSB) qualifies read/write accesses AAL1gator-32 device. signal must during read write accesses. When high, microprocessor interface signals ignored AAL1gator-32 device. required (register accesses controlled only RDB) then should connected inverted version RSTB signal. Note that CSB, low, chip outputs tristated.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name ACKB
Type OpenDrain Output
AD11
Function ACKB active signal which indicates when processor read data valid when processor write operation completed. When inactive this signal tristated. ACKB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX)
INTB
OpenDrain Output
AE10
interrupt signal (INTB) active signal indicating that enabled MSTR_INTR_REG register set. When INTB low, interrupt active enabled. When INTB tristate, there interrupt pending disabled. INTB open drain output should pulled high externally with fast resistor. Maximum output current (IMAX)
10.3 Interface Signals(41) Name RAM1_D[15] RAM1_D[14] RAM1_D[13] RAM1_D[12] RAM1_D[11] RAM1_D[10] RAM1_D[9] RAM1_D[8] RAM1_D[7] RAM1_D[6] RAM1_D[5] RAM1_D[4] RAM1_D[3] RAM1_D[2] RAM1_D[1] RAM1_D[0] Type Function bi-directional data signals (RAM1_D[15:0]) provide data allow AAL1gator-32 device access external 256Kx16(18) RAM. RAM1 used A1SP blocks Maximum output current (IMAX)
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RAM1_A[17] RAM1_A[16] RAM1_A[15] RAM1_A[14] RAM1_A[13] RAM1_A[12] RAM1_A[11] RAM1_A[10] RAM1_A[9] RAM1_A[8] RAM1_A[7] RAM1_A[6] RAM1_A[5] RAM1_A[4] RAM1_A[3] RAM1_A[2] RAM1_A[1] RAM1_A[0] RAM1_OEB
Type Output
Function address signals (RAM1_A[17:0]) provide address allow AAL1gator-32 device address external 256Kx16(18) RAM. Maximum output current (IMAX)
Output
RAM1 Output Enable active signal that enables SRAM drive data. Maximum output current (IMAX) RAM1 Write Enable active signal high-byte write. Maximum output current (IMAX) RAM1 Write Enable Zero active signal low-byte write. Maximum output current (IMAX) RAM1 Chip Select active chip-select signal external memory. Maximum output current (IMAX)
RAM1_WEB[1]
Output
RAM1_WEB[0]
Output
RAM1_CSB
Output
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RAM1_ADSCB /RAM1_R/WB
Type Output
Function This signal different meanings depending upon type SSRAM that AAL1gator-32 programmed interface Pipelined Single-Cycle Deselect SSRAM: RAM1 Address Status Control active output external memory used cause external address loaded into RAM. Pipelined SSRAM: RAM1 indicates direction transfer. Maximum output current (IMAX)
RAM1_PAR[1] RAM1_PAR[0]
RAM1 Parity bi-directional signal that indicates parity upper lower byte RAM1_D[15:0]. Maximum output current (IMAX)
Note: different modes line interface redefined. Direct Speed mode there pairs bi-directional lines, which support links Mbps. H-MVIP mode there eight pairs Mbps bidirectional lines, which compatible with H-MVIP specification. High Speed mode there lines, which support unchannelized data streams Mbps. lastly, there mode, which supports interface. H-MVIP mode, high speed (HS) mode mode upper Direct Speed lines become interface. mode bottom Direct Speed lines become interface. Table defines which signal tables need used each possible mode. Select mode line interface that will used refer tables listed. Table page shows pins shared between different modes. Table Line Interface Signal Table Selection Line Mode Direct Speed H-MVIP Line Interface Table Direct Speed H-MVIP RAM2 Interface Table using upper lines)
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Line Mode High Speed
Line Interface Table High Speed
RAM2 Interface Table using lines)
10.4 Line Interface Signals(Direct Speed)(132) Name LINE_MODE[1] LINE_MODE[0] Type Input Function Determines mode operation line interface: 00)Direct Speed Mode 01)SBI Mode H-MVIP Mode High Speed Mode Note: Direct Speed Mode, UDF-HS Mbps) line supported. High Speed Mode, UDF-HS Mbps) lines supported. Mode, UDF-HS (DS3) lines supported. TL_SYNC[15] TL_SYNC[14] TL_SYNC[13] TL_SYNC[12] TL_SYNC[11] TL_SYNC[10] TL_SYNC[9] TL_SYNC[8] TL_SYNC[7] TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0] AC15 AC11 Transmit Line Synchronization transmit frame synchronization indicators used SDF-MF SDF-FR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multiframe boundary. Depending value GEN_SYNC LIN_STR_MODE register that line, sync signal either received from corresponding framer device generated internally Default mode this signal frame sync input. When MVIP_EN LS_Ln_CFG_REG then TL_SYNC[0] pin; common frame sync. Maximum output current (IMAX)
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TL_DATA[15] TL_DATA[14] TL_DATA[13] TL_DATA[12] TL_DATA[11] TL_DATA[10] TL_DATA[9] TL_DATA[8] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[15] TL_SIG[14] TL_SIG[13] TL_SIG[12] TL_SIG[11] TL_SIG[10] TL_SIG[9] TL_SIG[8] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]
Type Output
AF16 AC14 AD10
Function Transmit Line Serial Data carry received data corresponding framer devices. Maximum output current (IMAX)
Output
Transmit Line Signal signaling outputs corresponding framer devices SDF-MF mode. This default function this pin. Maximum output current (IMAX)
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TL_CLK[15]/TSM[15] TL_CLK[14]/TSM[14] TL_CLK[13]/TSM[13] TL_CLK[12]/TSM[12] TL_CLK[11]/TSM[11] TL_CLK[10]/TSM[10] TL_CLK[9]/TSM[9] TL_CLK[8]/TSM[8] TL_CLK[7]/TSM[7] TL_CLK[6]/TSM[6] TL_CLK[5]/TSM[5] TL_CLK[4]/TSM[4] TL_CLK[3]/TSM[3] TL_CLK[2]/TSM[2] TL_CLK[1]/TSM[1] TL_CLK[0]/TSM[0]
Type
Function Transmit Line Channel Clock clock lines sixteen lines. They clock data from AAL1gator-32 corresponding framer devices. Depending value TLCLK_OE CLK_SOURCE_TX field LIN_STR_MODE memory register, these pins either outputs inputs. TLCLK_OUTPUT_EN high, these pins outputs clock sourced internally power This later changed CLK_SOURCE_TX field. Note that CLK_SOURCE_TX "000" then this output, even driving clock. clock will only driven mode either internal clock synthesizer being used clock being looped. CLK_SOURCE_TX "001", "010, "011", "100", "101") Note that UDF_HS=1 HS_LIN_REG, TL_CLK[7:1] should tied high. Transmit Signaling Mirror copy TL_SIG output. Direct Speed mode, CLK_SOURCE_TX="111" then signaling output this pin. This option used with devices that share same clock signaling. this mode CTL_CLK used line clock. Maximum output current (IMAX)
CTL_CLK
Input
Common Transmit Line Clock transmit line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_TX LINE_STR_MODE memory register that line.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RL_SYNC[15] RL_SYNC[14] RL_SYNC[13] RL_SYNC[12] RL_SYNC[11] RL_SYNC[10] RL_SYNC[9] RL_SYNC[8] RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] RL_DATA[15] RL_DATA[14] RL_DATA[13] RL_DATA[12] RL_DATA[11] RL_DATA[10] RL_DATA[9] RL_DATA[8] RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0]
Type Input
AE15 AD16 AD15
Function Receive Line Synchronization receive frame synchronization indicators used SDF-MF SDF-FR modes. Depending value MF_SYNC_MODE LI_CFG_REG register line, these signals either indicate frame boundary multiframe boundary. ground unused.
Input
Receive Line Serial Data carries receive data from corresponding framer devices.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name RL_SIG[15] RL_SIG[14] RL_SIG[13] RL_SIG[12] RL_SIG[11] RL_SIG[10] RL_SIG[9] RL_SIG[8] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[15] RL_CLK[14] RL_CLK[13] RL_CLK[12] RL_CLK[11] RL_CLK[10] RL_CLK[9] RL_CLK[8] RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0]
Type Input
AE16 AF15 AC10
Function Receive Line Signaling carries data from corresponding framer devices.
Input
Receive Line Clock clock received from corresponding framer device used clock RL_DATA, RL_SIG, RL_SYNC.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name CRL_CLK
Type Input
Function Common Receive Line Clock receive line clock which shared across lines. Whether this clock used given line dependent value CLK_SOURCE_RX LIN_STR_MODE memory register that line. When MVIP_EN LS_Ln_CFG_REG then this input; common 4.096 clock.
10.5 Line Interface Signals(H-MVIP)(37) Name LINE_MODE[1] LINE_MODE[0] Type Input Function Determines mode operation line interface: Direct Speed Mode Mode H-MVIP Mode High Speed Mode Input Frame Sync active frame synchronization input signal used indicate start frame. Transmit Line Serial Data carry received data corresponding framer devices. H_MVIP backplane. Maximum output current (IMAX)
TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0]
Output
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0] C16B
Type Output
Function Transmit Line Signal signaling outputs corresponding framer devices SDF-MF mode. H-MVIP does support signaling directly, these signals used transport signaling needed. Maximum output current (IMAX) Clock clock used transfer data across H-MVIP bus. clock runs twice fast data rate. This common clock used both receive transmit direction. Receive Line Serial Data carries receive data from corresponding framer devices H-MVIP backplane.
Input
RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0]
Input
Input
Receive Line Signaling carries data from corresponding framer devices. H-MVIP does support signaling directly, these signals used transport signaling needed.
Input
Clock clock used generating sampling F0B. This common clock used both receive transmit direction.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
10.6 Interface Signals (only used mode)(64) Name LINE_MODE[1] LINE_MODE[0] Type Input Function Determines mode operation line interface: Direct Speed Mode Mode H-MVIP Mode High Speed Mode REFCLK Input Reference Clock (REFCLK). This signal externally generated 19.44MHz +/-50ppm clock with nominal duty cycle. Since DROP busses locked together this clock common both drop sides BUS.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name TL_CLK[31] TL_CLK[30] TL_CLK[29] TL_CLK[28] TL_CLK[27] TL_CLK[26] TL_CLK[25] TL_CLK[24] TL_CLK[23] TL_CLK[22] TL_CLK[21] TL_CLK[20] TL_CLK[19] TL_CLK[18] TL_CLK[17] TL_CLK[16] TL_CLK[15] TL_CLK[14] TL_CLK[13] TL_CLK[12] TL_CLK[11] TL_CLK[10] TL_CLK[9] TL_CLK[8] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0] RL_CLK[2] RL_CLK[0]
Type Input
Function Transmit Serial Clock input. When SRTS used mode clock with better jitter characteristics desired TL_CLK[16] TL_CLK[0] pins should used connect externally generated transmit line clock. When generating TL_CLK with external logic TL_CLK lines accessed. These pins should only used when CLK_SOURCE_TX "000". Note that CLK_SOURCE_TX equal "000", TL_CLK[15:0] output must driven externally. Note that UDF_HS=1 A1SP0 HS_LIN_REG, TL_CLK[7:1] should tied high, UDF_HS=1 A1SP2 HS_LIN_REG, TL_CLK[23:17] should tied high.
Input
When SRTS used mode clock with better jitter characteristics desired RL_CLK pins should used connect externally recovered receive line clock.
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PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Name C1FP
Type Input
Function Active High Frame Pulse (C1FP). This signal externally generated indicate first octet BUS. TWO_C1FP_EN then DROP busses locked together this signal common both DROP sides BUS. TWO_C1FP_EN high, then this signal DROP side C1FP. This frame pulse indicator single REFCLK signal long updated rising edge REFCLK. This signal sampled rising edge REFCLK. This signal also indicates multiframe alignment which occurs every frames, therefore this signal pulsed once every fourth octet produce 2KHz multiframe signal. frame pulse does need repeated every 2KHz. AAL1gator-32 will synchronize this signal also able flywheel absence. When tributary synchronous mode C1FP signal used indicate multiframe alignment must pulsed frame boundaries.
C1FP_ADD
Input
Frame Pulse bus. This optionally used C1FP pulse Drop need offset from each other. this TWO_C1FP_EN must SBI_BUS_CFG_REG. Drop Data (DDATA[7:0]). Drop data time division multiplexed which transports tributaries assigning them fixed octets within structure. Multiple devices drive this uniquely assigned tributary columns within structure. DDATA[7:0] sampled rising edge REFCLK.
DDATA[7] DDATA[6] DDATA[5] DDATA[4] DDATA[3] DDATA[2] DDATA[1] DDATA[0]
Input
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Name
Type Input
Function Drop Data Parity (DDP). This signal carries even parity drop signals. parity calculation encompasses DDATA[7:0], signals. selection even parity made SBI_PAR_CTL Extract Control Register. Multiple devices drive this signal uniquely assigned tributary columns within structure. This parity signal intended detect multiple sources column assignment. sampled rising edge REFCLK.
Input
Active High Drop Payload (DPL). This active high signal indicates valid data within structure. This signal asserted during octets making tributary. This signal goes high during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal goes during octet after octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. Multiple devices drive this signal uniquely assigned tributary columns within structure. sampled rising edge REFCLK.
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Name
Type Input
Function Active High Drop Payload Indicator (DV5). This active high signal locates position floating payloads each tributary within structure. Timing differences between port timing timing indicated adjustments this payload pointer relative fixed structure. Multiple devices drive this signal uniquely assigned tributary columns within structure. movements indicated this signal must accompanied appropriate adjustments signal. sampled rising edge REFCLK.
ADATA[7] ADATA[6] ADATA[5] ADATA[4] ADATA[3] ADATA[2] ADATA[1] ADATA[0]
Output
Data (ADATA[7:0]). data time division multiplexed which transports tributaries assigning them fixed octets within structure. AAL1gator-32 drives ADATA[7:0] only uniquely assigned tributary columns within structure. ADATA[7:0] asserted rising edge REFCLK. Maximum output current (IMAX) Data Parity (ADP). This signal carries even parity signals. parity calculation encompasses ADATA[7:0], signals. selection even parity made SBI_PAR_CTL Insert Control Register AAL1gator drives only uniquely assigned tributary columns within structure. asserted rising edge REFCLK. Maximum output current (IMAX)
Output
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Name
Type Output
Function Active High Payload (APL). This active high signal indicates valid data within structure. This active high signal asserted during octets making tributary. This signal goes high during octet within tributary accommodate negative timing adjustments between tributary rate fixed structure. This signal goes during octet after octet within tributary accommodate positive timing adjustments between tributary rate fixed structure. AAL1gator-32 drives only uniquely assigned tributary columns within structure. asserted rising edge REFCLK. Maximum output current (IMAX)
Output
Active High Payload Indicator (AV5). This active high signal locates position floating payload each tributary within structure. AAL1gator-32 drives only uniquely assigned tributary columns within structure. movements indicated this signal accompanied appropriate adjustments signal. asserted rising edge REFCLK. Maximum output current (IMAX)
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Name AJUST_REQ
Type Input
Function Active High Justification Request (AJUST_REQ). This signal used speed slow down AAL1gator-32 which sending data PHY. This signal only used when layer device timing master transmit direction. This active high signal indicates negative timing adjustments when asserted high during octet, depending tributary type. response this AAL1gator-32 will send extra byte octet next frame. This signal indicates positive timing adjustments when asserted high during octet following octet, depending tributary type. AAL1gator-32 will respond this sending octet during octet next frame. timing adjustments from AAL1gator-32 response justification request will still payload payload indicators appropriately timing adjustments. synchronous modes this signal unused must held low. AJUST_REQ sampled rising edge REFCLK.
AACTIVE
Output
Active Indicator (AACTIVE). This active high signal asserted high during octets when driving data control signals, ADATA[7:0], ADP, AV5, onto bus. other Link Layer devices (e.g. other AAL1gator-32 common bus) driving listen this signal detect multiple sources driving which occur configuration problems AACTIVE asserted rising edge REFCLK. Maximum output current (IMAX)
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Name ADETECT
Type Input
Function Active Detector (ADETECT). This input listens other Link Layer masters. AAL1gator-32 will listen other Link Layer AACTIVE signals. When AAL1gator-32 driving AACTIVE high detects ADETECT high from another device backs driving minimize eliminate contention. ADETECT asynchronous signal which used disable tristate drivers bus. This input must tied when used.
10.7 Line Interface Signals(High Speed)(10) Name LINE_MODE[1] LINE_MODE[0] Type Input Function Determines mode operation line interface: Direct Speed Mode Mode H-MVIP Mode High Speed Mode TL_DATA[2] TL_DATA[0] Output Transmit Line Serial Data carry received data corresponding framer devices. Maximum output current (IMAX) TL_CLK[2] TL_CLK[0] Transmit Line Channel Clock clock lines high speed lines. They clock data from AAL1gator-32 corresponding framer devices. clock always input high speed mode. Maximum output current (IMAX)
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Name RL_DATA[2] RL_DATA[0]
Type Input
Function Receive Line Serial Data carries receive data from corresponding framer devices. Receive Line Clock clock received from corresponding framer device used clock RL_DATA[2] RL_DATA[0].
RL_CLK[2] RL_CLK[0]
Input
10.8 Interface Signals (only used H-MVIP, modes)(41) Name RAM2_D[15] RAM2_D[14] RAM2_D[13] RAM2_D[12] RAM2_D[11] RAM2_D[10] RAM2_D[9] RAM2_D[8] RAM2_D[7] RAM2_D[6] RAM2_D[5] RAM2_D[4] RAM2_D[3] RAM2_D[2] RAM2_D[1] RAM2_D[0] Type AC11 AD10 Function bi-directional data signals (RAM2_D[15:0]) provide data allow AAL1gator-32 device access external 256Kx16(18) RAM. RAM2 used A1SP blocks Maximum output current (IMAX)
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Name RAM2_A[17] RAM2_A[16] RAM2_A[15] RAM2_A[14] RAM2_A[13] RAM2_A[12] RAM2_A[11] RAM2_A[10] RAM2_A[9] RAM2_A[8] RAM2_A[7] RAM2_A[6] RAM2_A[5] RAM2_A[4] RAM2_A[3] RAM2_A[2] RAM2_A[1] RAM2_A[0] RAM2_OEB
Type Output
AD16 AE16 AD15 AE15 AF15 AC10
Function address signals (RAM2_A[17:0]) provide address allow AAL1gator-32 device address external 256Kx16(18) RAM. Maximum output current (IMAX)
Output
RAM2 Output Enable active signal that enables SSRAM drive data. Maximum output current (IMAX) RAM2 Write Enable active signal high-byte write. Maximum output current (IMAX) RAM2 Write Enable Zero active signal low-byte write. Maximum output current (IMAX) RAM2 Chip Select active chip-select signal external memory. Maximum output current (IMAX)
RAM2_WEB[1]
Output
RAM2_WEB[0]
Output
RAM2_CSB
Output
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Name RAM2_ADSCB RAM2_R/WB
Type Output
Function This signal different meanings depending upon type SSRAM that AAL1gator-32 programmed interface Pipelined Single-Cycle Deselect SSRAM: RAM2 Address Status Control active output external memory used cause external address loaded into RAM. Pipelined SSRAM: RAM2 indicates direction transfer. Maximum output current (IMAX)
RAM2_PAR[1] RAM2_PAR[0]
RAM2 Parity bi-directional signal that indicates parity upper lower byte RAM2_D[15:0]. Maximum output current (IMAX)
10.9 Summary Line Interface Signals following table shows modes same time shows pins redefined different modes. Table Line Interface Summary Direct Speed TL_SYNC[15] TL_SYNC[14] TL_SYNC[13] TL_SYNC[12] TL_SYNC[11] TL_SYNC[10] TL_SYNC[9] TL_SYNC[8] TL_SYNC[7] RAM2_D[15] RAM2_D[10] RAM2_D[9] RAM2_D[7] RAM2_D[2] RAM2_P[0] RAM2_D[15] RAM2_D[10] RAM2_D[9] RAM2_D[7] RAM2_D[2] RAM2_P[0] RAM2_D[15] RAM2_D[10] RAM2_D[9] RAM2_D[7] RAM2_D[2] RAM2_P[0] H-MVIP High Speed AC15 AC11
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Direct Speed TL_SYNC[6] TL_SYNC[5] TL_SYNC[4] TL_SYNC[3] TL_SYNC[2] TL_SYNC[1] TL_SYNC[0] TL_DATA[15] TL_DATA[14] TL_DATA[13] TL_DATA[12] TL_DATA[11] TL_DATA[10] TL_DATA[9] TL_DATA[8] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0] TL_SIG[15] TL_SIG[14] TL_SIG[13] TL_SIG[12] TL_SIG[11]
H-MVIP
High Speed
AF16
RAM2_D[14] RAM2_D[12] RAM2_D[8] RAM2_D[6] RAM2_D[4] RAM2_D[1] TL_DATA[7] TL_DATA[6] TL_DATA[5] TL_DATA[4] TL_DATA[3] TL_DATA[2] TL_DATA[1] TL_DATA[0]
RAM2_D[14] RAM2_D[12] RAM2_D[8] RAM2_D[6] RAM2_D[4] RAM2_D[1] C1FP_ADD DDATA[6] DDATA[4] DDATA[2] DDATA[0] AJUST_REQ C1FP
RAM2_D[14] RAM2_D[12] RAM2_D[8] RAM2_D[6] RAM2_D[4] RAM2_D[1]
TL_DATA[2] TL_DATA[0]
AC14
RAM2_D[13] RAM2_D[11] RAM2_P[1]
RAM2_D[13] RAM2_D[11] RAM2_P[1]
RAM2_D[13] RAM2_D[11] RAM2_P[1]
AD10
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Direct Speed TL_SIG[10] TL_SIG[9] TL_SIG[8] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0] TL_CLK[15] TL_CLK[14] TL_CLK[13] TL_CLK[12] TL_CLK[11] TL_CLK[10] TL_CLK[9] TL_CLK[8] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0] CTL_CLK
H-MVIP RAM2_D[5] RAM2_D[3] RAM2_D[0] TL_SIG[7] TL_SIG[6] TL_SIG[5] TL_SIG[4] TL_SIG[3] TL_SIG[2] TL_SIG[1] TL_SIG[0]
RAM2_D[5] RAM2_D[3] RAM2_D[0] DDATA[7] DDATA[5] DDATA[3] DDATA[1] ADETECT TL_CLK[15] TL_CLK[14] TL_CLK[13] TL_CLK[12] TL_CLK[11] TL_CLK[10] TL_CLK[9] TL_CLK[8] TL_CLK[7] TL_CLK[6] TL_CLK[5] TL_CLK[4] TL_CLK[3] TL_CLK[2] TL_CLK[1] TL_CLK[0]
High Speed RAM2_D[5] RAM2_D[3] RAM2_D[0]
TL_CLK[2] TL_CLK[0]
C16B
REFCLK
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Direct Speed RL_SYNC[15] RL_SYNC[14] RL_SYNC[13] RL_SYNC[12] RL_SYNC[11] RL_SYNC[10] RL_SYNC[9] RL_SYNC[8] RL_SYNC[7] RL_SYNC[6] RL_SYNC[5] RL_SYNC[4] RL_SYNC[3] RL_SYNC[2] RL_SYNC[1] RL_SYNC[0] RL_DATA[15] RL_DATA[14] RL_DATA[13] RL_DATA[12] RL_DATA[11] RL_DATA[10] RL_DATA[9] RL_DATA[8] RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4]
H-MVIP
High Speed
RAM2_A[14] RAM2_A[11] RAM2_A[7] RAM2_A[6] RAM2_A[2] RAM2_OEB RAM2_CSB
RAM2_A[14] RAM2_A[11] RAM2_A[7] RAM2_A[6] RAM2_A[2] RAM2_OEB RAM2_CSB
RAM2_A[14] RAM2_A[11] RAM2_A[7] RAM2_A[6] RAM2_A[2] RAM2_OEB RAM2_CSB
AE15
ADATA[7] ADATA[4] TL_CLK[19] TL_CLK[18] TL_CLK[17] TL_CLK[16] RAM2_A[17] RAM2_A[15] RAM2_A[12] RAM2_A[8] RAM2_A[4] RAM2_A[3] RAM2_A[0] RAM2_WEB[0] RL_DATA[7] RL_DATA[6] RL_DATA[5] RL_DATA[4] ADATA[6] ADATA[3] RAM2_A[17] RAM2_A[15] RAM2_A[12] RAM2_A[8] RAM2_A[4] RAM2_A[3] RAM2_A[0] RAM2_WEB[0] RAM2_A[17] RAM2_A[15] RAM2_A[12] RAM2_A[8] RAM2_A[4] RAM2_A[3] RAM2_A[0] RAM2_WEB[0]
AD16 AD15
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Direct Speed RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RL_SIG[15] RL_SIG[14] RL_SIG[13] RL_SIG[12] RL_SIG[11] RL_SIG[10] RL_SIG[9] RL_SIG[8] RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0] RL_CLK[15] RL_CLK[14] RL_CLK[13] RL_CLK[12] RL_CLK[11] RL_CLK[10] RL_CLK[9] RL_CLK[8]
H-MVIP RL_DATA[3] RL_DATA[2] RL_DATA[1] RL_DATA[0] RAM2_A[16] RAM2_A[13] RAM2_A[10] RAM2_A[9] RAM2_A[5] RAM2_A[1] RAM2_WEB[1] RAM2_ADSCB RL_SIG[7] RL_SIG[6] RL_SIG[5] RL_SIG[4] RL_SIG[3] RL_SIG[2] RL_SIG[1] RL_SIG[0]
ADATA[1] AACTIVE RAM2_A[16] RAM2_A[13] RAM2_A[10] RAM2_A[9] RAM2_A[5] RAM2_A[1] RAM2_WEB[1] RAM2_ADSCB
High Speed
RL_DATA[2] RL_DATA[0] RAM2_A[16] RAM2_A[13] RAM2_A[10] RAM2_A[9] RAM2_A[5] RAM2_A[1] RAM2_WEB[1] RAM2_ADSCB
AE16 AF15 AC10
ADATA[5] ADATA[2] ADATA[0] TL_CLK[31] TL_CLK[30] TL_CLK[29] TL_CLK[28] TL_CLK[27] TL_CLK[26] TL_CLK[25] TL_CLK[24]
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Direct Speed RL_CLK[7] RL_CLK[6] RL_CLK[5] RL_CLK[4] RL_CLK[3] RL_CLK[2] RL_CLK[1] RL_CLK[0] CRL_CLK
H-MVIP
TL_CLK[23] TL_CLK[22] TL_CLK[21] TL_CLK[20] RL_CLK[2] RL_CLK[0]
High Speed
RL_CLK[2] RL_CLK[0]
10.10 Clock Generation Control Interface(18) Name CGC_DOUT[3] _DOUT[2] _DOUT[1] _DOUT[0] Type Output AF10 Function External Clock Generation Control Data Bits form SRTS correction code when SRTS_STBH asserted; otherwise CGC_DOUT[3:0] bits form channel status frame difference when ADAP_STBH asserted. Line Bits form line CGC_DOUT corresponds when SRTS_STBH asserted; otherwise CGC_LINE[4:0] bits form adaptive state machine index when ADAP_STBH asserted. SRTS Strobe indicates that SRTS value present CGC_DOUT[3:0]. CGC_LINE[4:0] indicates line SRTS code controls. Adaptive Strobe indicates that channel status byte difference being played CGC_DOUT[3:0]. nibbles identified values CGC_LINE[4:0].
_LINE[4] _LINE[3] _LINE[2] _LINE[1] _LINE[0] SRTS_STBH
Output
Output
ADAP_STBH
Output
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Name NCLK/ SRTS_DISB
Type Input
Function Network Clock Anetwork-derived clock used SRTS. this signal tied low, SRTS disabled. Internally this clock divided independently each A1SP block. This clock should 2.43 E1mode, 38.88 mode 77.76 mode. Transmit Line Clock Output Enable controls whether TL_CLK lines inputs outputs between time hardware reset when CLK_SOURCE_TX bits read. high, TL_CLK pins outputs. low, TL_CLK pins inputs. There internal pull-up resistor, TL_CLK pins outputs connected. value this input overwritten CLK_SOURCE_TX bits LIN_STR_MODE memory register. External Clock Generation Control Serial Data input used allow external clock control circuitry pass frequency information into internal clock synthesizer. External Clock Generation Control Valid signal active high input indicating that data CGC_SER_D valid. This signal must transition from high first valid data CGC_SER_D must stay high through whole clock control word.
TL_CLK_OE
Input
CGC_SER_D
Input
CGC_VALID
Input
10.11 JTAG/TEST Signals(5) Name TCLK Type Input Function test clock signal provides timing test operations carried using JTAG test access port. test mode select signal controls test operations that carried using JTAG test access port. Maintain tied high when using JTAG logic.
Input Internal Pull-up
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Name
Type Input Internal Pull-up
Function test data input signal JTAG serial input data test data output signal JTAG serial output data. active signal which, SCAN mode, used shift data. This signal should tied high normal operation. When tied enable SCAN mode. This signal should tied high normal operation. active test reset signal asynchronous reset JTAG circuitry. JTAG logic will used, option connect TRSTB RSTB input, keep tied high while RSTB high; this maintains JTAG logic reset during normal operation. JTAG logic will used, option described above, simply ground TRSTB.
SCAN_ENB
Output Input Internal Pull-up
SCAN_MODEB
Input Internal Pull-up
AC24
TRSTB
Schmitt Trigger Input Internal Pull-up
10.12 General Signals(3+power/gnd) Name RSTB Type Schmitt Trigger Input Internal Pull-up Function Reset active asynchronous hardware reset. When RSTB forced low, AAL1gator's internal registers reset their default states.
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Name SYS_CLK
Type Input
Function System Clock. maximum frequency MHz. This clock used clock majority logic inside chip also determines speed memory interface external clock control interface. This clock also used clock synthesis. When clock synthesis enabled this clock must 38.88 MHz. Power (VDD3.3). VDD3.3 pins should connected well decoupled +3.3V power supply. These pins power output ports device. pins "quiet" power pads.
VDD3.3 (PPH, PQH)
Power
AE25 AC13 AC18 AC23 AD24 AA26 AF17
VDD2.5 (PCH)
Power
Power (VDD2.5). VDD2.5 pins should connected well decoupled +2.5V power supply. These pins power core device.
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Name (PPL, PQL, PCL)
Type Ground
AD25 AE24 AE26 AF13 AF14 AF25 AF26
Function Ground (VSS). pins should connected GND. pins ground pins ports. pins "quiet" ground pins ports. pins core ground pins. grounds should connected together.
Notes Description: AAL1gator-32 inputs bi-directionals present minimum capacitive loading tolerant. AAL1gator-32 UTOPIA/Any-PHY outputs bi-directional pins have drive capability. TDO, outputs microprocessor outputs bi-directional pins have drive capability. other outputs bi-directional pins have drive capability. AAL1gator-32 outputs tristated under control IEEE P1149.1 test access port, even those which tristate under normal operation. outputs bi-directionals tolerant when tristated.
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clock inputs (except TL_CLK) Schmitt triggered. Inputs RPHY_ADD_RSX, RL_DATA[15:0], RL_SIG[15:8], RPHY_ADDR[3:0], TPHY_ADDR[4:0], RL_CLK[15:0], RL_SYNC[15:8,3:1], TL_SYNC[15:8], TL_CLK[15:0], RATM_DATA[15:0], RATM_PAR, RATM_CLK, RATM_SOC, TATM_CLK, D[15:0], RAM1_PAR[1:0], WRB, CSB, RDB, NCLK, CRL_CLK, CTL_CLK, SCAN_ENB, SCAN_MODEB, CGC_SER_D, CGC_VALID, RSTB, ALE, TL_CLK_OE, TMS, TCLK, TRSTB have internal pull-up resistors. Power VDD3.3 pins should applied before power VDD2.5 pins applied. Similarly, power VDD2.5 pins should removed before power VDD3.3 pins removed.
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FUNCTIONAL DESCRIPTION AAL1gator-32 divided into following major blocks, which explained this section: UTOPIA Interface Block (UTOPIAI) AAL1 Processing Block (A1SP) Processor Interface Block (PROCI) Interface Block (RAMI) Line Interface Block (LINEI) JTAG
11.1 UTOPIA Interface Block (UI) manages responds control signals UTOPIA passes cells from UTOPIA Dual A1SP blocks. Both 8-bit 16-bit UTOPIA interfaces with optional single parity supported. Each direction configured independently address configuration register. following UTOPIA modes supported. UTOPIA Level Master (8-bit only) UTOPIA Level UTOPIA Level Any-PHY
sink direction, uses 8-cell deep FIFO buffering cells they wait sent Dual A1SP blocks. addition, each Dual A1SP contains 8-cell deep FIFOs (one A1SP) with separate interfaces allow each A1SP process data pace. source direction, uses 4cell deep FIFOs holding cells before they sent onto UTOPIA bus. Also, each Dual A1SP contains 8-cell deep FIFOs (one A1SP), again with separate interfaces. data flow showing FIFOs shown Figure
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Figure Data Flow Buffering Dual A1SP Blocks
DUAL A1SP
TXA1SP cell FIFO) TXA1SP cell FIFO) Cell FIFO Cell FIFO RXA1SP cell FIFO) RXA1SP cell FIFO)
UTOPIAI
TUFIFO cells)
DUAL A1SP
TXA1SP cell FIFO) Cell FIFO TXA1SP cell FIFO) Cell FIFO RUFIFO cells) Cell FIFO RXA1SP cell FIFO) RXA1SP cell FIFO)
UTOPIA Level mode, AAL1gator-32 generally responds UTOPIA single port device. However, possible configure sink direction 4-port device where each A1SP different port. UTOPIA UTOPIA loopback, there 3-cell FIFO Block. Lineside Line-side loopback done A1SP Blocks. UI_EN UI_COMN_CFG register enables both source side sink side UTOPIA interface. This resets disabled state that chip resets with UTOPIA outputs tristated. Once modes have been configured interface enabled, then outputs will drive their correct values. block consists functions: Data Source Interface (SRC_INTF), Data Sink Interface(SNK_INTF), 8-cell FIFO (FF8CELL), 4-cell FIFO (FF4CELL), 3-cell FIFO (FF3CELL), UMUX, UI_REG. Figure block diagram AAL1_UI block.
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Figure Block Diagram
UTOPIA Interface (UI) Block UMUX SRC_INTF FF4CELL
Signals to/from each A1SP block
TXUTOPIA SIGNALS
UTOPIA Interface FIFO Output Logic
FF3CELL
Prioritization FIFO Input Logic
SNK_INTF FF8CELL UTOPIA Interface FIFO Input Logic
Signals to/from each A1SP block
RXUTOPIA SIGNALS
DEMUX FIFO Output Logic UI_REG
11.1.1 UTOPIA Source Interface (SRC_INTF) SRC_INTF block (shown Figure conveys cells received from UMUX block UTOPIA interface. Depending value UTOP_MODE field UI_SRC_CFG register, UTOPIA interface will either UTOPIA master (controls write enable signal) UTOPIA device (controls cell available signal). device, SRC_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device, SRC_INTF only function UTOPIA Level device. 16_BIT_MODE UI_SRC_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
master mode, SRC_INTF block sources TATM_D, TATM_PAR, TATM_SOC, TATM_ENB while receiving TATM_CLAV. Start-Of-Cell (SOC) indication generated coincident with first word (only 8-bit mode supported) each cell that transmitted TATM_D. TATM_D, TATM_PAR TATM_SOC driven times. TATM_ENB signal indicates which clock cycles contain valid data UTOPIA bus. device will assert TATM_ENB signal until full cell send target device activated TATM_CLAV. TATM_CLAV signal indicates whether target device able accept cells not. Only cell level handshaking supported. target device unable accept additional cells must deactivate TATM_CLAV later than byte current cell. additional cells will sent until TATM_CLAV activated. mode, SRC_INTF block sources RPHY_D[15:0], RPHY_PAR, RPHY_SOC, RPHY_CLAV, while receiving RPHY_ENB. indication generated coincident with first word (8-bit 16-bit) each cell that transmitted RPHY_D[15:0]. mode, RPHY_D[15:0], RPHY_PAR, RATM_SOC signals driven only when valid data being sent; otherwise they tristated. UTOPIA Level mode, RPHY_CLAV activated whenever complete cell available sent. remains active until last byte been read last available complete cell. cell sent cycle after RPHY_ENB goes low. RPHY_ENB goes high during cell transfer, data sent each cycle following where RPHY_ENB high. RPHY_ADD[4:0] input used only UTOPIA Level mode. cycle following where RPHY_ADD[4:0] matches CFG_ADDR(4:0) UI_SRC_ADD_CFG register, Block will drive RPHY_CLAV. Otherwise RPHY_CLAV tri-stated. addition, during previous cycle RPHY_ENB high current cycle, then device selected SRC_INTF begins transmitting cell next cycle. Parity driven TATM_PAR(RPHY_PAR) whenever TATM_D(RPHY_D[15:0]) driven. EVEN_PAR will determine whether even parity parity generated. Since parity required AForum, EVEN_PAR intended used error checking only. AAL1gator-32 tolerate temporary de-assertions TATM_CLAV/RPHY_ENB), assumed that enough UTOPIA bandwidth present accept cells that AAL1gator-32 produce timely manner. Once 4-Cell FIFO fills cells will begin filling 8cell FIFO each A1SP block. Anytime UTOPIA FIFO fills T_UTOP_FULL interrupt will active MSTR_INTR_REG enabled. This FIFO fill during normal operation usually indication
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
error. However, A1SP FIFOs should normally fill. they fill indicates there some congestion, which impacting UTOPIA interface TALP_FIFO_FULL will active A1SPn_INTR_REG. When TALP FIFO fills, then TALP longer able build cells data will start building transmit buffer frame_advance_fifo will fill. this continues that FR_ADV_FIFO_FULL goes active then data been lost transmit queues need reset. T_UTOP_FULL indicator used determine when UTOPIA Interface clears. also desirable disable UI_EN that stored cells flushed. SRC_INTF circuit controls when cell transmitted from internal cell FIFO. Since UTOPIA transmit cells higher speeds than TALP, since expected applications shared UTOPIA environment, cell transmission from SRC_INTF commences only when there full cell worth data available transmit. cell then transmitted interface UTOPIA TATM_CLK rate, accordance with TATM_FULLB/RPHY_ENB) input. maximum supported clock rate MHz. 11.1.1.1 Any-PHY Mode
ANY-PHY_EN UI_SRC_CFG register then SRC_INTF operates single port Any-PHY slave device. Any-PHY mode RPHY_ADDR(4) becomes depending value CS_MODE_EN, RPHY_ADDR(3) become RCSB signal instead. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address sending cell. SRC_INTF uses CFG_ADDR(15:0) UI_SRC_ADD_CFG register address prepend. 16_BIT_MODE then only lower bits used. During cycle that prepend address active bus, pulses high. Because large number possible ports, source direction, device addresses used polling device selection, instead port addresses. (Each device control many ports) When device selected send cell, device prepends port address front cell. Since, this direction AAL1gator-32 only single port, device address port address same. However, AAL1gator-32 only limited number address pins. accommodate systems, which using different port density Any-PHY devices, RCSB signal available handle additional external decoding that required. Any-PHY mode, devices respond with RPHY_CLAV cycles after their address instead cycle
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
required UTOPIA mode. However, timing RCSB matches UTOPIA timing that full cycle external decoding available. Table shows CFG_ADDR field used different modes. Table CFG_ADDR PHY_ADDR Usage direction Polling MODE UTOPIA-2 Single-Addr Any-PHY with Any-PHY without Notes: Any-PHY mode, direction AAL1gator-32 will prepend cell with CFG_ADDR[15:0]. 8-bit mode cell will prepended with CFG_ADDR[7:0] Any-PHY mode, CS_MODE_EN='1' then CFG_ADDR[4:3] "00". Any-PHY mode, CS_MODE_EN='0' then CFG_ADDR[4]="0". PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR [4:0]=device [2:0]=device Selection PHY_ADDR Pins [4:0]=device [2:0]=device CFG_ADDR prepended [3:0]=device [3:0]=device [3:0]=device CFG_ADDR prepended [15:0]=device CFG_ADDR [4:0]=device [15:0]=device
11.1.2 UTOPIA Sink Interface (SNK_INTF) SNK_INTF block receives cells from UTOPIA interface sends them UMUX interface. Depending value UTOP_MODE field UI_SNK_CFG register, UTOPIA interface acts either UTOPIA master (controls read enable signal) UTOPIA device (controls cell available signal). device SNK_INTF either UTOPIA Level device, where only device UTOPIA bus, UTOPIA Level device where other devices coexist UTOPIA bus. master device SNK_INTF only function UTOPIA Level device. 16_BIT_MODE UI_SNK_CFG register then bits UTOPIA data used. 16_BIT_MODE must UTOPIA master mode.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
master mode, SNK_INTF block receives RATM_D, RATM_PAR, RATM_SOC, RATM_CLAV while driving RATM_ENB. Once enabled this mode, and, RATM_CLAV input signal asserted, SNK_INTF block waits RATM_SOC signal from layer. Once RATM_SOC signal arrives, cell accepted soon possible. StartOf-Cell (SOC) indication received coincident with first word (only 8-bit mode supported) each cell that received RATM_D. cell FIFO allows interface accept data maximum rate. FIFO fills, RATM_ENB signal will asserted again until device ready accept entire cell. RATM_ENB signal depends only cell space independent state RATM_CLAV signal. RATM_CLAV signal indicates whether target device cell send not. Only cell level handshaking supported. mode, SNK_INTF block receives TPHY_D[15:0], TPHY_SOC, TPHY_ENB while driving TPHY_CLAV. cell available (TPHY_CLAV) signal indicates when device ready receive complete cell. UTOPIA Level mode, TPHY_CLAV always driven. UTOPIA Level mode, SNK_INTF normally responds single address device. However there situations some systems where groups cells targetted given A1SP clumped together. 8-cell A1SP FIFO fills that backs into 8-cell sink UTOPIA FIFO then head-ofline blocking problem exist. alleviate such situation, sink direction configured four separate addresses, where bottom bits address indicate which A1SP targeted receive cell. When polling A1SP addresses, full indication will given when A1SP FIFO associated with that address, reaches full state (room more cells) cell sink FIFO already cells that address. This will always allow room cells that still queued sink UTOPIA FIFO prevent head-of-line blocking. Full indications will given specific port until both full conditions cleared. When responding single address, TPHY_CLAV driven cycle following ones which TPHY_ADDR(4:0) matches CFG_ADDR(4:0) UI_SNK_ADD_CFG register. When responding addresses, TPHY_CLAV driven cycle following ones which TPHY_ADDR(4:2) matches CFG_ADDR(4:2) UI_SNK_ADD_CFG register. Otherwise TPHY_CLAV tristated. addition address match, during previous cycle TPHY_ENB high current cycle, then device selected SRC_INTF begins accepting cell that being received. SNK_INTF block waits SOC. When signal arrives, counter started, bytes received. occurs within cell, counter reinitializes. This means that corrupted cell will dropped
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
second good cell will received. SNK_INTF block stores cell receive FIFO. receive FIFO becomes full, stops receiving cells. bytes written FIFO with RATM_CLK. RATM_CLK input AAL1gator-32. maximum supported clock rate MHz. Parity always checked parity error will cause interrupt UTOP_PAR_ERR_EN MSTR_INTR_EN_REG. FORCE_EVEN_PARITY will determine whether even parity parity checked. Since parity required AForum, FORCE_EVEN_PARITY intended used error checking only. error detected UTOP_PAR_ERR MSTR_INTR_REG set, corresponding enable MSTR_INTR_EN_REG then INTB will active. cell received with parity will still processed normal. 11.1.2.1 Any-PHY Mode
ANY-PHY_EN UI_SNK_CFG register then SNK_INTF operates multi port Any-PHY slave device. Any-PHY mode TPHY_ADDR[4] becomes depending value CS_MODE_EN, TPHY_ADDR(3) become TCSB signal instead. Any-PHY mode in-band addressing used allow more than possible addresses available UTOPIA mode. extra word prepended front each cell that transmitted. prepended word indicates port address receive cell. SNK_INTF uses CFG_ADDR(15:2) UI_SNK_ADD_CFG register match with address prepend. 16_BIT_MODE then CFG_ADDR(7:2) used. During cycle that prepend address active bus, input pulses high. sink direction, port addresses used polling device selection, instead device addresses. Since, this direction AAL1gator-32 four ports, AAL1gator-32 will upper bits UI_SNK_ADD_CFG register address compares lower bits determine which A1SP being polled selected. However AAL1gator-32 only limited number address pins. accommodate systems, which using different port density Any-PHY devices, TCSB signal available handle additional external decoding that required. Any-PHY mode, devices respond with TPHY_CLAV cycles after their address instead cycle required UTOPIA mode. However timing TCSB matches UTOPIA timing that full cycle external decoding available. Table shows CFG_ADDR field used different modes.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Table CFG_ADDR PHY_ADDR Usage direction Polling MODE UTOPIA-2 Single-Addr UTOPIA-2 Multi-Addr Any-PHY with PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP [2]=device CFG_ADDR [4:0]=device [4:2]=device Selection PHY_ADDR Pins [4:0]=device [4:2]=device [1:0]=A1SP [2]=device [1:0]=A1SP addr prepended Any-PHY without [3:2]=device [1:0]=A1SP [3:2]=device [3:2]=device [1:0]=A1SP addr prepended [15:2]=device [15:2]=device CFG_ADDR [4:0]=device [4:2]=device
Notes: Any-PHY mode, CS_MODE_EN='1' then CFG_ADDR[4:3] "00". Else CS_MODE_EN='0' then CFG_ADDR[4]="0". Any-PHY mode upper bits prepended address compared with CFG_ADDR[15:2]. bottom bits compared with this field just used select target A1SP. 8-bit mode CFG_ADDR[7:2] used instead.
11.1.3 UTOPIA Block (UMUX) UMUX serves bridge between four A1SP blocks SNK_INTF SRC_INTF blocks. source direction, UMUX polls each four A1SP blocks Loopback FIFO using least recently serviced algorithm determine cell availability. this algorithm, once particular source serviced, lowest priority five sources. When higher priority source serviced, lower priority sources below move priority list. Thus, excluding initial start source which been serviced least recently will have highest priority. Figure below shows example changing priority list cells taken from A1SP0 A1SP2.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
RELEASED DATASHEET PMC-1980908 ISSUE
PM73122 AAL1GATOR-32
LINK CES/DBCES AAL1 PROCESSOR
Figure Source Priority Servicing Example
Time Priority Priority Priority Priority Priority A1SP0 A1SP1 A1SP2 A1SP3 LOOPB Priority Priority Priority Priority Priority Time A1SP1 A1SP2 A1SP3 LOOPB A1SP0 Priority Priority Priority Priority Priority Time A1SP1 A1SP3 LOOPB A1SP0 A1SP2
Initial Order
Order after A1SP0 sent cell
Order after A1SP1 does have cell send A1SP2 sent cell
When A1SP operated high-speed mode, companion A1SP within dual A1SP
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