The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.    


Datasheet Search Engine   
 
Part # or Description: • 5V RS232 Driver • 2SC5066* • "Real Time Clock" • "USB connector" • "blue led" 5mm • 10 watt zener diode • 2N3055* motorola
 
Search Tip: Try entering the part number only. Include a wildcard (eg. lm317* or 1n4148*)

 

 

FAST ETHERNET RISC PROCESSOR RISC Communication Semiconducto


Datasheet Thumbnail

   

Download PDF

Top Searches for this datasheet



R2010C
FAST ETHERNET RISC PROCESSOR
RISC Communication
Semiconductor Co., http://www.rdc.com.tw TEL: 886-3-666-2866 FAX: 886-3-563-1498
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
CONTENTS Features Block Diagram. Description.
Placement Functional Description. Capacitance Description. Pull-up/Pull-down Description.
Oscillator Characteristics
Fundamental Mode Third-Overtone Mode
Clock Unit Execution UNIT
General Registers Segment Registers. Instruction Pointer Status Flags Registers. Address Generation
Peripheral Register List.
Legacy Peripheral Registers (Base Address FF00h) 16550 UART Register Definitions (Base Address FF00h) Cache control register (Base Address FEC0h). SDRAM Control Registers (Base Address FE00h). Fast Ethernet Control Registers (Base Address: FE00h)
Peripheral Control Block Registers Reset
Power-up Reset.
Data Sheet Final Version December 2003
RDC®
10.1 10.2 10.3 10.4 10.5
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interface UNIT
Slow Memory Interface. Data Bus. Wait States Width
Chip Select UNIT.
11.1 11.2 11.3 11.4 UCS_n. LCS_n PCSx_n MCS_n
Refresh Control UNIT Interrupt Controller UNIT
13.1 13.2 13.3 Interrupt Vector, Type Priority Interrupt Requests Programming Registers.
UNIT
14.1 14.2 14.3 Operation External Requests Serial Port/DMA Transfer.
Timer Control UNIT.
15.1 15.2 Timer/Counter Unit Output Mode. Watchdog Timer
16550 UART Serial Port.
16.1 16.2 16.3 16.4 16.5 Receiver Buffer Register Transmitter Holding Register Divisor Latch Register. Interrupt Enable Register. Interrupt Identification Register. FIFO Control Register
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
16.6 Line Control Register 16.7 Modem Control Register. 16.8 Line Status Register 16.9 Modem Status Register 16.10 Scratchpad Register 16.11 Programmalbe Baud Generator. 16.12 FIFO Interrupt Mode Operation 16.13 FIFO Polled Mode Operation.
UNIT
17.1 Multi-Function List Table.
CACHE Controller
18.1 18.2 18.3 Cache Control Register Non-Cache Region Register. Write Invalid Region Register
SDRAM Controller.
19.1 19.2 19.3 SDRAM Mode Register SDRAM Control Register. SDRAM Timing Parameter Register
Fast Ethernet Controller.
20.1 Descriptor Format 20.2 Descriptor Format 20.3 MCR0: Control Register (00h) 20.4 MCR1: Control Register (04h) 20.5 MBCR: Control Register (08h).110 20.6 MTICR: Interrupt Control Register (0Ch). 20.7 MRICR: Interrupt Control Register (10h) 20.8 MTPR: Poll Command Register (14h).112 20.9 MRBSR: Buffer Size Register (18h).112 20.10 MRDCR: Descriptor Control Register (1Ah) .113 20.11 MLSR: Last Status Register(1Ch).113 20.12 MMDIO: MDIO Control Register (20h).114 20.13 MMRD: MDIO Read Data Register (24h) .115
Data Sheet Final Version December 2003
RDC®
20.14 20.15 20.16 20.17 20.18 20.19 20.20 20.21 20.22 20.23 20.24 20.25 20.26 20.27 20.28 20.29 20.30 20.31 20.32 20.33 20.34 20.35
R2010C
RISC Communication
Fast Ethernet RISC Processor
MMWD: MDIO Write Data Register (28h).115 MTDSA0: Descriptor Start Address (2Ch) .116 MTDSA1: Descriptor Start Address (30h).116 MRDSA0: Descriptor Start Address (34h).117 MRDSA1: Descriptor Start Address (38h).117 MISR: Status Register (3Ch).118 MIER: Enable Register (40h) .118 MECISR: Event Counter Status Register(44h) .119 MECIER: Event Counter Enable Register (48h) MRCNT: Successfully Received Packet Counter (50h) MECNT0: Event Counter (52H) MECNT1: Event Counter (54h). MECNT2: Event Counter (56h). MCENT3: Event Counter (58h). MTCNT: Successfully Transmit Packet Counter (5Ah) MCENT4: Event Counter (5Ch) MPCNT: Pause Frame Counter (5Eh) MAR0 Hash Table Word (60h, 62h, 64h, 66h) MID0 (68h, 6Ah, 6Ch). MID1 (70h, 72h, 74h). MID2 (78h, 7Ah, 7Ch). MID3 (80h, 82h, 84h).
Electrical Characteristics
21.1 21.2 Absolute Maximum Ratings (25) Operating Temperature.
Electrical Characteristics
22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Alphabetical Switching Parameter Symbols Numerical Switching Parameter Symbols. Bus. SDRAM Reset MDC/MDIO Timing Transmit Timing Parameters Transmit Timing Diagram
Data Sheet Final Version December 2003
RDC®
22.9 22.10
R2010C
RISC Communication
Fast Ethernet RISC Processor
Receive Timing Parameters. Receive Timing Diagram.
Instruction OP-Code Clock Cycles. R2010C Execution Timing. Package Information.
25.1 PQFP pins
Revision History.
Data Sheet Final Version December 2003
RDC®
Features
R2010C
RISC Communication
Fast Ethernet RISC Processor
Five-stage pipeline RISC architecture interface Multiplexed address Data Supports non-multiplexed address [20:0] 16-bit external dynamic access 16M-byte memory address space 64K-byte space Supports independent data/address external device Supports glueless simplified 16-bit PCMCIA interface
Three independent 16-bit timers independent programmable watchdog timer Interrupt controller with five maskable external interrupts independent channels Programmable chip-select logic Memory cycle decoder Programmable wait-state generator With 8-bit 16-bit Boot size 1-Port Fast Ethernet with interface Supports 8K-byte Uniform cache With 25MHz input frequency 100MHz maximum internal frequency. Compatible with 3.3V 2.5V core voltage. Package Type includes 128-pin PQFP.
Supports compatible UART serial channels with 16-byte FIFO hardware flow-control. Supports SDRAM control Interface
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Block Diagram
INT2 CLKOUTA INT6-INT5 INT0 INT1 TMROUT0 TMROUT1 TMRIN0 TMRIN1 DRQ0 DRQ1
Clock Power Management
Interrupt Control Unit
Timer Control Unit
Unit
RST_n
Cache MCS_n UCS_n PCS5_n, PCS3_n, PCS2_n, PCS0_n Chip Select Unit Instruction Decoder Control Signal Register File ARDY General, Refresh Control SD_CLK WE_n CAS_n RAS_n BA[1:0] SDRAM/Bus Interface Unit Unit Segment, Eflag Register Micro Instruction Queue (64bits)
Unit Address 16550 UART Serial Port0
DCD0_n SIN0 DSR0_n CTS0_n RI0_n RTS0_n SOUT0 DTR0_n SIN1
(Special, Logic, Adder, BSF)
Execution Unit
16550 UART Serial Port1
CTS1_n RTS1_n SOUT1
A[20:0] D[15:0]
RD_n WHB_n WLB_n WR_n/BWSEL
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Description
Placement
PCS0_n/PIO14 PCS5_n/PIO3 VDDIO ARDY VDDC RST_n COL1 TXEN1/CLKJMP TXD1_3/PDIVD0 TXD1_2/PDIVD1 TXD1_1/PDIVD2 VSSIO TXD1_0/PFEREQ0 TXCK1 RXCK1 RXD1_3 RXD1_2 RXD1_1 RXD1_0 RXDV1 MDC1 MDIO1 VSSC CLKOUTA
VSSIO VSSP2 VDDP2 INT2/PIO31 INT1 VSSC INT0/SA11 TMRIN1/PIO0/SA10 TMRIN0/PIO11/SA9 TMROUT1/PIO1/SA8 TMROUT0/PIO10/SA7 DRQ1/INT6/PIO13/SA6 DRQ0/INT5/PIO12/SA5 SIN0/SAD14 SOUT0/SAD13 RTS0_n/SAD9 VDDIO DTR0_n/SAD12 CTS0_n/SAD8 DSR0_n/SAD11 DCD0_n/SAD15 VDDC RI0_n/SAD10 SIN1 SOUT1 RTS1_n/TDO CTS1_n/TMS JTAGEN/SA3 PCS2_n/PIO25/IOR_n PCS3_n/PIO26/IOW_n VSSIO WHB_n/SA1 WLB_n/SA0 RD_n
R2010C 128-pin PQFP
SA16 VDDIO VSSIO VDDC UCS_n MCS_n VDDIO DQML WE_n CAS_n VSSC RAS_n VSSIO A10/MA10 A0/MA0 A1/MA1 A2/MA2/ A3/MA3 VDDIO SD_CLK VSSIO A4/MA4 A5/MA5 A6/MA6 A7/MA7 A8/MA8 A9/MA9 A11/SAD0
Data Sheet Final Version December 2003
WR_n/BWSEL VSSC A19/PIO9/ALE A18/PIO8/SAD7 VDDIO A17/PIO7/SAD6 A16/SAD5 A15/SAD4 A14/SAD3 A13/SAD2 A12/SAD1 VSSIO VDDC VSSP1 VDDP1 DQMH MA11/A20 VDDIO
RDC®
Input; Output;
R2010C
RISC Communication
Fast Ethernet RISC Processor
Functional Description
Pull 75K; Pull down 75K; Pull when PIOn used; Pull down when PIOn used;
Core
Symbol Type Description Reset input with Schmitt trigger. When RST_n asserted, immediately terminates operations, clears internal registers logic, changes address reset address FFFF00h. 25MHz frequency input, within tolerance, amplifier (oscillator). Frequency output from inverting amplifier (oscillator). CLKOUTA output frequency same input frequency. When high, CLKOUTA from Multiple-PLL. When low, CLKOUTA from
RST_n
I/PU
CLKOUTA
Interface Symbol Type Description Write high byte. This indicates that high byte data (D[15:8]) written memory device. This floats during reset hold conditions. SA1: slow address Write byte. This indicates that byte data (D[7:0]) written memory device. This floats during reset hold conditions. This must pulled low. SA0: slow address Read Strobe. active signal indicates that microcontroller performing memory read cycle. RD_n floats during hold reset. Write strobe. This indicates that data written into memory device. WR_n active during write cycle, floating during hold reset. BWSEL used decide boot width when RST_n
WHB_n/SA1
WLB_n/SA0
O/PU
RD_n
WR_n/BWSEL
O/PU
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
goes from high. BWSEL with external pull-low resistor (4.7k ohm), boot width bits. Otherwise boot width bits. Asynchronous ready. This indicates microcontroller that addressed memory space device will complete data transfer. ARDY accepts rising edge input that asynchronous SD_CLK active high. However, falling edge ARDY must synchronized SD_CLK. ARDY high, microcontroller always asserted ready condition. guarantee wait states inserted, ARDY must pulled before phase phase Please note that ARDY signal internally pulled high.
ARDY
I/PU
A19/PIO9/ALE A18/PIO8/SAD7 A17/ PIO7/SAD6 A16/SAD5 A15/SAD4 A14/SAD3 A13/SAD2 A12/SAD1 A11/SAD0 A10/MA10 A9/MA9 A8/MA8 A7/MA7 A6/MA6 A5/MA5 A4MA4 A3/MA3 A2/MA2 A1/MA1 A0/MA0
Address bus. Non-multiplexed memory addresses. address one-half SD_CLK period earlier than bus. address high-impedance state during hold reset. [7:0]: combination pins with addresses data. They designed slower peripheral bus. ALE: Address latch enable. Active high. This indicates address output bus. Address guaranteed valid trailing edge ALE. [10:0]: SDRAM column address output.
data memory accesses. data phase t2-t4 cycle. floating state during hold reset condition this also used load system configuration information (with pull-up pull-low resistor) into RESCON register when RST_n goes from high Watchdog timeout reset.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
SA16 O/PD I/O/PU I/O/PD SA4: slow address SA4: slow address SA16: slow address
Chip Select Unit Interface Symbol Type Description Upper memory chip select. UCS_n, this active when system accesses defined portion upper bytes (800000-FFFFFF) memory block. UCS_n defaulted active address region from FF0000h FFFFFFh after power-on reset. address range UCS_n programmed software. This incorporates weak pull-up resistor. Midrange Memory Chip Select MCS_n feature, this active when microcontroller accesses defined portion memory region. Peripheral chip selects/latched address bit. PCS_n feature, these pins active when micro-controller accesses fifth sixth region peripheral memory (I/O memory space). base address PCS_n programmable. These pins asserted with multiplexed address float during hold conditions. Peripheral chip selects. These pins active when microcontroller accesses defined peripheral memory block (I/O memory address). access, base address programmed region from 00000h 0FFFFh. memory address access, base address located 16M-Byte memory address region. These pins assert with multiplexed address float during holds. Peripheral chip selects. These pins active when micro controller accesses defined peripheral memory block (I/O memory address). access, base address programmed region from 00000h 0FFFFh. memory address access, base address located 16M-Byte memory address region. These pins assert with multiplexed address float during holds. When register FFEAh set, PIN36 IOR_n PIN37 IOW_n. IOR_n/IOW_n PCMCIA bus.
UCS_n
I/O/PU
MCS_n
O/PU
PCS5_n/PIO3
I/O/PU*
PCS0_n/PIO14
I/O/PU*
PCS2_n/PIO25/IOR_n PCS3_n/PIO26/IOW_n
I/O/PU*
Interrupt Control Unit Interface Symbol INT2/PIO31 Type I/O/PU* Description Maskable Interrupt Request
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
It's active high. interrupt input configured either edge-triggered level-triggered. requesting device must hold INT2 until request acknowledged guarantee interrupt recognition. Mask able Interrupt Request 1/slave select. Except differences interrupt line interrupt address vector, function INT1 same that INT2. Mask able interrupt request Except differences interrupt line interrupt address vector, function INT0 same that INT2. SA11: slow address
INT1
I/PD
INT0/SA11
I/PD
Timer Control Unit Interface Symbol Type Description Timer input. These pins used clock control signal input, depending upon programmed timer mode. After internally synchronizing high transitions TMRIN, timer controller increments. These pins must pulled being used. SA[10:9]: slow address Timer output. Depending timer mode select. These pins provide single pulse continuous waveform. duty cycle waveform programmable. These pins floated during hold reset. SA[8:7]: slow address
TMRIN1/PIO0/SA10 TMRIN0/PIO11/SA9
I/O/PU*
TMROUT1/PIO1/SA8 TMROUT0/PIO10/SA7
I/O/PD*
Unit Interface request. These pins asserted high external device when device ready channel channel perform transfer. These pins level-triggered internally synchronized. signals latched must remain active until serviced. INT6/INT5: When function used, INT6 INT5 used additional external interrupt request. they share corresponding interrupt type register control bits. INT6/5 level-triggered only. SA[6:5]: slow address
DRQ1/INT6/PIO13/SA6 DRQ0/INT5/PIO12/SA5
I/O/PU*
16550 UART
Symbol Type Description SIN0: Serial Input. Serial Data Input from communications link. SAD14: combination with Address Data. slower device bus. SOUT0: Serial Output. Composite serial data output communications link. SAD13: combination with Address Data.
SIN0/SAD14
I/O/PU
SOUT0/SAD13
I/O/PU
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
slower device bus. RTS0_n: Request Send. When low, this indicates MODEM data that URAT ready exchange data. SAD9: combination with Address Data. slower device bus. DTR0_n: Data Terminal Ready. When low, this informs MODEM data that UART ready establish communication link. SAD12: combination with Address Data. slower device bus. CTS0_n: Clear Send. When low, this indicates UART that MODEM data ready exchange data. SAD8: combination with Address Data. slower device bus. DSR0_n: Data Ready. When low, this indicates that MODEM data ready establish communication link with UART. SAD11: combination with Address Data. slower device bus. DCD0_n: Data Carry Detection. When low, indicates that data carrier been detected MODEM data set. SAD15: combination with Address Data. slower device bus. RI0_n: Ring Indicator. This indicates that telephone-ringing signal been received MODEM data set. SAD10: combination with Address Data. slower device bus. SIN1: Serial Data Input. SOUT1: Serial Data Output. This must pulled low. RTS1_n: Request Send. TDO: JTAG test data output pin. CTS1_n: Clear Send. JTAG Test mode select TCK: JTAG test clock input TDI: JTAG test data input
RTS0_n/SAD9
I/O/PU
DTR0_n/SAD12
I/O/PU
CTS0_n/SAD8
I/O/PU
DSR0_n/SAD11
I/O/PU
DCD0_n/SAD15
I/O/PU
RI0_n /SAD10
I/O/PU
SIN1 SOUT1 RTS1_n/TDO CTS1_n/TMS
I/PU I/PU I/PU
Data Sheet Final Version December 2003
RDC®
Interface
R2010C
RISC Communication
Fast Ethernet RISC Processor
Symbol TXD1_3/PDIVD0 TXD1_0/PEFREQ0
Type I/O/PU
Description Four parallel transmit data lines. This data synchronized assertion signal latched external rising edge signal. PDIVD [2:0] PFEREQ hardware configured pins during reset Multiple PLL. (See Chapter.5) PDIVD [2:0]: Multiple selections. PFEREQ [0]: Input clock range selection. This functions transmit enable. indicates that transmission active port external device. CLKJMP: hardware-configured pin, used select CLKOUTA output from internal Multiple When high, CLKOUTA from Multiple-PLL. When low, CLKOUTA from Supports transmit clock supplied external device. This clock should always active. Supports receive clock supplied external device. This clock should always active. Four parallel receive data lines. This data driven external that media attached should synchronized with signal. Data valid asserted external when received data present RXD1 [3:0] lines de-asserted packet. This functions collision detection. When external physical layer protocol (PHY) device detects collision, asserts this pin. management data clock sourced R2010C external devices timing reference information transfer MDIO signal. management data input/output transfers control information status between external R2010C.
TXD1_2/PDIVD1 TXD1_1/PDIVD2
I/O/PD
TXEN1/CLKJMP
I/O/PD
TXC1 RXC1 RXD1_3 RXD1_2 RXD1_1 RXD1_0 RXDV1
I/PD I/PD
I/PD
I/PD
COL1
I/PD
MDC1
MDIO1
I/O/PD
JTAG Enable
Symbol JTAGEN/SA3 Type I/O/PD Description JTAG function enable. Default pulled disabled. SA3: slow address
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
SDRAM Interface
Symbol Type Description SDRAM clock output. This clock output from internal De-skew PLL. four multiple input clock depending setting PFEREQ during power-on resets. [11]: SDRAM column address output Address SDRAM module must tied high. SDRAM/EDO write enable. SDRAM column address selector. SDRAM address selector. SDRAM bank address SDRAM bank address Input/Output mask. Input/Output mask.
SD_CLK
MA11/A20 WE_n CAS_n RAS_n DQML DQMH
Power Pins
17,43,64,74, 92,101,124 1,35,53,72,82, 100,115 22,57,99,122 6,40,84,104 Symbol VDDIO VSSIO VDDC VSSC VDDP1 VSSP1 VDDP2 VSSP2 Type power pin, pure 3.3V. ground pin. Core power pin, pure 2.5V. Core ground pin. De-skew power pin, pure 2.5V. De-skew ground pin. Multiple power pin, pure 2.5V. Multiple ground pin. Description
Notes: When Mode register Direction register configured modes, definition pins used pins. example, PCS5_n/PIO3 (Pin 125) used PIO3. Normal Mode (Bus Mode Memory mapped [20:0] [15:0]. [15:0] inactive this mode. Change Mode Mode means setting internal Control Register. This action must initialized software.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Since all/partial Slow Address, SA[11:0], multiplexed pins required, Control Register should enabled, then default settings disabled.
Symbol COUT CBID
Capacitance Description
Parameter 3.3V Input Capacitance 3.3V Output Capacitance 3.3V Bi-directional Capacitance Min. Typ. Max. Unit
Pull-up/Pull-down Description
Schmitt Trigger Tolerant When normal operation, these pins with neither pull-up pull-down resistors. However, when PIO, they input with pull-down resistors.
Name RST_n ARDY INT0/SA11 INT1 WR_n/BWSEL WLB_n/SA0 TMROUT0/SA7 TMROUT1/SA8 /PIO UCS_n MCS_n INT2 PCS0_n PCS2_n/IOR_n PCS3_n/IOW_n PCS5_n TMRIN0/SA9 TMRIN1/SA10 DRQ0/INT5/SA5 DRQ1/INT6/SA6 /PIO
Pull-up
Pull-down PIO10 PIO1
Description (0.25uM)
PIO31 PIO14 PIO25 PIO26 PIO3 PIO11 PIO0 PIO12 PIO13
When normal operation, these pins with neither pull-up pull-down resistors. However, when PIO, they input with pull-up, pull-down, schimitt trigger listed left table.
Data Sheet Final Version December 2003
RDC®
DCD0_n SIN0 SOUT0 DTR0_n DSR0_n RI0_n RTS0_n CTS0_n /SAD15-8 SOUT1 TXC1 RXC1 RXD1_3 RXD1_2 RXD1_1 RXD1_0 RXDV1 COL1
R2010C
RISC Communication
Fast Ethernet RISC Processor
41,42,44 66~71 75~79 45~49 50~52 54~56 58~59 88~91 93~96
TXD1_3/PDIVID0 TXD1_0/PFREQ0 TXD1_2/PDIVID1 TXD1_1/PDIVID2 TXEN1/CLKJMP MDIO1 JTAGEN/SA3 CLKOUTA WHB_n/SA1 RD_n A[17:19]/PIO A[0:10] A[11:16]
D[0:15]
SIN1 RTS1_n/TDO
Data Sheet Final Version December 2003
RDC®
MDC1 SD_CLK WE_n CAS_n RAS_N BA[0:1] DQML DQMH A20/MA11
R2010C
RISC Communication
Fast Ethernet RISC Processor
80~81
Note: pins never pull-up, pull-down, schimitt trigger, status shown above table.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Oscillator Characteristics
Fundamental Mode
R2010C
20pF 20pF mega-ohm
Third-Overtone Mode
Normally, high frequency third overtone mode price advantage, additional needed.
R2010C
200pF
Typical value suggestions follows:
20pF 20pF 200pF± Mega-Ohm 4.7uH, 6.8uH, 8.2uH, 10uH (25MHz)
Note: input clock must within 100ppm tolerance.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Clock Unit
CLKOUTA
Multiple
186Core
PFEREQ[0] TXC1 RXC1
PDIVD[2:0]
De-skew
SD_CLK
Configuration Table: Input Clock Range (Mhz) PFEREQ[0] PDIVD[2:0] Multiple Output Clock (Mhz) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved
example: input clock Mhz, then PFEREQ=1b. PDIVD[2:0]=000b, then output clock PDIVD[2:0]=011b, then output clock =100
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Execution UNIT
General Registers
R2010C eight 16-bit general registers. subdivided into 8-bit registers (AH, DL). functions these registers described follows: Word Divide, Word Multiply, Word operation. Byte Divide, Byte Multiply, Byte I/O, Decimal Arithmetic, Translate operation. Byte Divide, Byte Multiply operation. Translate operation. Loops, String operation Variable Shift Rotate operation. Word Divide, Word Multiply, Indirect operation Stack operations (POP, POPA, POPF, PUSH, PUSHA, PUSHF) General-purpose registers which used determine offset address operands Memory. String operations String operations
High
Data Group
Accumulator Base Register Count/Loop/Repeat/Shift Data Stack Pointer Base Pointer Source Index Destination Index
Index Group Pointer
GENERAL REGISTERS
Segment Registers
R2010C four 16-bit segment registers: segment registers contain base
addresses (starting location) these memory segments, they immediately addressable code (CS), data ES), stack (SS) memory. (Code Segment): register points current code segment, which contains instruction fetched. default location memory space instructions 64K. initial value register 0FFFFh. (Data Segment): register points current data segment, which generally contains program variables. register initialized 0000H. (Stack Segment): register points current stack segment, which stack operations, such
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
pushes pops. stack segment used temporary space. register initialized 0000H. (Extra Segment): register points current extra segment, which typically data storage, such large string operations large data structures. register initialized 0000H.
Code Segment Data Segment Stack Segment Extra Segment
SEGMENT REGISTERS
Instruction Pointer Status Flags Registers
(Instruction Pointer): 16-bit register contains offset next instruction
fetched. register cannot directly accessed software. This register update interface unit. changed, saved restored result program execution. register initialized 0000H starting execution address CS:IP 0FFFF00H.
Register Name: Reset Value
Processor Status Flags Register 0000h
Rsvd
Rsvd
Rsvd
Reserved
These flags reflect status after Execution Unit executed. 15-12 Name Rsvd Reserved. Overflow Flag. arithmetic overflow occurs, this flag will set. Direction Flag. this flag set, string instructions process incrementing address. cleared, string instructions process decrementing address. Refer instructions clear flag. Interrupt-Enable Flag. Refer instructions clear flag. enables mask able interrupt request. disables mask able interrupt request. Trace Flag. enable single-step mode debugging; Clear disable single-step mode. application program sets flag with POPF IRET instruction, debug
Description
Data Sheet Final Version December 2003
RDC®
Rsvd Rsvd Rsvd
R2010C
RISC Communication
Fast Ethernet RISC Processor
exception generated after instruction (The automatically generates interrupt after each instruction) that follows POPF IRET instruction. Sign Flag. this flag set, high-order result operation will indicating state being negative. Zero Flag. this flag set, result operation will zero. Reserved Auxiliary Flag. this flag set, there will carry from nibble high borrow from high nibble nibble general-purpose register. used operation. Reserved This flag will result low-order bits operation even parity. Reserved Carry Flag. set, there will carry borrow into high-order instruction result.
Address Generation
Execution Unit generates 24-bit physical address Interface Unit Address Generation.
Memory organized sets segments. Each segment contains 16-bit value. Memory addressed with two-component address that consists 16-bit segment 16-bit offset. Physical Address Generation figure describes logical address transferred physical address.
Shift left bits
Segment Base Logical Address Offset
Physical Address
Memory
Physical Address Generation
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Peripheral Register List
Peripheral Control Block mapped into either Memory space programming Peripheral Control Block Relocation Register (FEh). After reset, default Legacy Peripheral Control Block offset located FF00h space, SDRAM Control Register, EDO, Cache speed clock located FE00h space, Ethernet Control Register located FD00h FE00h space. following table lists definitions Peripheral Control Block Registers, detailed descriptions will arranged related Block Unit.
Legacy Peripheral Registers (Base Address FF00h)
Offset Register Name (HEX) Data Register Direction Register Mode Register Timer Mode Control Register Timer Maxcount Compare Register Timer Count Register Timer Mode Control Register Timer Maxcount Compare Register Timer Maxcount Compare Register Timer Count Register Timer Mode Control Register Timer Maxcount Compare Register Timer Maxcount Compare Register Timer Count Register Serial Port interrupt control register Serial port interrupt control register Interrupt Control Register INT2 Control Register INT1 Control Register INT0 Control Register 1/INT6 Interrupt Control Register 0/INT5 Interrupt Control Register Timer Interrupt Control Register Interrupt Status Register Interrupt Request Register Interrupt In-service Register Interrupt Priority Mask Register Interrupt Mask Register Interrupt Poll Status Register Interrupt Poll Register
Offset Register Name Page (HEX) Peripheral Control Block Relocation Register Processor Extended Register Reset Configuration Register Processor Release Level Register Auxiliary Configuration Register Control Register Watchdog Timer Control Register Enable Register Clock Pre-scaler Register Control Register Transfer Count Register Destination Address High Register Destination Address Register Source Address High Register Source Address Register Control Register Transfer Count Register Destination Address High Register Destination Address Register Source Address High Register Source Address Register Chip Size Multiplier Register MCS_n Extended Register PCS_n MCS_n Auxiliary Register Midrange Chip Select Register Peripheral Chip Select Register Memory Chip Select Register Upper Memory Chip Select Register (See 7.2) (See 7.2)
Data Sheet Final Version December 2003
Page
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt End-of-Interrupt (See 7.2) (See 7.2) (See 7.2) (See 7.2) (See 7.2)
(See 7.2) (See 7.2) (See 7.2) Data Register Direction Register Mode Register
16550 UART Register Definitions (Base Address FF00h) Mnemonic Page
RBR0 THR0 DLL0 IER0 DLH0 IIR0 FCR0 LCR0 MCR0 LSR0 MSR0 SCR0 RBR1 THR1 DLL1 IER1 DLH1 IIR1 FCR1 LCR1 MCR1 LSR1 MSR1 SCR1
Offset Register Name (HEX) Receiver Buffer Register (when DLAB=0 Read) UART0 Transmitter Holding Register (when DLAB=0 Write) UART0 Divisor Latch [Low Byte] (when DLAB=1) UART0 Interrupt Enable Register (when DLAB=0) UART0 Divisor Latch [High Byte] (when DLAB=1) UART0 Interrupt Identification Register (when Read) UART0 FIFO Control Register (when Write) UART0 Line Control Register UART0 MODEM Control Register UART0 Line Status Register UART0 MODEM Status Register UART0 Scratch Register UART1 Receiver Buffer Register (when DLAB=0 Read) UART1 Transmitter Holding Register (when DLAB=0 Write) UART1 Divisor Latch [Low Byte] (when DLAB=1) UART1 Interrupt Enable Register (when DLAB=0) UART1 Divisor Latch [High Byte] (when DLAB=1) UART1 Interrupt Identification Register (when Read) UART1 FIFO Control Register (when Write) UART1 Line Control Register UART1 MODEM Control Register UART1 Line Status Register UART1 MODEM Status Register UART1 Scratch Register
Offset (HEX)
Cache control register (Base Address FEC0h) Register Name
Cache control register Non-Cache region0 Starts Address High Non-Cache region0 Starts Address Non-Cache region0 Address High Non-Cache region0 Address Non-Cache region1 Starts Address High Non-Cache region1 Starts Address Non-Cache region1 Address High Non-Cache region1 Address Non-Cache region2 Starts Address High
Mnemonic Page
NCR0SH NCR0SL NCR0EH NCR0EL NCR1SH NCR1SL NCR1EH NCR1EL NCR2SH
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
NCR2SL NCR2EH NCR2EL NCR3SH NCR3SL NCR3EH NCR3EL WIRSH WIRSL WIREH WIREL
Non-Cache region2 Starts Address Non-Cache region2 Address High Non-Cache region2 Address Non-Cache region3 Starts Address High Non-Cache region3 Starts Address Non-Cache region3 Address High Non-Cache region3 Address Write-Invalidate region Starts Address High Write-Invalidate region Starts Address Write-Invalidate region Address High Write-Invalidate region Address
Offset (HEX)
SDRAM Control Registers (Base Address FE00h) Register Name
SDRAM Mode Register SDRAM Control Register SDRAM Timing Parameter Register
Mnemonic Page
SDRAMMSR SDRAMCR SDRAMTPR
Offset (HEX)
Fast Ethernet Control Registers (Base Address: FE00h) Register Name
Control Register Control Register Control Register Interrupt Control Register Interrupt Control Register Poll Command Register Buffer Size Register Descriptor Control Register Last Status Register MDIO Interface Register Read Data Register Write Data Register Descriptor Start Address Register Descriptor Start Address Register Descriptor Start Address Register Descriptor Start Address Register Status Register Enable Register Event Counter Status Register Event Counter Mask Register Successfully Received Packet Counter Event Counter Register Event Counter Register Event Counter Register Event Counter Register Successfully Transmit Packet Counter Register
Mnemonic Page
MCR0 MCR1 MBCR MTICR MRICR MTPR MRBSR MRDCR MLSR MMDIO MMRD MMWD MTDSA0 MTDSA1 MRDSA0 MRDSA1 MISR MIER MECISR MECIER MRCNT MECNT0 MECNT1 MECNT2 MECNT3 MTCNT
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
MECNT4 MPCNT MAR0 MAR1 MAR2 MAR3 MID0L MID0M MID0H MID1L MID1M MID1H MID2L MID2M MID2H MID3L MID3M MID3H
Event Counter Register Pause Frame Counter Register Hash Table Word Hash Table Word Hash Table Word Hash Table Word Multicast Address first bytes Register Multicast Address second bytes Register Multicast Address last bytes Register Multicast Address first bytes Register Multicast Address second bytes Register Multicast Address last bytes Register Multicast Address first bytes Register Multicast Address second bytes Register Multicast Address last bytes Register Multicast Address first bytes Register Multicast Address second bytes Register Multicast Address last bytes Register
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Peripheral Control Block Registers
peripheral control block mapped into either memory space programming Peripheral Control Block Registers (FEh Registers). starts FF00h space after reset.
Register Offset: Register Name: Reset Value
Reserved
Peripheral Control Block Relocation Register 20FFh
M/IO_n
R[23:12] R[19:8]
Peripheral Control Block (PCB) mapped into either memory space programming this register. When other chip selects (PCSx_n) programmed zero wait state external ready ignored, PCSx_n overlap control block. 15-13 Name Rsvd Attribute Reserved. Memory/IO space. reset, this starts FF00h space. located memory space. located space (Default). Relocation Address Bits. upper address bits base address. space, lower eight bits defaulted 00h. When mapped into space, R[19:16] must programmed 0000b. memory space, R[19:8] mapped into A[23:12] lower twelve bits defaulted 000h. Description
M/IO_n
11-0
R[23:12] R[19:8]
Register Offset: Register Name: Reset Value
Processor Release Level Register 1AD9h
read only registers specify processor release version identification number. 15-12 11-8 Name Attribute 4'b0001 Processor version. identification number 8'hD9. Description
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Processor Extended Register 1602h
PEID
15-0
Name PEID
Attribute
Description This read only register specifies identification extended number.
Data Sheet Final Version December 2003
RDC®
Reset
R2010C
RISC Communication
Fast Ethernet RISC Processor
Processor initialization accomplished with activation RST_n pin. reset processor, this should held least seven oscillator periods. Reset Status Figure shows status RST_n other related pins. When RST_n goes from high, state input pins (with weak pull-up pull-down resistors) will latched, each will perform individual function. D[15:0] will latched into register F6h. D[15:0] will drive address phase data phase during UCS_n LCS_n cycles WLB_n with pull-high resistor.
Power-up Reset
SD_CLK
RST_n
A[23:0] (float)
ffff0
D[15:0]
(input)
fff0
(float)
RD_n
(float)
(input)
UCS_n
Reset Status
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
SD-CLK min.=10ms RST_n
Internal Reset 819.2us Input 25MHz)
Power-up Reset Timing
Register Offset: Register Name: Reset Value
Reset Configuration Register D[15:0]
Name
Attribute
Description Reset Configuration D[15:0]. D[15:0] must with weak pull-up pull-down resistors correspond contents when they latched into this register RST_n signal goes from high. value reset configuration register provides system information when software reads this register. This register read only contents remain valid until next processor reset.
15-0
Data Sheet Final Version December 2003
RDC®
10.1
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interface UNIT
Slow
Control Register 0000h
PCSE SLAS Reserved
Register Offset: Register Name: Reset Value
BMOD
Reserved
Name
Attribute
Description Mode Select bit. Slow mode. When PCS/MCS regions accessed, cycle mapped [15:0] [7:0]. Normal mode. When PCS/MCS regions accessed, cycle mapped [23:0] [15:0]. inactive this mode. Reserved IOR_n, IOW_n control signal enable When this set. PIN36 IOR_n PIN37 IOW_n. When this clear. PIN36 PCS2/PIO25 PIN37 PCS3/PIO26. address selection bits 000: slow address. 001: SLA5.0 010: SLA7.0 011: SLA11.0 Reserved
BMOD
14-7
Rsvd PCSE
SLAS
Rsvd
10.2
Memory Interface
memory space consists bytes 16-bit port) space consists bytes (32k 16-bit port). Memory devices exchange information with during memory read, memory write instruction fetch cycles. read write cycles separate address space. Only IN/OUT instruction access address space, information must transferred between peripheral devices register. first bytes space accessed directly instructions. entire bytes address space accessed indirectly, through register. instructions always force address A[23:16] level.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
FFFFFFH
Memory Space
Bytes 0FFFFH
Space
Bytes
Memory Space
10.3
Data
memory address space data physically implemented dividing address space into banks bytes. Each bank connects lower half data contains even-addressed bytes (A0=0). other bank connects upper half data contains odd-addressed bytes (A0=1). WHB_n WLB_n determine whether bank both banks participate data transfer.
Bytes FFFFFF FFFFFD
Bytes FFFFFE FFFFFC
A23:1
D15:8
WHB_n
D7:0
WLB_n
Physical Data Models
Data Sheet Final Version December 2003
RDC®
10.4
R2010C
RISC Communication
Fast Ethernet RISC Processor
Wait States
Wait states extend data phase cycle. ARDY input with level will insert wait states. avoid wait states, ARDY must high within specified setup time prior phase keep phase insert wait states, ARDY must driven within specified setup time prior phase phase When SDRAMEN SDRAM Control Register (FEF4h) external ready ARDY internal wait states ignored while accessing SDRAMs.
Case Case Case Case
SD_CLK
ARDY(Normally Not-Ready System)
Asynchronous Ready Waveforms
SD_CLK
ARDY (Normally Ready System)
Asynchronous Ready Waveforms
Data Sheet Final Version December 2003
RDC®
10.5
R2010C
RISC Communication
Fast Ethernet RISC Processor
Width
R2010C default 16-bit access programmed 8-bit 16-bit access during memory access located LCS_n PCSx_n address space. UCS_n code- fetched selection 8-bit 16-bit width, which decided BWSEL (pin42) input status when RST_n goes from high. When BWSEL with pull-low resistor, width code-fetched selection bits. SDRAM width unchangeable bits. R2010C been 16-bit mode, cannot changed 8-bit mode.
Register Offset: Register Name: Reset Value
PCS5
Auxiliary Configuration Register 0080h
PCS2 Reserved USIZ MSIZ PCS0
PCS3
11-8
Name Rsvd PCS5 PCS3 PCS2 Rsvd
Attribute Reserved
Description
Space Data Size selection. This determines width data space accesses. 8-bit data access. 16-bit data access. Space Data Size selection. This determines width data space accesses. 8-bit data access. 16-bit data access. Space Data Size selection. This determines width data space accesses. 8-bit data access. 16-bit data access. Reserved Boot code width. This reflects BWSEL input status when RST_n goes from high. 16-bit width booting when BWSEL without pull-low resistor. (Default: internal pull-high resistor.) 8-bit width booting when BWSEL with 4.7k external pull-low resistor. Reserved Midrange Data Size selection. This determines width data space accesses mapped memory space). 8-bit data access. 16-bit data access. Space Data Size selection. This determines width data space accesses. 8-bit data access. 16-bit data access.
USIZ
Rsvd
MSIZ
PCS0
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Chip Select UNIT
Chip Select Unit provides programmable chip select pins access specific memory peripheral device. chip selects programmed through four peripheral control registers (A0h, A2h, A8h) chip selects insert wait states programming peripheral control registers.
11.1
UCS_n
UCS_n default active reset Code access. active memory range upper (800000h FFFFFFh), which programmable. default memory active range UCS_n (FF0000h FFFFFFh). UCS_n will drive within four SD_CLK cycles when active wait state inserted. There fifteen wait states inserted UCS_n active cycle reset.
Register Offset: Register Name: Reset Value
Upper Memory Chip Select Register F03Bh
LB[2:0]
Name Rsvd
Attribute Reserved.
Description
14-12
LB[2:0]
LB[2:0], Memory block size selection UCS_n chip select pin. active region UCS_n chip select configured LB[2:0]. default memory block size from 800000h FFFFFFh. Please refer following Upper Memory Block Size table register FFAAh 5-3. Reserved Bit[1:0]. Ready Mode. This used configure ready mode UCS_n chip select. external ready ignored. external ready required. Bit3, 1-0: R[1:0], Wait-State value. R2010C insert wait states access UCS_n memory cycle. reset value (R3, Wait States
11-4
Rsvd
R[1:0]
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Upper Memory Block Size table: LB[2:0] FFAAh 512K 256K 512K 128k 256K 512K 128k 256K 512K
11.2
LCS_n
LCS_n means lower memory region chip selects. active memory range lower (000000h 7FFFFFh), which programmable. expanded bytes FFAAh b2:0.
Register Offset: Register Name: Reset Value
Memory Chip Select Register
LB[2:0]
Name Rsvd
Attribute Reserved
Description
14-12 LB[2:0]
LB[2:0], Memory block size selection LCS_n chip select pin. active region LCS_n chip select configured LB[2:0].The LCS_n active reset, read write access Memory Chip Select Register (A2h) activates this pin. Please refer following Memory Block Size table register FFAAh 2-0. Reserved
11-0
Rsvd
Memory Block Size table: LB[2:0] FFAAh bit2-0 128K 256K 512K 128K 256K 512K 256K 512K 512K
Data Sheet Final Version December 2003
RDC®
11.3
R2010C
RISC Communication
Fast Ethernet RISC Processor
PCSx_n
order define these pins, peripheral memory chip selects programmed through registers. base address memory block located anywhere within bytes memory space, exclusive areas associated with LCS_n UCS_n. chip selects mapped space, access range bytes. PCS5_n configured from 31wait states) wait states). PCS3_n PCS0_n configured from wait states) wait states). PCSx_n pins active reset. PCSx_n pins activated chip selects writing peripheral chip select register
Register Offset: Register Name: Reset Value
Peripheral Chip Select Register 0000h
BA23 BA22 BA21 BA20
BA[19:12]
15-8
Name BA[19:12] BA[23:20]
Attribute
Description Base Address. BA[23:12] corresponds [23:12] 16M-Byte(24-bits) programmable base address PCS_n chip select block. When PCS_n chip selects mapped space, BA[23:16] must written 0000b because address only bytes (16-bits) wide. Please refer following Peripheral Chip Size table register FFAAh 8-6. Bit[1:0]. Ready Mode. This configured enable/disable ready mode PCS3_n PCS0_n chip selects. external ready ignored. external ready required. 1-0: Wait-State Values. (refer register), determine number wait states inserted into PCS3_n PCS0_n access. PR4, Wait States -100 -125 -150 -180 -210 -255
R[1:0]
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Peripheral Chip Size table: FFAAh bit8-6 PCS0 BASE BASE BASE BASE BASE PCS2 BASE+512 BASE+1024 BASE+2048 BASE+4096 BASE+8192 PCS3 BASE+768 BASE+1536 BASE+3072 BASE+6144 BASE+12288 PCS5 BASE+1280 BASE+2560 BASE+5120 BASE+10240 BASE+20480
11.4
MCS_n
Midrange Chip Select Register 0000h
BA23 BA22 BA21 BA20
Register Offset: Register Name: Reset Value
BA[19:12]
base address integer multiple size memory block size selected this Midrange Chip Select Register. example, midrange block 16Kbytes, block could located 100000h, 104000h, 108000h, 102000h. Name Attribute Description Base Address. BA[23:12] corresponds [23:12] 16M-Byte (24-bits) programmable base address chip select block. Bit[1:0]. Ready Mode. This configured enable/disable ready mode chip selects. external ready ignored. external ready required. 1-0: Wait-State Values. determine number wait states inserted into MCS_n access. With regard values please refer FFACh register. Wait States
15-4 BA[19:12] BA[23:20]
R[1:0]
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
-100
Register Offset: Register Name: Reset Value
PCS_n MCS_n Auxiliary Register
M[6:0] Rsvd
Name Rsvd
Attribute Reserved MCS_n Block Size (M[6:0]). M[6:0] 0000001b 0000010b 0000100b 0001000b 0010000b 0100000b 1000000b Reserved
Description
14-8
M[6:0]
Total Block Size 128K Reserved Reserved
Rsvd
Memory space selector. This determines whether PCS_n pins active during memory cycle cycle. PCS_n active memory cycle. PCS_n active cycle. bit[1:0] register. bit[1:0] Ready Mode. This only applies PCS5_n chip select. external ready ignored. external ready required. 1-0: Wait-State Values. determine number wait states inserted into PCS5_n access. Wait States
R[4:3]
R[1:0]
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Register Offset: Register Name: Reset Value
Rsvd
Chip Size Multiplier Register 0000h
Reserved P[2:0] U[2:0] L[2:0]
W[2:0]
Name Rsvd
Attribute Reserved
Description
Wait-State Value. W[2:0] determine number wait states inserted into PCS5_n PCS3_n PCS0_n access. Wait States Reserved chip select size multiplier chip select size multiplier chip select size multiplier
14-12
W[2:0]
11-9
Rsvd P[2:0] U[2:0] L[2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
MCS_n Extended Register
15-5
Name Rsvd Rsvd W[2:0]
Attribute Defaulted
Description
Deaulted Please description register. Defaulted Wait-State Value. Defaulted
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Refresh Control UNIT
Refresh Control Unit (RCU) automatically generates refresh cycle. After period time, generates memory read request interface unit. user guide program SDRAM: Configure Lower Memory Chip Select Register (A2h) Chip Size Multiplier Register (AAh) SDRAM space. Clock Pre-scaler Register (E2h) enable Register (E4h) enable SDRAM refresh.
Register Offset: Register Name: Reset Value
Clock Pre-scaler Register 0080h
RC[14:0]
Name Rsvd
Attribute Reserved
Description
14-0 RC[14:0]
Refresh Counter Reload Value. contains value desired clock count interval between refresh cycles. counter value should less than 12h, otherwise there would never sufficient cycle available processor execute code. Example: SDRAM specification specifies refresh time every 15.6 system clock 25Mhz. Refresh Counter Reload Value 15.6us*25Mhz 15.6us 40ns 390.
Register Offset: Register Name: Reset Value
Enable Register 8000h
T[14:0]
Name
Attribute
Description Enable Enable refresh counter unit. Clear refresh counter stop refresh requests, will reset refresh address. Refresh Count. This read-only field contains present value down counter which triggers refresh requests.
14-0
T[14:0]
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt Controller UNIT
There interrupt request sources connected controller: maskable interrupt pins (INT[0:2], INT5, INT6); non-mask able interrupts (WDT); internal unit request sources (Timer MAC; Asynchronous Serial Port
Timer0/1/2 Interrupt REQ.
Interrupt Type
DMA0 DMA0 Interrupt REQ. INT5 DMA1 DMA1 Interrupt REQ. INT6
Interrupt REQ.
Execation Unit
Watchdog Timer
INT0
Interrupt Control Logic
INT1
INT2
Register
Asynchronous Serial Port
Acknowledge
In-Service Register
Asynchronous Serial Port
Acknowledge DMA, Timer,Serial port Unit
Internal Address/Data
Interrupt Control Unit Block Diagram
Data Sheet Final Version December 2003
RDC®
13.1
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt Vector, Type Priority
following table shows interrupt vector address, type priority. maskable interrupt priority changed programming priority registers. vector address each interrupt fixed. Interrupt source Divide Error Exception Trace interrupt Breakpoint Interrupt INTO Detected Over Flow Exception Array Bounds Exception Undefined code Exception code Exception Timer Reserved 0/INT5 1/INT6 INT0 INT1 INT2 Asynchronous Serial port Timer Timer Asynchronous Serial port Reserved Interrupt Type 15h-1Fh Vector Address Type Priority Note
Note When interrupt occurs same time, priority (1-1 1-2); (2-1> 2-3)
13.2
Interrupt Requests
When interrupt requested, internal interrupt controller verifies interrupt enabled (the flag enabled set) that there higher priority interrupt requests being serviced pending. interrupt granted, interrupt controller uses interrupt type access vector from interrupt vector table. external active (level-trigger) request interrupt controller service, pins must held till micro controller entering interrupt service routine. There interrupt-acknowledge output when running fully nested mode, should simulate interrupt-acknowledge necessary.
Data Sheet Final Version December 2003
RDC®
13.3
R2010C
RISC Communication
Fast Ethernet RISC Processor
Programming Registers
Software programmed through registers (44h, 42h, 40h, 3Ch, 3Ah, 38h, 36h, 34h, 32h, 30h, 2Eh, 2Ch, 2Ah, 28h, 26h, 22h) define interrupt controller operation.
Register Offset: Register Name: Reset Value
Serial Port Interrupt Control Register 001Fh
Reserved
15-4
Name Rsvd
Attribute Reserved
Description
Mask. Mask interrupt source asynchronous serial port Enable serial port interrupt. Priority. These bits determine priorities serial ports relative other interrupt signals. priority selection: PR2, PR1, Priority (High) (Low)
PR[2:0]
Register Offset: Register Name: Reset Value
Serial Port Interrupt Control Register 001Fh
Reserved
Data Sheet Final Version December 2003
RDC®
15-4 Name Rsvd
R2010C
RISC Communication
Fast Ethernet RISC Processor
Attribute Reserved
Description
Mask. Mask interrupt source asynchronous serial port Enable serial port interrupt. Priority. These bits determine priorities serial ports relative other interrupt signals. priority selection: PR2, PR1, Priority (High) (Low)
PR[2:0]
Register Offset: Register Name: Reset Value
Interrupt Control Register 000Fh
Reserved
Reserved
15-8
Name Rsvd ERsvd L
Attribute Reserved
Description
Edge trigger mode enabled. When this cleared interrupt triggered edge from MAC, which goes from high. high edge will latched (one level) till this interrupt serviced. Reserved Level-Triggered Mode. high active level triggers interrupt. interrupt triggered high edge. Mask. Mask interrupt source MAC. Enable interrupt. Interrupt Priority. These settings priority selections same those register.
PR[2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
INT2 Control Register 000Fh
Rsvd
Reserved
15-8
Name Rsvd ERsvd
Attribute Reserved
Description
Edge trigger mode enable. When this cleared interrupt triggered edge going from high. high edge will latched (one level) till this interrupt serviced. Reserved Edge/Level Select Falling edge/Low level trigger. Rising edge/High level trigger. Level-Triggered Mode. Interrupt triggered level. interrupt triggered edge. Mask. Mask interrupt source INT2. Enable INT2 interrupt. Interrupt Priority. These settings priority selections same those register.
L
PR[2:0]
Register Offset: Register Name: Reset Value
INT1 Control Register 000Fh
SFNM
Reserved
15-8
Name Rsvd E
Attribute Reserved
Description
Edge trigger mode enabled. When this cleared interrupt triggered edge going from high. high edge will latched (one level) till this interrupt serviced. Special Fully Nested Mode. Enable special fully nested mode INT1 Edge/Level Select
SFNM
Data Sheet Final Version December 2003
RDC®
L
R2010C
RISC Communication
Fast Ethernet RISC Processor
falling edge level trigger rising edge /High level trigger Level-Triggered Mode. Interrupt triggered level. interrupt triggered edge. Mask. Mask interrupt source INT1. Enable INT1 interrupt. Interrupt Priority. These settings priority selections same those register.
PR[2:0]
Register Offset: Register Name: Reset Value
INT0 Control Register 000Fh
SFNM
Reserved
15-8
Name Rsvd E
Attribute Reserved
Description
Edge trigger mode enabled. When this cleared interrupt triggered edge going from high. high edge will latched (one level) till this interrupt serviced. Special Fully Nested Mode. Enable special fully nested mode INT0 Edge/Level Select Falling edge/Low level trigger. Rising edge/High level trigger. Level-Triggered Mode. Interrupt triggered level. interrupt triggered edge. Mask. Mask interrupt source INT0. Enable INT0 interrupt. Interrupt Priority. These settings priority selections same those register.
SFNM
L
PR[2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
DMA1/INT6 Interrupt Control Register 000Fh
15-6
Name Rsvd Rsvd
Attribute Reserved Level Select Low-level trigger. High-level trigger. Reserved
Description
Mask. Mask interrupt source DMA1 controller. Enable DMA1 controller interrupt. Interrupt Priority. These settings priority selections same those register.
PR[2:0]
Register Offset: Register Name: Reset Value
DMA0/INT5 Interrupt Control Register 000Fh
15-6
Name Rsvd Rsvd
Attribute Description Reserved Level Select Low-level trigger. High-level trigger. Reserved Mask. Mask interrupt source DMA0 controller. Enable DMA0 controller interrupt. Interrupt Priority. These settings priority selections same those register.
PR[2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Interrupt Control Register 000Fh
15-4
Name Rsvd
Attribute Reserved
Description
Mask. Mask interrupt source timer controller. Enable timer controller interrupt. Interrupt Priority. These settings priority selections same those register.
PR[2:0]
Register Offset: Register Name: Reset Value
DHLT
Interrupt Status Register 0000h
Reserved Rsvd
TMR2 TMR1 TMR0
reset value defined. 14-6 Name DHLT Rsvd Rsvd TMR[2:0] Attribute Description Halt. Halt activity when non-mask able interrupts occur. When IRET instruction executed. Reserved Indicate that controller interrupt request while Reserved Indicate that corresponding timer interrupt request pending while
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt Request Register 0000h
D1/I6 D0/I5 Rsvd
Reserved
Interrupt Request register read-only register. internal interrupts (SP0, SP1, D1/I6, D0/I5, MAC, TMR), corresponding when device requests interrupt. reset during internally generated interrupt acknowledge. INT[2:0] external interrupts, corresponding bits (I[3:0]) reflect current values external signals. 15-11 Name Rsvd I[3:0] D1/I6 D0/I5 Rsvd Attribute Description Reserved Serial Port Interrupt Request. Indicates interrupt status serial port Serial Port Interrupt Request. Indicates interrupt status serial port Interrupt Request. Indicates interrupt status MAC. Interrupt Requests. corresponding interrupt pending. Channel Interrupt Request. corresponding channel interrupt pending. Reserved Timer Interrupt Request. timer control unit interrupt pending.
Register Offset: Register Name: Reset Value
In-Service Register 0000h
D1/I6 D0/I5 Rsvd
Reserved
These bits this Register interrupt controller when interrupt taken. Each register cleared writing corresponding interrupt type register. 15-11 Name Rsvd Attribute Reserved Serial Port Interrupt In-Service. serial port interrupt currently being serviced.
Description
Data Sheet Final Version December 2003
RDC®
I[3:0] D1/I6 D0/I5 Rsvd
R2010C
RISC Communication
Fast Ethernet RISC Processor
Serial Port Interrupt In-Service. serial port interrupt currently being serviced. In-Service. Indicates interrupt currently being serviced. Interrupt In-Service. corresponding interrupt currently being serviced. Channel Interrupt In-Service. corresponding channel interrupt currently being serviced. Reserved Timer Interrupt In-Service. timer interrupt currently being serviced.
Register Offset: Register Name: Reset Value
Priority Mask Register 0007h
PRM2 PRM1 PRM0
determines minimum priority level which mask able interrupts generate interrupts. 15-3 Name Rsvd Attribute Reserved Priority Field Mask, determining minimum priority that required order mask able interrupt source generate interrupt. PR[2:0] Priority (High) (Low) Description
PRM[2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt Mask Register FFFFh
D1/I6 D0/I5 Rsvd
Reserved
15-11
Name Rsvd I[3:0] D1/I6 D0/I5 Rsvd
Attribute Reserved
Description
Serial Port Interrupt Mask. When this indicates that asynchronous serial port interrupt masked. Serial Port Interrupt Mask. When this indicates that asynchronous serial port interrupt masked. Interrupt Mask. When this indicates that interrupt masked. External Interrupt Mask. When I3-I0 bits indicate that corresponding interrupts masked. Channel Interrupt Masks. When these bits indicate that corresponding interrupts masked. Reserved Timer Interrupt Mask. When this indicates that Timer controller interrupt masked.
Register Offset: Register Name: Reset Value
IREQ
Poll Status Register
S[4:0]
Reserved
Poll Status (POLLST) register mirrors current state Poll register. POLLST register read without affecting current interrupt requests. 14-5 Name IREQ Rsvd S[4:0] Attribute Description Interrupt Request. interrupt pending. S[4:0] field contains valid data. Reserved Poll Status. indicates interrupt type highest priority pending interrupts.
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
IREQ
R2010C
RISC Communication
Fast Ethernet RISC Processor
Poll Register
S[4:0]
Reserved
When Poll register read, current interrupt acknowledged next interrupt takes place Poll register. 14-5 Name IREQ Rsvd S[4:0] Attribute Description Interrupt Request. interrupt pending. S[4:0] field contains valid data. Reserved Poll Status. indicates interrupt type highest priority pending interrupts.
Register Offset: Register Name: Reset Value
NSPEC
Interrupt Write Only
S[4:0]
Reserved
14-5
Name NSPEC Rsvd S[4:0]
Attribute
Description Non-Specific EOI. indicates non-specific EOI. indicates specific interrupt type S[4:0]. Reserved Source Type. specifies type interrupt that currently being processed.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
UNIT
controller provides data transfer between memory peripherals without intervention CPU. There channels unit. Each channel accept requests from three sources: external pins (DRQ0 channel DRQ1 channel serial ports (port port Timer overflow. data transfer from sources destinations memory memory, memory I/O, I/O, memory. Either bytes words transferred from even addresses cycles necessary (read from sources write destinations) each data transfer.
24-bit Adder/Subtractor
Adder Control Logic
CAH.4-Channel TDRQ DAH.4-Channel
Timer Request C8h-Transfer Counter Channel C2h,C0h-Source Address Channel C6h,C4h-Destination Address Channel D8h-Transfer Counter Channel D2h,D0h-Source Address Channel D6h,D4h-Destination Address Channel DAh.8-Channel Channel Control Register0,CAh
Control Logic
Request Arbitration Logic
DRQ0 DRQ1 Serial Port0 Serial Port1 Interrupt Request CAh.8-Channel
Channel Control Register1,DAh
Internal Address/Data
Unit Block
14.1
Operation
Every transfer consists cycles (see figure Typical Transfer) cycles cannot separated hold request, refresh request, another request. registers (CAh, C8h, C6h, C4h, C2h, C0h, DAh, D8h, D6h, D4h, D2h, D0h) used configure operate channels.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
SD_CLK A[23:0] D[15:0] RD_n
Address Address
Data
Data
WR_n
Typical Trarsfer
Register Offset: Register Name: Reset Value
(DMA0) DMA0 Control Register 0000h
SINC
SYN1
SYN0
TDRQ
B_n/W
DM/IO_n DDEC
DINC SM/IO_n SDEC
definitions [15:0] DMA0 same those [15:0] Register DMA1.
Register Offset: Register Name: Reset Value
(DMA0) DMA0 Transfer Count Register 0000h
TC[15:0]
15-0
Name TC[15:0]
Attribute
Description transfer Count. value this register will decremented after each transfer.
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
(DMA0) DMA0 Destination Address High Register
Reserved
DDA[23:16]
15-8
Name Rsvd
Attribute Reserved
Description
DDA[23:16]
High Destination Address. These bits mapped A[23:16] during transfer when destination address memory space space. destination address space (64Kbytes), these bits must programmed 00000000b.
Register Offset: Register Name: Reset Value
(DMA0) DMA0 Destination Address Register
DDA[15:0]
Name
Attribute
Description Destination Address. These bits mapped A[15:0] during transfer. value [23:0] will incremented decremented after each transfer.
15-0 DDA[15:0]
Register Offset: Register Name: Reset Value
(DMA0) DMA0 Source Address High Register
Reserved
DSA[23:16]
15-8
Name Rsvd
Attribute Reserved
Description
DSA[23:16]
High Source Address. These bits mapped A[23:16] during transfer when source address memory space space. source address space (64Kbytes), these bits must programmed 00000000b.
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
(DMA0) DMA0 Source Address Register
DSA[15:0]
Name
Attribute
Description Source Address. These bits mapped A[15:0] during transfer. value [23:0] will incremented decremented after each transfer.
15-0 DSA[15:0]
Register Offset: Register Name: Reset Value
(DMA1) DMA1 Control Register 0000h
SINC
SYN1
SYN0
TDRQ
B_n/W
DM/IO_n DDEC
DINC DM/IO_n SDEC
Name DM/IO_n
Attribute
Description Destination Address Space Select. destination address memory space. destination address space. Destination Decrement. destination address automatically decremented after each transfer. B_n/W (bit determines decrement value, which when both DDEC DINC bits address remains constant. Disable decrement function. Destination Increment. destination address automatically incremented after each transfer. B_n/W (bit determines incremented value Disable increment function. Source Address Space Select. Source address memory space. Source address space. Source Decrement. Source address automatically decremented after each transfer. B_n/W (bit determines decremented value when both SDEC SINC bits address remains constant. Disable decrement function.
Data Sheet Final Version December 2003
DDEC
DINC
SM/IO_n
SDEC
RDC®
SINC
R2010C
RISC Communication
Fast Ethernet RISC Processor
Source Increment. Source address automatically incremented after each transfer. B_n/W (bit determines incremented value Disable decrement function. Terminal Count. synchronized transfer terminated when Transfer Count Register reaches synchronized transfer terminated when Transfer Count Register reaches Unsynchronized transfer always terminated when transfer count register reaches regardless setting this bit. Interrupt. unit generates interrupt request when transfer count completed. must generate interrupt. Synchronization Type Selection. SYN1 SYN0 Synchronization Type Unsynchronized Source synchronized Destination synchronized Reserved Priority. selects high priority this channel when both transferred same time. Timer Enable/Disable Request. Enable requests from timer Disable requests from timer This enables external interrupt functionality corresponding pin. external requests passed interrupt controller. functions pin. Changed Start Bit. This must when modified. Start/Stop channel. Start channel Stop channel Byte/Word Select. address incremented decremented after each transfer. 0:The address incremented decremented after each transfer. Only byte transfer supported either source destination width bit.
SYN[1:0]
TDRQ
B_n/W
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
(DMA1) DMA1 Transfer Control Register 0000h
TC[15:0]
15-0
Name TC[15:0]
Attribute
Description transfer Count. value this register will decremented after each transfer.
Register Offset: Register Name: Reset Value
(DMA1) DMA1 Destination Address High Register
Reserved
DDA[23:16]
15-8
Name Rsvd
Attribute Reserved
Description
DDA[23:16]
High Destination Address. These bits mapped A[23:16] during transfer when destination address memory space space. destination address space (64Kbytes), these bits must programmed 00000000b.
Register Offset: Register Name: Reset Value
(DMA1) DMA1 Destination Address Register
DDA[15:0]
Name
Attribute
Description Destination Address. These bits mapped A[15:0] during transfer. value [23:0] will incremented decremented after each transfer.
15-0 DDA[15:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
(DMA1) DMA1 Source Address High Register
Reserved
DSA[23:16]
15-8
Name Rsvd
Attribute Reserved
Description High Source Address. These bits mapped A[23:16] during transfer when source address memory space space. source address space (64Kbytes), these bits must programmed 00000000b.
DSA[23:16]
Register Offset: Register Name: Reset Value
(DMA1) DMA1 Source Address Register
DSA[15:0]
Name
Attribute
Description Source Address. These bits mapped A[15:0] during transfer. value DSA[23:0] will incremented decremented after each transfer.
15-0 DSA[15:0]
14.2
External Requests
External requests asserted pins. pins sampled falling edge SD_CLK. takes minimum four clocks before cycle initiated Interface. request cleared four clocks before cycle. acknowledge provided, since chip-selects (PCSx_n) programmed active given block memory space, source destination address registers programmed point same given block. transfer either source- destination-synchronized, also unsynchronized. Source-Synchronized Transfer figure shows typical source-synchronized transfer, which provides source device least three clock cycles from time. acknowledged dessert line.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Fetch Cycle CLKOUTA
Fetch Cycle
DRQ(Case1) DRQ(Case2)
NOTES: Case1 Current source synchronized transfer will immediately followed another transfer. Case2 Current source synchronized transfer will immediately followed antoher transfer.
Source-Synchronized Transfers
Destination-Synchronized Transfer figure shows typical destination-synchronized transfer, which differs from source-synchronized transfer which idle states added deposit cycle. idle states extend cycle allow destination device de-assert four clocks before cycle. idle states were inserted, destination device would have time de-assert signal.
Fetch Cycle CLKOUTA
Deposit Cycle
DRQ(Case1) DRQ(Case2) NOTES: Case1 Current destination synchronized transfer will immediately followed another transfer. Case2 Current destination synchronized transfer will immediately followed another transfer.
Destination-Synchronized Transfers
Data Sheet Final Version December 2003
RDC®
14.3
R2010C
RISC Communication
Fast Ethernet RISC Processor
Serial Port/DMA Transfer
serial port data transfer from memory space. B_n/W Control Register must byte transfer. address Transmit Data Register written Destination Address Register memory address written Source Address Register, when data transmitted. address Receive Data Register written Source Address Register memory address written Destination Address Register, when data received. software programmed through Serial Port Control Register perform serial port/ transfer. When channel serial port, corresponding external request signal deactivated. serial port, channel should configured being destination-synchronized. from serial port, channel should configured source-synchronized.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Control UNIT
TMRIN1 TMRIN0 Microprocessor Clock
50h,Timer Count Register TMROUT1 52h,54h,Timer0 Maxcount Compare Register 58h,Timer Count Register 5Ah,5Ch,Timer Maxcount Compare Register 60h,Timer Count Register 62h,Timer Compare Register Counter Element Control Logic TMROUT0 (Timer2) (Timer0,1,2) Request Interrupt Request
56h,Timer Control Register
5Eh,Timer Control Register 66h,Timer Control Register
Internal Address/Data
Timer Counter Unit Block
There three 16-bit programmable timers R2010C. timer operation independent CPU. These three timers programmed timer element counter element. Timer each connected external pins (TMRIN0, TMROUT0, TMRIN1 TMROUT1), which used count time external events, used generate variable-duty-cycle waveforms. Timer connected external pins. used pre-scaler Timer Timer request source.
Register Offset: Register Name: Reset Value
INH_n
Timer Mode/Control Register 0000h
CONT
These definitions timer same those register timer
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Count Register
TC[15:0]
Name
Attribute
Description Timer Count Value. This register contains current count Timer count incremented every internal processor clocks, pre-scaled Timer incremented every external clock which through configuring external clock select based TMRIN0 signal.
15-0 TC[15:0]
Register Offset: Register Name: Reset Value
Timer Maxcount Compare Register
TC[15:0]
Name
Attribute Timer Compare Value.
Description
15-0 TC[15:0]
Register Offset: Register Name: Reset Value
Timer Maxcount Compare Register
TC[15:0]
Name
Attribute Timer Compare Value.
Description
15-0 TC[15:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
INH_n
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Mode/Control Register 0000h
CONT
Name
INH_n
11-6
Rsvd
Attribute Description Enable Bit. timer enabled. timer inhibited from counting. INH_n must during writing bit, INH_n must same write. Inhibit Bit. This allows selective updating bit. INH_n must during writing bit, both INH_n must same write. This stored always read Interrupt Bit. interrupt request generated when count register equals maximum count. timer configured dual max-count mode, interrupt generated each time count reaches Max-Count Max-Count Timer will issue interrupt request. Register Bit. Maxcount Compare Register timer being used. Maxcount Compare Register timer being used. Reserved Maximum Count Bit. When timer reaches maximum count, will H/W. dual maxcount mode, this each time either Maxcount Compare Maxcount Compare register reached. This regardless (offset [15]). Re-trigger Bit. This defines control function input signal TMRIN1 pin. When EXT=1 (5Eh.2), this ignored. Timer1 Count Register (58h) counts internal events; Reset counting every TMRIN1 input signal going from high (rising edge trigger). input holds timer Count Register (58h) value; High input enables counting which counts internal events. definition setting (EXT, RTG) Timer1 counts internal events. TMRIN1 remains high. Timer1 counts internal events; count register resets every rising transition TMRIN1 pin. TMRIN1 input acts clock source timer1 count register incremented every external clocks. Pre-scaler Bit. This (5Eh [2]) define timer clock source. definition setting (EXT, Timer1 Count Register incremented every internal processor clocks. Timer1 Count Register incremented which pre-scaled Timer TMRIN1 input acts clock source Timer1 Count Register incremented every external clocks.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
CONT
External Clock Bit. Timer clock source from external. Timer clock source from internal. Alternate Compare Bit. This controls whether timer runs single dual maximum count mode. Specify dual maximum count mode. this mode, timer counts Maxcount Compare then resets count register timer counts Maxcount Compare then resets count register again, starts over with Maxcount Compare Specify single maximum count mode. this mode, timer counts value contained Maxcount Compare reset then timer counts Maxcount Compare again. Maxcount Compare used this mode. Continuous Mode Bit. timer runs continuously. timer will halt after each counting maximum count will cleared.
Register Offset: Register Name: Reset Value
Timer Count Register
TC[15:0]
Name
Attribute
Description Timer Count Value. This register contains current count timer count incremented every internal processor clocks, pre-scaled Timer incremented every external clocks which through configuring external clock select based TMRIN1 signal.
15-0 TC[15:0]
Register Offset: Register Name: Reset Value
Timer Maxcount Compare Register
TC[15:0]
Name
Attribute Timer Compare Value.
Description
15-0 TC[15:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Maxcount Compare Register
TC[15:0]
Name
Attribute Timer Compare Value.
Description
15-0 TC[15:0]
Register Offset: Register Name: Reset Value
INH_n
Timer Mode/Control Register 0000h
CONT
Name
Attribute
Description Enable Bit. Timer enabled. Timer inhibited from counting. INH_n must during writing bit, INH_n must same write. Inhibit Bit. This allows selective updating bit. INH_n must during writing bit, both INH_n must same write. This stored always read Interrupt Bit. interrupt request generated when count register equals maximum count. Timer will issue interrupt request. Reserved Maximum Count Bit. When timer reaches maximum count, will H/W. This regardless (66h.15). Reserved Continuous Mode Bit. timer continuously running when reaches maximum count. (66h [15]) cleared timer held after each timer count reaches maximum count.
INH_n
12-6
Rsvd Rsvd
CONT
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timer Count Register
TC[15:0]
Name
Attribute
Description Timer Count Value. This register contains current count Timer count incremented every internal processor clocks.
15-0 TC[15:0]
Register Offset: Register Name: Reset Value
Timer Maxcount Compare Register
TC[15:0]
Name
Attribute Timer Compare Value.
Description
15-0 TC[15:0]
15.1
Timer/Counter Unit Output Mode
Timers maximum count value maximum count values. Timer only maximum count value. Timer Timer1 configured single dual maximum count mode, TMROUT0 TMROUT1 signals used generate waveforms various duty cycles.
Maxcount Dual Maximum Count Mode Single Maximum Count Mode Maxcount
Maxcount
Maxcount
Maxcount
Maxcount
Maxcount
1T:One Microprocessor clock
Timer/Counter Unit Output Modes
Data Sheet Final Version December 2003
RDC®
15.2
R2010C
RISC Communication
Fast Ethernet RISC Processor
Watchdog Timer
R2010C independent watchdog timer, which programmable. watchdog timer active after reset timeout count with maximum count value. keyed sequence (3333h, CCCCh) must written register (E6h) first, then configuration Watchdog Timer Control Register. single write, every writing Watchdog Timer Control Register will follow this rule. When watchdog timer activates, internal counter counting. this internal count over watchdog timer duration, watchdog timeout happens. keyed sequence (AAAAh, 5555h) must written register (E6h) reset internal count prevent watchdog timeout. internal count should reset before Watchdog Timer timeout period modified ensure that immediate timeout will occur.
Register Offset: Register Name: Reset Value
WRST
Watchdog Timer Control Register C080h
Rsvd
RSTFLAG NMIFLAG
COUNT
Name
Attribute Enable Watchdog Timer. Enable Watchdog Timer. Disable Watchdog Timer.
Description
WRST
Watchdog Reset. generates system reset when timeout count reached. generates interrupt when timeout count reached NMIFLAG NMIFLAG will generate system reset when timeout. Reset Flag. When watchdog timer reset event occurred, hardware will this This will cleared keyed sequence write this register external reset. This after external reset after watchdog timer reset. Flag. After generates interrupt, this will H/W. This will cleared keyed sequence written this register. Reserved
RSTFLAG
11-8
NMIFLAG Rsvd
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Timeout Count. COUNT setting determines duration watchdog timer timeout interval. Exponent duration equation: Duration (Frequency/2) Exponent COUNT setting: (Bit (Exponent) (N/A) Watchdog timer Duration reference table: example: System clock =100Mhz frequency exponent=10, then Duration 100Mhz 2048 100Mhz 20.48
Frequency\ Exponent
COUNT
27.3 20.5
55.9 111.8 223.7 447.4 894.8 1.79 41.9 83.9 167.8 335.5 1.34
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
16550 UART Serial Port
system programmer access UART registers summarized following Table CPU. These registers control UART operation which transmission reception data status included, each register Table name.
Register Address
Register Name
Receiver Buffer Register Transmitter Holding Register Divisor Latch(LS) Interrupt Enable Register Divisor Latch(MS) Interrupt Identified Register FIFO Control Register
Mnem. 15-8
Note.
RBR[0] DLAB=0 read only DLAB=0 write only DLAB=1
80h/10h
RBR[7] RBR[6] RBR[5]
RBR[4] RBR[3] RBR[2] RBR[1]
THR[7] THR[6]
THR[5]
THR[4] THR[3] THR[2] THR[1]
THR[0]
DL[7]
DL[6]
DL[4]
DL[4]
DL[3]
DL[2]
DL[1]
DL[0]
82h/12h
EMSI
ERLSI ETHREI
ERDAI
DLAB=0
DL[15] DL[14] FIFO Enabled (Note)
DL[13]
DL[12]
DL[11] DL[10]
DL[9]
DL[8]
DLAB=1
84h/14h
FIFO Enable (Note) RCVR DMAC Trigger TL2-0 Level (MSB) DLAB
IID[2]
IID[1]
IID[0]
Read Only
RCVR Trigger Reserve Reserve Mode Level Select (LSB)
XMIT FIFO Reset
RCVR FIFO Reset WLS[1]
FIFO Enabled
Write Only
86h/16h
88h/18h
Line Control Register MODEM Control Register Line Status Register MODEM Status Register Scratch Register
WLS[0]
Loop
LDCD
8Ah/1Ah
Error RCVR TEMT FIFO (Note)
THRE
8Ch/1Ch
DDCD
TERI
DDSR
DCTS
8Eh/1Eh
SCR[7] SCR[6] SCR[5]
SCR[4] SCR[3] SCR[2] SCR[1]
SCR[0]
Note: These bits always 16450 mode.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
RCLK RCLK_BAUD BRGE
BAUD RATE GENRATOR
BAUD
A[2:0]
FIFO TRANSMIT MACHINE
SOUT
DI[7:0] DA[7:0]
S.R:Shift Register
UARTINT
Control
RECEIVE MACHINE FIFO
Modem Outputs
MODEM CONTROL
Modem Iutputs
UART Block Diagram
16.1
Receiver Buffer Register Transmitter Holding Register
UART0 Receiver Buffer Register
Register Offset: Register Name: Reset Value
[7:0]
This register Receiver Buffer Register when DLAB=0 read function operated.
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
UART0 Transmitter Holding Register
[7:0]
This register Transmitter Holding Register when DLAB=0 write function operated.
16.2
Divisor Latch Register
divisor value, DLL[15:0], host clock Baud Rate. example: Host Clock=75Mhz, Baud Rate=57600, then Divisor=75Mhz/16/57600=81.3
Register Offset: Register Name: Reset Value
UART0 Divisor Latch (LS) Register
[7:0]
This register Divisor Latch (LS) Register when DLAB=1.
Register Offset: Register Name: Reset Value
UART0 Divisor Latch (MS) Register
[15:8]
This register Divisor Latch (MS) Register when DLAB=1.
Data Sheet Final Version December 2003
RDC®
16.3
R2010C
RISC Communication
Fast Ethernet RISC Processor
Interrupt Enable Register
This Interrupt Enable Register (IER) enables four types UART interrupts. Each interrupt individually activate interrupt output signal (UARTINT). possible totally disable interrupt system resetting bits through Interrupt Enable Register. Similarly, setting relative register will enable selected interrupt(s). Disabling interrupt prevents from being indicated being active from activating UARTINT output signal. other system functions operate their normal manners, including setting Line Status MODEM Status Registers. details each described below:
Register Offset: Register Name: Reset Value
UART0 Interrupt Enable Register XX00h
BMSI ERLSI ETHREI ERDAI
Name Rsvd EMSI ERLSI ETHREI
Attribute Reserved always
Description
MODEM Status Interrupt bit. enable MODEM Status Interrupt. Enable Receiver Line Status Interrupt bit. enable Receiver Line Status Interrupt. Enable Transmitter Holding Register Empty Interrupt bit. enable Transmitter Holding Register Empty Interrupt. Enable Received Data Interrupt bit. enable Received Data Available Interrupt (and timeout interrupts FIFO mode).
ERDAI
16.4
Interrupt Identification Register
This read only register. order provide minimum software overhead during data character transfers, UART prioritizes interrupts into four levels records these Interrupt Identification Register (IIR). four levels interrupt conditions priority order Receiver Line Status, Received Data Ready, Transmitter Holding Register Empty, MODEM Status. When accesses IIR, UART freezes interrupts indicates highest priority pending interrupt CPU. While this access occurring, UART records interrupts, does change current indication until access complete. details each Interrupt Identification Register described below.
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
UART0 Interrupt Identified. Register (Read Only) XX01h
FIFOs
FIFOs
IID2
IID1
IID0
Enabled Enabled
Name FIFOs Enabled Rsvd IID2
Attribute
Description These bits when [0]=1. Reserved always Interrupt indicator. NS16450 Mode, this FIFO mode, this along with when timeout interrupt pending. Interrupt indicator. These bits used identify highest priority interrupt pending indicated following table: Interrupt Pending indicator. This used prioritized interrupt environment indicate whether interrupt pending not. Indicate that interrupt pending. Indicate that interrupt pending contents used pointer appropriate interrupt service routine.
IID[1:0]
Interrupt Control Function: FIFO Interrupt Mode Identification Only Register Interrupt Reset Functions Priority Interrupt Type Level None Highest Receiver Line Status Interrupt Source none overrun error, parity error, framing error, break interrupt received data available trigger level reached Interrupt Rest Control reading line status register reading receiver buffer register FIFO dropping below trigger level reading receiver buffer register
Second
Received Data Available
Second
Character Timeout Indication
Third
Transmitter Holding Register Empty
character been removed from input RCVR FIFO during last characters times there least character during this time transmitter holding reading register register empty source interrupt available) writing into transmitter holding register
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
MODEM Status clear send, data reading modem status ready, ring indicator, data register carrier detect
Fourth
16.5
FIFO Control Register
FIFO Control Register (write only) same location Interrupt Identification Register (read only). This register used enable FIFO, clear FIFO, RCVR FIFO trigger level, select type signaling.
Register Offset: Register Name: Reset Value
UART0 FIFO Control Register (Write Only) X000h
DMACTL[2:0] Rsvd
RCVR RCVR Trigger Trigger (MSB) (LSB)
XMIT RCVR FIFO Mode FIFO FIFO Enabled Select Reset Reset
Name
Attribute
Description With transfers listed follows, users configure these bits UART Port. DMACTL [2:0] Receive Transmit DMA0 DMA1 DMA1 DMA0 Reserved Reserved DMA0 DMA1 DMA0 DMA1 RCVR Trigger. These bits used trigger level RCVR FIFO interrupt. RCVRTL[1:0] RCVR FIFO Trigger Level (Bytes) Bytes Bytes Bytes Bytes Reserved Mode Select. Setting FCR0[3]=1 will cause UART change from mode mode FCR0[0]=0. XMIT FIFO Reset. Writing FCR0[2] clears bytes XMIT FIFO resets counter logic shift register cleared. that written this position self-clearing.
10-8
DMACTL [2:0]
RCVRTL [1:0]
Rsvd Mode Select XMIT FIFO Reset
Data Sheet Final Version December 2003
RDC®
RCVR FIFO Reset
R2010C
RISC Communication
Fast Ethernet RISC Processor
FIFO Enabled
RCVR FIFO Reset. Writing FCR0[1] clears bytes RCVR FIFO resets counter logic shift register cleared. that written this position self-clearing. FIFO Enable. Writing FCR0 enables both XMIT RCVR FIFO. Resetting FCR0[0] will clear bytes both FIFO. When changing from FIFO Mode NS16450 Mode vice versa, data automatically cleared from FIFOs. This must when written other bits they will programmed.
16.6
Line Control Register
system programmer specifies format asynchronous data communications exchange sets Divisor Latch Access Line Control Register (LCR). programmer also read contents Line Control Register. read capability simplifies system programming eliminates need separate storage system memory line characteristics. detailed contents each register follows:
Register Offset: Register Name: Reset Value
UART0 Line Control Register XX00h
DLAB Break Stick Parity
WSL1 WSL0
Name
Attribute
Description Divisor Latch Access bit. access Divisor Latches Baud Generator during Read Write operation. access Receiver Buffer, Transmitter Holding Register, Interrupt Enable Register Break Control bit. causes break condition transmitted receiving UART. serial output (SOUT) forced Spacing (logic state. Break disabled. Break Control acts only SOUT effect transmitter logic. Note: This feature enables alert terminal computer communications system. following sequence followed, erroneous extraneous characters will transmitted because break. 1.Load character, response THRE.
Data Sheet Final Version December 2003
DLAB
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
2.Set break after next THRE. 3.Wait transmitter idle, (TEMT clear break when normal transmission restored. During break, Transmitter used character timer accurately establish break duration.
Stick Parity bit. 5=1, 4=1, 3=1, Parity transmitted checked logic 5=1, 4=0, 3=1, Parity transmitted checked logic 5=0, Stick Parity disabled. Even Parity Select bit. 3=1, number logic transmitted checked data word bits Parity bit. 3=1, even number logic transmitted checked. Parity Enable bit. Parity generated (transmit data) checked (receive data) between last data word Stop serial data. (The Parity used produce even number when data word bits Parity summed.) Stop bit. This specifies number Stop bits transmitted received each serial character. Stop generated transmitted data. half stop bits generated 5-bit word length characters. stop bits generated 8-bit word length characters. receiver checks first Stop only, regardless number Stop bits selected. These specify number bits each transmitted received serial character. WLS[1:0] Character Length 5-bit character 6-bit character 7-bit character 8-bit character
WLS[1:0]
16.7
Modem Control Register
This Modem Control Register controls interface with MODEM data peripheral device emulating MODEM). details described below:
Register Offset: Register Name: Reset Value
UART0 MODEM Control Register XX00h
Data Sheet Final Version December 2003
RDC®
Name Rsvd
R2010C
RISC Communication
Fast Ethernet RISC Processor
Loop LDCD
Attribute Reserved always
Description
Autoflow Control Enabled when set. configured bits 1and shown following table. bit5(AFE) bit1(RTS) Auto-RTS auto-CTS enabled Auto-CTS enabled disabled This provides local loop back feature diagnostic testing UART. following occur: transmitter Serial Output (SOUT) Marking (logic state. receiver Serial Input (SIN) disconnected. output Transmitter Shift Register "looped back" into Receiver Shift Register input. four MODEM Control inputs (CTS_n, DSR_n, RI_n, DCD_n) disconnected, MODEM Control outputs (DTR_n RTS_n) internally connected MODEM Control inputs (DSR_n, CTS_n), MODEM Control output pins forced their inactive state (high). diagnostic mode, data transmitted immediately received. This feature allows processor verify transmitted received data paths UART. diagnostic mode, receiver transmitter interrupts fully operational. MODEM Control Interrupts also operational, sources interrupts lower four bits MODEM Control Register instead four MODEM Control inputs. interrupts still controlled Interrupt Enable Register. Bit3: controls DCD_n signal internal loop back mode enabled. Bit2: controls RI_n signal internal loop back mode enabled. Request Send bit. This controls Request Send (RTS_n) output. RTS_n output forced logic RTS_n output forced logic Data Terminal Ready indicator. This controls Data Terminal Ready (DTR_n) output. DTR_n output forced logic DTR_n output forced logic Note: DTR_n output UART applied inverting line driver (such DS1488) obtain proper polarity input succeeding MODEM data set.
Loop
LDCD,
Data Sheet Final Version December 2003
RDC®
16.8
R2010C
RISC Communication
Fast Ethernet RISC Processor
Line Status Register
This register provides status information part processing data transfer. contents each Line Status Register described below.
Register Offset: Register Name: Reset Value
UART0 Line Status Register XX60h
THRE
Error RCVR TEMT (Note
Name
Attribute
Description Error Receive FIFO. NS16450 Mode, this FIFO mode, when there least parity error, framing error break indication FIFO. cleared when reads LSR, there subsequent errors FIFO. Note: Line Status Register intended read operations only. Writing this register recommended this operation only used factory testing. Transmitter Empty indicator. This whenever Transmitter Holding Register (THR) Transmitter Shift Register (TSR) both empty. This reset whenever either Transmitter Holding Register Transmitter Shift Register contains data character. FIFO mode, this whenever transmitter FIFO shift register both empty. Transmitter Holding Register Empty indicator. This indicates that UART ready accept character transmission. addition, this causes UART issue interrupt when Transmit Holding Register Empty Interrupt Enable high. This will when character transferred from Transmitter Holding Register into Transmitter Shift Register. This reset upon loading character Transmitter Holding Register. FIFO mode, this when XMIT FIFO empty; cleared when least byte written XMIT FIFO. Break Interrupt indicator. This will whenever received data input held Spacing (logic state longer than full word transmission time (that total time Start Data Bits Parity Stop Bit). This will reset whenever reads contents Line Status Register. FIFO mode, this error associated with particular character FIFO applies This error revealed when associated character FIFO. When break occurs, only zero character loaded into FIFO. next character transfer enabled after goes marking state receives next valid start bit.
Error RCVR (Note
TEMT
THRE
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
Note: Bits through error conditions that produce Receiver Line Status interrupt whenever corresponding conditions detected interrupt enabled. Framing Error indicator. This indicates that received characters don't have valid Stop Bit. This will whenever Stop follows last data Parity detected logic (Spacing level). Automatic whenever reads contents Line Status Register. FIFO mode, this error associated with particular character FIFO applies This error revealed when associated character FIFO. UART will resynchronize after framing error occurs. this, assumes that framing error next start bit, samples this "start" twice then takes "data". Parity Error indicator. This indicates that received data character does have correct even parity, selected even-parity select bit. This will upon detection parity error. Automatic whenever reads contents Line Status Register. FIFO mode, this error associated with particular character FIFO applies This error revealed when associated character FIFO. Overrun Error indicator. This indicates that data Receiver Buffer Register were read before next character transferred into Receiver Buffer Register, thereby destroying previous character. Indicate indicator logic upon detection overrun condition. Automatic reset whenever reads contents Line Status Register. data FIFO mode continue fill FIFO beyond trigger level, overrun error will occur only after FIFO full next character been completely received shift register. indicated soon happens. character shift register overwritten, transferred FIFO. Data Ready indicator. Indicate whenever complete incoming character been received transferred into Receiver Buffer Register FIFO. Automatic reading data Receiver Buffer Register FIFO.
Data Sheet Final Version December 2003
RDC®
16.9
R2010C
RISC Communication
Fast Ethernet RISC Processor
Modem Status Register
This Modem Status Register (MSR) provides current state control lines from MODEM peripheral device) CPU. addition this current-state information, four bits MODEM Status Register provide change information. These bits logic whenever control input from MODEM changes state. They reset logic whenever reads MODEM Status Register. contents register described below.
Register Offset: Register Name: Reset Value
UART0 MODEM Status Register XXX0h
DDCD
TERI
DDSR DCTS
Name
Attribute
Description Data Carrier Detect. This complement Data Carrier Detect (DCD_n) input. (Loop Bit) this equivalent OUT2 MCR. Ring Indicator. This complement Ring Indicator (RI_n) input. (Loop Bit) this equivalent OUT1 MCR. Data Ready. This complement Data Ready (DSR_n) input. (Loop Bit) this equivalent MCR. Clear Send. This complement Clear Send (CTS_n) input. (Loop Bit) this equivalent MCR. Delta Data Carrier Detect. This indicates that DCD_n input changed state. Note: Whenever logic MODEM Status Interrupt generated. Trailing Edge Ring Indicator. This indicates that RI_n input changed from high state. Delta Data Ready. This indicates that DSR_n input changed state since last time read CPU. Delta Clear Send. This indicates that CTS_n input changed state since last time read CPU.
DDCD
TERI
DDSR
DCTS
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
16.10 Scratchpad Register
This 8-bit Read/Write Register does control UART way. intended scratchpad register used programmer hold data temporarily.
Register Offset: Register Name: Reset Value
UART0 Scratch Register
SCR[7:0]
16.11 Programmalbe Baud Generator
UART contains programmable Baud Generator that divided divisor from 216-1. output frequency Baud Generator times Baud [divisor (CPU frequency)/(baud rate*16)]. 8-bit latches store divisor 16-bit binary format. These Divisor Latches must loaded during initialization ensure proper operation Baud Generator. Upon loading either Divisor Latches, 16-bit Baud counter immediately loaded. Baud Rates 1200 2400 4800 9600 19200 38400 57600 115200 230400 460860 CPUCLK=75MHz Baud Dev.(%) 1200 2400 4798 0.04 9606 0.06 19211 0.06 38422 0.06 57870 114329 0.76 234375 1.73 468750 1.71 CPUCLK=100MHz Baud Dev.(%) 1200 2400 4800 9601 19171 0.15 38344 0.15 57339 0.45 115741 0.47 231481 0.47 446428 3.13
16.12 FIFO Interrupt Mode Operation
When RCVR FIFO receiver interrupts enabled (FCR [0]=1, [0]=1), RCVR interrupt will occur follows: receive data available interrupt will issued when FIFO reached programmed trigger level; will cleared soon FIFO drops below programmed trigger level.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
receive data available indication also occurs when FIFO trigger level reached, like interrupt, cleared when FIFO drops below trigger level. receiver line status interrupt (IIR=06), before, higher priority than received data available (IIR=04) interrupt. data ready (LSR [0]) soon character transferred from shift register RCVR FIFO. reset when FIFO empty.
When RCVR FIFO receiver interrupts enabled, RCVR FIFO timeout interrupts will occur follows: FIFO timeout interrupt will occur, following conditions exist: least character FIFO. most recent serial character received longer than continuous character times stop bits programmed second included this time delay). most recent read FIFO longer than continuous character times ago. This will cause maximum character received interrupt issued delay BAUD with 12-bit character. Character times calculated using RCLK input clock signal (this makes delay proportional baud rate). When timeout interrupt occurred: cleared timer reset when reads character from RCVR FIFO. When timeout interrupt occurred: timeout timer reset after character received after reads RCVR FIFO.
When XMIT FIFO transmitter interrupts enabled (FCR [0]=1, [1]=1), XMIT interrupts will occur follows: transmitter holding register interrupt (02) occurs when XMIT FIFO empty; cleared soon transmitter holding register written characters written XMIT FIFO while servicing this interrupt) read. transmitter FIFO empty indications will delayed character time minus last stop time whenever following occurs: THRE=1 there have been least bytes same time transmit FIFO, since last THRE=1. first transmitter interrupt after changing FCR0 will immediate, enabled. Character timeout RCVR FIFO trigger level interrupts have same priority current received data available interrupt; XMIT FIFO empty same priority current transmitter holding register empty interrupt.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
16.13 FIFO Polled Mode Operation
With [0]=1, resetting [0], [1], [2], zero puts UART FIFO Polled Mode operation. Since RCVR XMITTER controlled separately, either both polled mode operation. this mode, user's program will check RCVR XMITTER status LSR. stated previously: will long there byte RCVR FIFO. will specify which error(s) occurred. Character error status handled same interrupt mode, affected since IER2=0. will indicate when XMIT FIFO empty. will indicate that both XMIT FIFO Shift Register empty. will indicate whether there errors RCVR FIFO. There trigger level reached timeout condition indicated FIFO Polled Mode, however, RCVR XMIT FIFOs still fully capable holding characters.
Data Sheet Final Version December 2003
RDC®
R2010C
RISC Communication
Fast Ethernet RISC Processor
UNIT
R2010C provides programmable signals, which multi-functional pins with other signals normal functions. Software must used configure these multi-functional pins normal functions means programming through these registers (7Ah, 78h, 76h, 74h, 72h, 70h).
internal pull-up
Mode Direction
Normal Function
Data In/Out
Write PDATA
Read PDATA
Microprocessor Clock
internal pull-down
Normal Data "0":un-normal function
Operation Diagram
17.1
Multi-Function List Table
No.(PQFP) Direction Multi Function TMRIN1/SA10 TMROUT1/SA8 PCS5_n TMROUT0/SA7 TMRIN0/SA9 DRQ0/INT5/SA5 DRQ1/INT6/SA6 PCS0_n PCS2_n/IOR_n PCS3_n/IOW_n INT2 Reset status/PIO internal resister PIO/ Input with pull-up PIO/ Input with pull-down PIO/ Input with pull-up PIO/ Input with pull-down PIO/ Input with pull-up PIO/ Input with pull-up PIO/ Input with pull-up PIO/ Input with pull-up PIO/ Input with pull-up PIO/ Input with pull-up PIO/ Input with pull-up
Mode
Function Normal Operation input with pull-up/pull-down output input without pull-up/pull-down
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Data Register
PDATA[31:16]
15-0
Name PDATA [31:16]
Attribute
Description Data Bits. These bits PDATA[31:16] mapped PIO[31:16] that indicate driven level when output reflect external level when input.
Register Offset: Register Name: Reset Value
Direction Register FF9Fh
PDIR[31:16]
15-0
Name PDIR [31:16]
Attribute
Description Direction Register. Configure input pin. Configure output normal function.
Register Offset: Register Name: Reset Value
Mode Register 0000h
PMODE[(31:16)
Name
Attribute
Description Mode Bit. definitions pins configured combination Mode Direction. pins programmed individually. definitions (PIO Mode, Direction) functions pins: Normal operation input with pull-up/pull-down output input without pull-up/pull-down
15-0
PMODE [31:16]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
Data Register
PDATA[15:0]
Name PDATA [15:0]
Attribute
Description Data Bits. These bits PDATA[15:0] mapped PIO[15:0] that indicate driven level when output reflect external level when input.
15-0
Register Offset: Register Name: Reset Value
Direction Register FC4Fh
PDIR[15:0]
15-0
Name PDIR [15:0]
Attribute
Description Direction Register. Configure input pin. Configure output normal function.
Register Offset: Register Name: Reset Value
Mode Register 0000h
PMODE[15:0]
15-0
Name PMODE [15:0]
Attribute Mode Bits.
Description
Data Sheet Final Version December 2003
RDC®
18.1
R2010C
RISC Communication
Fast Ethernet RISC Processor
CACHE Controller
Cache Control Register
FEC0h Cache Control Register 0000h
Reserved
Register Offset: Register Name: Reset Value
Reserved
NCR3 NCR2 NCR1 NCR0
13-12
Name Rsvd NCR3 NCR2 NCR1 NCR0 Rsvd
Attribute Instruction Cache enable when Data Cache enable when Reserved
Description
Non-Cache region3 enable when Non-Cache region2 enable when Non-Cache region1 enable when Non-Cache region0 enable when Write Invalid region enable when Reserved
18.2
Non-Cache Region Register
FEC2h Non-Cache Region0 Start Address Register NCRS[15:3] Reserved
Register Offset: Register Name: Reset Value
15-3
Name NCRS
Attribute
Description Non-Cache Region start address [15:3] Must 000b mapped Non-Cache Region start address [2:0]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
FEC4h Non-Cache Region0 Start Address High Register
Reserved
NCRS[23:16]
15-8
Name Rsvd NCRS
Attribute Reserved
Description
Non-Cache Region start address [23:16]
Register Offset: Register Name: Reset Value
FEC6h Non-Cache Region0 Address Register NCRE[15:3] reserved
15-3
Name NCRE
Attribute
Description Non-Cache Region address [15:3] Must 000b mapped Non-Cache Region address [2:0]
Register Offset: Register Name: Reset Value
FEC8h Non-Cache Region0 Address High Register
Reserved
NCRE[23:16]
15-8
Name Rsvd NCRE
Attribute Reserved
Description
Non-Cache Region address [23:16]
Data Sheet Final Version December 2003
RDC®
Register Offset: Register Name: Reset Value
R2010C
RISC Communication
Fast Ethernet RISC Processor
FECAh Non-Cache Region1 Start Address Register NCRS[15:3] Reserved
15-3
Name NCRS
Attribute
Descri

Other recent searches


UNRF2A4 - UNRF2A4   UNRF2A4 Datasheet
Si8417DB - Si8417DB   Si8417DB Datasheet
Si8411DB - Si8411DB   Si8411DB Datasheet
PL008 - PL008   PL008 Datasheet
BD242 - BD242   BD242 Datasheet
BD242A - BD242A   BD242A Datasheet
BD242B - BD242B   BD242B Datasheet
BD242C - BD242C   BD242C Datasheet
BD241 - BD241   BD241 Datasheet

 

Privacy Policy | Disclaimer
© 2012 Datasheet Archive