16K-Channel Digital Switch with High Jitter Tolerance, Single Rate 16M
|
|
|
Top Searches for this datasheet
ZL50062/4
16K-Channel Digital Switch with High Jitter Tolerance, Single Rate 16Mbps), Inputs Outputs Data Sheet Features
16,384-channel 16,384-channel non-blocking unidirectional switching.The Backplane Local inputs outputs combined form non-blocking switching matrix with input streams output streams 8,192-channel 8,192-channel non-blocking Backplane input Local output stream switch 8,192-channel 8,192-channel non-blocking Local input Backplane output stream switch 8,192-channel 8,192-channel non-blocking Backplane input Backplane output switch 8,192-channel 8,192-channel non-blocking Local input Local output stream switch Backplane port accepts input output ST-BUS streams with fixed data rates 2.048Mbps, 4.096Mbps, 8.192Mbps 16.384Mbps Local port accepts input output STBUS streams with fixed data rates 2.048Mbps, 4.096Mbps, 8.192Mbps 16.384Mbps Exceptional input clock jitter tolerance (17ns) Ordering Information ZL50062GAC ZL50064QCC 256-Ball PBGA 256-Pin LQFP
-40°C +85°C Per-stream delay Local Backplane input streams Per-stream advancement Local Backplane output streams Constant 2-frame throughput delay frame integrity Per-channel high impedance output control Local Backplane streams Per-channel driven-high output control Local Backplane streams Per-channel message mode Local Backplane output streams Connection memory block programming fast device initialization
VDD_IO VDD_CORE
(GND)
RESET
BSTi0-31
Backplane Data Memories (8,192 channels)
Local Interface
LSTi0-31
Backplane Interface BSTo0-31
Backplane Connection Memory (8,192 locations)
Local Connection Memory (8,192 locations)
Local Interface LSTo0-31
BORS
Local Data Memories (8,192 channels)
LORS
FP8i
Input Timing Unit
Output Timing Unit
FP8o FP16o C16o
Microprocessor Interface Internal Registers
Test Port
VDD_PLL
A14-0
D15-0
TRST
Figure ZL50062/4 Functional Block Diagram
Zarlink Semiconductor Inc. Zarlink, Zarlink Semiconductor logo trademarks Zarlink Semiconductor Inc. Copyright 2003, Zarlink Semiconductor Inc. Rights Reserved.
ZL50062/4
Automatic selection between ST-BUS GCI-Bus operation Non-multiplexed Motorola microprocessor interface Conforms mandatory requirements IEEE-1149.1 (JTAG) standard Memory Built-In-Self-Test (BIST), controlled microprocessor register 1.8V core supply voltage 3.3V supply voltage tolerant inputs, outputs I/Os
Data Sheet
Applications
Central Office Switches (Class Media Gateways Class-independent switches Access Concentrators Scalable TDM-Based Architectures Digital Loop Carriers
Zarlink Semiconductor Inc.
ZL50062/4
Device Overview
Data Sheet
ZL50062 ZL50064 different packages same device. They have same functionality except that ZL50064 does have 16.384MHz output clock frame pulse (C16o FP16o) package differences. ZL50062/4 data ports, Backplane Local port. device operate four different data rates, 2.048Mbps, 4.096Mbps, 8.192Mbps 16.384Mbps. input output streams must operate same data rate. ZL50062/4 contains data memory blocks (Backplane Local) provide following switching path configurations: Input-to-Output Unidirectional, supporting switching Backplane-to-Local Bi-directional, supporting data switching, Local-to-Backplane Bi-directional, supporting data switching, Backplane-to-Backplane Bi-directional, supporting data switching. Local-to-Local Bi-directional, supporting data switching.
device contains connection memory blocks, Backplane output Local output. Data output serial streams come from either data memories (Connection Mode) directly from connection memory contents (Message Mode). Connection Mode, contents connection memory define, each output stream channel, source stream channel (stored data memory) switched. Message Mode, microprocessor data written connection memory broadcast output streams channel basis. This feature useful transferring control status information external circuits other ST-BUS devices. device uses master frame pulse (FP8i) master clock (C8i) define input frame boundary timing both Backplane port Local port. device will automatically detect whether ST-BUS GCIBus style frame pulse being used. There two-frame delay from time RESET de-asserted establishment full switch functionality. During this period, input frame pulse format determined before switching begins. device provides FP8o, FP16o, C16o outputs support external devices connected outputs Backplane Local ports. non-multiplexed Motorola microprocessor port allows programming various device operation modes switching configurations. microprocessor port provides access Register read/write, Connection Memory read/write Data Memory read-only operations. port 15-bit address bus, 16-bit data control signals. microprocessor monitor channel data Backplane Local data memories. mandatory requirements IEEE-1149.1 (JTAG) standard fully supported dedicated test port. ZL50062 ZL50064 each available package: ZL50062: 17mm 17mm body, ball-pitch, 256-PBGA. ZL50064: 28mm 28mm body, 0.40mm pin-pitch, 256-LQFP.
Zarlink Semiconductor Inc.
ZL50062/4 Table Contents
Data Sheet
Unidirectional Bi-directional Switching Applications Flexible Configuration 1.1.1 Non-Blocking Unidirectional Configuration (Typical System Configuration) 1.1.2 Non-Blocking Bi-directional Configuration 1.1.3 Blocking Bi-directional Configuration Functional Description Switching Configuration. 2.1.1 Unidirectional Switch 2.1.2 Backplane-to-Local Path 2.1.3 Local-to-Backplane Path 2.1.4 Backplane-to-Backplane Path 2.1.5 Local-to-Local Path 2.1.6 Port Data Rate Modes Selection. 2.1.6.1 Local Output Port 2.1.6.2 Backplane Output Port Frame Pulse Input Master Input Clock Timing Input Frame Pulse Generated Frame Pulse Alignment Jitter Tolerance Improvement Circuit Frame Boundary Discriminator. Input Clock Jitter Tolerance. Input Output Offset Programming Input Offsets 3.1.1 Input Delay Programming (Backplane Local Input Streams) Output Advancement Programming (Backplane Local Output Streams) Port high impedance Control Data Delay Through Switching Paths Microprocessor Port Device Power-up, Initialization Reset Power-Up Sequence Initialization Reset Connection Memory Local Connection Memory. Backplane Connection Memory. Connection Memory Block Programming 8.3.1 Memory Block Programming Procedure: Memory Built-In-Self-Test (BIST) Mode 10.0 JTAG Port 10.1 Test Access Port (TAP) 10.2 Registers 10.2.1 Test Instruction Register 10.2.2 Test Data Registers 10.2.2.3 Device Identification Register 10.3 Boundary Scan Description Language (BSDL) File 11.0 Memory Address Mappings 11.1 Local Data Memory Definition 11.2 Backplane Data Memory Definition 11.3 Local Connection Memory Definition 11.4 Backplane Connection Memory Definition 12.0 Internal Register Mappings 13.0 Detailed Register Descriptions
Zarlink Semiconductor Inc.
ZL50062/4 Table Contents
Data Sheet
13.1 Control Register (CR) 13.2 Block Programming Register (BPR) 13.3 Local Input Delay Registers (LIDR0 LIDR31). 13.3.1 Local Input Delay Bits (LID[4:0]) 13.4 Backplane Input Delay Registers (BIDR0 BIDR31) 13.4.1 Backplane Input Delay Bits (BID[4:0]) 13.5 Local Output Advancement Registers (LOAR0 LOAR31) 13.5.1 Local Output Advancement Bits (LOA1-LOA0) 13.6 Backplane Output Advancement Registers (BOAR0 BOAR31) 13.6.1 Backplane Output Advancement Bits (BOA1-BOA0). 13.7 Memory BIST Register 13.8 Rate Register 13.9 Device Identification Register 14.0 Electrical Characteristics 15.0 Electrical Characteristics
Zarlink Semiconductor Inc.
ZL50062/4 List Figures
Data Sheet
Figure ZL50062/4 Functional Block Diagram Figure ZL50064 LQFP Connections (256 LQFP, 28mm 28mm) Diagram viewed through package) Figure ZL50062 PBGA Connections (256 PBGA, 17mm 17mm) Diagram viewed through package) Figure 16,384 16,384 Channels (16Mbps), Unidirectional Switching Figure 8,192 8,192 Channels (16Mbps), Bi-directional Switching Figure 12,288 4,096 Channels Blocking Bi-directional Configuration Figure ST-BUS GCI-Bus Input Timing Diagram Different Data Rates Figure Input Output Frame Pulse Alignment Different Data Rates Figure Backplane Local Input Delay Timing Diagram Data Rate 16Mbps. Figure Backplane Local Input Delay Sampling Point Selection Timing Diagram Data Rate 8Mbps Figure Local Backplane Output Advancement Timing Diagram Data Rate 16Mbps Figure Data Throughput Delay with Input Switched Output Ch0. Figure Data Throughput Delay with Input Switched Output Ch13. Figure Data Throughput Delay with Input Ch13 Switched Output Ch0. Figure Hardware RESET De-assertion. Figure Frame Boundary Conditions, ST-BUS Operation Figure Frame Boundary Conditions, GCI-Bus Operation Figure Input Output Clock Timing Diagram ST-BUS Figure Input Output Clock Timing Diagram GCI-Bus Figure ST-BUS Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) Figure ST-BUS Local/Backplane Data Timing Diagram (16Mbps) Figure GCI-Bus Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps) Figure GCI-Bus Local/Backplane Data Timing Diagram (16Mbps). Figure Serial Output External Control Figure Output Driver Enable (ODE) Figure Motorola Non-Multiplexed Timing. Figure JTAG Test Port Timing Diagram
Zarlink Semiconductor Inc.
ZL50062/4 List Tables
Data Sheet
Table Local Backplane Output Enable Control Priority Table Variable Range Input Streams Table Variable Range Output Streams. Table Local Connection Memory Block Programming Mode Table Backplane Connection Memory Block Programming Mode Table Local Backplane Connection Memory Configuration Table Address Data Connection Memory Locations (A14 Table Local Data Memory (LDM) Bits Table Backplane Data Memory (BDM) Bits. Table Bits Source-to-Local Switching Table Bits Source-to-Backplane Switching Table Address Registers (A14 Table Control Register Bits Table Block Programming Register Bits Table Local Input Delay Register (LIDRn) Bits Table Local Input Delay Sampling Point Programming Table Table Backplane Input Delay Register (BIDRn) Bits Table Backplane Input Delay Sampling Point Programming Table. Table Local Output Advancement Register (LOAR) Bits Table Local Output Advancement (LOAR) Programming Table Table Backplane Output Advancement Register (BOAR) Bits Table Backplane Output Advancement (BOAR) Programming Table Table Memory BIST Register (MBISTR) Bits Table Rate Register (BRR) Bits Table Device Identification Register (DIR) Bits
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
BST010 BSTo11 BSTo12 BSTo14 BSTo13 VDD_IO BSTo15 VDD_CORE BSTo16 BSTo18 BSTo17 BSTo20 BSTo19 BSTo22 BSTo21 BSTo23 VDD_IO VDD_CORE BSTo24 BSTo25 BSTo26 BSTo27 BSTo28 BSTo29 BSTo30 BSTo31 BORS VDD_IO VDD_CORE BSTi0 BSTi1 BSTi2 BSTi3 BSTi4 BSTi5 BSTi6 BSTi7 BSTi8 BSTi10 BSTi9 BSTi12 BSTi11 BSTi14 BSTi13 VDD_IO BSTi15 VDD_CORE BSTi16 BSTi18 BSTi17 BSTi20 BSTi19 BSTi22 BSTi21 BSTi23 BSTi24
BSTo9 BSTo8 VDD_IO BSTo6 BST07 BSTo4 BST05 BSTo2 BSTo3 BSTo0 BSTo1 VDD_CORE VDD_IO IC_GND IC_GND IC_GND IC_GND VDD_CORE VDD_IO RESET TRST IC_OPEN IC_OPEN IC_OPEN IC_OPEN IC_OPEN IC_OPEN VDD_CORE VDD_IO IC_OPEN IC_OPEN LSTo0 LSTo1
LQFP (TOP VIEW)
LSTo2 LSTo3 LSTo4 LSTo5 VDD_CORE LSTo6 VDD_IO LSTo8 LSTo7 LSTo10 LSTo9 LSTo12 LSTo11 LSTo13 VDD_CORE VDD_IO LSTo14 LSTo15 LSTo16 LSTo17 LSTo18 LSTo19 LSTo20 LSTo21 VDD_IO LSTo22 LSTo23 LSTo24 LSTo25 LSTo26 LSTo27 LSTo28 LSTo29 VDD_CORE VDD_IO LSTo30 LSTo31 LORS LSTi0 LSTi2 LSTi1 LSTi4 LSTi3 LSTi6 LSTi5 LSTi8 LSTi7 LSTi10 LSTi9 LSTi12 LSTi11 VDD_CORE VDD_IO LSTi13 LSTi14
Figure ZL50064 LQFP Connections (256 LQFP, 28mm 28mm) Diagram
viewed through package)
BSTi25 BSTi26 BSTi27 BSTI28 BSTI30 BSTi29 VDD_IO BSTi31 VDD_CORE VDD_IO VDD_CORE IC_GND IC_GND VDD_IO VDD_CORE VDD_PLL FP8o FP8i LSTi31 LSTi30 LSTi29 VDD_IO VDD_CORE LSTi27 LSTi28 LSTi25 LSTi26 LSTi23 LSTi24 LSTi21 LSTi22 LSTi19 LSTi20 LSTi18 LSTi17 LSTi16 LSTi15
Zarlink Semiconductor Inc.
ZL50062/4
Pinout Diagram: viewed through package) corner identified metallized marking
Data Sheet
OPEN
OPEN
OPEN RESET
OPEN
OPEN LSTo0
OPEN LSTo1
OPEN LSTo2
OPEN LSTo3
BSTo0
BSTo1
BSTo2
BSTo3
BSTo4
BSTo5
BSTo6
BSTo7
LSTo4
LSTo5
LSTo6
LSTo7
BSTo8
BSTo9
BSTo10 BSTo11
BORS
IC_GND IC_GND IC_GND IC_GND
TRST
LORS
LSTo8
LSTo9
LSTo10 LSTo11
BSTo12 BSTo13 BSTo14 BSTo15 VDD_IO VDD_IO
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_ CORE
VDD_IO VDD_IO LSTo12 LSTo13 LSTo14 LSTo15
BSTo16 BSTo17 BSTo18 BSTo19 VDD_IO
VDD_ CORE
VDD_ CORE
VDD_IO LSTo16 LSTo17 LSTo18 LSTo19
BSTo20 BSTo21 BSTo22 BSTo23 VDD_IO
VDD_IO LSTo20 LSTo21 LSTo22 LSTo23
BSTo24 BSTo25 BSTo26 BSTo27 VDD_IO
VDD_IO LSTo24
LST25
LSTo26 LSTo27
BSTo28 BSTo29 BSTo30 BSTo31
VDD_ CORE VDD_ CORE VDD_IO
VDD_ CORE VDD_ CORE VDD_IO
LSTo28 LSTo29 LSTo30 LSTo31
BSTi0
BSTi1
BSTi2
BSTi3
LSTi0
LSTi1
LSTi2
LSTi3
BSTi4
BSTi5
BSTi6
BSTi7
VDD_ CORE
VDD_ CORE
VDD_ CORE VDD_ OPEN C16o
VDD_ CORE
LSTi4
LSTi5
LSTi6
LSTi7
BSTi8
BSTi9
BSTi10
BSTi11 VDD_IO
VDD_IO
LSTi8
LSTi9
LSTi10
LSTi11
BSTi12
BSTi13
BSTi14
BSTi15
BSTi16
OPEN FP16o
LSTi12
LSTi13
LSTi14
LSTi15
LSTi16
BSTi17
BSTi18
BSTi19
BSTi20
BSTi21
LSTi17
LSTi18
LSTi19
LSTi20
LSTi21
BSTi22
BSTi23
BSTi24
BSTi25
BSTi26
FP8o
FP8i
LSTi22
LSTi23
LSTi24
LSTi25
LSTi26
BSTi27
BSTi28
BSTi29
BSTi30
BSTi31 IC_GND IC_GND IC_GND IC_GND
LSTi27
LSTi28
LSTi29
LSTi30
LSTi31
Figure ZL50062 PBGA Connections (256 PBGA, 17mm 17mm) Diagram
viewed through package)
Zarlink Semiconductor Inc.
ZL50062/4
Description ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
Device Timing Master Clock Tolerant Schmitt-Triggered Input). This accepts 8.192MHz clock. internal frame boundary aligned with clock falling rising edge, controlled C8IPOL Control Register. Input data both Backplane Local sides (BSTi0-31 LSTi0-31) must aligned this clock accompanying input frame pulse, FP8i. Frame Pulse Input Tolerant Schmitt-Triggered Input). When Frame Pulse Width (FPW) Control Register (default), this accepts 122ns-wide frame pulse. When HIGH, this accepts 244ns-wide frame pulse. device will automatically detect whether ST-BUS GCI-Bus style frame pulse applied. Input data both Backplane Local sides (BSTi0-31 LSTi0-31) must aligned this frame pulse accompanying input clock, C8i. Output Clock Tolerant Three-state Output). This outputs 8.192MHz clock generated within device. clock falling edge rising edge aligned with output frame boundary presented FP8o; this edge polarity alignment controlled COPOL Control Register. Output data both Backplane Local sides (BSTo0-31 LSTo0-31) will aligned this clock accompanying output frame pulse, FP8o. Frame Pulse Output Tolerant Three-state Output). When Frame Pulse Width (FPW) Control Register (default), this outputs 122ns-wide frame pulse. When HIGH, this outputs 244ns-wide frame pulse. frame pulse, running 8kHz rate, will have same format (ST-BUS GCI-Bus) input frame pulse (FP8i). Output data both Backplane Local sides (BSTo0-31 LSTo0-31) will aligned this frame pulse accompanying output clock, C8o. C16o Output Clock Tolerant Three-state Output). This outputs 16.384MHz clock generated within device. clock falling edge rising edge aligned with output frame boundary presented FP16o; this edge polarity alignment controlled COPOL Control Register. Output data both Backplane Local sides (BSTo0-31 LSTo0-31) will aligned this clock accompanying output frame pulse, FP16o.
FP8i
FP8o
C16o
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
FP16o
Frame Pulse Output Tolerant Three-state Output). When Frame Pulse Width (FPW) Control Register (default), this outputs 61ns-wide frame pulse. When HIGH, this outputs 122ns-wide frame pulse. frame pulse, running 8kHz rate, will have same format (ST-BUS GCI-Bus) input frame pulse (FP8i). Output data both Backplane Local sides (BSTo0-31 LSTo0-31) will aligned this frame pulse accompanying output clock, C16o.
Backplane Local Inputs BSTi0-15 228, 229, 230, 231, 232, 233, 234, 235, 236, 238, 237, 240, 239, 242, 241, 248, 250, 249, 252, 251, 254, 253, 255, 256,
Backplane Serial Input Streams Tolerant Inputs with Internal Pull-downs).
These pins accept serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream).
BSTi16-31
Backplane Serial Input Streams Tolerant Inputs with Internal Pull-downs).
These pins accept serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream).
Local Serial Input Streams Tolerant Inputs with Internal Pull-downs).
LSTi0-15
K13, K14, K15, K16, L13, L14, L15, L16, M13, M14, M15, M16, N12, N13, N14, N16, P12, P13, P14, P15, P16, R12, R13, R14, R15, R16, T12, T13, T14, T15,
These pins accept serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream).
Local Serial Input Streams Tolerant Inputs with Internal Pull-downs).
LSTi16-31
These pins accept serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream).
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
Backplane Local Outputs Control
Output Drive Enable Tolerant Input with Internal Pull-up).
asynchronous input providing Output Enable control BSTo0-31 LSTo0-31 outputs. When LOW, BSTo0-31 LSTo0-31 outputs driven HIGH high impedance (dependent BORS LORS settings respectively). When HIGH, outputs BSTo0-31 LSTo0-31 enabled. BORS
Backplane Output Reset State Tolerant Input with Internal Pull-down).
When this input LOW, device will initialize with BSTo0-31 outputs driven high. Following initialization, Backplane stream outputs always active. When this input HIGH, device will initialize with BSTo0-31 outputs high impedance. Following initialization, Backplane stream outputs active high impedance using per-channel basis with Backplane Connection Memory. BSTo0-15 182, 181, 184, 183, 186, 185, 188, 187, 191, 192, 193, 194, 195, 197, 196, 203, 205, 204, 207, 206, 209, 208, 210, 215, 216, 217, 218, 219, 220, 221,
Backplane Serial Output Streams Tolerant, Three-state Outputs with Slew-Rate Control).
These pins output serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream). Refer descriptions BORS pins control output HIGH high impedance state.
BSTo16-31
Backplane Serial Output Streams Tolerant, Three-state Outputs with Slew-Rate Control).
These pins output serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream). Refer descriptions BORS pins control output HIGH high impedance state.
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
LORS
Local Output Reset State Tolerant Input with Internal Pull-down).
When this input LOW, device will initialize with LSTo0-31 outputs driven high. Following initialization, Local stream outputs always active. When this input HIGH, device will initialize with LSTo0-31 outputs high impedance. Following initialization, Local stream outputs active high impedance using per-channel basis with Local Connection Memory. LSTo0-15 130, 129, 128, 127, 126, 125, 121, 118, 119, 116, 117, 114, 115, 113, 108, B13, B14, B15, B16, C13, C14, C15, C16, D13, D14, D15, D16, E13, E14, E15,
Local Serial Output Streams Tolerant Three-state Outputs with Slew-Rate Control).
These pins output serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream). Refer descriptions LORS pins control output HIGH high impedance state.
Local Serial Output Streams Tolerant Three-state Outputs with Slew-Rate Control).
LSTo16-31
106, 105, 104, 103, 102, 101,
F13, F14, F15, F16, G13, G14, G15, G16, H13, H14, H15, H16, J13, J14, J15,
These pins output serial data streams data rate 16.384Mbps (with channels stream), 8.192Mbps (with channels stream), 4.096Mbps (with channels stream) 2.048Mbps (with channels stream). Refer descriptions LORS pins control output HIGH high impedance state.
Microprocessor Port Signals 179, 180, 177, 178, 172, 171, 170, 169, 168, 167, 166, 165, 164, 163, Address Tolerant Inputs). These pins form 15-bit address internal memories registers.
Data Tolerant Inputs/Outputs with Slew-Rate Control). These pins form 16-bit data microprocessor port.
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
Chip Select Tolerant Input). Active input used microprocessor enable microprocessor port access. Note that minimum 30ns must separate de-assertion high) assertion and/or initiate next access. Data Strobe Tolerant Input). This active input works conjunction with enable microprocessor port read write operations. Note that minimum 30ns must separate de-assertion high) assertion and/or initiate next access. Read/Write Tolerant Input). This input controls direction data lines (D0-D15) during microprocessor access. Data Transfer Acknowledgment Tolerant Three-state Output). This active output indicates that data transfer complete. pull-up resistor required hold HIGH level. Note that minimum 30ns must separate de-assertion high) assertion and/or initiate next access. Device Reset Tolerant Input with Internal Pull-up). This input (active LOW) asynchronously applies reset synchronously releases reset device. reset state, outputs LSTo0-31 BSTo0-31 HIGH high impedance state, depending state LORS BORS external control pins, respectively. assertion this also clears device registers internal counters. Refer Section page timing requirements regarding this reset signal.
RESET
JTAG Control Signals
Test Clock Tolerant Input).
Provides clock JTAG test logic.
Test Mode Select Tolerant Input with Internal Pull-up).
JTAG signal that controls state transitions controller.
Test Serial Data Tolerant Input with Internal Pull-up).
JTAG serial test instructions data shifted this pin. Test Serial Data Tolerant Three-state Output). JTAG serial data output this falling edge TCK. This held high impedance state when JTAG enabled.
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
TRST
Test Reset Tolerant Input with Internal Pull-up). Asynchronously initializes JTAG controller Test-Logic-Reset state. This must pulsed during power-up JTAG testing. This must held normal functional operation device.
Power Ground Pins VDD_IO 109, 120, 134, 153, 173, 189, 198, 211, 224, 112, 124, 135, 156, 176, 202, 214, 227, 100, 110, 111, 122, 123, 133, 136, 154, 155, 174, 175, 190, 200, 201, 212, 213, 225, 226, 245, E11, E12, F12, G12, H12, L12, Power Supply Periphery Circuits: +3.3V
VDD_CORE
E10, F11, J12, K12, L10,
Power Supply Core Circuits: +1.8V
VDD_PLL (GND)
F10, G10, G11, H10, H11, J10, J11, K10, K11,
Power Supply Analog PLL: +1.8V Ground.
Zarlink Semiconductor Inc.
ZL50062/4
Description (continued) ZL50064 Package Coordinates (256-pin LQFP) ZL50062 Package Coordinates (256-ball PBGA)
Data Sheet
Name
Description
Unused Pins IC_OPEN 131, 132, 137, 138, 139, 140, 141, 158, 159, 160, A10, A11, A12, A13, A14, A15, A16, N10, Connects. These pins used tied HIGH, LOW, left unconnected. Internal Connections OPEN. These pins must left unconnected.
IC_GND
Internal Connections GND. These pins must tied LOW.
Zarlink Semiconductor Inc.
ZL50062/4
Unidirectional Bi-directional Switching Applications
Data Sheet
ZL50062/64 maximum capacity 16,384 input channels 16,384 output channels. This calculated from maximum number streams channels: input streams Backplane, Local) 16.384Mbps output streams Backplane, Local) 16.384Mbps. typical mode operation separate input output streams form unidirectional switch, shown Figure below.
BSTi0-31 streams INPUT LSTi0-31 streams ZL50062/64
BSTo0-31 streams OUTPUT LSTo0-31 streams
Figure 16,384 16,384 Channels (16Mbps), Unidirectional Switching this system, Backplane Local input streams combined, Backplane Local output streams combined, that switch appears input stream output stream switch. This gives maximum 16,384 16,384 channel capacity. Often system design needs differentiate between Backplane Local side, needs switch bi-directional configuration. this case, ZL50062/64 used shown Figure give 8,192 8,192 channel bi-directional capacity.
BSTi0-31 streams BACKPLANE BSTo0-31 streams ZL50062/64
LSTo0-31 streams LOCAL LSTi0-31 streams
Figure 8,192 8,192 Channels (16Mbps), Bi-directional Switching this system setup, chip capacity 8,192 input channels 8,192 output channels Backplane side, well 8,192 input channels 8,192 output channels Local side. Note that some output channels side come from other side, e.g., Backplane input Local output switching.
Zarlink Semiconductor Inc.
ZL50062/4
Flexible Configuration
Data Sheet
ZL50062/64 configured non-blocking unidirectional digital switch, non-blocking bi-directional digital switch, blocking switch with various switching capacities.
1.1.1
Non-Blocking Unidirectional Configuration (Typical System Configuration)
Because input output drivers synchronous, user combine input Backplane streams input Local streams well output Backplane streams output Local streams increase total number input output streams switch unidirectional configuration, shown Figure 16,384-channel 16,384-channel non-blocking switching from input output streams
1.1.2
Non-Blocking Bi-directional Configuration
Another typical application configure ZL50062/64 non-blocking bi-directional switch, shown Figure 8,192-channel 8,192-channel non-blocking switching from Backplane input Local output streams 8,192-channel 8,192-channel non-blocking switching from Local input Backplane output streams 8,192-channel 8,192-channel non-blocking switching from Backplane input Backplane output streams 8,192-channel 8,192-channel non-blocking switching from Local input Local output streams
1.1.3
Blocking Bi-directional Configuration
ZL50062/64 configured blocking bi-directional switch application requirement. example, configured bi-directional blocking switch, shown Figure 12,288-channel 4,096-channel blocking switching from Backplane input Local output streams 4,096-channel 12,288-channel blocking switching from Local input Backplane output streams 12,288-channel 12,288-channel non-blocking switching from Backplane input Backplane output streams 4,096-channel 4,096-channel non-blocking switching from Local input Local output streams
ZL50062/64 BSTi0-31 LSTi0-15 BSTo0-31 LSTo0-15 LSTi16-31 LSTo16-31
Total streams input streams output
Total streams input streams output
Figure 12,288 4,096 Channels Blocking Bi-directional Configuration
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
Functional Description
Switching Configuration
device supports five switching configurations: Unidirectional switch, Backplane-to-Local, Local-to-Backplane, Backplane-to-Backplane, Local-to-Local. following sections describe switching paths detail. Configurations enable non-blocking bi-directional switch with 8,192 Backplane input/output channels Backplane stream data rates 16.384Mbps, 8,192 Local input/output channels Local stream data rates 16.384Mbps. switching paths configurations operated simultaneously. When lower data-rates 8.192, 4.096 2.048Mbps used, there will corresponding reduction switch capacity.
2.1.1
Unidirectional Switch
device configured 16,384 16,384 unidirectional switch grouping together input streams output streams. streams operated data rate 16.384Mbps. Lower data rates used with corresponding reduction switch capacity.
2.1.2
Backplane-to-Local Path
device provide data switching between Backplane input port Local output port. Local Connection Memory determines switching configurations.
2.1.3
Local-to-Backplane Path
device provide data switching between Local input port Backplane output port. Backplane Connection Memory determines switching configurations.
2.1.4
Backplane-to-Backplane Path
device provide data switching between Backplane input output ports. Backplane Connection Memory determines switching configurations.
2.1.5
Local-to-Local Path
device provide data switching between Local input output ports. Local Connection Memory determines switching configurations.
2.1.6
Port Data Rate Modes Selection
Local port input (LSTi0-31) output (LSTo0-31) data streams. Similarly, Backplane port input (BSTi0-31) output (BSTo0-31) data streams. rate these streams selected writing Rate Registers, (see Table 24). streams operate same rate time. device operate 2.048, 4.096, 8.192 16.384 Mbps. default operation mode 2.048Mbps. timing input output clocks frame pulses shown Figure "Input Output Frame Pulse Alignment Different Data Rates" page input traffic aligned based FP8i input timing signals, while output traffic aligned based FP8o output timing signals.
2.1.6.1
Local Output Port
Operation stream data Connection Mode Message Mode determined state Local Connection Memory. channel high impedance state controlled Local Connection Memory. data source (i.e. from Local Backplane Data Memory) determined LSRC Local Connection Memory. Refer Section 8.1, Local Connection Memory, Section 11.3, Local Connection Memory Definition more details.
Zarlink Semiconductor Inc.
ZL50062/4
2.1.6.2 Backplane Output Port
Data Sheet
Operation stream data Connection Mode Message Mode determined state Backplane Connection Memory channel high impedance state controlled Backplane Connection Memory. data source (i.e. from Local Backplane Data Memory) determined BSRC Backplane Connection Memory. Refer Section 8.2, Backplane Connection Memory Section 11.4, Backplane Connection Memory Definition more details.
Frame Pulse Input Master Input Clock Timing
input frame pulse (FP8i) 8kHz input signal active 122ns 244ns frame boundary. Control Register must according applied pulse width. Description Table "Control Register Bits" page details. active state timing FP8i conform either ST-BUS GCI-Bus shown Figure ST-BUS GCI-Bus Input Timing Diagram Different Data Rates. ZL50062/64 device will automatically detect whether ST-BUS GCI-Bus style frame pulse being used master frame pulse (FP8i). output frame pulses (FP8o FP16o) always same style (ST-BUS GCI-Bus) input frame pulse. active edge input clock (C8i) shall selected state Control Register C8IPOL. Note that active edge ST-BUS falling edge, which default mode device, while GCI-Bus uses rising edge active edge. Although frame pulse will automatically detected, fully conform GCI-Bus operation, device should rising edge active edge setting C8IPOL HIGH) when GCI-Bus used. purposes describing device operation, remaining part this document assumes ST-BUS frame pulse format with single width frame pulse 122ns falling active clock-edge, unless explicitly stated otherwise. addition, ZL50062 device provides FP8o, FP16o, C16o outputs support external devices which connect output ports. ZL50064 only provides FP8o outputs. generated frame pulses (FP8o, FP16o) will provided same format master frame pulse (FP8i). polarity C16o, frame boundary, controlled Control Register bit, COPOL. analog phase lock loop (APLL) used multiply input clock frequency generate internal clock signal operating 131.072MHz.
Zarlink Semiconductor Inc.
ZL50062/4
FP8i (ST-BUS) (8kHz) (ST-BUS) (8.192MHz) FP8i (GCI-Bus) (8kHz) (GCI-Bus) (8.192MHz)
Channel Channel
Data Sheet
BSTi/LSTi0-31 (16Mbps) ST-BUS
Channel
Channel
BSTi/LSTi0-31 (16Mbps) GCI-Bus BSTi/LSTi0-31 (8Mbps) ST-BUS BSTi/LSTi0-31 (8Mbps) GCI-Bus BSTi/LSTi0-31 (4Mbps) ST-BUS BSTi/LSTi0-31 (4Mbps) GCI-Bus BSTi/LSTi0-31 (2Mbps) ST-BUS BSTi/LSTi0-31 (2Mbps) GCI-Bus
Channel Channel Channel Channel Channel Channel
Channel
Channel
Channel Channel Channel Channel
Figure ST-BUS GCI-Bus Input Timing Diagram Different Data Rates
Zarlink Semiconductor Inc.
ZL50062/4
Input Frame Pulse Generated Frame Pulse Alignment
Data Sheet
ZL50062 accepts frame pulse (FP8i) generates frame pulse outputs, FP8o FP16o, which aligned master frame pulse. ZL50064 only generates frame pulse output, FP8o. There constant throughput delay data being switched from input output device such that data which input during Frame output during Frame N+2. further details frame pulse conditions options, Section 13.1, Control Register (CR), Figure Frame Boundary Conditions, ST-BUS Operation, Figure Frame Boundary Conditions, GCI-Bus Operation.
FP8i BSTi/LSTi0-31 (2Mbps) BSTi/LSTi0-31 (4Mbps) BSTi/LSTi0-31 (8Mbps) BSTi/LSTi0-31 (16Mbps)
CH10
CH11
tFBOS
FP8o BSTo/LSTo0-31 (2Mbps) BSTo/LSTo0-31 (4Mbps) BSTo/LSTo0-31 (8Mbps) BSTo/LSTo0-31 (16Mbps)
CH10
CH11
Figure Input Output Frame Pulse Alignment Different Data Rates tFBOS offset between input frame pulse, FP8i, generated output frame pulse, FP8o. Refer Electrical Characteristics," page Note that although figure above shows traditional setups frame pulses clocks both ST-BUS GCI-Bus configurations, devices configured accept/generate double-width frame pulses Control Register set) well opposite clock edge frame-boundary determination (using C8IPOL COPOL bits Control Register). timing diagrams Electrical Characteristics," page available configurations.
Jitter Tolerance Improvement Circuit Frame Boundary Discriminator
improve jitter tolerance ZL50062/64, Frame Boundary Discriminator (FBD) circuit added device. This circuit enabled setting Control Register FBDEN HIGH. default disabled. operate modes, controlled FBD_MODE[2:0] bits Control Register. When bits FBD_MODE[2:0] 000B, handle lower frequency jitter only (<8kHz). When bits FBD_MODE[2:0] 111B, handle both frequency high frequency jitter. other values reserved. These bits ignored when FBDEN LOW. strongly recommended that FBDEN HIGH, bits FBD_MODE[2:0] should 111B improve high frequency jitter handling capability. achieve best jitter tolerance performance, also recommended that input data sampling point optimized. most applications, optimum sampling point instead default changed programming LIDR BIDR registers). This will give more allowance sampling point variations caused
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
jitter. There are, however, some cases where data experience more delay than timing signals. common example when multiple data lines tied together form bidirectional buses. large loading cause data delayed. this case, optimum sampling point instead 1/2. optimum sampling point dependent application. user should optimize sampling point achieve best jitter tolerance performance.
Input Clock Jitter Tolerance
Input clock jitter tolerance depends data rate. general, higher data rate, smaller jitter tolerance because period cell shorter, sampling point variation allowance smaller. Jitter tolerance accurately represented just number. Jitter same amplitude different frequency spectrum have different effect operation device. example, device that tolerate 20ns jitter 10kHz frequency only able tolerate 10ns jitter 1MHz frequency. Therefore, jitter tolerance should represented spectrum over frequency. highest possible jitter frequency half carrier frequency. case ZL50062/64, input clock 8.192MHz, jitter associated with this clock have highest frequency component 4.096MHz. above reasons, jitter tolerance ZL50062/64 been characterized 16.384Mbps. lower data rates (2.048Mbps, 4.096Mbps, 8.192Mbps) will have same better tolerance than that 16.384Mbps operation. Tolerance jitter different frequencies shown Electrical Characteristics" section, table "Input Clock Jitter Tolerance" page Jitter Tolerance Improvement Circuit enabled (Control Register, FBDEN HIGH, bits FBD_MODE[2:0] 111B), sampling point optimized.
Input Output Offset Programming
Various registers used control input sampling point (delay) output advancement Local Backplane streams. following sections explain details these offset programming features.
Input Offsets
Control Input Delay allows each input stream have different frame boundary with respect master frame pulse, FP8i. Each input stream individually delayed bits with resolution period.
3.1.1
Input Delay Programming (Backplane Local Input Streams)
Input Delay Registers LIDR0-31 BIDR0-31 work conjunction with SMPL_MODE Control Register allow users control input fractional delay well input sample point selection greater flexibility when designing switch matrices high speed operation. When SMPL_MODE (input fractional delay mode), bits LID[4:0] BID[4:0] LIDR0-31 BIDR0-31 registers respectively define input fractional delay corresponding local backplane stream. total delay bits with resolution selected data rate. When SMPL_MODE HIGH (sampling point select mode), bits LID[1:0] BID[1:0] define input sampling point stream. sampling point programmed 3/4, 4/4, location allow better tolerance input jitter. Bits LID[4:2] BID[4:2] define integer input delay, with maximum value bits resolution bit. Refer Figure Figure Input Delay Timing 16Mbps 8Mbps data rates, respectively. Refer Figure Input Sampling Point Selection Timing 8Mbps data rates.
Zarlink Semiconductor Inc.
ZL50062/4
SMPL_MODE
FP8i
Ch255
Data Sheet
BSTi/LSTi0-31 Delay (Default) BSTi/LSTi0-31 Delay
Delay, Ch255
Delay,
BSTi/LSTi0-31 Delay
Ch255
Delay,
BSTi/LSTi0-31 Delay
Ch255
Delay, Ch255
BSTi/LSTi0-31 Delay
BSTi/LSTi0-31 Delay
Ch254
Ch255
Delay,
BSTi/LSTi0-31 Delay
Ch254
Ch255
Delay,
Please refer Control Register (Section 13.1) SMPL_MODE definition. Figure Backplane Local Input Delay Timing Diagram Data Rate 16Mbps
Zarlink Semiconductor Inc.
ZL50062/4
SMPL_MODE
FP8i
Ch127
Data Sheet
BSTi/LSTi0-31 BID[4:0]/LID[4:0] 00000B delay (Default)
sample point Ch127 sample point
BSTi/LSTi0-31 BID[4:0]/LID[4:0] 00011B Delay
SMPL_MODE HIGH
FP8i
Ch127 sample point Ch127 sample point
BSTi/LSTi0-31 BID[4:0]/LID[4:0] 00000B sampling (Default)
BSTi/LSTi0-31 BID[4:0]/LID[4:0] 00011B sampling
Please refer Control Register (Section 13.1) SMPL_MODE definition. Figure Backplane Local Input Delay Sampling Point Selection Timing Diagram Data Rate 8Mbps
Output Advancement Programming (Backplane Local Output Streams)
This feature used advance output channel alignment individual Local Backplane output streams with respect frame boundary FP8o. Each output stream advancement value that programmed Output Advancement Registers. output advancement selection useful compensating various parasitic loading serial data output pins. Local Backplane Output Advancement Registers, LOAR0 LOAR31 BOAR0 BOAR31, used control Local Backplane output advancement respectively. advancement determined with reference internal system clock rate (131.072MHz). advancement cycles, cycles cycles, which converts approximately 0ns, -15ns, -31ns -46ns shown Figure
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8o System Clock 131.072
Ch255 Advancement, Ch255 Advancement, Ch255 Advancement, Ch255 Advancement,
BSTo/LSTo0-31 Advancement (Default) BSTo/LSTo0-31 Advancement BSTo/LSTo0-31 Advancement BSTo/LSTo0-31 Advancement
Figure Local Backplane Output Advancement Timing Diagram Data Rate 16Mbps
Port high impedance Control
input pins, LORS BORS, select whether Local (LSTo0-31) Backplane (BSTo0-31) output streams, respectively, high impedance output device itself, always driven (active HIGH active LOW). Setting LORS/BORS state will configure output streams, LSTo0-31/BSTo0-31, transmit bi-state channel data. Setting LORS/BORS HIGH state will configure output streams, LSTo0-31/BSTo0-31, device invoke high impedance output per-channel basis. Local/Backplane Output Enable (LE/BE) Local/Backplane Connection Memory direct per-channel control high impedance state Local/Backplane output streams, L/BSTo0-31. Programming state connection memory LE/BE will stream output device high impedance duration channel period. "Local Connection Memory Definition," page "Backplane Connection Memory Definition," page programming details. state LORS/BORS detected device configured accordingly during RESET operation, e.g. following power-up. LORS/BORS asynchronous input expected hard-wired particular system application, although driven under logic control preferred. Local/Backplane output enable control order highest priority RESET, ODE, OSB, LE/BE. LE/BE (Local LORS/BORS Backplane (input pin) Connection Memory bit)
RESET (input pin)
(input pin)
(Control Register bit)
LSTo0-31/ BSTo0-31 HIGH HI-Z HIGH HI-Z HIGH
Table Local Backplane Output Enable Control Priority
Zarlink Semiconductor Inc.
ZL50062/4
(Control Register bit) LE/BE (Local LORS/BORS Backplane (input pin) Connection Memory bit)
Data Sheet
RESET (input pin)
(input pin)
LSTo0-31/ BSTo0-31 HI-Z HIGH HI-Z ACTIVE (HIGH LOW)
Table Local Backplane Output Enable Control Priority (continued)
Data Delay Through Switching Paths
Serial data which goes into device converted into parallel format written consecutive locations data memory. Each data memory location corresponds input stream channel number. Channels written buffers during Frame will read during Frame N+2. input delay output advancement have impact overall data throughput delay. following paragraphs, data throughput delay represented function ST-BUS frames, input channel number, (m), output channel number (n). Table describes variable range input streams Table describes variable range output streams. data throughput delay under various input channel output channel conditions summarized frames
Input Stream Data Rate 2Mbps 4Mbps 8Mbps 16Mbps
Input Channel Number
Table Variable Range Input Streams
Output Stream Data Rate 2Mbps 4Mbps 8Mbps 16Mbps
Output Channel Number
Table Variable Range Output Streams
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
data throughput delay frames Assuming that (input channel) (output channel) equal, have figure below, which delay between input data being written output data being read exactly frames.
Frame Serial Input Data
Frame
Frame
Frame
Frame
Frame
Frame
Frame Data
Frame N+1Data Frames
Frame Data
Frame Data
Frame Data
Frame Data
Serial Output Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Figure Data Throughput Delay with Input Switched Output Assuming that (output channel) greater than (input channel), have figure below, which delay time between input channel being written output channel being read exceeds frames.
Frame Serial Input Data
Frame
Frame
Frame
Frame
Frame
Frame
Frame Data
Frame N+1Data
Frame Data
Frame Data
Frame Data
Frame Data
Frames
Serial Output Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Figure Data Throughput Delay with Input Switched Output Ch13 Assuming that (output channel) less than (input channel), have figure below, which delay time between input channel being written output channel being read less than frames.
Frame Serial Input Data
Frame
Frame
Frame
Frame
Frame
Frame
Frame Data
Frame N+1Data
Frame Data
Frame Data
Frame Data
Frame Data
Frames
Serial Output Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Frame Data
Figure Data Throughput Delay with Input Ch13 Switched Output
Zarlink Semiconductor Inc.
ZL50062/4
Microprocessor Port
Data Sheet
switch family supports non-multiplexed Motorola type microprocessor buses. microprocessor port consists 16-bit parallel data (D0-15), 15-bit address (A0-14) four control signals (CS, DTA). data provides access internal registers, Backplane Connection Data Memories, Local Connection Data Memories. Each memory 8,192 locations. Table Address Data Connection Memory Locations (A14 address mapping. Each Connection Memory read written 16-bit microprocessor port. Data Memories only read (but written) from microprocessor port. prevent 'hanging', event switch receiving master clock, microprocessor port shall complete handshake when accessed, data read from will invalid.
Device Power-up, Initialization Reset
Power-Up Sequence
recommended power-up sequence VDD_IO supply (nominally +3.3V) established before power-up VDD_PLL VDD_CORE supplies (nominally +1.8V). VDD_PLL VDD_CORE supplies powered simultaneously, neither should 'lead' VDD_IO supply more than 0.3V. supplies powered-down simultaneously.
Initialization
Upon power device should initialized applying following sequence: Ensure TRST permanently disable JTAG controller. LOW. This sets LSTo0-31 outputs HIGH high impedance, dependent LORS input value, sets BSTo0-31 outputs HIGH high impedance, dependent BORS input value. Refer Description details LORS BORS pins. Reset device asserting RESET zero least cycles input clock, C8i. delay additional 250µs must also applied before first microprocessor access performed following de-assertion RESET pin; this delay required determination input frame pulse format. Block Programming Mode initialize Local Backplane Connection Memories. Refer Section 8.3, Connection Memory Block Programming. HIGH after connection memories programmed ensure that contention will occur serial stream outputs.
Reset
RESET used reset device. When LOW, asynchronous reset applied device. then synchronized internal clock. During reset period, depending state input pins LORS BORS, output streams LSTo0-31 BSTo0-31 HIGH high impedance, internal registers counters reset default state. RESET must remain input clock cycles (C8i) guarantee synchronized reset release. delay additional 250µs must also waited before first microprocessor access performed following de-assertion RESET pin; this delay required determination frame pulse format.
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
addition, reset signal must de-asserted less than 12µs after frame boundary more than 13µs after frame boundary, illustrated Figure This achieved, example, synchronizing de-assertion reset signal with input frame pulse FP8i.
FP8i RESET (case RESET (case 12µs RESET assertion 13µs RESET de-assertion
De-assertion RESET must fall within this window
Figure Hardware RESET De-assertion
Connection Memory
device includes connection memories, Local Connection Memory Backplane Connection Memory.
Local Connection Memory
Local Connection Memory (LCM) 16-bit wide memory with 8,192 memory locations support Local output port. most significant each word, bit[15], selects source stream from either Backplane (LSRC LOW) Local (LSRC HIGH) port determines Backplane-to-Local Local-to-Local data routing. Bits[14:13] select control modes Local output streams, per-channel Message Mode per-channel high impedance output control modes. Connection Mode (bit[14] LOW), bits[12:0] select source stream channel number detailed Table Message Mode (bit[14] HIGH), bits[12:8] unused bits[7:0] contain message byte transmitted. Bit[13] must HIGH Message Mode ensure that output channel tri-stated.
Backplane Connection Memory
Backplane Connection Memory (BCM) 16-bit wide memory with 8,192 memory locations support Backplane output port. most significant each word, bit[15], selects source stream from either Backplane (BSRC HIGH) Local (BSRC LOW) port determines Local-to-Backplane Backplane-to-Backplane data routing. Bit[14:13] select control modes Backplane output streams, namely per-channel Message Mode per-channel high impedance output control mode. Connection Mode (bit[14] LOW), bits[12:0] select source stream channel number detailed Table Message Mode (bit[14] HIGH), bits[12:8] unused bits[7:0] contain message byte transmitted. Bit[13] must HIGH Message Mode ensure that output channel tri-stated. Control Register bits MS[2:0] must select Local Connection Memory write read operations microprocessor port. Control Register bits MS[2:0] must select Backplane Connection Memory write read operations microprocessor port. Section 6.0, Microprocessor Port, Section 13.1, Control Register (CR) details microprocessor port access.
Zarlink Semiconductor Inc.
ZL50062/4
Source Stream Rate 2Mbps 4Mbps 8Mbps 16Mbps Source Stream Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Bits[12:8] legal values 0:31 Source Channel Bits[7:0] legal values 0:31 Bits[7:0] legal values 0:63 Bits[7:0] legal values 0:127 Bits[7:0] legal values 0:255
Data Sheet
Table Local Backplane Connection Memory Configuration
Connection Memory Block Programming
This feature allows fast, simultaneous, initialization Local Backplane Connection Memories after power-up. When Memory Block Programming mode enabled, contents Block Programming Register (BPR) will loaded into connection memories. Table Table details Control Register Block Programming Register values, respectively.
8.3.1
Memory Block Programming Procedure:
Control Register from HIGH. HIGH Block Programming Register (BPR). Local Block Programming data bits, LBPD[2:0], Block Programming Register, will loaded into bits[15:13] Local Connection Memory. remaining positions loaded with zeros shown Table LBPD2 LBPD1 LBPD0
Table Local Connection Memory Block Programming Mode Backplane Block Programming data bits, BBPD[2:0], Block Programming Register, will loaded into bits[15:13] respectively, Backplane Connection Memory. remaining positions loaded with zeros shown Table BBPD2 BBPD1 BBPD0
Table Backplane Connection Memory Block Programming Mode Block Programming Register bit, will automatically reset within 125µs, indicate completion memory programming. Block Programming Mode terminated time prior completion clearing Block Programming Register Control Register. Note that default values (LOW) LBPD[2:0] BBPD[2:0] Block Programming Register, following device reset, used.
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
During reset, output channels HIGH high impedance, depending value LORS BORS pins, irrespective values bits[14:13] connection memory.
Memory Built-In-Self-Test (BIST) Mode
operation memory BIST will corrupt existing data, this test must only initiated when device placed "out-of-service" isolated from live traffic. memory BIST mode enabled through microprocessor port (Section 13.7, Memory BIST Register). Internal BIST memory controllers generate memory test pattern (S-march) control memory test. memory test result monitored through Memory BIST Register.
10.0
JTAG Port
ZL50062/64 JTAG interface conforms IEEE 1149.1 standard. operation boundary-scan circuit shall controlled external Test Access Port (TAP) Controller.
10.1
Test Access Port (TAP)
Test Access Port (TAP) consists four input pins output described follows: Test Clock Input (TCK) provides clock Controller independent on-chip clock. permits shifting test data into Boundary-Scan register cells under control Controller Boundary-Scan Mode. Test Mode Select Input (TMS) controller uses logic signals applied input control test operations. signals sampled rising edge pulse. This internally pulled VDD_IO when driven from external source. Test Data Input (TDi) Depending previously applied data input, serial input data applied port connected either Instruction Register Test Data Register. Both registers described Section 10.2, Registers. applied input data sampled rising edge pulses. This internally pulled VDD_IO when driven from external source. Test Data Output (TDo) Depending previously applied sequence input, contents either instruction register data register serially shifted towards TDo. data clocked falling edge pulses. When data shifted through boundary scan cells, output high impedance state. Test Reset (TRST) TRST provides asynchronous Reset JTAG scan structure. This internally pulled high when driven from external source. This MUST pulled normal operation.
10.2
Registers
ZL50062/64 implements public instructions defined IEEE-1149.1 standard with provision Instruction Register three Test Data Registers.
10.2.1
Test Instruction Register
JTAG interface contains four-bit instruction register. Instructions serially loaded into Instruction Register from when Controller shift-IR state. Instructions subsequently decoded achieve basic functions: select Test Data Register operate while instruction current, define serial Test Data Register path shift data between during data register scanning. Please refer Figure JTAG test port timing.
Zarlink Semiconductor Inc.
ZL50062/4
10.2.2 10.2.2.1 Test Data Registers Boundary-Scan Register
Data Sheet
Boundary-Scan register consists series Boundary-Scan cells arranged form scan path around boundary ZL50062/64 core logic.
10.2.2.2
Bypass Register
Bypass register single stage shift register provide one-bit path from TDo.
10.2.2.3
Device Identification Register
JTAG device ZL50062/64 0C38E14BH. Version, Bits <31:28>:0000 Part No., Bits <27:12>:1100 0011 1000 1110 Manufacturer Bits <11:1>:0001 0100 Header, (LSB):1
10.3
Boundary Scan Description Language (BSDL) File
Boundary Scan Description Language (BSDL) file available from Zarlink Semiconductor IEEE 1149.1 test interface.
11.0
Memory Address Mappings
When most significant bit, A14, address '1', microprocessor performs access device's internal memories. Control Register bits MS[2:0] indicate which memory (Local Connection, Local Data, Backplane Connection, Backplane Data) being accessed. Address bits A0-A13 indicate which location within particular memory being accessed. Address Description
Selects memory register access register, memory).
Note that which memory (Local Connection, Local Data, Backplane Connection, Backplane Data) accessed depends MS[2:0] bits Control Register. A13-A9 A8-A0
Stream address
Streams used
Channel address 511)
Channels used when serial stream 2.048Mbps Channels used when serial stream 4.096Mbps Channels used when serial stream 8.192Mbps Channels used when serial stream 16.384Mbps Table Address Data Connection Memory Locations (A14 device contains data memory blocks, received Backplane data received Local data. data rates, received data converted parallel format internal serial-to-parallel converters stored sequentially relevant data memory.
Zarlink Semiconductor Inc.
ZL50062/4
11.1 Local Data Memory Definition
Data Sheet
8-bit Local Data Memory (LDM) 8,192 positions. locations associated with Local input streams channels. explained section above, address bits A13-A0 microprocessor define addresses streams channels. read-only configured follows:
15:8
Name Reserved default value 8'h00.
Description
Local Data Memory Local Input Channel Data.
LDM[7:0] bits contain timeslot data from Local side input stream. LDM[7] corresponds first received, i.e. ST-BUS mode, GCI-Bus mode. Figure ST-BUS GCI-Bus Input Timing Diagram Different Data Rates arrival order bits. Table Local Data Memory (LDM) Bits Note that Local Data Memory actually 8-bit wide memory. most significant bits expressed table above presented provide 16-bit microprocessor read accesses.
11.2
Backplane Data Memory Definition
8-bit Backplane Data Memory (BDM) 8,192 positions. locations associated with Backplane input streams channels. explained previously, address bits A13-A0 microprocessor define addresses streams channels. read-only configured follows: 15:8 Name Reserved
default value 8'h00.
Description
Backplane Data Memory Backplane Input Channel Data. BDM[7:0] bits contain timeslot data from Backplane side input stream. BDM[7] corresponds first received, i.e. ST-BUS mode, GCI-Bus mode. Figure ST-BUS GCI-Bus Input Timing Diagram Different Data Rates arrival order bits Table Backplane Data Memory (BDM) Bits
Note that Backplane Data Memory actually 8-bit wide memory. most significant bits expressed table above presented provide 16-bit microprocessor read accesses.
11.3
Local Connection Memory Definition
Local Connection Memory (LCM) 8,192 addresses 16-bit words. Each address, accessed through bits A13-A0 microprocessor port, allocated individual Local output stream channel. definition each 16-bit word presented Table Source-to-Local connections. most-significant memory location, LSRC, selects switch configuration Backplane-to-Local Local-to-Local. When per-channel Message Mode selected (LMM memory HIGH), lower byte word (LCAB[7:0]) will transmitted data output stream (LSTo0-31) place data defined Source Control, Stream Channel Address bits.
Zarlink Semiconductor Inc.
ZL50062/4
Name LSRC
Local Source Control
Data Sheet
Description When LOW, source from Backplane input port (Backplane Data Memory). When HIGH, source from Local input port (Local Data Memory). Ignored when HIGH.
Local Message Mode
When LOW, channel Connection Mode (data output channel originated Local Backplane Data Memory). When HIGH, channel Message Mode (data output channel originated Local Connection Memory).
Local Output Enable
When LOW, channel high impedance, either device output, external buffer dependent upon LORS pin. When HIGH, channel active. 12:8 LSAB[4:0]
Source Stream Address Bits
binary value these bits represents input stream number. Ignored when HIGH. LCAB[7:0]
Source Channel Address Bits Message Mode Data
binary value these bits represents input channel number when LOW. Transmitted data when HIGH. Note: When HIGH, both ST-BUS GCI-Bus modes, LCAB[7:0] bits output sequentially timeslot with LCAB[7] being output first. Table Bits Source-to-Local Switching
11.4
Backplane Connection Memory Definition
Backplane Connection Memory (BCM) 8,192 addresses 16-bit words. Each address, accessed through bits A13-A0 microprocessor port, allocated individual Backplane output stream channel. definition each 16-bit word presented Table Source-to-Backplane connections. most-significant memory location, BSRC, selects switch configuration Local-to-Backplane Backplane-to-Backplane. When per-channel Message Mode selected (BMM memory HIGH), lower byte word (BCAB[7:0]) will transmitted data output stream (BSTo0-31) place data defined Source Control, Stream Channel Address bits.
Name BSRC
Backplane Source Control
Description When LOW, source from Local input port (Local Data Memory). When HIGH, source from Backplane input port (Backplane Data Memory). Ignored when HIGH.
Backplane Message Mode
When LOW, channel Connection Mode (data output channel originated Backplane Local Data Memory). When HIGH, channel Message Mode (data output channel originated Backplane Connection Memory). Table Bits Source-to-Backplane Switching
Zarlink Semiconductor Inc.
ZL50062/4
Name
Backplane Output Enable
Data Sheet
Description When LOW, channel high impedance, either device output, external buffer dependent upon BORS pin. When HIGH, channel active.
12:8
BSAB[4:0]
Source Stream Address Bits
binary value these bits represents input stream number. Ignored when HIGH. BCAB[7:0]
Source Channel Address Bits Message Mode Data
binary value these bits represents input channel number when LOW. Transmitted data when HIGH. Note: When HIGH, both ST-BUS GCI-Bus modes, BCAB[7:0] bits output sequentially timeslot with BCAB[7] being output first. Table Bits Source-to-Backplane Switching (continued)
12.0
Internal Register Mappings
When most significant bit, A14, address '0', microprocessor performing access device's internal registers. Address bits A13-A0 indicate which particular register being accessed. A14-A0 0000H 0001H 0023H 0042H 0063H 0082H 0083H 00A2H 00A3H 00C2H 014DH 1001H 3FFFH Control Register, Block Programming Register, Local Input Delay Register LIDR0 Backplane Input Delay Register BIDR0 Local Output Advancement Register LOAR0 Backplane Output Advancement Register BOAR0 Memory BIST Register, MBISTR Rate Register, Device Identification Register, Table Address Registers (A14 Register
Zarlink Semiconductor Inc.
ZL50062/4
13.0 Detailed Register Descriptions
Data Sheet
This section describes registers that used device.
13.1
Control Register (CR)
Address 0000H. Control Register defines which memory accessed. initiates memory block programming mode selects Backplane Local data rate modes. Control Register (CR) configured follows: 15:13 Name FBD_ MODE[2:0] Reset Value Description
Frame Boundary Discriminator Mode
When 111B, Frame Boundary Discriminator handle both frequency high frequency jitter. When 000B, Frame Boundary Discriminator handle lower frequency jitter only. other values reserved. These bits ignored when FBDEN LOW.
Sample Point Mode
SMPL_ MODE
Reserved FBDEN
Reserved
Reserved C8IPOL
COPOL
When input sampling point always location. input fractional delay programmed increments from value LIDR0 LIDR31 BIDR0 BIDR31 registers. When HIGH, input sampling point programmed 3/4, 4/4, 1/4, location value LIDR0 LIDR31 BIDR0 BIDR31 registers. addition, incoming data delayed bits increments. Table Table Table Table details. Reserved Must normal operation Frame Boundary Discriminator Enable When LOW, frame boundary discriminator function disabled. When HIGH, enables frame boundary discriminator function which allows device tolerate inconsistent frame boundaries, hence improving tolerance cycle-to-cycle variation input clock. Reserved Must normal operation Frame Pulse Width When LOW, user must apply 122ns frame pulse FP8i; FP8o will output 122ns wide frame pulse; FP16o will output 61ns wide frame pulse. When HIGH, user must apply 244ns frame pulse FP8i; FP8o will output 244ns wide frame pulse; FP16o will output 122ns wide frame pulse. Reserved Must normal operation 8MHz Input Clock Polarity frame boundary aligned falling rising edge input clock. When LOW, frame boundary aligned clock falling edge. When HIGH, frame boundary aligned clock rising edge. Output Clock Polarity When LOW, output clock same polarity input clock. When HIGH, output clock inverted. This applies both 8MHz (C8o) 16MHz (C16o) output clocks. Table Control Register Bits
Zarlink Semiconductor Inc.
ZL50062/4
Name Reset Value Description
Data Sheet
Memory Block Programming When LOW, memory block programming mode disabled. When HIGH, connection memory block programming mode ready program Local Connection Memory (LCM) Backplane Connection Memory (BCM). Output Stand This enables BSTo0-31 LSTo0-31 serial outputs.
BSTo0-31, LSTo0-31 Disabled Disabled Enabled
Reserved MS[1:0]
Output Control with When LOW, BSTo0-31 LSTo0-31 driven HIGH high impedance, dependent BORS LORS settings respectively. When HIGH, BSTo0-31 LSTo0-31 enabled. Reserved Must normal operation Memory Select Bits These three bits select connection data memory subsequent microport memory access operations: selects Local Connection Memory (LCM) read write operations. selects Backplane Connection Memory (BCM) read write operations. selects Local Data Memory (LDM) read-only operation. selects Backplane Data Memory (BDM) read-only operation. Table Control Register Bits (continued)
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
Frame Boundary
Frame Pulse Width 122ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Frame Pulse Width 122ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Frame Pulse Width 244ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Frame Pulse Width 244ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Figure Frame Boundary Conditions, ST-BUS Operation
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
Frame Boundary
Pulse Width 122ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Pulse Width 122ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Pulse Width 244ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Pulse Width 244ns, Control Register Bit8 (FPW) Control Register Bit6 (C8IPOL)
FP8i
Figure Frame Boundary Conditions, GCI-Bus Operation
Zarlink Semiconductor Inc.
ZL50062/4
13.2 Block Programming Register (BPR)
Data Sheet
Address 0001H. Block Programming Register stores patterns loaded into connection memories when Memory Block Programming feature enabled. BPE, LBPD[2:0] BBPD[2:0] bits register must defined same write operation. HIGH commence block programming operation. Programming completed frame period initiated time within frame. returns indicate that block programming function completed. When HIGH, other bits register changed least single frame period, except abort programming operation. programming operation aborted setting either LOW, Control Register bit, MBP, LOW. register configured follows. Reset Value
15:7
Name Reserved BBPD[2:0]
Description Reserved Must normal operation Backplane Block Programming Data These bits refer value loaded into Backplane Connection Memory (BCM) when Memory Block Programming feature activated. When Control Register (CR) HIGH this register) HIGH, contents bits BBPD[2:0] loaded into bits 15-13, respectively, BCM. Bits 12-0 LOW. Local Block Programming Data These bits refer value loaded into Local Connection Memory (LCM), when Memory Block Programming feature activated. When Control Register HIGH this register) HIGH, contents bits LBPD[2:0] loaded into bits 15-13, respectively, LCM. Bits 12-0 LOW. Block Programming Enable HIGH transition this enables Memory Block Programming function. will returned after 125µs, upon completion programming. abort programming operation. Table Block Programming Register Bits
LBPD[2:0]
Zarlink Semiconductor Inc.
ZL50062/4
13.3 Local Input Delay Registers (LIDR0 LIDR31)
Data Sheet
Addresses 0023H 0042H. There thirty-two Local Input Delay Registers (LIDR0 LIDR31). When SMPL_MODE Control Register LOW, input data sampling point defaults location LIDR0 LIDR31 define input fractional delay each Local stream. possible delay adjustment 73/4 bits, steps bit. When SMPL_MODE HIGH, LIDR0 LIDR31 define input sampling point well integer delay each Local stream. input sampling point adjusted increments. delay adjusted 1-bit increments from bits. LIDR0 LIDR31 registers configured follows: LIDRn
(where
Name Reserved LID[4:0]
Reset Value
Description Reserved Must normal operation Local Input Delay Register When SMPL_MODE LOW, binary value these bits refers input fractional delay value 73/4). When SMPL_MODE HIGH, binary value LID[1:0] refers input sampling point (1/4 4/4). LID[4:2] refer integer delay value bits).
15:5
Table Local Input Delay Register (LIDRn) Bits
Zarlink Semiconductor Inc.
ZL50062/4
13.3.1 Local Input Delay Bits (LID[4:0])
Data Sheet
When SMPL_MODE LOW, these five bits define amount input delay adjustment that receiver uses sample each input. Input delay adjustment range 73/4 periods forward, with resolution period. default sampling point location. This described bits delay LID[4:0] example, LID[4:0] 10011 (19), input delay 43/4. When SMPL_MODE HIGH, binary value LID[1:0] refers input sampling point (1/4 4/4). LID[4:2] refer integer delay value bits). This means that bits delayed integer value that sampling point vary from 1/4-bit increments. Table illustrates delay sampling point selection. SMPL_MODE LID1 LID0 Input Data Delay (Default) SMPL_MODE HIGH Input Data Delay (Default) Input Data Sampling Point
LIDn
LID4
LID3
LID2
Table Local Input Delay Sampling Point Programming Table
Zarlink Semiconductor Inc.
ZL50062/4
LIDn SMPL_MODE LID1 LID0 Input Data Delay SMPL_MODE HIGH Input Data Delay
Data Sheet
LID4
LID3
LID2
Input Data Sampling Point
Table Local Input Delay Sampling Point Programming Table (continued)
13.4
Backplane Input Delay Registers (BIDR0 BIDR31)
Addresses 0063H 0082H There thirty-two Backplane Input Delay Registers (BIDR0 BIDR31). When SMPL_MODE Control Register LOW, input data sampling point defaults location BIDR0 BIDR31 define input fractional delay each Backplane stream. possible delay adjustment 73/4 bits, steps bit. When SMPL_MODE HIGH, BIDR0 BIDR31 define input sampling point well integer delay each Backplane stream. input sampling point adjusted increments. delay adjusted 1-bit increments from bits. BIDR0 BIDR31 registers configured follows: BIDRn (where 15:5 Reset Value
Name Reserved BID[4:0]
Description Reserved Must normal operation Backplane Input Delay Register When SMPL_MODE LOW, binary value these bits refers input fractional delay value 73/4). When SMPL_MODE HIGH, binary value BID[1:0] refers input sampling point (1/4 4/4). BID[4:2] refer integer delay value bits).
Table Backplane Input Delay Register (BIDRn) Bits
Zarlink Semiconductor Inc.
ZL50062/4
13.4.1 Backplane Input Delay Bits (BID[4:0])
Data Sheet
When SMPL_MODE LOW, these five bits define amount input delay adjustment that receiver uses sample each input. Input delay adjustment range 73/4 periods forward, with resolution period. default sampling point location. This described bits delay BID[4:0] example, BID[4:0] 10011 (19), input delay 43/4. When SMPL_MODE HIGH, binary value BID[1:0] refers input sampling point (1/4 4/4). BID[4:2] refer integer delay value bits). This means that bits delayed integer value that sampling point vary from 1/4-bit increments. Table illustrates delay sampling point selection. SMPL_MODE BID1 BID0 Input Data Delay (Default) SMPL_MODE HIGH Input Data Delay (Default) Input Data Sampling Point
BIDn
BID4
BID3
BID2
Table Backplane Input Delay Sampling Point Programming Table
Zarlink Semiconductor Inc.
ZL50062/4
BIDn SMPL_MODE BID1 BID0 Input Data Delay SMPL_MODE HIGH Input Data Delay
Data Sheet
BID4
BID3
BID2
Input Data Sampling Point
Table Backplane Input Delay Sampling Point Programming Table (continued)
13.5
Local Output Advancement Registers (LOAR0 LOAR31)
Addresses 0083H 00A2H. Thirty-two Local Output Advancement Registers (LOAR0 LOAR31) allow users program output advancement output data streams LSTo0 LSTo31. possible adjustment (15ns), (31ns) (46ns) cycles internal system clock (131.072MHz). LOAR0 LOAR31 registers configured follows: LOARn (where 15:2 Reset Value
Name Reserved LOA[1:0]
Description Reserved Must normal operation Local Output Advancement Value
Table Local Output Advancement Register (LOAR) Bits
13.5.1
Local Output Advancement Bits (LOA1-LOA0)
binary value these bits indicates amount offset that particular stream output advanced with respect output frame boundary. When advancement serial output stream normal alignment with generated frame pulse FP8o. Corresponding Advancement Bits LOA1 LOA0
Local Output Advancement Clock Rate 131.072 (Default) cycles (~15ns) cycles (~31ns) cycles (~46ns)
Table Local Output Advancement (LOAR) Programming Table
Zarlink Semiconductor Inc.
ZL50062/4
13.6 Backplane Output Advancement Registers (BOAR0 BOAR31)
Data Sheet
Addresses 00A3H 00C2H Thirty-two Backplane Output Advancement Registers (BOAR0 BOAR31) allow users program output advancement output data streams BSTo0 BSTo31. possible adjustment (15ns), (31ns) (46ns) cycles internal system clock (131.072MHz). BOAR0 BOAR31 registers configured follows: BOARn
(where
Name Reserved BOA[1:0]
Reset Value
Description Reserved Must normal operation Backplane Output Advancement Value
15:2
Table Backplane Output Advancement Register (BOAR) Bits
13.6.1
Backplane Output Advancement Bits (BOA1-BOA0)
binary value these bits indicates amount offset that particular stream output advanced with respect output frame boundary. When advancement serial output stream normal alignment with generated frame pulse FP8o. Corresponding Advancement Bits BOA1 BOA0
Backplane Output Advancement Clock Rate 131.072 (Default) cycles (~15ns) cycles (~31ns) cycles (~46ns)
Table Backplane Output Advancement (BOAR) Programming Table
13.7
Memory BIST Register
Address 014DH. Memory BIST Register enables self-test chip memory. consecutive write operations required start MBIST: first with only (LV_TM) HIGH (i.e. 1000h); second with maintained HIGH with required start bit(s) also HIGH. MBISTR register configured follows: Reset Value
Reserved
15:13
Name Reserved
Description
Must normal operation Table Memory BIST Register (MBISTR) Bits
Zarlink Semiconductor Inc.
ZL50062/4
Name LV_Reset Value
MBIST Test Enable
Data Sheet
Description
HIGH enable MBIST mode. normal operation. BISTSDB BISTCDB
Backplane Data Memory Start BIST Sequence
Sequence enabled HIGH transition.
Backplane Data Memory BIST Sequence Completed (Read-only)
This must polled when HIGH, indicates completion Backplane Data Memory BIST sequence. BISTPDB
Backplane Data Memory Pass/Fail (Read-only)
This indicates Pass/Fail status following completion Backplane Data Memory BIST sequence (indicated assertion BISTCDB). HIGH indicates Pass, indicates Fail. BISTSDL BISTCDL
Local Data Memory Start BIST Sequence
Sequence enabled HIGH transition.
Local Data Memory BIST Sequence Completed (Read-only)
This must polled when HIGH, indicates completion Local Data Memory BIST sequence. BISTPDL
Local Data Memory Pass/Fail (Read-only)
This indicates Pass/Fail status following completion Local Data Memory BIST sequence (indicated assertion BISTCDL). HIGH indicates Pass, indicates Fail. BISTSCB BISTCCB
Backplane Connection Memory Start BIST Sequence
Sequence enabled HIGH transition.
Backplane Connection Memory BIST Sequence Completed (Read-only)
This must polled when HIGH, indicates completion Backplane Connection Memory BIST sequence. BISTPCB
Backplane Connection Memory Pass/Fail (Read-only)
This indicates Pass/Fail status following completion Backplane Connection Memory BIST sequence (indicated assertion BISTCCB). HIGH indicates Pass, indicates Fail. BISTSCL BISTCCL
Local Connection Memory Start BIST Sequence
Sequence enabled HIGH transition.
Local Connection Memory BIST Sequence Completed (Read-only)
This must polled when HIGH, indicates completion Local Connection Memory BIST sequence. BISTPCL
Local Connection Memory Pass/Fail (Read-only)
This indicates Pass/Fail status following completion Local Connection Memory BIST sequence (indicated assertion BISTCCL). HIGH indicates Pass, indicates Fail. Table Memory BIST Register (MBISTR) Bits (continued)
Zarlink Semiconductor Inc.
ZL50062/4
13.8 Rate Register
Data Sheet
Address 1001H This register allows rate input output streams 2.048, 4.096, 8.192 16.384 Mbps. register configured follows: Reset Value
Reserved
15:3
Name Reserved BRS[1:0]
Description
Must normal operation
Rate Selector
These bits define rate input output ST-BUS streams, which operate either 2.048, 4.096, 8.192 16.384 Mbps.
Rate ST-BUS Streams 2.048Mbps 4.096Mbps 8.192Mbps 16.384Mbps
Output Control with Reserved
Reserved
Must normal operation Table Rate Register (BRR) Bits
13.9
Device Identification Register
Address 3FFFH. Device Identification Register stores binary value silicon revision number Device This register read-only. register configured follows: 15:8 Name Reserved RC[3:0] Reserved DID[2:0] Reset Value 0000
Reserved
Description Will read normal operation
Revision Control Bits Reserved
Will read normal operation
Device
Table Device Identification Register (DIR) Bits
Zarlink Semiconductor Inc.
ZL50062/4
14.0 Electrical Characteristics
Data Sheet
Absolute Maximum Ratings* Parameter Core Supply Voltage Supply Voltage Supply Voltage Input Voltage (non-5V tolerant inputs) Input Voltage tolerant inputs) Continuous Current digital outputs Package power dissipation Symbol VDD_CORE VDD_IO VDD_PLL VI_5V -0.5 -0.5 -0.5 -0.5 -0.5 VDD_IO +0.5 +125 Units
Storage temperature Exceeding these values cause permanent damage. Functional operation under these conditions implied.
Recommended Operating Conditions Characteristics Operating Temperature Positive Supply Positive Supply Positive Supply Input Voltage Input Voltage Tolerant Inputs VDD_IO VDD_CORE VDD_PLL VI_5V 1.71 1.71 1.89 1.89 VDD_IO Units
Voltages with respect ground (VSS) unless otherwise stated.
Zarlink Semiconductor Inc.
ZL50062/4
Electrical Parameters Characteristics Input High Voltage Input Voltage Input Leakage (input pins) Input Leakage (bi-directional pins) Weak Pullup Current Weak Pulldown Current Input Capacitance Output High Voltage Output Voltage High impedance Leakage Output Capacitance Supply Current Supply Current IDD_IO IDD_IO Supply Current IDD_Core Supply Current IDD_Core Units
Data Sheet
Test Conditions Static IDD_Core current Applied clock 8.192 Static IDD_IO with output streams max. data rate unloaded
VDD_IO Note Input Input VDD_IO VDD_IO Note
Voltages with respect ground (Vss) unless otherwise stated. Note Maximum leakage pins (output pins high impedance state) over applied voltage
Zarlink Semiconductor Inc.
ZL50062/4
15.0 Electrical Characteristics
Data Sheet
Electrical Characteristics Timing Parameter Measurement: Voltage Levels Characteristics CMOS Threshold Rise/Fall Threshold Voltage High Rise/Fall Threshold Voltage Level 0.5VDD_IO 0.7VDD_IO 0.3VDD_IO Units Conditions 3.0V VDD_IO 3.6V 3.0V VDD_IO 3.6V 3.0V VDD_IO 3.6V
Input Output Clock Timing Characteristic FP8i, Input Frame Pulse Width Input Frame Pulse Setup Time (before clock falling/rising edge) Input Frame Pulse Hold Time (from clock falling/rising edge) Clock Period (Average value, does consider effects jitter) Clock Pulse Width High Clock Pulse Width Clock Rise/Fall Time Cycle Cycle Variation (This values with respect typical Clock Period, using mid-bit sampling) Output Frame Boundary Offset FP8o Frame Pulse Width tIFPW244 tIFPW122 tIFPS244 tIfPS122 tIFPH244 tIFPH122 tICP tICH tICL trIC, tfIC tCCVIC -7.0 -8.5 tOFBOS tOFPW8_244 tOFPW8_122 tFPFBF8_244 tFPFBF8_122 tFBFPF8_244 tFBFPF8_122 tOCP8 tOCH8 tOCL8 trOC8, tfOC8 FPW=0 CL=60pF FPW=0 CL=60pF FPW=0 CL=60pF CL=60pF Units 16Mbps lower. Notes
FP8o Output Delay (from frame pulse edge output frame boundary) FP8o Output Delay (from output frame boundary frame pulse edge) Clock Period Clock Pulse Width High Clock Pulse Width Clock Rise/Fall Time
Zarlink Semiconductor Inc.
ZL50062/4
Input Output Clock Timing (continued) Characteristic FP16o Frame Pulse Width tOFPW16_122 tOFPW16_61 tFPFBF16_122 tFPFBF16_61 tFBFPF16_122 tFBFPF16_61 tOCP16 tOCH16 tOCL16 trOC16, tfOC16 Units
Data Sheet
Notes FPW=0 CL=60pF FPW=0 FPW=0
FP16o Output Delay (from frame pulse edge output frame boundary) FP16o Output Delay (from output frame boundary frame pulse edge) C16o Clock Period C16o Clock Pulse Width High C16o Clock Pulse Width C16o Clock Rise/Fall Time
CL=60pF
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
tIFPW244 FP8i (244ns) tIFPS244 tIFPW122 tIFPH244
FP8i (122ns) tIFPS122 tICL tICH
tIFPH122 tICP
trIC
tfIC
CK_int tOFBOS FP8o (244ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122ns) tFPFBF8_122 tOCL8 trOC8 tOFPW16_122 FP16o (122ns) tFPFBF16_122 tOFPW16_61 FP16o (61ns) tFPFB16_61 tOCL16 C16o trOC16 tfOC16 tOCH16 tFBFP16_61 tOCP16 tFBFPF16_122 tfOC8 tOCH8 tFBFPF8_122 tOCP8
Note CK_int internal clock signal 131.072MHz Note Although figures above show frame boundary measured from falling edge C8i/C8o/C16o, frame-controlling edge C8i/C8o/C16o rising edge, configured C8iPOL COPOL bits Control Register.
Figure Input Output Clock Timing Diagram ST-BUS
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8i (244ns) tIFPS244 FP8i (122ns) tIFPS122 tICL tICH tIFPW122
tIFPW244
tIFPH244
tIFPH122 tICP
trIC
tfIC
CK_int tOFBOS FP8o (244ns) tFPFBF8_244
tOFPW8_122
tOFPW8_244
tFBFPF8_244
FP8o (122ns) tFPFBF8_122 tOCL8 tOCH8 tFBFPF8_122 tOCP8
trOC8 tOFPW16_122 FP16o (122ns) tFPFBF16_122 tOFPW16_61 FP16o (61ns) tFPFB16_61 tOCH16 C16o tfOC16 tOCL16 tFBFP16_61 tOCP16 tFBFPF16_122
tfOC8
trOC16
Note CK_int internal clock signal 131.072MHz Note Although figures above show frame boundary measured from rising edge C8i/C8o/C16o, frame-controlling edge C8i/C8o/C16o rising edge, configured C8iPOL COPOL bits Control Register.
Figure Input Output Clock Timing Diagram GCI-Bus
Zarlink Semiconductor Inc.
ZL50062/4
Local Backplane Data Timing Characteristic Local/Backplane Input Data Sampling Point tIDS16 tIDS8 tIDS4 tIDS2 tSIS16 tSIS8 tSIS4 tSIS2 tSIH16 tSIH8 tSIH4 tSIH2 tOFBOS tSOD16 tSOD8 tSOD4 tSOD2 Units
Data Sheet
Notes With SMPL_MODE (3/4-bit sampling) zero offset. With respect Min. Input Data Sampling Point
Local/Backplane Serial Input Set-up Time
Local/Backplane Serial Input Hold Time
With respect Max. Input Data Sampling Point
Output Frame Boundary Offset Local/Backplane Serial Output Delay
CL=50pF These numbers referencing output frame boundary.
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8i CK_int
tIDS8 tSIS8 tSIH8
L/BSTi0-31 8.192Mbps
tIDS4
tSIS4 tSIH4
L/BSTi0-31 4.096Mbps
Bit0 Ch63
Bit7
Bit6
Bit5
Bit4
tIDS2 tSIS2 tSIH2
L/BSTi0-31 2.048Mbps
Bit0 Ch31
Bit7
Bit6
tOFBOS FP8o CK_int
tSOD8
L/BSTo0-31 8.192Mbps
Bit1 Ch127
Bit0 Ch127
Bit7
Bit6
Bit5
Bit4
Bit3
Bit2
Bit1
tSOD4
L/BSTo0-31 4.096Mbps
Bit0 Ch63
Bit7
Bit6
Bit5
Bit4
tSOD2
L/BSTo0-31 2.048Mbps
Bit0 Ch31
Bit7
Bit6
Note CK_int internal clock signal 131.072MHz
Figure ST-BUS Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps)
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8i CK_int tIDS16
tSIS16 tSIH16
L/BSTi0-31 16.384Mbps
Bit1 Ch255
Bit0 Ch255
Bit7
Bit6
Bit5
tOFBOS FP8o CK_int tSOD16 L/BSTo0-31 16.384Mbps
Bit0 Ch255 Bit7 Bit6 Bit5
Note CK_int internal clock signal 131.072MHz
Figure ST-BUS Local/Backplane Data Timing Diagram (16Mbps)
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8i CK_int
tIDS8 tSIS8 tSIH8
L/BSTi0-31 8.192Mbps
tIDS4
tSIS4 tSIH4
L/BSTi0-31 4.096Mbps
Bit7 Ch63
Bit0
Bit1
Bit2
Bit3
tIDS2 tSIS2 tSIH2
L/BSTi0-31 2.048Mbps
Bit7 Ch31 Bit0 Bit1
tOFBOS
FP8o CK_int
tSOD8
L/BSTo0-31 8.192Mbps
Bit6 Ch127 Bit7 Ch127 Bit0 Bit1 Bit2 Bit3 Bit4 Bit5 Bit6
tSOD4
L/BSTo0-31 4.096Mbps
Bit7 Ch63 Bit0 Bit1 Bit2 Bit3
tSOD2
L/BSTo0-31 2.048Mbps
Bit7 Ch31 Bit0 Bit1
Note CK_int internal clock signal 131.072MHz
Figure GCI-Bus Local/Backplane Data Timing Diagram (8Mbps, 4Mbps, 2Mbps)
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
FP8i CK_int tIDS16
tSIS16 tSIH16
L/BSTi0-31 16.384Mbps
Bit6 Ch255
Bit7 Ch255
Bit0
Bit1
Bit2
tOFBOS FP8o CK_int tSOD16 L/BSTo0-31 16.384Mbps
Bit7 Ch255 Bit0 Bit1 Bit2
Note CK_int internal clock signal 131.072MHz
Figure GCI-Bus Local/Backplane Data Timing Diagram (16Mbps)
Zarlink Semiconductor Inc.
ZL50062/4
Local Backplane Output High Impedance Timing Characteristic delay Active High-Z High-Z Active Output Driver Enable (ODE) Delay Active Data Output Driver Enable (ODE) Delay high impedance tODE tODZ Units
Data Sheet
Test Conditions RL=1k, CL=50pF, Note
RL=1k, CL=50pF, Note RL=1k, CL=50pF, Note
Note
High Impedance measured pulling appropriate rail with with timing corrected cancel time taken discharge
Valid Data
Valid Data
Figure Serial Output External Control
tODE tODZ
Hi-Z
Valid Data
Hi-Z
Figure Output Driver Enable (ODE)
Zarlink Semiconductor Inc.
ZL50062/4
Input Clock Jitter Tolerance Jitter Frequency 1kHz 10kHz 50kHz 66kHz 83kHz 95kHz 100kHz 200kHz 300kHz 400kHz 500kHz 1MHz 2MHz 4MHz 16.384Mbps Data Rate Jitter Tolerance 1200 1200 Units
Data Sheet
Zarlink Semiconductor Inc.
ZL50062/4
Non-Multiplexed Microprocessor Port Timing Characteristics setup from falling setup from falling Address setup from falling hold after rising hold after rising Address hold after rising Data setup from Read tCSS tRWS tADS tCSH tRWH tADH tRDS tAKH Units
Data Sheet
Test Conditions
Memory Read Register Read CL=60pF CL=60pF, RL=1k Note
Data hold read Data setup write Data hold write Acknowledgment Delay: Reading/Writing Registers Reading/Writing Memory Acknowledgment Hold Time
tRDH tWDS tWDH tAKD
CL=60pF CL=60pF CL=60pF, RL=1k, Note
Note Note
High Impedance measured pulling appropriate rail with with timing corrected cancel time taken discharge There must minimum 30ns between accesses, allow device recognize accesses separate (i.e., minimum 30ns must separate de-assertion high) assertion and/or initiate next access).
Zarlink Semiconductor Inc.
ZL50062/4
Data Sheet
tCSS tRWS tADS A0-A14
VALID ADDRESS
tCSH
tRWH tADH tRDH
D0-D15 READ tWDS D0-D15 WRITE
VALID READ DATA
tWDH
VALID WRITE DATA
tRDS
tAKD tAKH
Figure Motorola Non-Multiplexed Timing
Zarlink Semiconductor Inc.
ZL50062/4
Electrical Characteristics JTAG Test Port Timing Characteristic Clock Period Clock Pulse Width High Clock Pulse Width Set-up Time Hold Time Input Set-up Time Input Hold Time Output Delay TRST pulse width tTCKP tTCKH tTCKL tTMSS tTMSH tTDIS tTDIH tTDOD tTRSTW Units
Data Sheet
Notes
CL=30pF
Characteristics over recommended operating conditions unless otherwise stated.
tTCKL
tTCKH
tTCKP
tTMSS
tTMSH
tTDIS tTDIH
tTDOD
tTRSTW TRST
Figure JTAG Test Port Timing Diagram
Zarlink Semiconductor Inc.
Zarlink Semiconductor 2003 rights reserved.
Package Code Previous package codes
ISSUE DATE APPRD.
Zarlink Semiconductor 2003 rights reserved.
Package Code Previous package codes
ISSUE DATE APPRD.
214440 26June03
more information about Zarlink products visit Site
www.zarlink.com
Information relating products services furnished herein Zarlink Semiconductor Inc. trading Zarlink Semiconductor subsidiaries (collectively "Zarlink") believed reliable. However, Zarlink assumes liability errors that appear this publication, liability otherwise arising from application such information, product service infringement patents other intellectual property rights owned third parties which result from such application use. Neither supply such information purchase product service conveys license, either express implied, under patents other intellectual property rights owned Zarlink licensed from third parties Zarlink, whatsoever. Purchasers products also hereby notified that product certain ways combination with Zarlink, non-Zarlink furnished goods services infringe patents other intellectual property rights owned Zarlink.
This publication issued provide information only (unless agreed Zarlink writing) used, applied reproduced purpose form part order contract regarded representation relating products services concerned. products, their specifications, services other information appearing this publication subject change Zarlink without notice. warranty guarantee express implied made regarding capability, performance suitability product service. Information concerning possible methods provided guide only does constitute guarantee that such methods will satisfactory specific piece equipment. user's responsibility fully determine performance suitability equipment using such information ensure that publication data used date been superseded. Manufacturing does necessarily include testing functions parameters. These products suitable medical products whose failure perform result significant injury death user. products materials sold services provided subject Zarlink's conditions sale which available request.
Purchase Zarlink's components conveys licence under Philips Patent rights these components System, provided that system conforms Standard Specification defined Philips. Zarlink, Zarlink Semiconductor logo trademarks Zarlink Semiconductor Inc. Copyright Zarlink Semiconductor Inc. Rights Reserved.
TECHNICAL DOCUMENTATION RESALE
Other recent searches
STR83145 - STR83145 STR83145 Datasheet
STR84145 - STR84145 STR84145 Datasheet
RJK0368DPA - RJK0368DPA RJK0368DPA Datasheet
PFC4500 - PFC4500 PFC4500 Datasheet
PFC1500 - PFC1500 PFC1500 Datasheet
NEA005 - NEA005 NEA005 Datasheet
NE440YL1A-A11 - NE440YL1A-A11 NE440YL1A-A11 Datasheet
NCP1086 - NCP1086 NCP1086 Datasheet
ISP1564 - ISP1564 ISP1564 Datasheet
A8450 - A8450 A8450 Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
