Four full-duplex multi-protocol channels, each running 134.4 kbits/sec
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CL-CD2431
Four full-duplex multi-protocol channels, each running 134.4 kbits/second (with MHz) Supports async, async-HDLC (high-level data link control), HDLC/SDLC (synchronous data link control; non-multidrop) channels 32-bit address, 16-bit data, double-buffered controller each transmitter receiver; independent bit-rate generators channel transmit receive On-chip (nonreturn-to-zero), NRZI (nonreturn-tozero inverted), Manchester data encoding decoding DPLL (digital phase locked loop) each receiver independent timers channel
Advanced Multi-Protocol Communications Controller
OVERVIEW
CL-CD2431 4-channel synchronous/asynchronous communications controller specifically designed reduce host-system processing overhead increase efficiency wide variety communications applications. CL-CD2431 packaged 100-pin PQFP, offers eight clock/modem pins channel. device four fully independent serial channels that support asynchronous, asynchronous-HDLC, bit-synchronous (HDLC/SDLC) protocols. CL-CD2431 based proprietary on-chip RISC processor that performs time-critical, lowlevel tasks that otherwise performed host system.
(cont.)
(Point-to-Point Protocol) Features
Supports data link level RFC-1661 Supports dual async control character maps control characters) RFC-1662
Async-HDLC Features
Compatible with 3309/4335 Addendum Automatic insertion deletion control/ escape characters complements Automatic generation detection 16-bit (frame check sequence)
(cont.)
Functional Block Diagram
HOST INTERFACE LOGIC HOST INTERFACE
MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL MODEM RECEIVE/CRC TRANSMIT/CRC TIMER/BRG/DPLL
SERIAL INTERFACE CHANNELS
ON-CHIP CONTROLLER INTERFACE LOGIC
FIRMWARE
PROPRIETARY RISC PROCESSOR
Version
World Wide Web: http://www.basiscomm.com
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
FEATURES (cont.)
MNP® V.42 Features
AppleTalk® Remote Access Protocol 1.0/2.0
Flow-control transparency, LNext Programmable timer closely coupled with character reception, especially asynchronous receive operation
SLIP Features
Supports data link level RFC-1055
Controller Features
interrupt selectable channel direction Dual Configuration register sets reduce realtime constraints Append Block mode Chain/unchain long frames into multiple buffers 32-bit address 16-bit data transfer Programmable buffers following receive character exception
HDLC/SDLC (Non-multidrop) Features
Four 8-bit 16-bit frame address matching generation validation (cyclic redundancy check) optionally readable Programmable leading-pad character transmission Supports shared flags receive frames Programmable number leading flags
Asynchronous Features
User-programmable automatic flow control modes In-band (software) XON/XOFF Out-of-band (hardware flow control) RTS/CTS DTR/DSR Line break detection generation Special-character character-range recognition transmission Transmit delay 8-bit character plus optional parity Enhanced features UNIX® environment Character expansion transmit (for example, sending <LF> will expanded <CR> <LF> automatically) Programmable translation receiving character with error different pattern (for example, character with parity error translated into FFh, 00h, character system side)
Other Features
Improved interrupt schemes Vectored interrupts channel allow direct jump into proper service routines Good Datainterrupts eliminate need status checks Easily cascadable multiple-device configurations 16-byte receive transmit FIFOs Local remote maintenance loopback modes Byte-endian-orientation selection allows easy interface 80X86 680X0 processors Eight clock/modem control signals channel addition RxD)
OVERVIEW (cont.)
CL-CD2431 boosts system efficiency with onchip DMA, on-chip FIFOs, intelligent vectored interrupts, intelligent protocol processing. onchip controller provides `fire-and-forget' transmit support host need only inform CL-CD2431 location packet sent. Similarly, receive, CL-CD2431 automatically receives complete packet with host intervention assistance required. controller also `Append mode' asynchronous applications. controller uses dual-buffer scheme that easily implements simple complex buffer schemes. Each channel direction active buffers. CL-CD2431 programmed interrupt host completion frame buffer. applications where buffers small, fixed size, dual-buffer scheme allows large frames divided into multiple buffers. applications where interface desired, device operated interruptdriven polled device. This choice available individually each channel each direction. example, channel programmed transmit interrupt-driven receive. either case, 16-byte FIFOs each channel each direction reduce latency time requirements, making both software hardware designs less
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CL-CD2431
Advanced Multi-Protocol Communications Controller
OVERVIEW (cont.)
time-critical. Threshold levels FIFOs userprogrammable. Efficient vectored interrupts another CL-CD2431 help system efficiency. Separate interrupts generated transmit, receive, modem-signal change, with unique user-defined vectors each type channel. This allows very flexible interfacing fast, efficient interrupt coding. example, Good Datainterrupt allows host vector directly routine that transfers data status error checking required.
Benefits
Substantially reduced host overhead means more channels faster overall throughput. time-critical host software enables faster, easier software development. Smallest possible footprint multi-channel device.
CL-CD2XXX Family Compatibility
Features
Number serial channels Interrupt on-chip mechanism FIFO depth (per channel direction) Data size (bits) ASYNC SDLC/HDLC X.21, BISYNC Async-HDLC, SLIP MNP® Serial data rate (kbits/second) Number modem leads (per channel, including TxD) On-chip timers UNIX® character processing In-band flow control Special character recognition Package System interface compatibility
CL-CD2231
CL-CD2401
128/134.4c 100-pin PQFP CL-CD2431/CD2231
CL-CD2431
256/230.4
128/134.4c (Revision 100-pin PQFP CL-CD2401/CD2231
100-pin PQFP CL-CD2401/CD2431
indicates identical operation register setting.
indicates available production revision (Revision later. clock frequency required obtain maximum rates. 134.4 kbps/230.4 kbps async modes, kbps/256 kbps sync modes: applies Revision later CL-CD2401, Revision later CL-CD2431, Revision later CL-CD2231. UNIX character processing available ASYNC only.
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Before beginning design with this device, please contact Basis Communications latest errata information. back cover this document sales office locations phone numbers.
TABLE CONTENTS REVISION HISTORY CONVENTIONS INFORMATION
Diagram CL-CD2431. Functions CL-CD2431 Descriptions. 3.3.6 Transmit Timer Operation 3.4.1 Acquisition Cycle 3.4.2 Data Transfer 3.4.3 Error Handling 3.4.4 Buffers Chaining 3.4.5 Transmit Transfer 3.4.6 Synchronous Transmitter Examples 3.4.7 Receive Transfer 3.4.8 Transmit Transfer 3.4.9 Receive Buffer Interrupts Rate Generation Data Encoding.50 3.5.1 DPLL Operation Hardware Configurations 3.6.1 Interface 32-Bit Data Bus.60 3.6.2 Connections CL-CD2431.60 3.6.3 Recommended CL-CD2431 Interface
REGISTER TABLE.
Memory Map. 2.1.1 Global Registers 2.1.2 Option Registers. 2.1.3 Rate Clock Option Registers 2.1.4 Channel Command Status Registers 2.1.5 Interrupt Registers 2.1.6 Registers 2.1.7 Timer Registers Register Definitions. 2.2.1 Global Registers 2.2.2 Option Registers. 2.2.3 Rate Clock Option Registers 2.2.4 Channel Command Status Registers 2.2.5 Interrupt Registers 2.2.6 Registers 2.2.7 Timer Registers
4.1.1 4.1.2 4.1.3 4.2.1 4.2.2 4.2.3 4.2.4 4.2.5 4.2.6 4.2.7 4.3.1 4.3.2 4.4.1 4.4.2
PROTOCOL PROCESSING.
FUNCTIONAL DESCRIPTION
Host Interface. 3.1.1 Host Read Write Cycles 3.1.2 Byte Word Transfers. Interrupts. 3.2.1 Contexts Channels 3.2.2 Interrupt Registers 3.2.3 Groups Types. 3.2.4 Hardware Signals IACK Cycles 3.2.5 Multi-CL-CD2431 Systems FIFO Timer Operations 3.3.1 Receive FIFO Operation. 3.3.2 Transmit FIFO Operation 3.3.3 Timers. 3.3.4 Timers Synchronous Protocols. 3.3.5 Timers Asynchronous Protocols
HDLC Processing (Frame Check Sequence).62 HDLC Transmit Mode.62 HDLC Receive Mode (Point-to-Point Protocol) Mode.63 Character Format.63 Frame Format (Frame Check Sequence).64 Transparency Definition Valid Frame Transmitter Receiver.66 SLIP Processing Framing.67 Debugging Aids MNP® 4/ARAP Protocol Processing.68 Framing.68 MNP® 4/ARAP (Frame Check Sequence) Calculation Async Processing 4.5.1 Transmitter In-Band Flow Control 4.5.2 Out-of-Band Flow Control
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CL-CD2431
Advanced Multi-Protocol Communications Controller
4.5.3 4.5.4 4.5.5
Line Break Detection Generation Special Character Transmission Special Character Recognition Special Character Range 4.5.6 Special Character Range 4.5.7 UNIX Support Features Non-8-Bit Data Transfers.
5.6.1 5.6.2
PROGRAMMING EXAMPLES.
Global Initialization. Async Interrupt Setup Example HDLC Channel Setup Example Receive Interrupt Service Routine Transmit Interrupt Service Routine Support Files. Basis Communications Server Access.
DETAILED REGISTER DESCRIPTIONS
Global Registers 6.1.1 Global Firmware Revision Code Register (GFRCR) 6.1.2 Channel Access Register (CAR) Option Registers 6.2.1 Channel Mode Register (CMR) 6.2.2 Channel Option Register (COR1). 6.2.3 Channel Option Register (COR2). 6.2.4 Channel Option Register (COR3). 6.2.5 Channel Option Register (COR4). 6.2.6 Channel Option Register (COR5). 6.2.7 Channel Option Register (COR6) Async Mode Only 6.2.8 Channel Option Register (COR7) Async Mode Only 6.2.9 Special Character Registers Async Modes Only 6.2.10 Special Character Range Register Async Mode Only 6.2.11 LNext Character (LNXT) Async Mode Only 6.2.12 Receive Frame Address Registers HDLC Sync Mode Only 6.2.13 Polynomial Select Register (CPSR)
6.2.14 Transmit Special Mapped Characters Mode only .106 6.2.15 Transmit Async Control Character Maps Mode Only .107 6.2.16 Receive Async Control Character Maps Mode Only .108 Rate Clock Option Registers .109 6.3.1 Receive Rate Generator Registers.109 6.3.2 Transmit Rate Generator Registers .111 Channel Command Status Registers.113 6.4.1 Channel Command Register (CCR) .113 6.4.2 Special Transmit Command Register (STCR) .116 6.4.3 Channel Status Register (CSR).119 6.4.4 Modem Signal Value Registers (MSVR) .123 Interrupt Registers .124 6.5.1 General Interrupt Registers .124 6.5.2 Receive Interrupt Registers .129 6.5.3 Transmit Interrupt Registers.140 6.5.4 Modem Interrupt Registers .145 Registers.149 6.6.1 Receive Registers.151 6.6.2 Transmit Registers .156 Timer Registers.165 6.7.1 Timer Period Register (TPR) .165 6.7.2 Receive Timeout Period Register (RTPR) Async Mode Only .166 6.7.3 General Timer (GT1) Sync Modes Only .167 6.7.4 General Timer (GT2) Sync Modes Only .168 6.7.5 Transmit Timer Register (TTR) Async Modes Only .168
ELECTRICAL SPECIFICATIONS.169
Absolute Maximum Ratings .169 Electrical Characteristics .169 Electrical Characteristics.170
PACKAGE SPECIFICATIONS .180 ORDERING INFORMATION EXAMPLE.181 INDEX .183 INDEX .187
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CL-CD2431
Advanced Multi-Protocol Communications Controller
REVISION HISTORY
Major changes between previous data book (dated March 1995) this version listed below. Section Revision been added register. This allows optional internal synchronization DTACK input BUSCLK. This must external logic does synchronize DTACK input with BUSCLK before applied input pin. register-description format been changed better describe register options. Timing diagrams tables that reflect maximum clock frequency (Revision later devices only) have been added. index been added.
Index
REVISION HISTORY
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CL-CD2431
Advanced Multi-Protocol Communications Controller
CONVENTIONS
This section lists abbreviations acronyms used this data book.
Acronyms
Acronym
Definition
alternating current rate generation byte synchronous complementary metal-oxide semiconductor cyclic redundancy chack direct current data communication equipment direct-memory access digital phase-locked loop dynamic random-access memory data terminal equipment frame check sequence first in/first high-level data link control industry standard architecture least-significant most-significant nonreturn zero nonreturn zero inverted point-to-point protocol plastic quad-flat pack random-access memory read/write synchronous data link control
Abbreviations
Symbol
Kbit kbits/sec. kbps Kbyte kbytes/sec. Mbyte
bisync
Units measure
degree Celsius microfarad microsecond (1,000 nanoseconds) hertz (cycle second) kilobit (1,024 bits) kilobit (1,000 bits) second kilobyte (1,024 bytes) kilobyte (1,000 bytes) second kilohertz kilohm megabyte (1,048,576 bytes) megahertz (1,000 kilohertz) milliampere millisecond (1,000 microseconds) nanosecond picovolt volt watt
CMOS DPLL DRAM FIFO HDLC NRZI PQFP SDLC SLIP
`tbd' indicates values that determined', `n/a' designates `not available', `n/c' indicates that connect'.
transistor-transistor logic
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DATA BOOK v3.0
CONVENTIONS
CL-CD2431
Advanced Multi-Protocol Communications Controller
INFORMATION
Diagram CL-CD2431
A/D[14] A/D[13] A/D[12] CD*[0] A/D[11] A/D[10] A/D[9] A/D[8] A/D[7] A/D[6] A/D[5] A/D[4] A/D[3] A/D[2] A/D[1] A/D[0] BERR*
RXCIN[3] TXCIN[3] DSR*[0] CTS*[0] TXCOUT/DTR*[0] RTS*[0] DSR*[1] CTS*[1] TXCOUT/DTR*[1] RTS*[1] DSR*[2] CTS*[2] TXCOUT/DTR*[2] RTS*[2] DSR*[3] CTS*[3] TXCOUT/DTR*[3] RTS*[3] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] A/D[15]
TXCIN[2] RXCIN[2] TXCIN[1] RXCOUT[3] RXCIN[1] TXCIN[0] RXCIN[0] TXD[3] TXD[2] TXD[1] TXD[0] RXD[3] RXCOUT[2] RXD[2] RXD[1] RXD[0] TEST RXCOUT[1] BYTESWAP
CL-CD2431
100-Pin PQFP
AEN* ADLD* DATEN* DATDIR* RESET* RXCOUT[0] IREQ*[3] IREQ*[2] CD*[3] IREQ*[1] IACKOUT* CD*[2] IACKIN* DTACK* R/W* BGACK* CD*[1] BGOUT* BGIN* BUSCLK SIZ[1] SIZ[0]
INFORMATION
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Functions CL-CD2431
Serial
[0-7] [0-15] R/W* DTACK* [0-1] BUSCLK BERR* RESET* TEST ADLD* AEN* DATDIR* DATEN* BYTESWAP IACKIN* IACKOUT* IREQ*[1-3] BGIN* BGOUT* BGACK*
Host Signals
TXCIN RXCIN TXCOUT/DTR* RXCOUT RTS* CTS* DSR*
CD2431
Serial Serial
Serial
Arbitration Signals
Interrupt Signals
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INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Descriptions
following conventions used pin-description tables:
after name indicates that signal active-low indicates input-only indicates output-only `I/O' indicates bidirectional `OD' indicates open-drain; pins must terminated 4.7-K resistor `TS' indicates tristate indicates ascending numbers indicates descending numbers
Table 1-1. Descriptions
Symbol
Number
Type
Description
CHIP SELECT*: When low, CL-CD2431 registers read written host processor. ADDRESS STROBE*: When CL-CD2431 master, this output that indicates that R/W*, A[0-7], externally latched A[8-31] valid. DATA STROBE*: When CL-CD2431 master, this input used strobe data into registers during write cycles enable data onto during read cycles. When CL-CD2431 master, output used control data transfer from system memory. READ/WRITE*: When CL-CD2431 master, this input that determines read write operation required when signals active. When CL-CD2431 master, R/W* output indicates whether read from write system memory being performed. DATA TRANSFER ACKNOWLEDGE*: When CL-CD2431 master, this output indicates host when read write CL-CD2431 complete. When driven CL-CD2431, DTACK* input that indicates that system longer use. When CL-CD2431 master, DTACK* input that indicates when system memory read write cycles complete.
(TS)
(TS)
R/W*
(TS)
DTACK*
(OD)
INFORMATION
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Symbol
Number
Type
Description
SIZE [0-1]: When active master, these inputs that determine size operand being read written host. SIZ[1] SIZ[0] Byte Bytes When CL-CD2431 master, this output determining size operand being transferred from system memory. SIZ[1] SIZ[0] Byte BYTESWAP description. CL-CD2431 drives DTACK* even though device does respond such byte alignment. INTERRUPT ACKNOWLEDGE IN*: This input qualified with DS*, A[0-6], acknowledges CL-CD2431 interrupts. INTERRUPT ACKNOWLEDGE OUT*: This output driven during interrupt acknowledge cycles which internal interrupt valid. INTERRUPT REQUEST* [1-3]: These outputs signal that CL-CD2431 valid interrupt modem-lead activity (IREQ*[1]), transmit activity (IREQ*[2]), receive activity (IREQ*[3]). REQUEST*: This output used signal (open drain) host processor arbiter that mastership required CL-CD2431. GRANT IN*: This input indicates that available after current master relinquishes bus. GRANT OUT*: This output asserted when BGIN* internal Request been made. daisy-chain scheme arbitration formed connecting BGOUT* BGIN* next device chain. priority scheme preferred, requests must prioritized externally grant routed BGIN* appropriate device GRANT ACKNOWLEDGE*: input, this signal used determine another alternate master control bus. output, signals other masters that this device control bus. ERROR*: this input becomes active while CL-CD2431 master, current cycle terminated, relinquished, interrupt generated indicate error host processor. ADDRESS [0-7]: When CL-CD2431 master, these pins inputs used determine which registers being accessed, which interrupt being acknowledged. When ADLD* low, A[0-7] output address bits through external latching. When CL-CD2431 master, A[0-7] output least-significant byte transfer address. ADDRESS/DATA [0-15]: When CL-CD2431 master, these pins provide 16-bit data reading writing CL-CD2431 registers. When ADLD* low, A/D[0-15] provide upper address bits external latching. When CL-CD2431 master, A/D[0-15] provide multiplexed address/data reading writing system memory.
SIZ[0-1]
(TS)
IACKIN* IACKOUT*
IREQ*[1-3]
(OD)
BGIN*
BGOUT*
BGACK*
(OD)
BERR*
A[7:0]
71-78
(TS)
A/D[15:0]
86-95,
(TS)
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INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Symbol
Number
Type
Description
ADDRESS LOAD*: This strobe used externally latch upper portion system address A[8-31]. While ADLD* low, address bits 16-31 available A/D[0-15], address bits through A[0-7]. ADDRESS ENABLE*: This output used output enable external address drivers during CL-CD2431 cycles. DATA ENABLE*: This output active when either CL-CD2431 master, pins low. used enable external data buffers during host register read/write operations during operations. operations 32-bit buses, this signal needs gated with A[1] select correct half data bus. DATA DIRECTION*: This output active when either CL-CD2431 master, low. used control external data buffers; when low, buffers should enabled CL-CD2431 system direction. CLOCK: System clock. CLOCK: This system clock divided which used internally control certain operations. This driven during hardware reset. RESET*: This signal should stay valid minimum reset state CL-CD2431 guaranteed rising edge this signal. When RESET* removed, CL-CD2431 also performs software initialization registers. TEST: normal operation, this should kept low. board-level testing purposes, provides mechanism forcing normal output pins HighImpedance mode. When TEST high, following pins HighImpedance mode: BUSCLK, BGOUT*, IACKOUT*, RXCOUT[0-1], RTS*[0-1], DTR*[0-1], TXD[0-1]. ensure CL-CD2431 outputs high-impedance, either following conditions must met: RESET* driven low, TEST driven high; CL-CD2431 kept idle state (not accessed read/write operations active), TEST driven high.
ADLD*
(TS)
AEN*
(TS)
DATEN*
(TS)
DATDIR*
(TS)
BUSCLK
RESET*
TEST
RTS*[0-3]
REQUEST SEND* [0-3]: This output controlled automatically CL-CD2431 indicate that data being sent pin. TRANSMIT CLOCK OUT/DATA TERMINAL READY* [0-1]: This output controlled automatically CL-CD2431 indicate programmable threshold been reached receive FIFO. also programmed output transmit data clock. Following reset, this high stays high Clock mode until transmit channel enabled first time; after which remains active, independent state transmit enable. modes, clock transitions every time, even during idle fill Asynchronous mode. Data transitions made negative-going edge TXCOUT. RECEIVE CLOCK [0-1]: This output provides one-time rate clock receive data modes, except when input (RXCIN) one-time receive clock used. After reset, this until channel receive enabled first time, after which remains active, independent state receive enable. When Asynchronous mode, output only transitions while receiving data during inter-character fill. receive data sampled positive-going edge this clock.
TXCOUT/DTR* [0-3]
RXCOUT[0-3]
INFORMATION
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Symbol
CTS*[0-3] CD*[0-3] TXCIN[0-3] RXCIN[0-3] DSR*[0-3] TXD[0-3] RXD[0-3]
Number
Type
Description
CLEAR SEND* [0-1]: This input programmed control flow transmit data, out-of-band flow control applications. CARRIER DETECT* [0-1]: This always visible MSVR register. input programmed validate receive data. TRANSMIT CLOCK [0-1]: This inputs transmit clock rate generator. RECEIVE CLOCK [0-1]: This inputs receive clock rate generator. DATA READY* [0-1]: This always visible MSVR register. input programmed validate receive data. TRANSMIT DATA [0-1]: Serial data output each channel. RECEIVE DATA [0-1]: Serial data input each channel. BYTESWAP: This alters byte ordering data during certain 16-bit transfers changes half data which byte transfers made comply with Intel® Motorola® processor systems. BYTESWAP does alter handshake signals. When BYTESWAP high, byte A/D[0-7] precedes that A/D[8-15] string transmit receive bytes; when BYTESWAP low, A/D[8-15] precedes A/D[0-7].
BYTESWAP
When BYTESWAP high, bytes transferred A/D[0-7] when A[0] low, A/D[8-15] when A[0] high. When BYTESWAP low, bytes transferred A/D[8-15] when A[0] low, A/D[0-7] when A[0] high. different register used, depending state this pin. Byteswap Byte Alignment Motorola® byte alignment Intel® byte alignment
POWER GROUND
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INFORMATION
CL-CD2431
Advanced Multi-Protocol Communications Controller
REGISTER TABLE
Registers CL-CD2431 either Global Per-Channel. column `Address mode' memory following pages defines this attribute each register. Only Global registers exists, accessible host time. sets Per-Channel registers exist, accessible time determined currently active channel number. channel number selected host normal (non-interrupt) processing writing Channel Access register. channel number Channel Access register remains force until changed host. channel number provided automatically CL-CD2431 during interrupt service routines transfers. following list, some register locations appear twice. They have different names functions asynchronous synchronous protocol operations. Chapter page this data book detailed descriptions register functions.
Memory
2.1.1 Global Registers
Name
GFRCR
Description
Global Firmware Revision Code Register Channel Access Register
Addr. Mode
Size
Access
Page
following notes applicable Section 2.1.1 through Section 2.1.7.
NOTES: Address mode Global register always accessible. Address mode Per-Channel register sets, channel, accessible interrupt context. address Intel®-style processor. address Motorola®-style processor.
REGISTER TABLE
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CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.2 Option Registers
Name
COR1 COR2 COR3 COR4 COR5 COR6 COR7 SCHR1 SCHR2 SCHR3 SCHR4 SCRl SCRh LNXT RFAR1 RFAR2 RFAR3 RFAR4 CPSR TSPMAP1 TSPMAP2 TSPMAP3 TXACCM0 TXACCM1 TXACCM2 TXACCM3
Description
Channel Mode Register Channel Option Register Channel Option Register Channel Option Register Channel Option Register Channel Option Register Channel Option Register Channel Option Register Special Character Register Special Character Register Special Character Register Special Character Register Special Character Range Special Character Range high LNext Character Receive Frame Address Register Receive Frame Address Register Receive Frame Address Register Receive Frame Address Register Polynomial Select Register Transmit Special Mapped Character Transmit Special Mapped Character Transmit Special Mapped Character Transmit Async Control Character Transmit Async Control Character Transmit Async Control Character Transmit Async Control Character
Addr. Mode
Size
Access
Async Async Async Async Async Async Async Sync Sync Sync Sync Sync
Page
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Name
RXACCM0 RXACCM1 RXACCM2 RXACCM3
Description
Receive Async Control Character Receive Async Control Character Receive Async Control Character Receive Async Control Character
Addr. Mode
Size
Access
Page
2.1.3 Rate Clock Option Registers
Name
RBPR RCOR TBPR TCOR
Description
Receive Rate Period Register Receive Clock Option Register Transmit Rate Period Register Transmit Clock Option Register
Addr. Mode
Size
Access
Page
2.1.4 Channel Command Status Registers
Name
STCR MSVR-RTS MSVR-DTR
Description
Channel Command Register Special Transmit Command Register Channel Status Register Modem Signal Value Registers
Addr. Mode
Size
Access
Page
REGISTER TABLE
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.5 Interrupt Registers
Name
LIVR LICR
Description
Local Interrupt Vector Register Interrupt Enable Register Local Interrupting Channel Register Stack Register
Addr. Mode
Size
Access
Page
2.1.5.1 Receive Interrupt Registers
Name
RPILR RISR RISRl RISRh RFOC REOIR
Description
Receive Priority Interrupt Level Register Receive Interrupt Register Receive Interrupt Status Register Receive Interrupt Status Register Receive Interrupt Status Register high Receive FIFO Output Count Receive Data Register Receive Interrupt Register
Addr. Mode
Size
Access
Page
2.1.5.2 Transmit Interrupt Registers
Name
TPILR TISR TFTC TEOIR
Description
Transmit Priority Interrupt Level Register Transmit Interrupt Register Transmit Interrupt Status Register Transmit FIFO Transfer Count Transmit Data Register Transmit Interrupt Register
Addr. Mode
Size
Access
Page
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.5.3 Modem Interrupt Registers
Name
MPILR MISR MEOIR
Description
Modem Priority Interrupt Level Register Modem Interrupt Register Modem (/Timer) Interrupt Status Register Modem Interrupt Register
Addr. Mode
Size
Access
Page
2.1.6 Registers
Name
BERCNT DMABSTS
Description
Mode Register Error Retry Count Buffer Status
Addr. Mode
Size
Access
Page
2.1.6.1 Receive Registers
Name
ARBADRL ARBADRU BRBADRL BRBADRU ARBCNT BRBCNT ARBSTS BRBSTS RCBADRL RCBADRU
Description
Receive Buffer Address Lower Receive Buffer Address Upper Receive Buffer Address Lower Receive Buffer Address Upper Receive Buffer Byte Count Receive Buffer Byte Count Receive Buffer Status Receive Buffer Status Receive Current Buffer Address Lower Receive Current Buffer Address Upper
Addr. Mode
Size
Access
Page
REGISTER TABLE
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CL-CD2431
Advanced Multi-Protocol Communications Controller
2.1.6.2 Transmit Registers
Name
ATBADRL ATBADRU BTBADRL BTBADRU ATBCNT BTBCNT ATBSTS BTBSTS TCBADRL TCBADRU
Description
Transmit Buffer Address Lower Transmit Buffer Address Upper Transmit Buffer Address Lower Transmit Buffer Address Upper Transmit Buffer Byte Count Transmit Buffer Byte Count Transmit Buffer Status Transmit Buffer Status Transmit Current Buffer Address Lower Transmit Current Buffer Address Upper
Addr. Mode
Size
Access
Page
2.1.7 Timer Registers
Name
RTPR RTPRl RTPRh GT1l GT1h
Description
Timer Period Register Receive Timeout Period Register Receive Timeout Period Register Receive Timeout Period Register high General Timer General Timer General Timer high General Timer Transmit Timer Register
Addr. Mode
Size
Access
Async Async Async Sync Sync Sync Sync Async
Page
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
Register Definitions
2.2.1 Global Registers Global Firmware Revision Code Register (GFRCR)
Firmware Revision Code
Channel Access Register (CAR)
2.2.2 Option Registers Channel Mode Register (CMR)
RxMode TxMode
chmd2
chmd1
chmd0
Channel Option Register (COR1) HDLC Mode
AFLO ClrDet AdMde1 AdMde0 Flag3
Flag2
Flag1
Flag0
Asynchronous Mode
Parity ParM1 ParM0 Ignore Chl3 Chl2 Chl1 Chl0
Channel Option Register (COR2) Asynchronous Async-HDLC Mode
TxlBE
RtsAO
CtsAE
DsrAE
HDLC Mode
FCSApd CRCNinv RtsAO CtsAE DsrAE
4/SLIP Mode
RtsAO CtsAE DsrAE
REGISTER TABLE
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Channel Option Register (COR3) Async-HDLC/PPP Mode
Stop2 FCSApd RxChk TxGen npad3
npad2
npad1
npad0
Mode
Stop2 FCSApd RxChk TxGen npad3 npad2 npad1 npad0
HDLC Mode
sndpad Alt1 FCSPre idle npad2 npad1 npad0
Asynchronous Mode
EDCDE RngDE SCDE Splstp Stop2 Stop1 Stop0
SLIP Mode
Stop2 npad3 npad2 npad1 npad0
Channel Option Register (COR4)
DSRzd CDzd CTSzd
FIFO Threshold
Channel Option Register (COR5)
DSRod CDod CTSod In/Out
Flow Control Threshold
Channel Option Register (COR6) Asynchronous Mode
IgnCR ICRNL INLCF IgnBrk NBrklnt
ParMrk
INPCK
Parlnt
Channel Option Register (COR7) Asynchronous Mode
IStrip FCErr
ONLCR
OCRNL
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
Special Character Registers Special Character Register (SCHR1) Special Character Register (SCHR2) Special Character Register (SCHR3) Special Character Register (SCHR4) Async Async Async Async
Special Character Ranges Special Character Range (SCRl) Special Character Range high (SCRh) Async Async
LNext Character (LNXT)
Async
Receive Frame Address Registers Receive Frame Address Register (RFAR1) Receive Frame Address Register (RFAR2) Receive Frame Address Register (RFAR3) Receive Frame Address Register (RFAR4) Sync Sync Sync Sync
Polynomial Select Register (CPSR)
Poly
Transmit Special Mapped Characters (PPP only) Transmit Special Mapped Character (TSPMAP1) Transmit Special Mapped Character (TSPMAP2) Transmit Special Mapped Character (TSPMAP3)
REGISTER TABLE
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Transmit Async Control Character Maps (PPP only) Transmit Async Control Character (TXACCM0) Transmit Async Control Character (TXACCM1) Transmit Async Control Character (TXACCM2) Transmit Async Control Character (TXACCM3)
Receive Async Control Character Maps (PPP only) Receive Async Control Character (RXACCM0) Receive Async Control Character (RXACCM1) Receive Async Control Character (RXACCM2) Receive Async Control Character (RXACCM3)
2.2.3 Rate Clock Option Registers Receive Rate Period Register (RBPR)
Receive Rate Period (Divisor)
Receive Clock Option Register (RCOR)
TLVal DpllEn Dpllmd1 Dpllmd0
ClkSel2
ClkSel1
ClkSel0
Transmit Rate Period Register (TBPR)
Transmit Rate Period (Divisor)
Transmit Clock Option Register (TCOR)
ClkSel2 ClkSel1 ClkSel0 Ext-1X
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.4 Channel Command Status Registers Channel Command Register (CCR)
ClrCh ClrT1 InitCh ClrT2 RstAll EnTx
DisTx
EnRx
DisRx
Special Transmit Command Register (STCR) Async-HDLC/PPP Mode
Abort sndsp
frame
Xoff
SLIP/MNP Mode
Abort sndsp frame
Asynchronous HDLC Modes
AbortTx AppdCmp SndSpc SSPC2 SSPC1 SSPC0
Channel Status Register (CSR) HDLC Mode
RxEn RxFlag RxFrame RxMark TxEn
TxFlag
TxFrame
TxMark
Asynchronous Mode
RxEn RxFloff RxFlon TxEn TxFloff TxFlon
Async-HDLC/PPP Mode
RxEn RxFloff RFram Rldle TxEn TxFloff TFram TIdle
SLIP/MNP Mode
RxEn RFram Rldle TxEn TFram TIdle
Modem Signal Value Registers (MSVR) Modem Signal Value Register (MSVR-RTS) Modem Signal Value Register (MSVR-DTR)
DTRop
REGISTER TABLE
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.5 Interrupt Registers Local Interrupt Vector Register (LIVR)
Interrupt Enable Register (IER)
TIMER
TxMpty
Local Interrupting Channel Register (LICR)
Interrupt Stack Register (STK)
CLvl MLvl TLvl
TLvl
MLvl
CLvl
2.2.5.1 Receive Interrupt Registers Receive Priority Interrupt Level Register (RPILR) Receive Interrupt Register (RIR)
Ract Reoi Rvct
Rvct
Rcn[1]
Receive Interrupt Status Register (RISR) Receive Interrupt Status Register (RISRl) HDLC Mode
RxAbt
Reslnd
ClrDct
Asynchronous Mode
Timeout SCdet2 SCdet1 SCdet0 Break
Async-HDLC Mode
RxAbt Break
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DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
SLIP Mode
Break
Receive Interrupt Status Register high (RISRh)
Berr BA/BB
Receive FIFO Output Count (RFOC)
RxCt4 RxCt3
RxCt2
RxCt1
RxCt0
Receive Data Register (RDR)
Receive Interrupt Register (REOIR) Asynchronous HDLC Modes
TermBuff DiscExc SetTm2 SetTm1 NoTrans
Gap2
Gap1
Gap0
Async-HDLC SLIP Modes
TermBuff DiscExc SetTm2 SetTm1 NoTrans
REGISTER TABLE
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.5.2 Transmit Interrupt Registers Transmit Priority Interrupt Level Register (TPILR) Transmit Interrupt Register (TIR)
Tact Teoi Tvct
Tvct
Tcn[1]
Transmit Interrupt Status Register (TISR)
Berr BA/BB
TxEmpty
TxDat
Transmit FIFO Transfer Count (TFTC)
TxCt4 TxCt3
TxCt2
TxCt1
TxCt0
Transmit Data Register (TDR)
Transmit Interrupt Register (TEOIR)
TermBuff SetTm2 SetTm1 NoTrans
2.2.5.3 Modem/Timer Interrupt Registers Modem Priority Interrupt Level Register (MPILR) Modem Interrupt Register (MIR)
Mact Mvct
Mvct
Mcn[1]
Modem (/Timer) Interrupt Status Register (MISR)
DSRChg CDChg CTSChg
Timer2
Timer1
Modem Interrupt Register (MEOIR)
SetTm2 SetTm1
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REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.6 Registers Mode Register (DMR)
EnSync ByteDMA
Error Retry Count (BERCNT)
Binary Value
Buffer Status (DMABSTS)
TDAlign RstApd CrtBuf Append Ntbuf
Tbusy
Nrbuf
Rbusy
2.2.6.1 Receive Registers Receive Buffer Address Lower (ARBADRL) Receive Buffer Address Upper (ARBADRU) Receive Buffer Address Lower (BRBADRL) Receive Buffer Address Upper (BRBADRU)
Buffer Receive Byte Count (ARBCNT) Buffer Receive Byte Count (BRBCNT)
Receive Buffer Status (ARBSTS) Receive Buffer Status (BRBSTS)
Berr
2431own
Receive Current Buffer Address Lower (RCBADRL) Receive Current Buffer Address Upper (RCBADRU)
REGISTER TABLE
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.6.2 Transmit Registers Transmit Buffer Address Lower (ATBADRL) Transmit Buffer Address Upper (ATBADRU) Transmit Buffer Address Lower (BTBADRL) Transmit Buffer Address Upper (BTBADRU)
Buffer Transmit Byte Count (ATBCNT) Buffer Transmit Byte Count (BTBCNT)
Transmit Buffer Status (ATBSTS) Transmit Buffer Status (BTBSTS) Async-HDLC/PPP Mode
Berr
map32
INTR
2431own
SLIP/MNP Mode
Berr INTR 2431own
Asynchronous HDLC Mode
Berr Append INTR 2431own
Transmit Current Buffer Address Lower (TCBADRL) Transmit Current Buffer Address Upper (TCBADRU)
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DATA BOOK v3.0
REGISTER TABLE
CL-CD2431
Advanced Multi-Protocol Communications Controller
2.2.7 Timer Registers Timer Period Register (TPR)
Binary Value
Receive Time-Out Period Register (RTPR)
Binary Value
Async
Receive Time-Out Period Register (RTPRl)
Binary Value, bits
Async
Receive Time-Out Period Register high (RTPRh)
Binary Value, bits 15:8
Async
General Timer (GT1) General Timer (GT1l) General Timer high (GT1h) General Timer (GT2)
Sync Sync Sync Sync
Transmit Timer Register (TTR)
Async
REGISTER TABLE
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
FUNCTIONAL DESCRIPTION
Host Interface
CL-CD2431 synchronous device with asynchronous interface. stable input clock required nominally MHz. divided internally, resulting signal output BUSCLK pin. baudrate generators timers also related CLK. Electrical Characteristics" Section shows that many input signal setup output signal transitions related edges BUSCLK signals. possible, however, CL-CD2431 purely asynchronous environment. CL-CD2431 either master, during transfers, slave device, during normal host read write transfers. Both byte
word transfers supported each Slave Master modes. Figure Figure show signals involved these transfers. 3.1.1 Host Read Write Cycles host read write cycles begin with activation (chip select) (data strobe) signals. DATADIR* (data direction) DATEN* (data enable) signals used control external data buffers. falling edge DTACK* (data transfer acknowledge) signal indicates that transfer complete. DTACK* released when deasserted. that time should also deasserted. (address strobe) used during slave cycles; output during transfers. Note that following open-drain tristate outputs should have pull-up resistors attached: AEN*, AS*, DATADIR*, DATEN*, DTACK*.
R/W* A/D[15:0] DOUT
A[7:0], SIZ[1:0] DTACK*
DATEN*
DATDIR*
Figure 3-1. Host Read Cycle
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
R/W*
A/D[15:0]
A[7:0], SIZ[1:0] DTACK*
DATEN*
DATDIR*
Figure 3-2. Host Write Cycle 3.1.2 Byte Word Transfers Data moved from CL-CD2431 either byte word transfers. accommodate various families host processors, BYTESWAP input indicate system byte-ordering scheme. pins (SIZ[1:0]) used indicate whether transfer bytes wide. systems where even addresses represent most-significant byte, BYTESWAP input should tied low, byte transfers occur A/D[15:8] pins even addresses A/D[7:0] pins addresses. systems where most-significant byte address, situation reversed, BYTESWAP should tied high. Byte transfers even addresses occur A/D[7:0] pins, addresses A/D[15:8] pins.
Interrupts
CL-CD2431 uses interrupt requests alert host that certain events have occurred. Interrupt operations CL-CD2431 tightly coupled with several registers described later. concept context affects accessibility these other registers. 3.2.1 Contexts Channels registers CL-CD2431 grouped into Global, Virtual, four sets Per-Channel registers. CL-CD2431 normally background context, where (Channel Access register) selects channel number Per-Channel registers. interrupt context begins with interrupt acknowledge cycle, ends with write access appropriate Interrupt register. interrupt context, only Per-Channel registers channel number being serviced available; effect. Most
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Global registers available times, some shared four channels, such FIFO registers. These called Virtual registers, must accessed only during interrupt context. Interrupt contexts nested that higher-priority interrupt service preempt lower priority interrupt already progress. CL-CD2431 pushes current interrupt context onto stack, visible (Stack register), enters context newly acknowledged interrupt. register accesses interrupt context until host performs write appropriate EOIR top-level context. CL-CD2431 then pops top-level context stack returns previous interrupt context. 3.2.2 Interrupt Registers (Interrupt Enable register) LIVR (Local Interrupt Vector register) Per-Channel
registers. contains bits enable disable various interrupt sources within CL-CD2431. LIVR value output data during interrupt acknowledge cycle. There sets three Global registers that correspond three types interrupts: Receive, Transmit, Modem. Priority Interrupt Level registers (RPILR, TPILR, MPILR) programmed contain value that present address during interrupt acknowledge cycle each type interrupt. Interrupt Status registers (RISR, TISR, MISR) examined during interrupt service routine determine cause each type interrupt. provide access FIFO buffers each channel. These registers must accessed outside proper interrupt context. write operation Interrupt registers REOIR, TEOIR, MEOIR must last access CL-CD2431 this handler routine return background context.
IREQn*
IACKIN* 1-CLOCK DELAY CL-CD2431 SAMPLES
R/W*, A/D[15:0] VECTOR*
A[7:0] DTACK*
DEN*
DATDIR* INTERRUPT VECTOR ALWAYS A/D[7:0]
Figure 3-3. Interrupt Acknowledge Cycle August 1996
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.3 Groups Types There general reasons CL-CD2431 request service from host processor data transfer exceptional conditions. Furthermore, interrupts grouped into three categories, each with associated Interrupt Request signal IREQ1*, IREQ2*, IREQ3*.
Group used only exceptions. Groups include both data transfer exceptions. Table shows possible causes transmit receive interrupt service requests. cause interrupt request encoded into least-significant bits vector presented data during interrupt acknowledge cycle. most-significant bits vector come from LIVR: Interrupt Vector LSBs Receive exception Modem signal change timer event Transmit data exception Receive Good Data
Group Modem signal change/timer events Group Transmit interrupts Group Receive interrupts
Table 3-1.
Transmit Receive Interrupt Service Requests
ASYNC
mode only mode only mode
Interrupt Cause
Receive Good DataBreak detect Framing error Parity error Receive timeout, data Special character match Transmitter empty FIFO threshold Receive overrun Clear detect error Residual count Receive abort frame Transmit underrun error buffer
HDLC
SLIP
Comments
mode
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.4 Hardware Signals IACK Cycles IACK (interrupt acknowledge) cycle begins with IACKIN* asserted, value matching appropriate PILR contents least-significant seven address bits, A[6:0]. IACK cycle valid (that PILR values match), corresponding vector from interrupting channel LIVR driven onto data DTACK* asserted. DTACK* released after removed. Figure shows interrupt acknowledge cycle timing. similar basic host read cycle, except that IACKIN* active inactive. three IREQn* pins open-drain outputs requiring external pull-up resistors, nominally IACKOUT* used form daisy chain systems with more than CL-CD2431. 3.2.4.1 Programming PILR three PILRs must programmed with values that correspond least-significant seven address bits present A[6:0] during interrupt acknowledge cycle. Some CPUs output priority level interrupts that being acknowledged during IACK cycle. these systems three PILR values unique. other systems that this scheme, PILR values same different depending specific design. When PILRs contain same value multiple IREQn* lines asserted, CL-CD2431 imposes following priority scheme determine which interrupt request acknowledged: Highest priority: Receive Interrupt register Transmit Interrupt register Modem Interrupt register
locations from CL-CD2431 produce IACKIN* instead CS*. PILR registers should programmed with addresses these three locations. Alternatively, single location decoded three PILRs given identical values described earlier. either case, host should read these locations before first access device interrupt service routine. CL-CD2431 enters interrupt acknowledge context proper type channel, data returned device interrupt vector from LIVR. 3.2.5 Multi-CL-CD2431 Systems Multiple CL-CD2431s chained systems requiring more than four channels. Each group interrupt request lines (IREQn*) connected parallel wired-OR fashion. system Interrupt Acknowledge signal connected IACKIN* first device, IACKOUT* then connected IACKIN* next device, forming chain CL-CD2431s. 3.2.5.1 Keep Pass Logic acceptance interrupt acknowledge cycle CL-CD2431 depends whether part requesting service whether least-significant seven address bits match contents appropriate PILR. following rules apply keepand-pass logic:
CL-CD2431 does have interrupt asserted, interrupt acknowledge passed IACKOUT*. CL-CD2431 asserting more interrupts, interrupt priority levels driven address host match contents appropriate PILR, this interrupt acknowledge also passed IACKOUT*. CL-CD2431 asserting interrupt interrupt priority level address matches PILR that interrupt type, interrupt acknowledge accepted CL-CD2431, vector from LIVR driven onto data bus.
Lowest priority:
3.2.4.2 Systems with Interrupt Controllers Some systems interrupt controller that supplies vector during interrupt acknowledge cycle. function properly, CL-CD2431 needs IACK cycle response interrupt request These systems decode three distinct
August 1996
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.2.5.2 Fair Share Scheme When multiple CL-CD2431s chained, Fair Share logic these devices guarantees that interrupts from CL-CD2431s system presented host with equal urgency. There positional hierarchy interrupt scheme. example, CL-CD2431 that farthest from host equal chance getting interrupts through CL-CD2431 that nearest interrupt chain. Fair Share scheme totally transparent user, enabling disabling required. When interrupt request line asserted, Fair that type interrupt asserting device cleared. Fair remains cleared until interrupt line returns high state. CL-CD2431 does assert interrupt that type while corresponding Fair cleared. Therefore, when multiple CL-CD2431s assert interrupts together, each serviced turn, before they reassert same interrupt type. IREQn* lines open-drain outputs that tied together groups same type, creating Fair Share scheme each group interrupts. Alternatively, three groups tied common request using CL-CD2431 internal-priority scheme (see Section 3.2.4.1).
3.3.1 Receive FIFO Operation Asynchronous mode, Good Data interrupt initiated when number characters FIFO greater than FIFO threshold. Note that receive timeout receive data exception conditions also cause interrupt host. Synchronous mode, interrupt request data transfer initiated when number characters greater than FIFO threshold frame reached. 3.3.2 Transmit FIFO Operation TxDat TxEmpty bits control generation transmit FIFO interrupts. CL-CD2431 initiates interrupt request more data when number empty bytes FIFO greater than threshold set. During synchronous operation when last byte frame transferred FIFO, CL-CD2431 stops asserting transmit interrupts until frame sent. 3.3.3 Timers global (Timer Period register) provides timer prescale `tick' clock source timers. counter clocked system clock (CLK) divided 2048. maintain timer accuracy, should programmed with value less than hex) `tick' about millisecond when MHz. Each channel timers: 16-bit general timer (GT1), 8-bit general timer (GT2). Their operation programming different synchronous asynchronous protocols. 3.3.4 Timers Synchronous Protocols synchronous protocols, timers have special significance CL-CD2431; they available support protocols. They started host commands interrupts generated CL-CD2431. General timers started either ways:
loading value when timer running.
FIFO Timer Operations
Each channel CL-CD2431 16-byte receive FIFO 16-byte transmit FIFO. FIFOs accessible through TDR. These Virtual registers shared among four channels; therefore, they accessed outside interrupt context. Each channel's threshold level common both FIFOs. COR4 (Channel Option Register with maximum threshold value FIFO threshold meaningful both non-DMA modes. mode, FIFO threshold determines when transfer bursts should occur. nonDMA mode, threshold level determines when transfer interrupts asserted.
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
setting SetTm1 SetTm2 bits EOIR when terminating interrupt service routine. this case, value should written appropriate Interrupt Status register (RISR, TISR, MISR).
simple Ownership Status used each buffer; this ensures that there deadlocks between host CL-CD2431 regarding particular buffer. using simple flexible management CL-CD2431, user host processor concerned with transmit/receive data block-byblock basis. user does need concerned with character-by-character transfers, even filling emptying FIFOs. controls user-selectable per-channel operate independently another. CL-CD2431 perform operations supported line protocols. special Append mode feature reduce host overhead asynchronous datastreams. operations channel- direction-specific. each channel, either transmitter receiver, both, independently programmed mode (Channel Mode register). When CL-CD2431 acquires transfer, only data channel direction transferred; then, ownership relinquished. maximum bytes depth transmit receive FIFOs transferred during ownership cycle. Whenever possible, cycles bits wide, buffers have proper byte alignment. Unaligned buffers sent using only 8-bit-wide transfers. buffer begins even address contains number bytes, CL-CD2431 uses 16-bit transfers words buffer except last transfer, which bits. buffer chain ends address, next buffer chain should also start address maintain proper alignment most efficient usage. this case, only last transfer first buffer first transfer next buffer bits wide; others bits. CL-CD2431 forced perform only bytewide operations setting ByteDMA (DMR[3]).
These timers disabled command through (Channel Command register). 3.3.5 Timers Asynchronous Protocols receive timer restarted from value programmed RTPR every time character received loaded into FIFO, data read host. example, receive FIFO threshold eight, characters stored receive FIFO. more characters received receiver timer times-out, receive interrupt asserted mode, transfer occurs). host expected retrieve characters from receive FIFO. Assuming host still enabling this feature (that IER[5] still set) there character being received receiver timer times-out, receive exception timeout interrupt group interrupt) asserted. timer disabled value RTPR (IER[5]) cleared. 3.3.6 Transmit Timer (Transmit Timer register) used only embedded transmit command enabled COR2. delay transmit command specifies delay period loaded TTR; further transmit operations performed until this timer reaches zero. current state line held either send break inter-character fill.
Operation
CL-CD2431 uses simple, powerful, double-buffering method that readily compatible with higher-level buffer control procedures, such circular queues, link lists, buffer pools. Each transmitter receiver assigned buffer. When transmitting, host processor alternately fills buffers commands CL-CD2431 transmit buffers time. When receiving, CL-CD2431 fills buffers informs host processor when each ready.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.1 Acquisition Cycle
CL-CD2431 asserts waits BGIN*. When BGIN* detected, CL-CD2431 access after current owner relinquishes control bus. BGACK* high when BGIN* goes low, then free access. step BGACK* when BGIN* goes low, then use. CL-CD2431 waits BGACK* high.
Once CL-CD2431 senses that BGACK* high, CL-CD2431 waits current cycle terminate (DS* DTACK* high) then asserts BGACK* driving low. that time, CL-CD2431 owns bus. After driving BGACK* low, CL-CD2431 drives high.
Figure 3-4, CL-CD2431 required wait access bus.
BGIN*
BGACK* Another component owns gives here. CL-CD2431 owns this point.
Figure 3-4. Acquisition Cycle August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.2 Data Transfer After CL-CD2431 acquires bus, pulses ADLD* once. This loads upper address bits external 24-bit latch. This happens only once grant cycle. AD[15:0] bits remapped memory address (MA) bits MA[31:16] A[7:0] mapped MA[15:8]. during upper bits need change, CL-CD2431 relinquishes then re-acquires bus.
During each read write cycle, leastsignificant eight memory address bits, MA[0-7] come from A[0-7]. Figure 3-5, access after acquired shown.
ADLD*
AEN*
DATDIR*
High read write
R/W*
High read write
DTACK*
Figure 3-5. Data Transfer Timing
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.3 Error Handling When error detected during sequence, CL-CD2431 terminates current cycle relinquishes bus. data transfer ownership cycle ignored, original conditions restored. subsequent retry attempt would start again from these original conditions. there non-zero value BERCNT register, register decremented failed transfer retried automatically. BERCNT zero, error interrupt generated transfers suspended failing buffer until interrupt serviced. 3.4.4 Buffers Chaining buffer management CL-CD2431 uses dual-buffer scheme. There buffer pair each transmitter each receiver. Each buffer controlled Ownership Status bit, called 2431own. When 2431own `1', Table 3-2. Buffers Chaining
Ntbuf
CL-CD2431 `owns' buffer. When 2431own `0', host `owns' buffer. simple rule prevents confusion buffer management neither CL-CD2431 host seizes buffer ownership. Each always relinquishes ownership other. host relinquishes ownership receive buffer CL-CD2431 when receive buffer ready. CL-CD2431 then free write received data into buffer. CL-CD2431 returns ownership receive buffer after receive data buffer. host gives ownership transmit buffer CL-CD2431 when transmit buffer ready transmit. CL-CD2431 then transmits contents buffer. When this complete, CL-CD2431 returns ownership back host. CL-CD2431 keeps track which buffer used next status bits Ntbuf transmit Nrbuf receive. relationship between 2431own `next' bits shown later. receive buffers handled same using Nrbuf (next receive buffer).
2431own Buffer
2431own Buffer
Send nothing
Transmit Action
Host sets buffer CL-CD2431 accepts buffer marks next CL-CD2431 completes passes host Host sets buffer CL-CD2431 accepts marks next Host sets buffer CL-CD2431 completes passes host, accepts marks next CL-CD2431 completes passes host
Chaining used break relatively long frames into shorter blocks memory, useful where there frequent smaller frames occasional long frames. Chaining allows more efficient user RAM. Status controls chaining Synchronous modes. Chaining applies both transmit
receive. transmit, host determines bit; receive, CL-CD2431 determines bit. Transmit when first buffer supplied CL-CD2431, treated start frame reset leading pad/flag/syn characters transmitted, followed data. August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
set, closing flag/syn appended, next buffer again treated start frame. set, CL-CD2431 treats buffer first part larger frame chains into next buffer (does reset CRC); this process continues until buffer supplied with set. 3.4.5 Transmit Transfer receive data transfers, buffers available transmit transfers. A/BTBADR A/BTBCNT (Transmit Buffer Address Transmit Buffer Count registers) contain start address byte count buffers. These registers host when initiating transfer. CL-CD2431 makes copy registers perform transfer, leaving originals unchanged. transfer buffers between host CL-CD2431 controlled A/BTBSTS (Transmit Buffer Status) registers. Buffers contain either complete frames blocks data, linked together form complete frame block, used Append mode transmit data arrives from another process. first transfer types Block mode transfers, last Append mode, both described later. management buffers reduces processor overhead associated with short data transfers increases minimum response time requirements frame-based transmissions.
Transmit buffers chained support large frames. minimize usage, first buffer chain should begin even address host memory. CL-CD2431 begins fetching frame from buffer performing transfer, reading bytes time. CL-CD2431 cannot realign data between external memory FIFO. buffer chain ends address, next buffer chain should begin address. Otherwise, only single-byte transfers made rest buffer.
Append Mode Transfer (Buffer Only)
Append mode available buffer Asynchronous mode only. buffer Append mode, host enable CL-CD2431 transmit data buffer before completely filled. CL-CD2431 starts transmitting data when appended buffer. This mode useful terminal echo routines that wait complete block formed before starting transmission. this mode, transmission started when buffer made available CL-CD2431 host; ATBADR[3:0] ATBCNT[L, initialized. Subsequent triggering transfer occurs programming ATBCNT[L, with accumulated byte count. ATBCNT should written 16-bit word this case, avoid confusion between byte operations. ATBADR[3:0] should reprogrammed during Append mode. memory space moved, Append mode must first disabled. When final data added append buffer ATBCNT been updated, host should AppdCmp (STCR[5]). When CL-CD2431 completed final transmission, clears 2431own ATBSTS register, generates end-of-buffer interrupt.
Chain Mode Transfer
Chain mode, frame should complete buffers memory before transmission started. Append Status should set; Start Frame must begin transmission, Last Buffer must this buffer last chained block complete frame block. When set, CL-CD2431 generates transmits cyclic redundancy check word frame using polynomial selected CPSR (CRC Polynomial Select register). Interrupt Required set, host interrupt generated after buffer transmitted.
used Buffer register abbreviation indicating buffer buffer followed register acronym.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
CL-CD2431 Transmit Registers
Starting Address ATBADR (32) ATBCNT (16) ATBSTS
(Status register)
Physical Memory
Transmit Buffer
Buffer Byte Count
TABADR (32)
(Currently using Buffer
Current Count
BTBADR (32) BTBCNT (16) BTBSTS
(Status register)
Starting Address Buffer Byte Count Transmit Buffer
NOTE: Number bits each register shown parentheses Buffer buffer need same length.
Figure 3-6. Transmitter Buffers 3.4.6 Synchronous Transmitter Examples Figure 3-6, buffers contained external CL-CD2431. others (DMABSTS, ATBADR, TCBADR, ATBCNT, ATBSTS, BTBADR, BTBCNT, BTBSTS) inside CL-CD2431.
transmission progresses, current buffer pointer (TCBADR) updated CL-CD2431. Also, start transmission, Ntbuf (Next Buffer) notify host that buffer next. CL-CD2431 completes frame transmission adding necessary CRCs trailing frame delimiters. When CL-CD2431 completes transmission, clears Tbusy bit. Then, sets clears 2431own ATBSTS. This notifies host that transmission complete, return ownership buffer back host. CL-CD2431 optionally interrupts host, with TISR both indicate that transmission complete there chaining.
Example
Transmit frame channel chaining.
host checks Ntbuf DMABSTS register channel determine which buffer next. this example, Ntbuf indicating that buffer used next. host sets buffer data, starting address ATBADR, buffer byte count ATBCNT. host sets ATBSTS Buffer Status) register. indicate that there chaining. 2431own give ownership CL-CD2431. setting 2431own, host commands CL-CD2431 start transmission. Thus, everything must ready (starting address, buffer data, byte count) prior setting 2431own. CL-CD2431 starts frame transmission channel When transmission started, CL-CD2431 sets Tbusy DMABSTS.
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Example
Transmit channel chain three buffers into frame. frame bytes long, maximum buffer size 100.
host checks Ntbuf DMABSTS register channel determine which buffer next. this example, Ntbuf indicating that buffer used next. host sets buffer data, starting address (BTBADR), buffer byte count (BTBCNT) first `link' chain transmitted. this example, BTBCNT `100'. host sets BTBSTS Buffer Status) register. cleared indicate that this buffer first link chain. 2431own give ownership CL-CD2431. setting 2431own, host commands CL-CD2431 start transmission. Thus, everything must ready (starting address, buffer, data count) prior setting 2431own. this point, host enough time transmit bytes next buffer link. host fails this time, there transmitter underrun, frame aborted HDLC. CL-CD2431 starts transmitting buffer from channel When this started, Ntbuf cleared indicate that buffer next. This helps host keep track which buffer next. transmission progresses, current buffer CL-CD2431. During this prior, host readied buffer buffer ATBSTS register cleared host, indicating that buffer chain. transmission this buffer, CL-CD2431 does CRCs frame delimiters because there more data current frame. After CL-CD2431 completed transmission first link buffer CL-CD2431 sets clears 2431own BTBSTS. This notifies host that transmission complete, returns ownership buffer back host.
CL-CD2431 optionally interrupts host with clear TISR indicate that transmission complete chaining occurred. ATBSTS register indicates that CL-CD2431 ownership buffer transmission next `link'. cleared that this link last link transmitted chain. CL-CD2431 continues transmission current frame, transmission from buffer This second link, which bytes long. During this time, host must buffer third final link. BTBCNT last link bytes. After CL-CD2431 completed transmission second link buffer sets clears 2431own ATBSTS. This notifies host that transmission completed, returns ownership buffer back host. with first link, CL-CD2431 does CRCs ending frame delimiters this link. CL-CD2431 optionally interrupts host with cleared, (TISR[6:5]) indicate that transmission complete chaining occurred. this time, host buffer buffer BTBSTS indicate that this last link chain. CL-CD2431 transmits buffer same manner explained earlier. before, CL-CD2431 transmits number bytes indicated BTBCNT, which bytes third segment. When CL-CD2431 completes transmission, necessary CRCs ending frame delimiters transmitted. CL-CD2431 optionally interrupts host with bits (TISR[6:5]) indicate that transmission completed, that this last link chain.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.7 Receive Transfer protocol modes, host memory buffers made available each receive channel, A/BRBADR A/BRBCNT (Receive Buffer Address Receive Buffer Count registers) registers. make buffer available, user must supply buffer address Receive Buffer Address registers; number free bytes buffer must written Receive Buffer Count registers, buffer status must updated A/BRBSTS registers. CL-CD2431 then free buffer receive data, updates Buffer Status register appropriate. When buffer longer use, CL-CD2431 writes number bytes stored buffer RBCNT updates status RBSTS. This frees host take control this buffer supply buffer place. CL-CD2431 automatically switches other buffer whenever buffer becomes full, frame been reached. other buffer been allocated, host still time required fill CL-CD2431 16-byte FIFO, respond, avoid loss data. Special actions taken depending channel protocol. HDLC, PPP, SLIP, endof-frame/data block boundaries recognized CL-CD2431. When data-block boundary detected, current buffer automatically terminated. other buffer allocated owned CL-CD2431, becomes current buffer. Endof-frame block interrupts also generated host. Asynchronous mode, host interrupt generated when there receive exceptions (framing error, special character, buffer terminated. data exception status made available host, just when Asynchronous mode purely interrupt-driven. data
buffered internally FIFO until host services exception interrupt. host following three options when terminating exception interrupt:
exception character discarded. buffer terminated there additional interrupt generated. transfer count provided A/BRBCNT, calculated RCBADR. user-defined left buffer.
These selections communicated CL-CD2431 value written host REOIR, when Receive Interrupt service complete. Leaving byte enables host insert status current buffer, while continuing receive data same buffer. This eliminates overhead allocating buffer. host must have noted starting location while exception interrupt. This done reading RCBADR. address this register guaranteed stable during Receive Interrupt, point next free character location current buffer. size supplied host sufficient fill complete current buffer, CL-CD2431 automatically switches other buffer advances Receive Current Buffer Address enough complete desired gap. CL-CD2431 readjusts data alignment internal FIFO needed maintain alignment with external buffer.
Receiver Buffers
Figure 3-7, buffers contained external CL-CD2431. others (DMABSTS, ARBADR, ARBCNT, ARBSTS, RCBADR, BRBADR, BRBCNT, BRBSTS) inside CL-CD2431.
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
CL-CD2431 Transmit Registers
Starting Address ARBADR (32) ARBCNT (16) ARBSTS
(Status register)
Physical Memory
Receiver Buffer
Buffer Byte Count
RCBADR (32)
(Currently using Buffer
Current Address
BRBADR (32) BRBCNT (16) BRBSTS
(Status register)
Starting Address Buffer Byte Count Receiver Buffer
NOTE: Number bits each register shown parentheses Buffer buffer need same length.
Figure 3-7. Receiver Buffers
Example
Receive frame from channel chaining.
host must first make receive buffer available before frame received. Thus, host checks Nrbuf (DMABSTS[1]) channel determine which buffer next. this example, Nrbuf indicating that buffer used next. host sets starting address ARBADR, buffer byte count ARBCNT. When host writes count ARBCNT, host defined size limit buffer. host then gives buffer CL-CD2431 setting 2431own ARBSTS status register. This notifies CL-CD2431 that write received. Rbusy DMABSTS register channel until frame star received. When frame data starts coming CL-CD2431 sets Nrbuf notify host that buffer next. data bytes written into buffer, current buffer pointer (RCBADR) updated CL-CD2431.
received frame, CL-CD2431 tests correct frame delimiter CRC. When received frame complete, CL-CD2431 clears Rbusy bit. this example, there receive chaining, received frame byte count less than equal buffer size count ARBCNT. CL-CD2431 writes value actual received byte count into same register ARBCNT. (Note that host written maximum buffer size ARBCNT when buffer given CL-CD2431; however, when buffer returned back host, CL-CD2431 written actual byte count received buffer into ARBCNT.) CL-CD2431 sets bits. This notifies host that buffer frame have been reached. CL-CD2431 also clears 2431own return buffer host.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Example
Receive frame channel which consists three buffers chained together. frame bytes long, maximum buffer size 100.
host checks Nrbuf (DMABSTS[1]) channel determine which buffer next. this example, Nrbuf indicates that buffer used next. host sets starting address (BRBADR). Buffer size `100' this example. Thus, host sets BRBCNT `100'. host then sets 2431own give ownership CL-CD2431. host should know amount time takes receive bytes, because this minimum time host next buffer link. host fails this time, there receiver overrun, received frame lost. Suppose that CL-CD2431 starts receiving data into buffer channel When this started, Nrbuf cleared CL-CD2431 help host keep track which buffer next. (During this time prior, host made buffer ready.) After CL-CD2431 received first link frame into buffer sets bits clears bit. This indicates that first link chain been received. Also, CL-CD2431 clears 2431own bit, returns ownership buffer host. first received link, received byte count (BRBCNT) remains unchanged 100, since received data filled buffer. CL-CD2431 optionally interrupts host with clear (RISRh[6]) (RISRh[5]) indicate that received buffer complete, that there chaining.
ARBSTS register indicates that CL-CD2431 ownership buffer transmission next link. frame continues received, data goes into buffer This second link, which bytes long. During this time, host must buffer third final link. After CL-CD2431 received second link into buffer CL-CD2431 sets clears 2431own ARBSTS. This returns ownership buffer host. with first link, received byte count (ARBCNT) remains unchanged since received data filled buffer. CL-CD2431 optionally interrupts host with clear RISR indicate that received buffer complete that there chaining. this time host buffer buffer CL-CD2431 receives data into buffer same manner previously explained. this example, third link does fill buffer. Thus, when end-of-frame delimiter detected CL-CD2431, value (for received bytes) written into received byte count (BRBCNT). Next, CL-CD2431 sets bits show that buffer complete, that this last link chain. CL-CD2431 optionally interrupts host with bits (RISRh[6:5]) indicate that received frame complete, this last link chain.
FUNCTIONAL DESCRIPTION
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CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.8 Transmit Transfer CL-CD2431 contains descriptors that loaded specify transmit buffers. These descriptors designated each consists 32-bit address (A/BTBADR), 16-bit count (A/BTBCNT), 8-bit status (A/BTBSTS). Status register contains Ownership Status (2431own). When this CL-CD2431 owns descriptor, should written CPU. When this clear, descriptor owned CPU. When selected channel enabled, CL-CD2431 waits ownership buffer When ownership given setting 2431own bit, buffer transmitted ownership cleared. CL-CD2431 waits ownership buffer this process continues, toggling between buffer descriptors. DMABSTS register contains status (NtBuf) that informs next buffer transmit ensure that CL-CD2431 stay synchronization. This procedure ensures that pipeline data available CL-CD2431 send, maximizing bandwidth utilization minimizing possibility underruns. Figure illustrates this procedure. 3.4.8.1 Interrupts Transmit Buffers types transmit interrupts available mode; they enabled controlled TxMpty bits.
When TxMpty interrupt enabled, interrupts generated when there transmit data available send. example, TxMpty interrupt used determine when line turnaround occur half-duplex lines. Normally, interrupt indicates each transmit buffer. interrupt scheduled internally when last data read from transmit buffer into FIFO. Because only interrupt generated each buffer, (IER[0]) left permanently enabled. interrupts required selectively individual buffers, INTR ATBSTS/BTBSTS registers selectively enable interrupts. 3.4.8.2 Chained Buffers Synchronous modes when frame size exceeds maximum buffer size, frame transmitted from number separate buffers. This achieved simply setting A/BTBSTS registers until last buffer frame. CL-CD2431 transmits buffers frame; appends only when data transmitted from buffer with flag set. above procedure allocating buffers used, transmission time last buffer allocate next avoid possible underrun. (TISR[6]) interrupt associated with last buffer.
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Start
Read DMABSTS Determine Next Transmit Buffer (NtBuf)
Next Buffer 2431own
Update Descriptor 2431own
More Data Send
Other Buffer 2431own
Update Descriptor 2431own
Figure 3-8. Transmit Buffer Selection August 1996
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.8.3 Append Mode Append mode reduces overhead required provide asynchronous terminal echoing functionality; this also necessary similar application that involves unpredictable datastream. buffer into Append mode ATBSTS register. This buffer then used echoed data, while buffer used other output data. append buffer allows data transmission start from buffer before data available transmission. example, terminal echoing requires that each character echoed translated echoed) before complete line typed. operate Append mode, ATBADR ATBCNT normal (the ATBCNT zero), 2431own Append bits ATBSTS. When data available transmission, placed buffer CPU, total buffer byte count updated ATBCNT. CL-CD2431 scans ATBCNT register changes; data found, read from buffer transmitted. When more data found append buffer, CL-CD2431 scans buffer ownership. buffer owned CL-CD2431, data that buffer transmitted uninterrupted; transmission, buffer count continues scanned data. correct operation this feature, ATBCNT register should updated with word-write operation. only byte access possible, value should exceed bytes. This mode allows multiple transfers performed through single buffer; saves overhead either processing multiple buffers handling interrupts with every character. Line retransmission becomes simple `stepping back' buffer resending. terminate Append mode, command given STCR terminate buffer when current data been sent. 3.4.8.4 Transmit Errors When transmit error interrupt generated, TISR A/BTBSTS registers both indicate error status. current transfer address avail-
able TCBADR[0-3] registers, error occurred last transfer that started this address. This means actual error address bytes further buffer. Following error condition, either discontinue current buffer retry from start last transfer. discontinue, current buffer TermBuff should when TEOIR written interrupt. Synchronous mode, frame still progress needs aborted STCR. retry frame, should 2431own A/BTBSTS register, TermBuff when writing TEOIR interrupt. This causes last transfer retried; should error occur again, above procedure repeated. should check ensure that location continually retried. 3.4.9 Receive Buffer Interrupts When receive buffer complete, CL-CD2431 generates end-of-frame receive exception interrupt. provides with RISR status information which buffer complete. When receive error occurs, device stops point error generates error receive exception interrupt. RISR indicates cause exception, RCBADR provides next location receive buffer. following five options:
Terminate buffer. Discard exception. Terminate buffer discard exception. Continue from current position buffer. Leave `n'-byte buffer then continue.
required option written REOIR terminate interrupt. terminate buffer option chosen, 2431own A/BRBSTS register should first cleared CPU, buffer supplied CPU.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.4.9.1 Receive Timeout Asynchronous Mode Asynchronous mode, only that CL-CD2431 releases ownership reaching end-of-buffer. Receive timeouts exceptions release ownership end-of-buffer condition met. following illustrates recommended procedures handle receive timeout Asynchronous mode. Scenario Buffer currently selected, receive timeout occurs, host wants continue Recommendation: nothing receive timeout interrupt service routine. Scenario Buffer currently selected, receive timeout occurs, host longer requires DMA. Recommendation: Reset ownership bits ARBSTS/BRBSTS, TermBuff REOIR receive timeout interrupt service routine. Scenario Buffer currently used, receive timeout occurs, host wants start buffer Recommendation: TermBuff REOIR receive timeout interrupt service routine. CL-CD2431 switches buffer
NOTE: When receive timeout occurs buffer CL-CD2431 pops back buffer unless host clears both Ownership Status bits.
transfer that failed first buffer (due error) still receive FIFO transferred next buffer following interrupt. retry buffer from failure point, should 2431own A/BRBSTS register. should TermBuff when writing REOIR interrupt, this causes last transfer retried. Should error occur again, above procedure repeated. should check ensure that location continually retried.
Rate Generation Data Encoding
3.5.1 DPLL Operation Data clocks generated CL-CD2431 feeding number clock sources into programmable divider. clock source divisor user-programmable separately each channel direction. Clock options programmed TCOR RCOR. divisors programmed TBPR RBPR. possible clock sources following:
Transmit
input/8 input/32 input/128 input/512 input/2048 TXCIN Receive clock
above scenarios applies buffer selected first. 3.4.9.2 Receive Errors When receive error interrupt generated, RISR A/BRBSTS registers both indicate error status. current transfer address available RCBADR[0-3] registers, error occurred last transfer that started this address. This means that actual error address bytes further buffer. Following bus-error condition, either discontinue current buffer retry from start last transfer. buffer discontinued, number valid receive bytes calculated subtracting starting address A/BRBADR[0-3] from current address RCBADR[0-3]. should TermBuff REOIR terminate this buffer move next.
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Receive
input/8 input/32 input/128 input/512 input/2048 RXCIN
Section examples programming standard rates provided. value loaded given rate determined following equation:
rate divisor Frequency chosen clock source -Desired rate Equation
input nominally MHz. divisor programmed values from 1-255. maximize accuracy edge detection Asynchronous DPLL (digital phase locked loop) modes, select highest frequency clock largest divisor combination. external clock input used multiple desired rate. appropriate divisor value must loaded into Rate Period register. external clock desired rate clock) value must loaded into associated Rate Period register. receive rate generator also programmed DPLL. that mode, clock select divisor programmed near possible nominal receive rate. Clock phase adjustments made DPLL logic lock incoming datastream. receive clock optional input transmitter. This makes possible DPLL derived clock synchronize transmit datastream.
general Equation yields non-integer result. nearest integer value, along with clock source, optimum choice that rate. value loaded Period register must that integer expressed 8-bit binary value. bit-rate error difference between integer value ideal value, expressed percentage.
Example
This example illustrates programming rate generator 19.2 kbps using internal clock with system clock frequency MHz. Divisor loaded into R/TBPR Value loaded into R/TCOR 00h, select
Example
This example illustrates programming rate generator 56,000 using external clock with system clock frequency MHz. user provides 1.25-MHz clock RXCIN TXCIN pin. Divisor loaded into R/TBPR Value loaded into RCOR 06h, select External Clock mode Value loaded into TCOR C0h, select External Clock mode
used register abbreviation indicating Receive/ Transmit followed register acronym.
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Period Register (RBPR TBPR) Adjustments applied here (for DPLL only) System Clock 2048 Count Register (RBCR TBCR)
dec/inc Zero Detect
RXCIN TXCIN (for only)
From RCOR/TCOR
Figure 3-9. DPLL
Receive Clock Option Register (RCOR)
TLVal dpllEn Dpllmd1 Dpllmd0
ClkSel2
ClkSel1
ClkSel0
Transmit Clock Option Register (TCOR)
ClkSel2 ClkSel1 ClkSel0 Ext-1X
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-3.
ClkSel2
Clock Source Select
ClkSel1
ClkSel0
Select
Reserved External clock Reserved Receive clock (RCOR) (TCOR)
Table 3-4.
Rate
1200 2400 3600 4800 7200 9600 19200 38400 56000 64000
Rate Constants,
Divisor
Clock
Error
0.16% 0.25% 0.16% 0.16% 0.16% 0.16% 0.16% 0.22% 0.16% 0.22% 0.16% 0.16% 0.16% 0.80% 0.16%
divisors hexadecimal.
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-5.
Rate
1200 2400 3600 4800 7200 9600 19200 38400 56000 64000 76800
Rate Constants,
Divisor
Clock
Error
0.06% 0.02% 0.47% 0.15% 0.47% 0.15% 0.47% 0.01% 0.15% 0.45% 0.47% 0.15% 0.47% 0.35% 0.35% 0.76%
divisors hexadecimal.
Table 3-6.
Rate
1200 2400 3600 4800 7200 9600 19200
Rate Constants,
Divisor
Clock
Error
0.13% 0.35% 0.16% 0.35% 0.16% 0.35% 0.16% 0.16% 0.16% 0.35% 0.16%
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-6.
Rate
38400 56000 64000 76800 115200
Rate Constants, (cont.)
Divisor
Clock
Error
0.35% 0.05% 0.69% 0.35% 1.38%
divisors hexadecimal.
Table 3-7.
Rate
1200 2401 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 12800 134400
Rate Constants,
Divisor
Clock
Error
0.23% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.06% 0.16% 0.53% 0.06% 0.06% 0.53% 1.38%
divisors hexadecimal.
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DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
Transmit receive data encoded decoded NRZ, NRZI, Manchester formats. NRZI, start transmission, learning datastream contiguous zeros achieves synchronization; Manchester, alternating pattern ones zeros required. NRZ, NRZI, Manchester data encoding schemes used various synchronous protocols. NRZ, signal condition represents data type, high logic logic `0'. NRZI encoding, transitions datastream occur beginning cell. NRZI encoding, signal condition switches opposite state send binary `0'. Manchester encoding, transitions always middle cell. high-to-low transition made send logic `1', low-to-high transition send logic `0'. timing diagrams (Figure 3-10 Figure 3-12) illustrate encoding method. data bits `0110010'.
Divisor loaded into RCOR Value loaded into RCOR 28h, enable DPLL, NRZI framing select
Example
This example illustrates programming DPLL External Clock mode with Manchester encoding. Divisor loaded into RBPR enable external clock Value loaded into RCOR enable DPLL, select Manchester framing, external clock When using n-times external clock, highest possible clock frequency largest divisor combination recommended. frequency external clock should less than system input divided (that 33-MHz operation, data clock should less than MHz). Note that R/TBPR 8-bit register; therefore largest divisor value 255.
Example
This example illustrates programming DPLL kbits/second NRZI mode, using internal clock with system clock frequency MHz.
equation compute divisor value
Frequency external clock source rate divisor Desired rate
Equation
FUNCTIONAL DESCRIPTION
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CL-CD2431
Advanced Multi-Protocol Communications Controller
DATA CLOCK
NRZI
MANCHESTER
Figure 3-10. Data Encoding
TXCIN
TxData
NOTE: When using external receive clock Receive mode, data sampled low-to-high going edge RXCIN.
Figure 3-11. Transmit Data With External Clock
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FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
TXCOUT
TxData
Figure 3-12. Transmit Data With External Clock
FUNCTIONAL DESCRIPTION
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CL-CD2431
Advanced Multi-Protocol Communications Controller
Table 3-8.
Data Clock Selection Using External Clock
External Clock Frequency
Rate
Divisor (hex)
1200 2400 3600 4800 7200 9600 19200 38400 56000 64000 76800 115200 128000
9.765 9.765 9.765 39.062 39.062 156.250 156.250 625.00 625.00 1.250 1.250 1.250 1.250 1.250 1.250 1.250 2.00 2.00
Hardware Configurations
demultiplex A/D[15:0] into separate address data buses, external buffers latches required. reduce external circuitry, multi-CL-CD2431 applications. common control lines (ADLD*, AEN*, DATDIR*, DATEN*) external devices wire-OR'ed together. These pins tristate, open collector, external pull-up resistor (2.2-5.0 must connected each line ensure logic when CL-CD2431 master. When higher-priority alternate masters present, daisy-chain priority scheme August 1996
implemented wire OR'ing BGACK* connecting directly 680X0. 680X0 signal then connected first device chain daisy-chained remaining devices. lower-priority master then connected chain. higher-priority master present, signal must qualified before being passed into highest priority CL-CD2431. priorityencoded scheme required, signals must prioritized externally signals routed individual devices.
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
3.6.1 Interface 32-Bit Data interface 32-bit data bus, 16-bit data buffers must used isolate CL-CD2431 A/D[15:0] pins from either half 32-bit bus. A[1] address determines lower upper 3.6.2 Connections CL-CD2431
half data particular cycle. CL-CD2431 always drives data bits during register-read DMA-write operation, regardless size actual transfer.
DATEN*
16-BIT DATA Xcvr
DATDIR* R/W* CD2431 DTACK* [15:0] ADLD* A[7:0]
DATA[15:0]
24-BIT LATCH [31:16] STROBE* [31:8] [15:8] [7:0]
32-BIT ADDRESS DRIVER MA[31:0]
AEN*
Figure 3-13. Connections CL-CD2431
NOTES: 24-bit latch required. 16-bit transceiver optional depending application. 32-bit driver optional depending drive requirements.
FUNCTIONAL DESCRIPTION
DATA BOOK v3.0
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CL-CD2431
Advanced Multi-Protocol Communications Controller
3.6.3 Recommended CL-CD2431 Interface following table shows recommended (data terminal equipment) connections between CL-CD2431 RS-232C standard interfaces.
CL-CD2431
RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT
following table shows recommended (data communications equipment) connections between CL-CD2431 RS-232C standard interfaces.
CL-CD2431 RS-232C
DB/CC DA/-
RS-232C
-/CD -/CF
RTS* CTS* DSR* TXCOUT/DTR* RXCIN TXCIN RXCOUT
Reference: CCITT 1988 Blue Book.
August 1996
DATA BOOK v3.0
FUNCTIONAL DESCRIPTION
CL-CD2431
Advanced Multi-Protocol Communications Controller
PROTOCOL PROCESSING
HDLC Processing
4.1.1 (Frame Check Sequence) 16-bit standard computation used HDLC, defined 3309. This algorithm same that used with synchronous HDLC operation CL-CD2431. basic characteristics following: Accumulation: computation starts after opening flag continues closing flag. Pre-load: 16-bit accumulator pre-set `1's. Transmit order: bits identified most-significant X15, transmitted first. Thus, first character transmitted bits X15-X8 character positions D1-D8, respectively. second character bits X7-X0 character positions D1-D8, respectively. Transmit polarity: Inverted. Correct remainder: receiver calculates entire received frame, including received field. frame received error-free, then correct remainder accumulation (X15 leftmost bit). individually enabled disabled transmitter receiver. enabled transmitter, device appends transmitted frames. disabled, device adds frame. enabled receiver, device computes received reports results. append also enabled, device includes 2byte received data presented host. disabled, device does test received FCS.
4.1.2 HDLC Transmit Mode transmitter programmed idle either Flag (01111110) Mark (continuous 1's) mode Idle (COR3[3]). When idle Mark mode, frame transmission programmed prepended programmable number characters flags. character selected either characters allow remote receivers phase locked loop synchronize quickly data. When NRZI encoding used Manchester encoding, character guarantees transition every time, character guarantees exactly transition time. transmitter idle Mark mode, frame transmission started when data made available transmitter, either (Transmit Data register) buffer. First, programmable number characters transmitted, then programmable number flag characters. Data characters then transmitted value accumulated using each data character. When end-of-frame status passed CL-CD2431 TEOIR A/BTBSTS, remaining data transmitted, closing flag appended frame. frame available immediately, correct number opening flags transmitted data transmission starts. data available, line returned idle condition. data underrun occurs, CL-CD2431 does append CRC, aborts transmission sending eight continuous `1's, then reverts idle condition. underrun interrupt generated, interrupt transfer being used, should provide response TEOIR. Transfer mode being used, CL-CD2431 discards buffers until buffer found; transmission then resumes from next buffer. This ensures correct operation when multiple buffer frame underruns. When programmed NRZI mode idle Mark mode, after closing flag first eight `1's transmitted, transmit data line sampled determine logic high low. low, extra transmitted force line logic high.
PROTOCOL PROCESSING
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CL-CD2431
Advanced Multi-Protocol Communications Controller
When idle Flag mode selected, send opening number flags have significance; transmission started when data first made available FIFO. data underrun occurs, frame terminated normally with CRC, then continuous flags generated. underrun does occur, then appended, eight `1's transmitted, then continuous flags underrun interrupt generated. 4.1.3 HDLC Receive Mode When enabled, receiver enters Flag Hunt mode. When first flag detected, next nonflag/abort character treated start frame. address recognition enabled, frame reception then continues; Address Recognition mode enabled, incoming data compared with receive address registers. following modes address recognition available:
(end frame) interrupt generated. either validated ignored. CL-CD2431 does check CRC, passed onto host. validated discarded passed onto host diagnostic purposes. next non-flag/abort character restarts process; current state receive process visible register, which indicates whether data, flag, mark currently being received. support data phase X.21 connection, clear detect feature enabled COR1. When enabled, receive data CTS* monitored clear indication off) from remote. detected, remainder current frame discarded, clear detect indication passed RISR. However, channel remains HDLC mode until modified CPU.
First byte address field only (four possible matches available against RFAR1-4). First second byte address field (two possible matches available against RFAR1-2, RFAR3-
(Point-to-Point Protocol) Mode
4.2.1 Character Format mode uses async-HDLC character format, which fixed start bit, eight data bits, stop bit. There parity bit. character format shown Figure 4-1. Using definitions from standard format (Figure 4-1), data bits identified D1-D8. LSB. Characters identified either bits (D1-D8) hexadecimal values showing value bits D5-D8 first, followed value D1-D4. Thus, flag character `01111110', indicated controlescape character `10111110'
purposes address matching, Address Extension interpreted device. address matching occurs either complete first byte, complete first second byte frame. address match recognized, Flag Hunt mode once again entered, thereby discarding current frame. match found, normal frame reception continues. When closing flag frame detected, data remaining FIFO passed CPU, either through transfers Good Data interrupts, then
START
STOP
line high prior Start bit. high value either line idle Stop from previous character.
Start next character could begin earlier than immediately after previous
Figure 4-1. Character Format
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PROTOCOL PROCESSING
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.2.2 Frame Format standard frame format follows:
FLAG
A-FIELD C-FIELD FRAME DATA CHARACTERS
FCS-1
FCS-2
FLAG
Interframe idle time fill next address.
closing flag (7E) previous frame same flag used opening next frame. This shared flag.
Figure 4-2. Point-to-Point Protocol Frame
fields
device passes fields from host. device does special processing these fields. 4.2.3 (Frame Check Sequence) mode uses same 16-bit HDLC mode (V.41). Everything between flags included calculation with exceptions: control-escape (7D) characters added transparency, mapped characters received without preceding controlescape. characters preceded controlescape, calculation made after inverted. 4.2.4 Transparency Transparency means that there protocol method prevent confusion ambiguity between control characters data characters frame. mode, there control-escape mechanism. Specific characters identified `control mapped' characters. control called ACCM (async-control-character map). Whenever there mapped character data stream, transmitter precedes that character with controlescape character After control-escape, character itself transmitted with inverted. example, character mapped character, then transmission 7D-33.
When receiver sees control-escape character, removed following character inverted. resultant reconstructed character passed host received character. 4.2.4.1 Mapped Characters from 00-1F When channel selected mode, ACCMs assigned. Each ACCM consists four registers bits) define mapped characters range 00-1F. ACCM transmitter (TXACCM), receiver (RXACCM). Each within ACCM points particular character within range. When set, that character mapped character. When clear, that character mapped character. example, suppose TXACCM pointing character set, that TXACCM pointing character clear. Then whenever present transmission, actual transmission 7D-32. Whenever present transmission, transmitted without modification. Continuing example, receiver ACCM bits pointing also clear, respectively. Then received (without preceding discarded, received (without preceding passed through host unchanged. 4.2.4.2 Mapped Characters from Above Three characters above mapped. These characters defined Channel Specific registers TSPMAP[1], TSPMAP[2], TSPMAP[3].
PROTOCOL PROCESSING
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.2.4.3 Characters Transmitted Data Whenever transmitter sees either data transmission, transmitter treats these mapped characters. Thus, data transmitted 7D-5D, data transmitted 7D-5E. 4.2.4.4 Mapped Characters Field Whenever transmitter sees that result transmitted contains mapped character, handles that character other mapped character. Section 4.2.4. example, field A7-7E, transmitter would send three characters field, A7-7D-5E. receiver would convert received back A7-7E before completing computation. 4.2.5 Definition Valid Frame This section discusses valid frames from viewpoint CL-CD2431 devices. characters formatted standard async-HDLC format shown Section 4.2.1. When channel placed mode, that channel transmits expects received characters shown Section 4.2.1. There exception Section 4.2.6.2 Section 4.2.6.4.
Async-HDLC protocols have minimum frame size requirements. However, CL-CD2431 devices makes requirement minimum frame size. frame opens ends with flag (7E). device complies with this transmit, requires opening closing flags receiver. closing flag from preceding frame same flag opening flag next frame. This shared flag. device send receive both shared non-shared flags. frame never ends with control-escape followed flag (7D-7E). device does send 7D-7E frame normal mode. device commanded send abort either 7D-7E character with stop bit. device receives frame that ends 7D-7E, that frame indicated host being error. mode requires transparency described Section 4.2.4. transparency always enabled when channel mode.
August 1996
DATA BOOK v3.0
PROTOCOL PROCESSING
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.2.6 Transmitter 4.2.6.1 Fixed Transmitter Operations mode, transmitted characters format shown Section 4.2.1, transmitter always sends opening flag.
4.2.6.2 Transmitter Options device transmitter control-bit selected following options:
Option
map32 (ATBSTS) (BTBSTS) npad3, (COR3) TxGen (COR3) frame (STCR)
Description
When map32 set, characters TXACCM (00-1F) mapped. characters transmitted with preceding with flipped. When map32 clear, normal TXACCM used. minimum number idle character times between transmitted frames programmable from 0-15 character times. TxGen set, device adds character each frame. TxGen clear, device ends frame with closing flag after last data byte from host. When commanded setting frame STCR, device sends character frame with Stop forced `0'.
4.2.6.3 Transmission Abort When commanded through STCR (Special Transmit Command register), device ends transmission current frame with abort sequence 7D-7E. After executing abort, device clears STCR. rules shared flag transmission Section 4.2.6.2 followed trailing flag (7E) abort sequence (7D-7E). device sending frame when Command set, device clears STCR does send abort sequence. 4.2.6.4 Transmit Framing Error test purposes, character with framing error transmitted inside frame. Command STCR notifies device transmit character with Stop forced `0'. channel transmitting frame, framing error character inserted. After transmission, channel continues with frame transmission. After executing command, device clears STCR.
device sending frame when Command set, device clears STCR does send framing error character. 4.2.7 Receiver 4.2.7.1 Fixed Receiver Operations receiver accepts frame character when received data brought through device presented host. Async-HDLC mode, receiver accepts only characters format shown Section 4.2.1. receiver accepts only frames that have opening flag; there more than opening flag.
PROTOCOL PROCESSING
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
4.2.7.2 Receiver Options device receiver control-bit selected following options:
Option
RxChk (COR3) RTPR
Description
RxChk set, receiver tests each frame reports result. RxChk clear, receiver makes computation. RTPR timer disabled when bits zero. RTPR enabled with non-zero value. Section 4.5.
SLIP Processing
NOTE: SLIP, Automatic In-Band Flow Control modes only available Revision later devices.
During receipt frame, CL-CD2431 makes following substitutions:
4.3.1 Framing defined original implementation, SLIP frames with `END' character have beginning character. However, RFC-1055 suggests that frames begin with `END' characters. CL-CD2431 uses `END' character essentially opening closing flags. defined characters (see table below) fixed (hardcoded) cannot changed user.
Defined Character
ESC_END ESC_ESC
When `ESC' character found data stream, only `ESC_END' `ESC_ESC' characters follow. These character sequences replaced with single character: sequence `ESC', replaced with `END'. sequence `ESC', replaced with `ESC'. `ESC_END' `ESC_ESC'
Encoding
0xC0 0xDB 0xDC 0xDD
Even though characters `ESC_END' `ESC_ESC' only valid characters following `ESC', RFC-1055 suggests that when other characters encountered, `ESC' should discarded second character should kept unmodified. CL-CD2431 follows this convention.
SLIP protocol prohibits in-band flow control. such, CL-CD2431 does respond XOFF characters special way, they treated normal data. 4.3.2 Debugging Aids debug purposes, CL-CD2431 send sequence `ESC', `END', STCR (Special Transmit Command register). This intended abort frame function. STCR also command sending value) Stop bit, which causes framing error receiving end. When CL-CD2431 receives sequence `ESC', `END', reported `receive abort' RISR register. Stop reported (framing error) RISR.
CL-CD2431 uses following conventions when transmitting SLIP frame:
When `END' character sent, replaced character sequence `ESC', `ESC_END'. When `ESC' character sent, replaced character sequence `ESC', `ESC_ESC'.
August 1996
DATA BOOK v3.0
PROTOCOL PROCESSING
CL-CD2431
Advanced Multi-Protocol Communications Controller 4®/ARAP Protocol Processing
NOTE: SLIP, Automatic In-Band Flow Control modes only available Revision later devices.
Table 4-1.
Special Character Definition
ARAP
Special Character Register
SCHR1 contains start character SCHR2 contains escape character
ARAP
4.4.1 Framing (V.42) frame consists start flag, data octets, stop flag, 16-bit (frame check sequence). uses polynomial preset `1's, transmitted, inverted. character format uses asynchronous framing with data bits, parity, Stop bit. In-band flow control (XON/XOFF) permitted this mode. start flag three octet sequence consisting start character, escape character, (0x02). stop flag octet sequence consisting escape character (0x03). During transmit, escape character encountered data stream, duplicated. Conversely, receiver discards second sequential escape characters. data-link layer ARAP (AppleTalkRemote Access Protocol). ARAP same except start escape characters. CL-CD2431 uses Special Character registers (SCHR1 SCHR2) hold definition start escape characters. There mode selection within CL-CD2431 that allows determine whether ARAP ARAP environment. builds detects frames using values Special Character registers. user must load Special Character registers with appropriate start escape characters version during channel initialization. special characters each protocol shown Table 4-1.
both versions ARAP, frames begin with SCHR1, SCHR2, STX, with SCHR2 ETX:
ARAP SYN, DLE, STX, data, data, data, DLE, ARAP SOH, ESC, STX, data, data, data, ESC,
Both versions escape escape character SHCR2) duplicating appears within data stream. 4.4.2 MNP® 4/ARAP (Frame Check Sequence) Calculation Both versions polynomial, preset `1's, transmitted inverted with remainder equal 0x1D0F. frame body octet stop flag included calculation both versions. start flag (ARAP 1.0)/ESC (ARAP 2.0) octets that used transparency excluded from calculation. Figure Figure illustrate characters used calculation. Data used calculation bold print.
PROTOCOL PROCESSING
DATA BOOK v3.0
August 1996
CL-CD2431
Advanced Multi-Protocol Communications Controller
Start Flag data data
data data
Flag FCS1 FCS2
Figure 4-3. ARAP Frame
Start Flag data data data data Flag FCS1 FCS2
Figure 4-4. ARAP Frame
NOTE: (ARAP 1.0) (ARAP 2.0) characters middle data stream, indicated column, inserted transparency thus included calculation.
Async Processing
Data transmitted according format options defined Channel Option registers. These options determine character length, parity, Stop length. data sent from host transmitted continuous stream, unless following occurs:
Transmitter disabled transmission terminated current character until transmitter enabled. XOFF received from line transmission terminated current character until received transmitter enabled. Out-of-band flow control transmission terminated current character until out-of-band flow control removed. In-line command received data stream from host in-line command executed transmission resumed. Send special character command from host current character completed special character transmitted after which normal transmission resumed.
COR2, meaning. XOFF characters defined Special Character registers SCHR[1:2]. When in-band flow control enabled (TxIBE XOFF character received, channel stops transmission after current character transmit shift register current character transmit holding register transmitted. When transmission restarts after character received. When transmission restarts after character received. (flow control transparency) Mode (COR3[6]) used determine received flow control characters passed host. characters passed host. they passed host exception characters. This does affect non-flow control special characters. Additional status information about transmitter inband flow control available (Channel Status register). TxFloff (Transmit Flow Off) TxFlon (Transmit Flow bits used. TxFloff normal. TxFloff indicates that channel been requested remote stop transmission. This reset when channel receives restart, described earlier. This reset when transmitter enabled disabled, channel reset. TxFlon normal. TxFlon indicates that channel been requested remote
4.5.1 Transmitter In-Band Flow Control in-band flow control modes active, Special Character Detect mode must enabled. Transmit in-band flow control enabled when TxIBE (Transmit In-Band Enable) COR2 `1'. When TxIBE `0', in-band flow control disabled, (Implied Mode) bit, also August 1996
DATA BOOK v3.0
PROTOCOL PROCESSING
CL-CD2431
Advanced Multi-Protocol Communications Controller
restart transmission. This reset once channel restarted transmission. This reset when transmitter enabled disabled, channel reset. 4.5.1.1 Receiver In-Band Flow Control channel request remote stop transmission sending XOFF character. Likewise, channel request remote restart transmission sending characters. XON/XOFF characters transmitted setting SndSpc (STCR[3]) `1'. contains status bits RxFloff (Receive Flow Off) RxFlon (Receive Flow which used receiver in-band flow control. RxFloff normal. RxFloff indicates channel requested that remote stops transmission. This reset when channel requests that remote restart transmission. This reset when receiver enabled disabled, channel reset. RxFlon normal. RxFlon indicates that channel requested that remote restarts transmission. This rese
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