64CH COMMON DRIVER MATRIX QFP-1420C KS0107B driver with channel o
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KS0107B
64CH COMMON DRIVER MATRIX
QFP-1420C KS0107B driver with channel outputs matrix liquid crystal graphic display systems. This device provides shift registers output drivers. generates timing signal control KS0108B channel segment driver). KS0107B fabricated power CMOS high voltage process technology, composed liquid crystal display system combination with KS0108B channel segment driver).
FEATURES
matrix common driver with channel output 64-bit shift register internal driver circuit Internal timing generator circuit dynamic display Selection master/slave mode Applicable duty 1/48, 1/64, 1/96, 1/128 Power supply voltage: ±10% driving voltage 8V~17V (VDD-VEE) Interface Driver COMMON Other KS0107B SEGMENT KS0108B Controller
TQFP-1414
High voltage CMOS process 100QFP 100TQFP bare chip available
1/20
KS0107B
64CH COMMON DRIVER MATRIX
BLOCK DIAGRAM
64-bit driver
64-bit bi-directional shift register
DIO1 PCLK2
Data shift direction Phase selection control circuit
DIO2
Timing generator circuit CLK1 CLK2
KS0107B Functional block diagram
2/20
KS0107B CONFIGURATION 100QFP
64CH COMMON DRIVER MATRIX
KS0107B
DIO1
PCLK2
DIO2
Fig2. View
3/20
CLK2
CLK1
KS0107B DIAGRAM Chip layout 100QFP
64CH COMMON DRIVER MATRIX
KS0107B
CHIP
SIZE
3450 4000
SIZE UNIT
There mark KS0107B center chip
4/20
KS0107B LOCATION (100QFP)
NUMBER NAME DIO1 COORDINATE -1314.5 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1499.9 -1345.6 -1127.6 -979.6 -827.6 -677.6 -527.6 -377.6 1775.4 1630 1505 1380 1255 1130 1005 -120 -245 -370 -495 -620 -745 -870 -995 -1120 -1245 -1370 -1495 -1775 -1775 -1775 -1775 -1775 -1775 -1775 NUMBER NAME CLK2 CLK1 PCLK2 DIO2
64CH COMMON DRIVER MATRIX
UNIT (µm)
COORDINATE -227.6 -77.6 113.8 308.7 458.7 608.7 758.7 908.7 1058.7 1208.7 1358.7 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 1500.9 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1775 -1495 -1370 -1245 -1120 -995 -870 -745 -620 -495 -370 -245 -120 1005 1130 1255 NUMBER NAME COORDINATE 1500.9 1500.9 1500.9 1310.5 1185.5 1060.5 935.5 810.5 685.5 560.5 435.5 310.5 185.5 60.5 -64.5 -189.5 -314.5 -439.5 -564.5 -689.5 -814.5 -939.5 -1064.5 -1189.5 1380 1505 1630 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4 1775.4
5/20
KS0107B 100TQFP
64CH COMMON DRIVER MATRIX
DIO2 PCLK2 CLK1 CLK2
KS0107B
DI01
Fig3.
TQFP View
6/20
KS0107B DIAGRAM (Chip layout 100TQFP)
64CH COMMON DRIVER MATRIX
KS0107BTQ
CHIP SIZE SIZE UNIT
3850 4100
There mark KS0107BTQ center chip.
7/20
KS0107B LOCATION (100TQFP)
64CH COMMON DRIVER MATRIX
UNIT (µm)
NAME DIO1 CLK2 CLK1 PCLK2
COORDINATE -1697 1534 -1697 1409 -1697 1284 -1697 1159 -1697 1034 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -1697 -216 -1697 -341 -1697 -466 -1697 -591 -1697 -716 -1697 -841 -1697 -966 -1697 -1091 -1697 -1216 -1697 -1341 -1697 -1466 -1245 -1821 -1095 -1821 -945 -1821 -795 -1821 -645 -1821 -495 -1821 -345 -1821 -195 -1821 -1821 -1821 -1821 -1821 -1821 -1821 -1821
NAME DIO2
COORDINATE 1095 -1821 1245 -1821 1697 -1466 1697 -1341 1697 -1216 1697 -1091 1697 -966 1697 -841 1697 -716 1697 -591 1697 -466 1697 -341 1697 -216 1697 1697 1697 1697 1697 1697 1697 1697 1697 1697 1034 1697 1159 1697 1284 1697 1409 1697 1534 1500 1822 1375 1822 1250 1822 1125 1822 1000 1822 1822 1822 1822 1822 1822 1822 1822 1822 -125 1822 -250 1822 -375 1822 -500 1822
NAME
COORDINATE -625 1822 -750 1822 -875 1822 -1000 1822 -1125 1822 -1250 1822 -1375 1822 -1500 1822
8/20
KS0107B DESCRIPTION
QFP(TQFP) 28(25) 40(37) 23(20),58(55) 27(24), 54(51) 24(21), 57(54) 25(22), 56(53) 26(23), 55(52) SYMBOL V0L, V1L, V4L, V5L, INPUT/OUTPUT Power
64CH COMMON DRIVER MATRIX
DESCRIPTION internal logic circuit (+5V ±10%) driver circuit Bias supply voltage terminals drive LCD. Select Level V0L(R), V5L(R) Non-Select Level V1L(R), V4L(R)
Power
42(39)
Input
39(36)
Input
(V1L V1R, V4R, V5R) should connected same voltage. Selection master/slave mode Master mode (MS=1) DIO1, DIO2, output state. Slave mode (MS=0) SHL=1DIO1 input state (DIO2 output state) SHL=0DIO2 input state (DIO1 output state) input state. Selection data shift direction. Data shift direction DIO1C1 C64DIO2 DIO2C64 C1DIO1
49(46)
PCLK2
Input
Selection shift clock (CL2) phase. PCLK2 Shift clock (CL2) phase data shift rising edge data shift falling edge
30(27)
Input
31(28) 32(29)
Input
Selection oscillation frequency. Master mode When frame frequency oscillation frequency should fosc=430 FS=1 (VDD) fosc=215 FS=0 (VSS) Slave mode Connect VDD. Selection display duty. Master mode Slave mode Connect VDD. Duty 1/48 1/64 1/96 1/128
9/20
KS0107B DESCRIPTION (continued)
QFP(TQFP) 33(30) 35(32) 37(34) SYMBOL INPUT/OUTPUT
64CH COMMON DRIVER MATRIX
DESCRIPTION Oscillator Master mode these terminals shown below.
KS0107B open external clock open KS0107B
Slave mode stop oscillator shown below.
KS0107B
open
open
44(41), 43(40)
CLK1 CLK2
Output
46(43)
Output
47(44)
Input Output
52(49)
Input Output
29(26) 50(47)
DIO1 DIO2
Input Output
Operating clock output KS0108B Master mode connection CLK1 CLK2 KS0108B Slave mode open Synchronous frame signal. Master mode connection KS0108B Slave mode open Alternating signal input driving. Master mode output state Connection KS0108B Slave mode input state Connection controller Data shift clock Master mode output state Connection KS0108B Slave mode input state Connection shift clock terminal controller. Data input/output internal shift register. DIO1 Output Output Input Output DIO2 Output Output Output Input
22~1 (19~1) 100~59 (100~56)
Common signal output driving. C1~C64 Output DATA
34(31),36(33) 38(35),41(38) 45(42),48(45) 51(48),53(50)
Connection
10/20
KS0107B MAXIMUM ABSOLUTE LIMIT
Characteristic
Operating Voltage Supply Voltage Driver Supply Voltage Operating Temperature Storage Temperature
64CH COMMON DRIVER MATRIX
Symbol
VLCD
Value
-0.3~+7.0 VDD-19.0~VDD+0.3 -0.3~VDD+0.3 VEE-0.3~VDD+0.3 -30~+85 -55~+125
Unit
Note
*1,2 *3,4
Based VSS=0 Applies input terminals terminals high impedance. (Except V0L(R), V1L(R), V4L(R) V5L(R)) Applies V0L(R), V1L(R), V4L(R) V5L(R). Voltage level: V0L= V1L= V4L= V5L= VEE.
ELECTRICAL CHARACTERISTICS
Characteristics (VDD=+5V ±10%, VSS=0V, |VDD-VEE |=8~17V, +85°C) Characteristic Symbol condition
Input High Voltage Output High Voltage Input Leakage Current Frequency Resistance (Vdiv-Ci) Operating Current ILKG fOSC IOH=-0.4 IOL=0.4 VIN=VDD~VSS Rf=47 Cf=20pf VDD-VEE =17V Load current ±150µA Master mode 1/128 Duty Slave mode 1/128 Duty Master mode 1/128 Duty Master mode External clock Slave mode 0.7VDD VDD-0.4 -1.0
0.3VDD
Unit
Note
IDD1 IDD2
1500
Supply Current Operating Frequency
fop1 fop2
Applies input terminals DS1, DS2, SHL, PCLK2 terminals DIO1, DIO2, input state. Applies output terminals CLK1, CLK2 terminals DIO1, DIO2, output state. This value specified about current flowing through VSS. Internal oscillation circuit: Rf=47 Cf=20 Each terminal DS1, DS2, connected load. This value specified about current flowing through VSS. Each terminal DS1, DS2, SHL, PCLK2 connected VDD, connected VSS. CL2, DIO1 external clock. This value specified about current flowing through VEE. Don't connect VLCD (V1~V5).
11/20
KS0107B
Characteristics (VDD=5V ±10%, Ta=-30°C~+85°C)
Master mode (MS=VDD, PCLK2=VDD, Cf=20 Rf=47
0.7VDD
64CH COMMON DRIVER MATRIX
0.7VDD
CLK1
CLK2
Characteristic Data Setup Time Data Hold Time Data Delay Time Delay Time Delay Time Level Width High Level Width CLK1 Level Width CLK2 Level Width CLK1 High Level Width CLK2 High Level Width CLK1-CLK2 Phase Difference CLK2-CLK1 Phase Difference CLK1, CLK2 Rise/Fall Time
Symbol tWLC tWHC tWL1 tWL2 tWH1 tWH2 tD12 tD21 tR/tF
2100 2100
Unit
12/20
KS0107B
Slave mode (MS=VSS)
64CH COMMON DRIVER MATRIX
PLK2
tWLC1 0.7V tWHC1 tWHC2 tWLC 0.3V
PLK2 DIO1 DIO2 Input Data DIO1 DIO2 Output Data thcl
0.7VDD 0.3VDD
0.7VDD 0.3V
Characteristics Level Width High Level Width Level Width High Level Width Data Setup Time Data Hold Time Data Delay Time Output Data Hold Time Rise/Fall Time Connect load CL=30
Symbol tWLC1 tWHC1 tWLC2 tWHL tR/tF
Unit
Note PCLK2=VSS PCLK2=VSS PCLK2=VDD PCLK2=VDD
OUTPUT 30pF
13/20
KS0107B FUNCTIONAL DESCRIPTION
64CH COMMON DRIVER MATRIX
Oscillator Oscillator generates CL2, KS0107B, CLK1 CLK2 KS0108B oscillation resister capacitor When selecting master/slave mode, oscillation circuit following: Master Mode master mode, these terminals shown below.
KS0107B open 20pF
KS0107B
open external clock
Internal Oscillation
Slave Mode slave mode, stop oscillator shown below.
External Clock
KS0107B
open
open
Timing Generation Circuit generates CL2, FRM, CLK1 CLK2 frequency from oscillation circuit. Selection Master/Slave (M/S) Mode When "H", generates CL2, FRM, CLK1 CLK2 internally. When "L", operates receiving from master device. Frequency Selection (FS) adjust frequency oscillation frequency should follows: Oscillation Frequency fOSC=430 fOSC=215
slave mode, connected VDD. Duty Selection (DS1, DS2) provides various duty selections according DS2. DUTY 1/48 1/64 1/96 1/128
14/20
KS0107B
64CH COMMON DRIVER MATRIX
Data Shift Phase Select Control Phase Selection circuit shift data synchronization rising edge, falling edge according PCLK2. PCLK2 Phase Selection Data shift rising edge Data shift falling edge
Data Shift Direction Selection When connected VDD, DIO1 DIO2 terminal only output. When connected VSS, depends SHL. DIO1 Output Output Input Output DIO2 Output Output Output Input Direction Data C1C64 C64C1 DIO1C1C64DIO2 DIO2C64C1DIO1
15/20
KS0107B TIMING DIAGRAM
1/48 Duty Timing (Master Mode)
Condition: DS1=L, DS2=L, SHL=H(L), PCLK2=H
64CH COMMON DRIVER MATRIX
CLK1 CLK2
DIO1 DIO2
DIO2 DIO1 relation
DIO1 DIO2
CLK2
DIO1 DIO2
16/20
KS0107B
1/128 duty timing (Master mode)
Condition: DS1=H, DS2=H, SHL=H(L), PCLK2=H
64CH COMMON DRIVER MATRIX
CLK1 CLK2
DIO1 DIO2
DIO2 DIO1
relation CLK2
DIO1 DIO2
DIO1 DIO2
17/20
KS0107B
1/48 Duty Timing (Slave Mode)
Condition: PCLK2=L, SHL=H(L)
64CH COMMON DRIVER MATRIX
DIO1 DIO2
DIO2 DIO1
18/20
KS0107B
Power Driver Circuit
64CH COMMON DRIVER MATRIX
V0L/R V1L/R
KS0107B
V4L/R V5L/R KS0108B
Relation duty bias DUTY 1/48 1/64 1/96 1/128 BIAS 1/11 1/12 Rdiv R2=4R1 R2=5R1 R2=7R1 R2=8R1
*When duty factor 1/48, value should satisfy. R1/(4R1+R2)=1/8 R1=3 R2=12
19/20
KS0107B
CS1B
CS2B
RSTB
V0R/L V3R/L V5R/L CLK1 CLK2 S1~S64 V2R/L V2R/L V3R/L V5R/L V0R/L S1~S64
CS1B
CS2B
RSTB
CLK1 CLK2
APPLICATION CIRCUIT
1/128 Duty Segment Drive(KS0108B)
KS0108B
KS0108B
COM1 SEG1 KS0107B (Master)
PCLK2
SEG128
OR/L IR/L V4R/L V5R/L COM128 open open S1~S64 PCLK2 CLK2 CLK1 V0R/L V2R/L V3R/L V5R/L CS1B CS2B CLK1 CLK2 CLK2 DIO2 CLK1 DIO1 DIO1 DIO2
Interface Circuit
PANEL
64CH COMMON DRIVER MATRIX
20/20
VOR/L VIR/L V4R/L V5R/L open RSTB CS1B CS2B open open open open CLK2 CLK1 RSTB KS0108B KS0107B (Slave)
S1~S64
V0R/L V2R/L V3R/L V5R/L CS1B CS2B RSTB KS0108B
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