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9710 Data Compression Processor Hi/fnsupplies Internet's most important materials: compression encryption. Hi/fn also world's first company both single chip, creating processor that performs compression encryption faster speed than conventional alone could handle, much less than cost Pentium comparable processor. October 1998, address Hi/fn, Inc. University Avenue Gatos, 95032 info@hifn.com http://www.hifn.com Tel: 408-399-3500 Fax: 408-399-3501 Hi/fn Applications Support Hotline: 408-399-3544
Disclaimer Hi/fn reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. Hi/fn warrants performance semiconductor products related software specifications applicable time sale accordance with Hi/fn's standard warranty. Testing other quality control techniques utilized extent Hi/fn deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). HI/FN SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion Hi/fn products such critical applications understood fully risk customer. Questions concerning potential risk applications should directed Hi/fn through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. Hi/fn does warrant that products free from infringement patents, copyrights other proprietary rights third parties. event shall Hi/fn liable special, incidental consequential damages arising from infringement alleged infringement patents, copyrights other third party intellectual property rights. "Typical" parameters vary different applications. operating parameters, including "Typicals," must validated each customer application customer's technical experts. this product require license from Motorola. license agreement right Motorola patents obtained through Hi/fn directly from Motorola.
DS-0010-01 (9/98) 1997-1998 Hi/fn, Inc., including more U.S. patents No.: 4,701,745, 5,003,307, 5,016,009, 5,126,739, 5,146,221, 5,414,425, 5,414,850, 5,463,390, 5,506,580, 5,532,694. Other patents pending.
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9710 Data Compression Processor
Table Contents
Product Description descriptions Interface.6 Interface Compression Interface.9 Miscellaneous Signals Product Overview.10 Source FIFO Data Flow.10 Dest FIFO Data Flow Command/Result Pipeline Compression RAM.13 Register Description Overview Data (0).14 Command Stack Command Termination Conditions Commands.16 Command Stack Fields.18 Result Stack Configuration Interrupt Enable 4.10 Status 4.11 FIFO Status (6).31 4.12 FIFO Configuration Register Summary.33 Timing Descriptions Interface.34 Electrical Specifications Timing Specifications.40
Figures
Figure System Concept.5 Figure 100-pin TQFP Connections Figure Modes usage.8 Figure Internal block diagram.11 Figure Command/Result Pipeline Figure Register list.14 Figure Commands.16 Figure Example CRAM usage Figure DRAM size values Figure Refresh frequency.25 Figure 9710 performance.26 Figure Effect Compression Performance field with SRAM Figure Effect Compression Performance field with DRAM.27 Figure Absolute maximum ratings.38 Figure Recommended operating conditions Figure electrical characteristics.39 Figure specification definition.39 Figure Reset timing.40 Figure External PCLK clock Figure External BCLK clock DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Figure External clock.40 Figure Asynchronous Timing.41 Figure Asynchronous Timing Figure Synchronous Timing.43 Figure Synchronous Timing Figure 68360 Timing Figure 68360 Timing.46 Figure Compression SRAM Read Timing.47 Figure Compression SRAM Write Timing Figure Compression DRAM Read Write Timing Figure Compression DRAM Read Write Timing Diagram.49 Figure Compression DRAM Refresh Timing Figure 100-pin TQFP package Figure 100-pin TQFP pinout
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9710 Data Compression Processor
Product Description
Hi/fn 9710 high-performance lossless data compression processor which used variety applications, including data communication applications. This product implements LZS® data compression algorithm. algorithm been standardized many standards organizations including ANSI (X3.241), (122), IETF (RFC-1967, RFC1974), TIA/EIA (655), Frame Relay Forum (FRF.9). Multiple compression histories supported, providing maximum compression ratio possible multi-stream data communication applications. intervention required between operations, eliminating latency issues. Operations pipelined, will switch automatically when operation completes. Features Supports data compression algorithm Maximum Mbyte/s compression, Mbyte/s decompression speed intervention required between operations latency) Simple operation Multiple compression histories 2048 simultaneous histories) Single slave interface Applications Data communication products Routers Bridges Remote Access Mass storage products Part Number 9710 Package 100-pin thin plastic quad flat pack
Controller Compression
9710
Figure System Concept
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor
100-pin TQFP Interface 18-7,5,100-82 Interface Compression 32,19,75-73 72-70 69,67,65-56 54,52-38 Miscellaneous Signals 37,36 6,31,55,68,81 4,29,53,66,79
descriptions
Signal
DATA31-0 ADDR2-0 IRQ#
Type PI/O4 O6/OD6 O6/OD6 I/O4
Description 32-bit data bus. (16-bit option) Register select Read/Write Command Strobe Interrupt output Data Strobe Source FIFO request Source FIFO acknowledge Source FIFO terminal count Dest FIFO request Dest FIFO acknowledge Dest FIFO terminal count CRAM Address CRAM Address CRAM Address CRAM Data Write enable Output enable Lower Byte enable Upper Byte enable Reset mode clock Processing Unit clock volts Ground
SDREQ# SDACK# STC# DDREQ# DDACK# DTC#
CADDR19-15 CADDR14-12 CADDR11-0 CDATA15-0
RESET# BMODE1-0 BCLK PCLK
I=TTL input, SI=schmitt input; CI=clock input; Ox=output; I/Ox=bidirectional; ODx=open drain output. Numerals indicate levels. Electrical Specifications section more details.
Figure 100-pin TQFP Connections
Interface
2.1.1 Address (A2-A0) Address input signals Interface. These inputs significant only Register accesses, accesses.
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9710 Data Compression Processor 2.1.2 Data (D31-D0) Bi-directional data Interface. This configured either 16-bits 32-bits with WIDTH Configuration Register. After hardware reset, will configured 16-bit mode. While configured 16-bit mode, upper bits (D31-D16) will remain tristated. necessary unused data signals high low. They terminated internally with high impedance pull-ups. 2.1.3 Command Strobe (CS#) Active input. While this signal active, register access will take place. data direction determined signal. 2.1.4 Read/Write Command (R/W) This input signal determines direction data during register transfer. polarity this signal selected state BMODE (Bus Mode) signals. Figure proper polarity. 2.1.5 Interrupt (IRQ#) Active output. This signal will become active when event occurs that enabled Configuration register. Interrupt Enable register description further information about when this signal asserted deasserted. This signal open drain output requiring external pull-up resistor 2.1.6 Data Strobe (DS#) This input used additional control information timing. operation this signal selected setting BMODE (Bus Mode) signals shown Figure Timing section timing details. While asynchronous modes (BMODE 01), signal must asserted while signal asserted accesses, must asserted while SDACK# DDACK# signals asserted accesses. Timing section timing details. When using Motorola 68302, signal tied signal 68302. While synchronous mode (BMODE 10), signal asserted shown timing section. Otherwise, DS#signal must tied high. While 68360 mode (BMODE 11), signal must tied high low. 2.1.7 Mode (BMODE1-0) These pins select timing mode interface. Figure summary modes. Refer BCLK description brief description modes. Refer Timing section timing details. These pins must tied high throughout entire operation 9710.
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9710 Data Compression Processor
BMODE1-0
type Asynchronous Asynchronous (BCLK=PCLK/2) Synchronous Motorola 68360
polarity
R/W# R/W#
used Timing section Timing section high high
R#/W R/W#
Figure Modes usage
Interface
2.2.1
Source FIFO Request (SDREQ#)
Active output. This signal will become active when Source FIFO ready accept transfer. Source FIFO Data Flow section more information. This signal will become inactive when Source FIFO becomes full. 2.2.2
Source FIFO Acknowledge (SDACK#)
Active input. While this signal active, write operation will take place Source FIFO. 2.2.3
Source FIFO Terminal Count (STC#)
Active output. This signal either open drain totem pole output, depending setting DRIVE configuration register. open drain after reset. This signal will become active just before during last transfer Source FIFO current command. further Source activity will next command Command pipeline. 2.2.4
Dest FIFO Request (DDREQ#)
Active output. This signal will become active when Dest FIFO ready accept transfer. Dest FIFO Data Flow section more information. This signal will become inactive when Dest FIFO becomes empty. 2.2.5
Dest FIFO Acknowledge (DDACK#)
Active input. While this signal active, read operation will take place from Dest FIFO. 2.2.6
Dest FIFO Terminal Count (DTC#)
Active output. This signal either open drain totem pole output, depending setting DRIVE configuration register. open drain after reset.
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9710 Data Compression Processor This signal will become active just before during last transfer from Dest FIFO current command. further Dest activity will from next command Command pipeline.
Compression Interface
2.3.1 Compression Address (CADDR19-CADDR0) These output signals select address Compression accessed. Either SRAM DRAM used Configuration register. SRAM used, these address signals tied directly address Compression RAM. DRAM used, CADDR11-CADDR0 attached multiplexed address Compression RAM. CADDR12 becomes RAS# signal. CADDR13 becomes LCAS# signal. CADDR14 becomes UCAS# signal. CADDR15 becomes signal. CADDR16 becomes signal. 2.3.2 Compression Data (CDATA15-CDATA0) This 16-bit bi-directional data Compression used perform compression decompression functions. 16-bit compression must used. 2.3.3 Compression Write Enable (WE#) Active output. SRAM used, this signal will become active during each write access Compression RAM. DRAM used, this signal must left unconnected. CADDR15 signal used DRAM WE#. 2.3.4 Compression Output Enable (OE#) Active output. SRAM used, this signal will become active during each read access Compression RAM. DRAM used, this signal must left unconnected. CADDR16 signal used DRAM OE#. 2.3.5 Upper Byte Enable (UB#) Active output. This signal will become active during each access upper byte Compression SRAM used. This signal used DRAM. must left unconnected. 2.3.6 Lower Byte Enable (LB#) Active output. This signal will become active during each access lower byte Compression SRAM used. This signal used DRAM. should left unconnected.
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9710 Data Compression Processor
Miscellaneous Signals
2.4.1 Reset (RESET#) Active input. While this signal active, this chip will immediately stop current activity will into known state. After hardware reset, each Compression History should cleared first use. access chip after RESET#is deasserted until after BCLK PCLK cycles have occurred. 2.4.2 Processing Unit Clock (PCLK) This input drives clock internal logic, including interface logic configured asynchronous (BCLK=PCLK/2) mode operation (see below). clock frequency determines speed Processing Unit. speed Processing Unit directly linear with clock frequency. duty cycle this clock input must least 60/40. 2.4.3 Clock (BCLK) This input drives clock bus, which determines speed bus. duty cycle this clock input must least 60/40. There modes operation. asynchronous mode used when system timing interface relative clock. asynchronous interface uses BCLK generating timing. this case input frequency BCLK must greater than 33MHz, input frequency PCLK must greater than 66MHz. asynchronous (BCLK=PCLK/2) mode uses PCLK signal internally divided rather than BCLK. this case BCLK must tied high low. timing same asynchronous mode timing. synchronous mode used when system timing interface relative clock. this case BCLK used generate interface timing PCLK used generate compression engine timing. 68360 mode used when Motorola 68360 connected 9710. This mode utilizes 68360's CPUCLK signal tied directly 9710's BCLK provides 68360 compatible timing PCLK used generate compression engine timing.
Product Overview
Source FIFO Data Flow
Source FIFO will request data unless there active command there room Source FIFO additional data. After command issued, Source FIFO will request data. request will remain active until Source FIFO becomes full, until command termination conditions listed Command Stack register description occurs. most common command termination condition when Source Counter reaches zero. Source FIFO requests data transfers asserting SDREQ#signal setting SOURCE FIFO READY Status register one.
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9710 Data Compression Processor Although Source FIFO only bytes size, more than bytes could transferred into Source FIFO burst because Processing Unit reading data from Source FIFO same time, making room additional data. Once FIFO becomes full, Source FIFO will stop requesting data. Source FIFO will request data again once number bytes empty space Source FIFO greater than SOURCE FIFO THRESHOLD value FIFO Configuration register. Most command termination conditions affect input side Source FIFO. example, when number bytes entering Source FIFO matches value SOURCE COUNT field Command Stack register, Stop command issued, last byte Source FIFO time termination condition occurs allowed flow through output side Source FIFO (and through Processing Unit) before command actually terminates. Source FIFO will stop requesting data current command when number bytes entering Source FIFO matches value SOURCE COUNT field Command Stack. STC# signal will asserted during last data transfer into source FIFO. Source FIFO accepted number bytes specified SOURCE COUNT field, there pipelined command, then Source Counter input side Source FIFO) will value SOURCE COUNT, data will continue requested Source FIFO. other words, Source FIFO contain data from different commands simultaneously. 9710 will handle this condition automatically. signal will still asserted during last data transfer command, even though request will remain active this case.
Source Handshaking Interface Byte FIFO Source Counter
Data
Command Structure
Registers
Result Structure
Processing Unit
CRAM CRAM Interface
Byte FIFO
Destination
Handshaking
Dest Counter
Figure Internal block diagram
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor When last byte source data given command exits Source FIFO enters Processing Unit indicated Source Counter output side Source FIFO reaching zero), trailing bytes that 32-bit 16-bit) aligned will discarded. first byte data next command will come from next 32-bit 16-bit) aligned value.
Dest FIFO Data Flow
Dest FIFO will request data transfer unless there data available Dest FIFO. After data enters Dest FIFO will begin requesting data transfers once number bytes residing Dest FIFO greater than DEST FIFO THRESHOLD value FIFO Configuration register. request will remain active until Dest FIFO becomes empty. Dest FIFO requests data transfers asserting DDREQ# signal setting DEST FIFO READY Status register one. Although Dest FIFO only bytes size, more than bytes could transferred Dest FIFO burst because Processing Unit writing data Dest FIFO same time, adding additional data. Once Dest FIFO becomes empty, Dest FIFO will stop requesting data transfers. will request data again once number bytes residing Dest FIFO greater than value FIFO Configuration register. After last byte data from command entered Dest FIFO, Dest FIFO will request data transfers, independent FIFO threshold FIFO Configuration register, until FIFO empty. DTC# signal will asserted during transfer last byte Dest FIFO. After last byte data from command entered Dest FIFO, next pipelined command begin transfer data Dest FIFO immediately. other words, Dest FIFO contain data from different commands simultaneously. 9710 will handle this condition automatically. DTC# signal will still asserted during transfer last byte current command, even though request will remain active this case. When last byte data enters Dest FIFO from Processing Unit, data padded with dummy data fill entire 32-bit 16-bit) value. value dummy byte undefined. first byte data from next command will 32-bit 16-bit) aligned.
Command/Result Pipeline
order eliminate latency while issuing commands reading results, command result registers architected into multi-stage pipeline. Commands results pipelined allow issue commands read results without severe timing constraints. pipeline consists three stages. first stage Command Stack. second stage Processing Unit. third stage Result Stack When command written chip, written Command Stack pipeline. Processing Unit available command active), command will transferred Processing Unit. When command trans_ Page DS-0010-01 DATA SHEET
9710 Data Compression Processor ferred Processing Unit, Command Stack ready accept another command. COMMAND READY Status register will one.
Command
Command
Command
Commands
Command Stack
Processing Engine
Result Stack
Results
Figure Command/Result Pipeline Once Processing Unit completed command, result information will transferred Result Stack. RESULT READY Status register will one. When result transferred Result Stack, Processing Unit ready accept another command from Command Stack. After detecting RESULT READY (via interrupt, polling), read result from Result Stack. three stages allow buffering three operations. pipeline allows ample time issue commands read results without slowing down Processing Unit.
Compression
9710 utilizes 16-bit maintain history information each fullduplex channel data. Either SRAM DRAM used this storage. 66MHz PCLK speed, 12ns faster SRAM must used 60ns faster DRAM must used. 9710 only supports DRAM. PCLK speed adjusted accommodate slower speeds. This will affect compression decompression performance. Each full-duplex compression/decompression history requires 16Kbytes storage LZS. When using maximum 2Mbytes SRAM, fullduplex histories maintained. When using maximum 32Mbytes DRAM, 2048 full-duplex histories maintained. Please refer Figure selecting proper DRAM configuration. Suitable DRAMs must support 16-bit data widths byte-write capability with single upper lower byte CAS-.
Overview
Register Description
9710 uses address locations configuration use. 9710 registers accessed either 16-bit 32-bit registers, defined WIDTH Configuration register. Reserved bits must written zeros ignored when read.
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Name Data Command Stack Result Stack Configuration Interrupt Enable Status FIFO Status FIFO Configuration Address
Figure Register list
Data
Data (31-16)
Data (15-0)
This register read written. used transfer data Source FIFO from Dest FIFO. WIDTH Configuration register description data width. configured 32-bit bus, four bytes bits) will transferred each access. configured 16-bit bus, bytes bits) will transferred each access. ENDIAN Configuration register description byte ordering. write operation will transfer four two) bytes Source FIFO (depending data width). read operation will transfer four two) bytes from Dest FIFO. During normal operation, interface should used transfer data Source FIFO from Dest FIFO. Therefore, this register should only used under special conditions, testing. Transfers from Data register only take place under same conditions that transfer take place. This described Source FIFO Data Flow Dest FIFO Data Flow sections. SOURCE FIFO READY DEST FIFO READY bits Status register (instead SDREQ DDREQ pins) determine when valid read write Data register much data written, much data read, command will terminate, DATA ERROR Result Stack Status register will one. This error will produce undefined results data stream, data should ignored, associated history should cleared.
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9710 Data Compression Processor
Write Order
Command Stack
Reserved
Command
Strip
History Source (D17-D16)
Clear Hist Ignore Source Ignore Dest Reserved Check Enable CRC/LCB
Reserved Dest Source (D17-D16) (D17-D16)
Source Dest Align Align
Reserved
Source Count (D15-D0)
Reserved
Dest Count (D15-D0)
This register read written. used specify command executed. addition, several parameters related command here. This register operates stack. Four write operations required properly start command. COMMAND PROGRESS Status register used verify synchronization write operations. four writes must take place unless specified differently command description. command only issued COMMAND READY Status register before first write Command register. Most commands will produce result information when they completed. result information read from Result Stack. Command/Result Pipeline section further details operation Command/Result pipeline. Although normally required, command stack read CPU. This done testing purposes. last command written read after written. four words must written command stack before Command Stack read. COMMAND PROGRESS Status register also used verify synchronization read operations.
Command Termination Conditions
commands (except Reset command) will terminate normally when following conditions occur. "normal termination" means that Results Stack contains valid status from previously executed command, indicated RESULT READY Status register. Reset command does terminate normally, causes immediate termination results generated. Source Counter reaches zero (unless IGNORE SOURCE currently executing command Read CRAM). Result Stack, SOURCE DONE will one. Read CRAM command terminates when Dest counter reaches zero. Stop command issued. currently executing command will terminate when last byte currently Source FIFO time
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Dest (D17-D16)
Padding
9710 Data Compression Processor Stop command issued, enters Processing Unit. command termination, Result Stack contains results currently executing command. Stop command generates results own. Reset command issued. There will Result Stack. Everything stops immediately, data FIFOs will discarded. associated history should reset. attempt made write data full Source FIFO attempt made read data from empty Dest FIFO. Result Stack, DATA ERROR will one. command will terminate when last byte Source FIFO time data error, enters Processing Unit. associated history should reset.
Note: Dest Counter cannot terminate command. Dest Counter decrements below zero during operation command, command will continue process incoming data, additional data will output Dest FIFO. DEST OVERRUN Result Stack will asserted this case.
Commands
COMMAND field specifies command executed. valid values listed Figure other values invalid. Command Compress Decompress Update History Pass-Through Reset Stop Read CRAM Write CRAM Command field
Note: other values command field reserved.
Figure Commands Compress This command will compress block data using Compression History specified HISTORY field. termination, Processing Unit will flush internal data, append Marker compressed data stream. This command will optionally append padding compressed data stream other options this command. Decompress This command will decompress block data using Decompression History specified HISTORY field. Marker found before command terminates, source data between Marker last source byte (except check field, there one) will discarded. Marker present last source byte, Page DS-0010-01 DATA SHEET
9710 Data Compression Processor then data will discarded. there Marker source data, Decompression History become invalid. This command will optionally analyze compressed data stream stripping padding verifying other options this command. Update History This command will pass block uncompressed data from source destination without modifying data way. Decompression History specified HISTORY field will updated with uncompressed source data. Pass-Through This command will pass block data from source destination without modifying data way. Compression Decompression History affected. This command mainly used debugging purposes. Reset This command will cause chip immediately enter known start-up state. This single word command. additional writes Command Stack register will interpreted start next command. effect Reset command identical asserting RESET pin, except that Configuration register will initialized. When this command issued, chip operations will immediately Stop. pipelined commands will discarded. Source Dest FIFOs will cleared. intermediate information still residing chip will lost. Compress operation stopped this manner, Compression History will corrupt must cleared next time used. This command pipelined, will operate immediately. COMAND Status register must zero when this command issued. result data generated this command. access chip after Reset command issued until after BCLK cycles have occurred. Read CRAM This command used read data directly from CRAM (Compression RAM). This normally used debugging purposes CRAM memory testing. CRAM starting address combined HISTORY field SOURCE field. CRAM address bits 24-14 entire HISTORY field. CRAM address bits 13-1 bits 13-1 SOURCE COUNT field. SOURCE COUNT field must zero.
COUNT
PROGRESS
PCLK
DEST COUNT field determines number bytes read. Since HISTORY field does increment, CRAM address bits 24-14 fixed cannot incremented. value SOURCE CNT, DEST COUNT, HISTORY fields must chosen prevent CRAM address bits 24-14 from incrementing. DEST COUNT field must zero. value entire DEST COUNT field must zero. DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Write CRAM This command used write data directly CRAM (Compression RAM). This normally used debugging purposes CRAM memory testing. CRAM starting address combined HISTORY field DEST COUNT field. CRAM address bits 24-14 entire HISTORY field. CRAM address bits 13-1 bits 13-1 DEST COUNT field. DEST COUNT field must zero. SOURCE COUNT field determines number bytes write. Since field does increment, CRAM address bits 24-14 fixed cannot incremented. value SOURCE COUNT, DEST COUNT, HISTORY fields must chosen prevent CRAM address bits 24-14 from incrementing. SOURCE COUNT field must zero. value entire SOURCE COUNT field must zero.
HISTORY
Stop This command will cause currently executing Compress, Decompress, Update History, Pass-Through command terminate soon last byte currently Source FIFO time Stop command issued, enters Processing Unit. normal termination processing will take place. This single word command. additional writes Command Stack register will interpreted start next command. This command will affect command residing pipeline. there command currently operating, then Stop command will ignored. This command useful terminate command IGNORE SOURCE COUNT set. This command pipelined, will operate immediately. result data generated this command (except result data command that being stopped). Typical this command assumes that there data transfers occurring (for example, DMA).
Command Stack Fields
4.6.1 Strip This used enable "Strip mode compression format. Enabling this feature reduce size compressed data stream byte. this Compress operation, last byte compressed data eliminated value this last byte zero. Based format, this last byte always part Marker will zero approximately time. last byte eliminated, will counted Dest Counter. Decompress operation, zero inserted source compressed data stream just before check field, compressed data stream there check field. inserted byte will counted Source Counter.
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9710 Data Compression Processor Strip mode enabled during Decompress operation, 9710 must know exact number source bytes that insert zero correct location data stream. IGNORE SOURCE COUNT Command Stack cannot used, Stop command cannot used. Many data communication standards define this feature option. However, this mode incompatible with ANSI X3.241-1994 compression format standard. STRIP zero, this feature will disabled. 4.6.2 History This field utilized Compress, Decompress, Update History commands. This field specifies history number used. specify history number that supported size Compression RAM. Each full duplex history requires Kbytes Compression (CRAM). Although individual Compression History functionally independent Decompression History, associated memory areas allocated together single Kbyte memory block. History type compression history decompression history compression history decompression history History field value Actual CRAM location
Figure Example CRAM usage 4.6.3 Clear History This utilized Compress command only. this one, compression history specified History field will cleared before compress operation begins. this zero, compression history will cleared. compress operation will history information from previous compress operations which used same history number. Note: This must first compress operation which uses specified History number after hardware reset. nature compression format, unless there data corruption data loss errors, never necessary clear Decompression History. 4.6.4 Ignore Source Count This utilized Compress, Decompress, Update History, PassThrough commands. this one, Source Counter will terminate command when counter reaches zero. Source Counter will wrap from zero 0x3FFFF.
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9710 Data Compression Processor this zero, specified command will terminate when Source Counter reaches zero. either case, Source Counter will initialized value SOURCE COUNT field. Also, command terminate from other conditions listed previously. 4.6.5 Ignore Dest Count This utilized Compress, Decompress, Update History, PassThrough commands. this one, Dest Counter will cause Processing Unit stop producing data when counter reaches zero. Dest Counter will wrap from zero 0x3FFFF. this zero, Processing Unit will stop producing data when Dest Counter reaches zero. Also, dest counter will decrement further. either case, Dest Counter will initialized value DEST field. 4.6.6 Check Enable This utilized only Compress Decompress commands. enables in-line generation verification check field (with optional padding). this zero, there will padding in-line check fields generated verified. CHECK ENABLE does affect calculation CHECK FIELD Result Stack register. Compress command, this one, padding defined PADDING field) check field defined CRC/LCB field) will generated appended compressed destination data stream. check field CRC, byte appended first, followed high byte. Decompress command, this one, data between Marker check field will ignored, check field will verified. check value calculated current block data does match check field embedded data stream check value missing from data stream, CHECK ERROR Result Stack will one. Also, CHECK ERROR Status register will (and associated interrupt generated). 4.6.7 CRC/LCB This utilized Compress, Decompress, Update History, PassThrough commands. selects between check field. This affects value reported Result Stack well value optionally inserted checked data stream. this zero, 8-bit (Longitudinal Check Byte) will used. byte-wise exclusive-OR uncompressed data. initialized FF16 before each compress decompress operation.
COUNT
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9710 Data Compression Processor this one, 16-bit will used. calculated uncompressed data. initialized FFFF16 before each compress decompress operation. polynomial 4.6.8 Padding This field utilized Compress Decompress commands only ENABLE CHECK one. This field determines number bytes inserted removed from data stream between last byte compressed data, selected check field (LCB CRC). PADDING field zero, byte padding will generated stripped. check field will immediately follow last byte compressed data. Compress command, PADDING field one, zero byte (with value zero) will inserted between last byte compressed data check field that check field coincident with word (16-bit) boundary. Compress command, PADDING field zero, one, two, three bytes (with value 0x00) will inserted between last byte compressed data check field that check field coincident with double-word (32-bit) boundary. Decompress command, PADDING field two, bytes between last byte compressed data check field will discarded. this case, 9710 must know exact number source bytes that locate check field. IGNORE SOURCE COUNT Command Stack cannot used, Stop command cannot used. PADDING value reserved. 4.6.9 Source Align This field utilized Compress, Decompress, Update History, PassThrough commands. first byte source data 32-bit 16-bit) aligned, SOURCE ALIGN field used ignore first bytes source data. number bytes ignored this field. ignored bytes counted Source Counter. width configured bits, then SOURCE ALIGN field must zero. Otherwise values three zero valid. 4.6.10 Dest Align This field utilized Compress, Decompress, Update History, PassThrough commands. desired force first byte destination data non-32-bit non-16-bit) alignment, DEST ALIGN field used produce bytes data that will inserted front destination data. value inserted bytes undefined. number bytes inserted this field.
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9710 Data Compression Processor inserted bytes counted Dest Counter. width configured bits, then DEST ALIGN field must zero. Otherwise values three zero valid. 4.6.11 Source Count This field utilized commands except Reset Stop commands. This initial value used Source Counter. Source Counter decremented each source byte processed Processing Unit. Source Count will decrement every byte processed, including bytes specified SOURCE ALIGN field, data, padding, check value enabled). will decrement extra bytes inserted non-word alignment last transfer. 32-bit mode WIDTH Configuration register), bits SOURCE COUNT word Command Stack. 16-bit mode, D17-D16 cannot written word, these bits assumed zero. this case, D17-D16 SOURCE COUNT bits word Command Stack. general, Source Counter bits D17-D16 will logical both D17-D16 bits Command Stack. 4.6.12 Dest Count This field utilized commands except Reset Stop commands. This initial value used Dest Counter. Dest Counter decremented each destination byte produced Processing Unit. Dest Count will decrement every byte processed, including bytes specified DEST ALIGN field, data, padding, check value enabled). will decrement extra bytes inserted non-word alignment last transfer. 32-bit mode WIDTH Configuration register), bits DEST COUNT word Command Stack. 16-bit mode, D17-D16 cannot written word, these bits assumed zero. this case, D17-D16 DEST COUNT bits word Command Stack. general, Dest Counter bits D17-D16 will logical both D17-D16 bits Command Stack.
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9710 Data Compression Processor
Read Order
Result Stack
Source (D17-D16)
Data Error Dest Overrun Check Error Reserved Marker Source Zero Reserved
Reserved
Reserved
Reserved Dest Source (D17-D16) (D17-D16)
Check Value
Reserved
Source Count (D15-D0)
Reserved
Dest Count (D15-D0)
This register only read. used read result completed operation. This register operates stack. Four read operations required properly read result. RESULT PROGRESS Status register used verify synchronization read operations. four reads must take place even some information will used. This register must only read when RESULT READY Status register set, which occurs after currently executing command terminates last data byte enters dest FIFO. Command/Result Pipeline section further details operation Command/Result pipeline. 4.7.1 Data Error This significant commands. This will attempt made write data full Source FIFO attempt made read data from empty Dest FIFO. This error condition will cause automatic execution Stop command. current command will terminate soon Source FIFO becomes empty. Stop command description Command Stack additional information. Also, pipelined commands will cleared. commands written until DATA ERROR status register cleared. This condition reason operation terminated. 4.7.2 Dest Overrun this one, command produced more data than expected. Dest Counter attempted decrement below zero, IGNORE DEST COUNT zero. This condition does terminate command, additional data output Dest FIFO. further source data discarded until command terminates. Dest Counter will remain zero. this zero, then Dest Counter attempt decrement below zero, IGNORE DEST COUNT one. DATA SHEET DS-0010-01 Page
Dest (D17-D16)
9710 Data Compression Processor 4.7.3 Check Error This significant Decompress command only, only CHECK ENABLE Decompress command. CHECK ERROR one, check value calculated current block data match check field embedded data stream, check value missing from data stream (due Source Count reaching zero prematurely, example). this zero, check value matched correctly. 4.7.4 Marker This significant Decompress command only. this one, Processing Unit detected Marker source data stream. This condition reason decompress operation terminated. this zero, Marker detected before operation terminated. 4.7.5 Source Zero This significant Compress, Decompress, Update History, Write CRAM, Pass-Through commands. this one, Source Counter reached zero. This condition reason operation terminated. this zero, Source Counter reach zero before operation terminated, IGNORE SOURCE COUNT one. 4.7.6 Check Value This field significant Compress, Decompress, Update History, Pass-Through commands. This calculated CRC/LCB Command Stack). configured LCB, then only bits significant. other bits unused. configured CRC, then bits significant. This field significant even CHECK ENABLE Command Stack register zero. 4.7.7 Source Count This field significant commands except Reset Stop commands. This final value source counter command termination. source counter decremented each source byte processed Processing Unit. 32-bit mode WIDTH Configuration register), bits D17-D16 Source Counter will present both first third words Result Stack. 16-bit mode, bits D17-D16 will present only first word Result Stack. 4.7.8 Dest Count This field significant commands except Reset Stop commands. This final value Dest counter command termination. Dest counter decremented each destination byte produced Processing Unit. Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
32-bit mode WIDTH Configuration register), bits D17-D16 Dest Counter will present both first fourth words Result Stack. 16-bit mode, bits D17-D16 will present only first word Result Stack.
Configuration
Output Drive
Endian
Width
ChipID
Reserved
DRAM Size
DRAM Refresh Reserved Rate
DRAM
Performance
This register read written. used configure chip options. default value fields this register after hardware reset zero, except PERFORMANCE field which defaults value 4.8.1 DRAM Size This field significant only DRAM used Compression RAM. selects DRAM address configuration. Value Size (16-bit words) 256K 512K Reserved Rows Columns
Figure DRAM size values 4.8.2 DRAM Refresh This field significant only DRAM used Compression RAM. selects frequency DRAM refresh cycles. refresh frequency divisor PCLK frequency, bits this field. Value Divisor 1024 Reserved
Figure Refresh frequency 4.8.3 Drive This determines whether STC# DTC# signals driven with open drain totem-pole drivers.
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor this zero, then outputs open drain drivers. this then outputs totem-pole drivers. default open drain drivers. 4.8.4 Endian This selects byte order data transferred interface, Data register this zero, this chip operates were attached Little Endian processor. Bits 9710 data will enter leave Processing Unit first. this one, this chip operates were attached Endian processor. Bits 31-24 9710 data will enter leave Processing Unit first. 4.8.5 Width This selects data width when performing accessing Data register. this zero, 16-bit assumed. this one, 32-bit assumed. only registers affected setting this are: Data register. Command Stack. SOURCE COUNT DEST COUNT fields. Result Stack. SOURCE COUNT DEST COUNT fields.
4.8.6 ChipID This allows ChipID value read from Status register. When this one, ChipID value read once from Status register. After ChipID value read from Status register, this returns zero. This readable. When this one, returns value until after ChipID value read from Status register. After ChipID value read from Status register this read value zero. 4.8.7 DRAM This selects type used Compression RAM. This must zero SRAM used. This must DRAM used. 9710 compression decompression performance affected setting DRAM memory speed differences. Figure shows difference 9710 performance PCLK input 66MHz under different memories. Compression 12ns SRAM 60ns DRAM Compress (Mbytes/s) Decompress (Mbytes/s)
Figure 9710 performance
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor 4.8.8 Performance This field sets compression performance compression algorithm. general, there trade-off between compression speed compression ratio. fastest setting produces lowest compression ratio. slowest setting produces highest compression ratio. Figure Illustrates effect PERFORMANCE field when compressing text file containing Constitution United States when compression SRAM. Figure illustrates effect PERFORMANCE field when compressing text file containing Constitution United States when compression DRAM. 9710 decompression speed 15Mbytes/s with SRAM 5MBytes/sec with DRAM. Some full-duplex applications require both compression decompression operations performed simultaneously. 9710 performance these types applications calculated, explained "9710/9710 SRAM DRAM Full-Duplex Performance" application note (APP-0026).
Speed (Mbytes/s) Perform ance Field Speed Ratio pression Ratio (x:1)
Figure Effect Compression Performance field with SRAM
Speed (Mbytes/s) Performance Field Compression Ratio (x:1) Speed Ratio
Figure Effect Compression Performance field with DRAM
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor
Interrupt Enable
Reserved
Result Ready Enable Comand Enable FIFO Enable Dest FIFO Enbl Cmnd/Result Overrun Enbl Data Error Enable Dest Overrun enable Check Error Enable
Reserved
This register read written. used configure chip. default value fields this register after reset zero. 4.9.1 Result Ready Interrupt Enable While this one, IRQ# signal will asserted while RESULT READY Status register one. 4.9.2 Command Ready Interrupt Enable While this one, IRQ# signal will asserted while COMMAND READY Status register one. 4.9.3 Source FIFO Ready Interrupt Enable While this one, IRQ# signal will asserted while SOURCE FIFO READY Status register one. 4.9.4 Dest FIFO Ready Interrupt Enable While this one, IRQ# signal will asserted while DEST FIFO READY Status register one. 4.9.5 Command/Result Overrun Interrupt Enable While this one, IRQ# signal will asserted while COMMAND/RESULT OVERRUN Status register one. 4.9.6 Data Error Interrupt Enable While this one, IRQ# signal will asserted while DATA ERROR Status register one. 4.9.7 Dest Overrun Interrupt Enable While this one, IRQ# signal will asserted while DEST OVERRUN Status register one. 4.9.8 Check Error Interrupt Enable While this one, IRQ# signal will asserted while CHECK ERROR Status register one.
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
4.10
Status
Result Ready
Dest Overrun
Command Ready Source FIFO Ready Destination FIFO Ready Cmnd/Result Overrun
Reserved
Reserved
Command Progress Result Progress
Check Error
Data Error
Reserved
This register read written. used monitor status chip. default value bits this register valid values quiescent chip, listed under each description. 4.10.1 Result Ready This when result ready read from Result Stack. This cleared writing this bit. This also cleared reading first word Result Stack. When cleared, this will again until result next command ready read (after reading four words current result). default value this zero. 4.10.2 Command Ready This when Command Stack ready accept command. This cleared writing this bit. This also cleared writing first word Command Stack. When cleared, this will again until chip ready accept another command (after writing four words current command). default value this one. 4.10.3 Source FIFO Ready This when available space Source FIFO exceeds threshold programmed FIFO Configuration register. This will remain until cleared writing this bit. default value this zero. 4.10.4 Dest FIFO Ready This when number bytes Dest FIFO exceeds threshold programmed FIFO Configuration register. This will remain until cleared writing this bit. default value this zero. 4.10.5 Command/Result Overrun This Command Stack written when ready, Result Stack read when ready.
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor This error condition will affect command operation, command successfully pipelined. However, commands written until this status cleared. This cleared writing this bit. default value this zero. 4.10.6 Data Error This Data register written when ready, Data register read when ready. This error condition will cause automatic execution Stop command. current command will terminate soon Source FIFO becomes empty. Stop command description Command Stack additional information. Also, pipelined commands will cleared. commands written until this status cleared. DATA ERROR Result Stack will also when reading Result Stack currently executing operation. This cleared writing this bit. default value this zero. 4.10.7 Dest Overrun This command produced more data than specified DEST COUNT field Command Stack, IGNORE DEST COUNT zero. When Dest Counter attempted decrement below zero, command continued process incoming data, additional data output Dest FIFO. This cause command terminate. Dest Counter will remain zero. This cleared writing this bit. default value this zero. 4.10.8 Check Error This check value calculated current block data does match check field embedded data stream. This cleared writing this bit. default value this zero. 4.10.9 Command Progress This indicates that command currently middle being written read. This becomes after first access Command Stack register. This returns zero after last (fourth) access Command Stack register. default value this zero. 4.10.10 Result Progress This indicates that result currently middle being read. This becomes after first read from Result Stack register. This returns zero after last (fourth) read from Result Stack register. default value this zero. Page DS-0010-01 DATA SHEET
9710 Data Compression Processor 4.10.11 Chip When ChipID (bit Configuration register set, this register returns Chip value 0x00XX. upper bits defined product code lower bits reserved. Setting ChipID allows only read this register. ChipID value read again ChipID Configuration register must again.
4.11
FIFO Status
Reserved
Reserved
Source FIFO
Reserved
Destination FIFO
This read-only register. used determine number bytes residing Source FIFO Dest FIFO. During normal operation, interface should used transfer data Source FIFO from Dest FIFO. Therefore, this register should only used under special conditions (e.g. PIO), testing. While asynchronous modes (BMODE=00 01), value this register latched each access 9710. value read always previously latched value. Therefore, unknown when previous access 9710 took place, user should read value this register twice, only second value. Source FIFO Dest FIFO each bytes size. 4.11.1 Source FIFO This field indicates number bytes available written Source FIFO. example, Source FIFO empty, this field will indicate default value this field 4.11.2 Dest FIFO This field indicates number bytes residing Dest FIFO. example, Dest FIFO empty, this field will indicate zero. default value this field zero.
4.12
FIFO Configuration
Reserved
Reserved
Source FIFO Threshold
Reserved
Dest FIFO Threshold
This register read written. used configure FIFO thresholds which FIFO will begin request data transfer. This threshold used determine when FIFO ready status bits Status register will
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor one. This optionally assert interrupt configured Configuration register. threshold also used determine when Interface logic will begin request block transfers. Product Overview section more information. 4.12.1 Source FIFO Threshold This field sets Source FIFO Threshold. When number bytes available written Source FIFO greater than value this field, SOURCE FIFO READY Status register will SDREQ signal will become active. Source FIFO Data Flow section more information regarding this field. default value this field zero. 4.12.2 Dest FIFO Threshold This field sets Dest FIFO Threshold. When number bytes residing Destination FIFO greater than value this field, DEST FIFO READY Status register will DDREQ signal will become active. Dest FIFO Data Flow section more information regarding this field. default value this field zero.
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
Register Summary
Data
Data (31-16) Data (15-0)
Command Stack
Reserved Command Strip History Source (D17-D16) Source (D17-D16)
Command Progress Result Progress
Clear Hist Ignore Source Ignore Dest Reserved Check Enable CRC/LCB
Reserved Dest Source (D17-D16) (D17-D16)
Source Dest Align Align
Reserved
Source Count (D15-D0)
Reserved
Dest Count (D15-D0)
Result Stack
Data Error Dest Overrun Check Error Reserved Marker Source Zero Result Queue Reserved Reserved Dest (D17-D16)
Reserved
Reserved Dest Source (D17-D16) (D17-D16)
Check Value
Reserved
Source Count (D15-D0)
Reserved
Dest Count (D15-D0)
Configuration
STC-/DTCOutput Drive Endian Width ChipID Reserved DRAM Size DRAM Refresh Reserved Rate DRAM Performance
Interrupt Enable
Reserved Result Ready Enable Comand Enable FIFO Enable Dest FIFO Enbl Cmnd/Result Overrun Enbl Data Error Enable Dest Overrun enable Check Error Enable Reserved
Status
Result Ready Dest Overrun Command Ready Source FIFO Ready Destination FIFO Ready Cmnd/Result Overrun Reserved Check Error Data Error Reserved
FIFO Status
Reserved Reserved Source FIFO Reserved Destination FIFO
FIFO Configuration
Reserved Reserved Source FIFO Threshold Reserved Dest FIFO Threshold
DATA SHEET DS-0010-01 Page
Dest (D17-D16)
Padding
9710 Data Compression Processor
Timing Descriptions
Interface
configured Asynchronous, Synchronous, 68360 timing modes. This configured BMODE pins. following discussions (including timing section), signals DREQ# DACK# used place signals SDREQ#, DDREQ#, SDACK#, DDACK#. Furthermore signal used place signals STC# DTC#. 6.1.1 Asynchronous Modes Interface configured Asynchronous operation, interface driven either externally BCLK input internally half frequency PCLK input pin, depending BMODE settings. typical access ADDR signals must asserted prior assertion signals. ADDR signals must remain stable after trailing edge DS#. read cycle, 9710 will drive data with valid data after later leading edge signal leading edge signal. data will become tri-state after earlier trailing edge trailing edge DS#. write cycle, data must valid before earlier trailing edge trailing edge signals. data must remain valid after earlier trailing edge trailing edge DS#. DS#signal used help shape signal. Internally, these signals logically ORed together. That means that command strobe active (low) only when both these inputs active (low). This useful when using certain CPUs, such Motorola 68302. used, must tied low. 6.1.2 Asynchronous Modes Interface configured Asynchronous operation, interface driven either externally BCLK input internally half frequency PCLK input pin, depending BMODE settings. typical transfer consists DREQ# being asserted 9710, then more assertions DACK# signal system initiate more transfers. minimum transfer cycle time approximately four BCLK cycle. start cycle controlled Controller with assertion DACK# signal. DACK# signal must asserted unless corresponding DREQ$ signal asserted. read cycle, 9710 will drive data with valid data after later leading edge DACK# signal leading edge signal. data will become tri-state after earlier trailing edge DACK# trailing edge DS#. Page DS-0010-01 DATA SHEET
9710 Data Compression Processor write cycle, data must valid before earlier trailing edge DACK# trailing edge signals. data must remain valid after earlier trailing edge DACK# trailing edge DS#. 9710 will deassert DREQ# signal after leading edge DACK# signal last transfer burst. signal indicates last transfer either Source FIFO (STC#) from Dest (DTC#) FIFO current command. 9710 will assert signal after trailing edge DACK# second last transfer. 9710 will deassert signal after trailing edge DACK# last transfer. DS#signal used help shape DACK# signal. Internally, these signals logically ORed together. That means that command strobe active (low) only when both these inputs active (low). This useful when using certain CPUs, such Motorola 68302. used, must tied low. 6.1.3 Synchronous Mode Interface configured Synchronous operation, interface driven BCLK signal. signals relative rising edge BCLK. typical access consists clock cycles T2), with number wait states (Tw) between cycles. cycle with activity identified Synchronous mode supports minimum cycle time clock cycles. cycle identified assertion signal clock. Addr signals must also valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will There number cycles (including zero). During cycle, data will active. Addr signals longer need valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will During data transfer remains active. following clock cycle will either based value signal following cycle. active then this cycle will inactive then this cycle will There number cycles (including zero). During cycle, data will inactive. 6.1.4 Synchronous Mode Interface configured Synchronous operation, interface driven BCLK signal. signals relative rising edge BCLK. DATA SHEET DS-0010-01 Page
9710 Data Compression Processor typical transfer consists clock cycles T2), with number wait states (Tw) between cycles. cycle with activity identified Synchronous mode will support minimum cycle time clock cycles. start cycle controlled Controller with assertion DACK# signal. DREQ# signal must valid previous clock same clock) that DACK# signal asserted. There number clock cycles (including zero) between assertion DREQ# signal assertion DACK# signal. These will clock cycles. cycle identified assertion DACK# signal clock. following clock cycle will either based value DACK# signal following cycle. DACK# active, then this cycle will DACK# inactive, then this cycle will There number cycles (including zero). During cycle, data will active. following clock cycle will either based value DACK# signal following cycle. DACK# active, then this cycle will DACK# inactive, then this cycle will During data transfer remains active. following clock cycle will either based value DACK# signal following cycle. DACK# active then this cycle will DACK# inactive then this cycle will There number cycles (including zero). During cycle, data will inactive. DREQ# signal will deassert during clock following last transfer burst. signal indicates last transfer Source FIFO (STC#) from Dest (DTC# FIFO current command. signal will asserted during clock following cycle last transfer. will remain asserted three clocks, then deasserted. DS#signal used help shape DACK# signal. Internally, these signals combined follows: COMMAND STROBE# (DACK#+DS##). That internally COMMAND STROBE# active when externally DACK# active (low) DS#is inactive (high). This useful when using certain CPUs, such Intel i960 family. this CPU, must connect i960's BLAST# signal signal. used, must tied high. 6.1.5 68360 Mode Interface configured 68360 mode operation, interface driven BCLK signal. Most signals relative falling edge BCLK. typical access consists half-clock phases (three clock cycles total) through with number wait states (Tw) between half
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor clocks (second third clock). 68360 mode supports minimum cycle time three clock cycles. typical cycle 68360 asserts address signals after rising edge after falling edge read cycle 9710 drives valid data after rising edge phase BCLK, will hold data until after deasserts. 68360 latches read data falling edge write cycle 68360 drives data after rising edge will hold data until after deasserts. 9710 latches write data trailing edge CS#. Wait states inserted programming internal cycles memory controller greater than clocks. During wait state, data will active. cycle ends when deasserted half-clock next cycle begins when address asserted rising edge asserted falling edge This usually next clock (BCLK) unless there idle states. Idle states defined when inactive. There number idle clock cycles (including zero). During idle cycle, data will inactive. 6.1.6 68360 Mode Interface configured 68360 mode operation, interface driven BCLK signal. signals relative falling edge BCLK. 68360 mode will support minimum cycle time three clock cycles. typical 68360 IDMA transfer consists same half-clock clock cycles) through cycles. There also number wait states IDMA cycles. start IDMA cycle controlled 68360's IDMA Controller with assertion DACK# signal, after having processed DREQ# signal received from 9710. 68360 asserts DACK# signal falling edge 68360 will hold DACK# active programmed number external wait states. this read cycle, then 9710 will drive valid data after rising edge phase BCLK, will hold data until after DACK# deasserts. this write cycle, then system memory will provide data after rising edge hold data until after CSX# CAS# deasserts. 9710 will latch data trailing edge DACK#. 9710 will deassert DREQ# signal BCLK falling clock edge when DACK# sampled inactive just before last transfer burst. signal indicates last transfer either Source FIFO (STC#) from Dest FIFO (DTC# current command. 9710 will assert signal BCLK falling clock edge when DACK# sampled inactive just prior last transfer burst. will remain asserted until falling edge BCLK that DACK# sampled inactive.
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor 9710 requires single IDMA transfer, then cycle begins with both DREQ# being asserted. IDMA transfer completes normally with DACK# being asserted. DREQ# deasserted falling edge BCLK that DACK# sampled inactive. DS#signal used 68360 mode must tied high.
Electrical Specifications
Supply Voltage (VDD) Input Voltage Input Current Storage Temperature -0.3V +6.0V -0.3V 0.3V ±10mA -40°C +125°C
Caution: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Figure Absolute maximum ratings Supply Voltage Operating Temperature +4.75V +5.25V +70°C
Figure Recommended operating conditions
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
Symbol
Parameter level input voltage Clock Input (CI) High level input voltage Clock Input (CI) Schmitt hysteresis (SI) level input current With pullup (PI) High level input current level output voltage (O2) (O4) (O6) (O8) High level output voltage (O2) (O4) (O6) (O8) High impedance output leakage current
Conditions
5.25V 5.25V 4.75V 4.75V -2mA -4mA -6mA -8mA 5.25V 5.0V 5.0V 5.0V 5.25V
Units
COUT CI/O
Quiescent supply current Input capacitance Output capacitance capacitance Power dissipation
Figure electrical characteristics Symbol Parameter Output load Data Output load CRAM Interface Output load IRQ# Output load pins Output load other pins Supply voltage Ground potential Ambient operating temperature Conditions min., max. +70°C Figure specification definition
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor
Number
Timing Specifications
Description Reset width First 9710 access after Reset tBCLK tBCLK tPCLK
Units
RESET
Figure Reset timing Number Description Oscillator frequency Clock period Clock width high Clock width Clock rise time from Clock fall time from Figure External PCLK clock Number Description Oscillator frequency Clock period Clock width high Clock width Clock rise time from Clock fall time from Figure External BCLK clock 33.3 Units 66.67 Units
CLOCK
Figure External clock
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor Number Description Addr setup before CS#, active Addr hold after CS#, inactive setup before CS#, active CS#, active width CS#, inactive width hold after CS#, inactive Read data valid after CS#, active Read data hold after CS#, inactive Write data setup before CS#, inactive Write data hold after CS#, inactive
tBCLK tBCLK
Units
Addr
CS#, Read Operation
Data Write Operation
Data
Figure Asynchronous Timing
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor
Number
Description active width DACK#, inactive width DREQ# inactive after DACK#, active inactive after DACK#, inactive
DACK# active after DACK#, inactive
tBCLK tBCLK
Read data valid after DACK#, active Read data hold after DACK#, inactive
Write data setup before DACK#, inactive
DACK#
Write data hold after DACK#, inactive asserted after DREQ# asserted
tBCLK
tBCLK tBCLK
Units
DREQ#
DACK#,
Read Operation Data Write Operation Data
Figure Asynchronous Timing
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
Number
Description Addr setup Addr hold setup hold setup hold Read data output valid delay Read data hold Write data setup Write data hold
Access
Units
Access wait state
BCLK
Addr
Read Operation
Data Write Operation
Data
Figure Synchronous Timing
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Number Description output valid delay DREQ# hold DACK# setup DACK# hold setup hold output valid delay totem pole mode output valid delay tri-state mode hold Read data output valid delay Read data hold Write data setup Write data hold
DREQ#
Access wait state
Units
Access
BCLK
DREQ#
DACK#
Read Operation Data Write Operation Data
Note First access minimum chip timing. Second access typical 80960Cx timing. Note DACK- internally gated form internal command strobe defined timing descriptions section, that when DACK- (low) deasserted (high). Data accessed when these signals changes state. second access data accessed clock that asserts when DACK- asserted.
Figure Synchronous Timing
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
Number
Description Addr setup active Addr hold from inactive setup falling edge BCLK hold from falling edge BCLK setup active hold from inactive Read data output valid before falling edge Read data hold after inactive Write data setup inactive Write data hold after inactive
Units
Addr
Read Operation
Data Write Operation
Data
Figure 68360 Timing
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Number Description setup falling edge BCLK DACK# hold from falling edge BCLK Read data output valid before falling edge Read data hold after DACK# inactive Write data setup DACK# inactive Write data hold after DACK# inactive DREQ# output delay after falling edge BCLK DREQ# hold after falling edge BCLK active delay after falling edge BCLK (totem-pole mode active delay after falling edge BCLK (tristate mode hold after falling edge BCLK
DACK#
Units
DREQ#
DACK#
Read Operation Data Write Operation Data
Figure 68360 Timing
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
Number
Description Data valid after Addr/LB/UB valid (access time) Data valid after active Address valid width (cycle time) Data hold after inactive
tPCLK tPCLK15 tPCLK
Units
tPCLK
Addr
Data
Figure Compression SRAM Read Timing Number Description Addr/LB/UB setup valid active width Addr hold after inactive Data setup before inactive Data hold after inactive Addr valid inactive
Addr
tPCLK tPCLK tPCLK tPCLK
Units
Data
Figure Compression SRAM Write Timing
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor Number Description read/write cycle time RAS# pulse width RAS# precharge time CAS# read/write cycle time RAS# hold time from precharge CAS# hold time RAS# CAS# delay CAS# pulse width CAS# hpage precharge time CAS# RAS# precharge CAS# precharge time RAS# col. Address delay time address setup time address hold time Column address setup time Column address hold time Column address Read command setup (read) Read command hold from RAS# (read) Read command hold from CAS# (read) Access time from precharge (read) Read data access time from Read data access time from RAS# Read data access time from col. Address Read data access time from CAS# Read data output hold time Output buffer turn-off from (read) setup CAS# (write) hold from CAS# (write) Write data setup CAS# Write data hold from CAS# Output buffer turn-off from active (not drawn) Pulse Width RAS# hold after CAS#
RAS#
tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
tPCLK
tPCLK
tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK tPCLK
Units
Figure Compression DRAM Read Write Timing
Page DS-0010-01 DATA SHEET
9710 Data Compression Processor
RAS#
UCAS#/LCAS#
Addr Read Operation
Col.
Col.
Data Write Operation
Data
Data
Data
Data
Data
Figure Compression DRAM Read Write Timing Diagram
Number
Description setup hold from
tBCLK tBCLK
Units
Note: other relevant timing referenced above.
RAS#
UCAS#/LCAS#
Figure Compression DRAM Refresh Timing
DATA SHEET DS-0010-01 Page
9710 Data Compression Processor
16.0±0.2 14.0±0.2
14.0±0.2 0.2±0.1 1.4±0.2 0.08
0.127
+0.10 -0.05
0.5±0.2 units millimeters
Figure 100-pin TQFP package
Page DS-0010-01 DATA SHEET
0~5°
15.0±0.2
+0.15 -0.15
1.85
16.0±0.2
9710 Data Compression Processor
CADDR17 CADDR16 CADDR15 CADDR14 CADDR13 CADDR12 CADDR11 CADDR10 CADDR9 CADDR8 CADDR7 CADDR6 CADDR5 CADDR4 CADDR3 CADDR2` CADDR1 CADDR0 CDATA15 CDATA14 CDATA13
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18
CDATA12 CDATA11 CDATA10 CDATA9 CDATA8 CDATA7 CDATA6 CDATA5 CDATA4 CDATA3 CDATA2 CDATA1 CDATA0 BMODE1 BMODE0 DDREQ DDACK CADDR19 SDACK SDREQ
ADDR0 ADDR1 ADDR2 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 CADDR18 PCLK RESET BCLK
Figure 100-pin TQFP pinout
DATA SHEET DS-0010-01 Page
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