2401 Bipolar Features Heterodyne receiver with demodula
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Receiver Circuit
2401
Bipolar
Features
Heterodyne receiver with demodulator Down mixing from receiver band base
band Demodulation generation I/Q-baseband components mixer noise (SSB) Input high intercept point Integrated phase shifter AGC-range On-chip second LO-oscillator with external tuning circuit differential operational amplifiers power consumption highly flexible powerdown capability Wide input frequency range Wide IF-range from P-DSO-28 package P-DSO-28-4 shrink package Temperature range
P-DSO-28
P-DSO-28-4 Applications
Digital mobile cellular systems GSM, DAMPS, Various demodulation schemes, such PSK, FSK, QAM, QPSK, GMSK Space power saving optimizations existing discrete demodulator circuits
Type 2401T 2401T 2401S 2401S
Version
Ordering Code Q67000-A6061 Q67006-A6061 Q67000-A6062 Q67006-A6062
Package P-DSO-28 (SMD) P-DSO-28 (SMD, Tape Reel) P-DSO-28-4 (Shrink, SMD) P-DSO-28-4 (Shrink, SMD, Tape Reel)
Semiconductor Group
01.94
2401
Functional Description 2401 single-chip single-conversion heterodyn PM-receiver with phase shifting circuitry I/Q-phase baseband demodulation chip. also includes second local oscillator, gain controlled second IF-amplifier, differential operational amplifiers baseband filtering purposes power down circuitry. 2401 designed digital mobile telephones according GSM-standard other digital systems.
Configuration (top view)
Semiconductor Group
2401
Definitions Functions Symbol OUTQ OUTQ LO2E LO2B LO2O Function Non-inverting in-phase signal output Non-inverting quadratur signal output Inverting amp. signal output Non-inverting amp. signal output Inverting amp. signal output Non-inverting amp. signal input Inverting quadratur signal output External capacitors oscillator VCO-tuning circuit Ground Inverting input Non-inverting input Gain control input VCO-signal output Inverted output first mixer Non-inverted output first mixer Supply voltage Non-inverted signal input first mixer Inverted signal input first mixer Power-down input Non-inverting input first local oscillator Inverting input first local oscillator Power-down input Inverting in-phase signal output Non-inverting amp. signal input Inverting amp. signal output Non-inverting amp. signal output Inverting amp. signal input
OUTI OUTI
Semiconductor Group
2401
Block Diagram
Semiconductor Group
2401
Circuit Description input signal SI/SI amplified first local oscillator signal LO1/LO1 mixed down intermediate frequency (IF). open collector output mixer generates differential current pins MO/MO which filtered external resonant circuit. resulting voltage drives external SAW-filter. second local oscillator signal generated chip dividers, which generate orthogonal signals quarter VCO-frequency. internal LO-signal additionally divider, whose output signal LO2O RF-signal PLL-synthesizer. filtered IF-signal reenters chip IFI/IFI input, where amplified demodulated final baseband output frequency with each orthogonal signals. resulting in-phase quadrature signals pass through differential output drivers appear SOI/SOI SOQ/SOQ outputs, respectively. amplification IF-signal before second mixer stage performed gain-controlled amplifier, gain being determined voltage gain control input differential operational amplifiers with input signals INI/INI (INQ/INQ) output signals OUTI/OUTI (OUTQ/OUTQ) used active filters. Differential signals symmetrical circuitry used throughout, except signal output. Bias drivers generate internal temperature- supply voltage-compensated reference voltages required various circuit blocks. Switching power down inputs from high (see table) sets circuit from normal operating mode into mode with reduced supply current.
RF-Part
IF-Part
VCO/Divders
Semiconductor Group
2401
Internal Input Output Circuits Semiconductor Group
2401
Electrical Characteristics Absolute Maximum Ratings maximum ratings exceeded under circumstances, even momentarily individually, permanent damage will result.
Parameter Supply voltage Input/output voltage (any except open collector) Open collector output voltage (MO/MO) Differential input voltage (any differential input) Junction temperature Storage temperature Thermal resistance (junction ambient) Symbol min. Limit Values max. P-DSO-28 P-DSO-28-4 Unit Remarks
Tstg
pins have additional internal protection circuitry
Semiconductor Group
2401
Operational Range Within operational range operates described circuit description. AC/DCcharacteristics limits guaranteed.
refer test circuit
Parameter SI/SI input level SI/SI input frequency LO1/LO1 input level LO1/LO1 input frequency Intermediate frequency IFI/IFI input level IFI/IFI input frequency input level input frequency frequency range LO2O output level LO2O output frequency SOI/SOI, SOQ/SOQ output Bandwidth input voltage L-PD1/PD2 voltage H-PD1/PD2 voltage Symbol Limit Values min. max. 1000 1100 mVpp roll with ext. capacitors external Unit Remarks
PLO1 fLO1 PIFI fIFI PLO2 fLO2 fVCO PLO2O fLO2O VPDL VPDH
Note: Power levels referred resistance
Semiconductor Group
2401
AC/DC Characteristics AC/DC-characteristics involve spread values guaranteed within specified supply voltage ambient temperature range. Typical characteristics median production.
4.75 5.25
Parameter Supply current Symbol Limit Values min. typ. 15.5 24.5 max. 18.5 11.5 Unit Test Condition Test Circuit
First Mixer Signal Input SI/SI Input resistance Input inductance Max. input level Input intercept Point Blocking level Input interference level fint Input frequency Noise figure
PIPI Pint
series compr. MO/MO
DSB-noise, SSB-noise, including optimum noise matching
attenuation wanted Signal interference (fint fLO1)
11.5
Output First Mixer MO/MO (open collector) Output resistance
11.2
20.8
parallel
Output capacitance Total output current Power gain from Signal input Intermediate frequency
Semiconductor Group
2401
AC/DC Characteristics (cont'd) Parameter Symbol Limit Values min. typ. max. Unit Test Condition Test Circuit
Input First Mixer Local Oscillator LO1/LO1 Input resistance Input capacitance Input level Input frequency
RLO1 CLO1 PLO1 VLO1 fLO1
mVpp
fLO1
parallel RLO1 diagram
1100
Isolation First Mixer From
MHz; fLO1 MHz; fLO1 MHz; fLO1 MHz; fLO1 MHz; fLO1 MHz; fLO1
ALO1 ALO1
Input IFI/IFI Input resistance Input capacitance Max. input level Input intercept point Input frequency Noise figure
RIFI CIFI PIFI VIFI PIPI
0.35
0.65
mVpp parallel RIFI
compr.
diagram
diagram SSB-noise
Input Second Local Oscillator (VCO external) Input resistance
RLO2
fLO2 fLO2
Semiconductor Group
2401
AC/DC Characteristics (cont'd) Parameter Input capacitance Input level Input frequency Symbol Limit Values min. typ. max. mVpp into Unit Test Condition Test Circuit
CLO2 PLO2 VLO2 fLO2
Voltage Controlled Oscillator (LO2) VCO-frequency Output LO2O Output resistance Output level Output frequency
fVCO
with ext. capacitors
RLO2O VLO2O fLO2O
mVpp mVpp
Output capacitance CLO2O
Signal Outputs SOI/SOI, SOQ/SOQ Output resistance frequency roll output level Diff. output offset voltage Voltage gain from I/Q-output
VSO/SO
diagram between
Output capacitance
diagram
Gain Control Input GC-input voltage GC-input current Gain control factor
dB/V
dGSO/dVGC
diagram
Semiconductor Group
2401
AC/DC Characteristics (cont'd) Parameter Symbol Limit Values min. Power-Down Inputs PD1, L-PD input voltage L-PD input current typ. max. Unit Test Condition Test Circuit
VPDL IPD1L IPD2L
VPD1, VPD1,
H-PD input voltage VPDH H-PD input current
IPDH
Differential Operational Amplifier (open loop) Slew rate Gain Bandwidth Prod. Voltage gain Phase margin Gain margin Common mode Rejection Ratio Offset voltage Output voltage
V/µs degr.
CMRR VOFF VOUT
Semiconductor Group
2401
Balun "NEOSID" 00553110 Balun "NEOSID" 00553100 Transformer "Vogt"1 5171100002 0.008 Tuned resonance
Test Circuit Semiconductor Group
2401
Test Circuit
Test Circuit Semiconductor Group
2401
Test Circuit
Test Circuit
Test Circuit Semiconductor Group
2401
S-parameters tested indicated frequency equivalent parallel series circuit calculated this base. Test Point LO1-input impedance SI-input impedance IFI-input impedance LO2-input impedance MO-output impedance Test Circuit Test Frequency 180,
Semiconductor Group
2401
Test Circuit
wanted input signal from received channel fint unwanted interfering signal within band fint local oscillator signal fIFW wanted signal from received channel fIFi unwanted signal from interfering channel: fIFint fint fIF2in unwanted harmonic signal fIF2in fIF2in fIFint
Semiconductor Group
2401
Application Circuit Semiconductor Group
2401
Diagram First Mixer Gain versus LO-Level PLO1 dBm,
Diagram Gain Control Characteristic Output Level versus input Level PIFI
Diagram Gain Control Characteristic Voltage Gain versus GC-Voltage
Diagram Gain Control Characteristic Max. Input Level PIFI versus GC-Voltage VGC: Compression
Semiconductor Group
2401
Diagram Gain-Control Characteristic Input Intercept Point PIPI versus GC-Voltage
Diagram Frequency Transfer Characteristic Outputs
Semiconductor Group
2401
Diagram Worst-Case Signal Levels without Blocking Level
Semiconductor Group
2401
Diagram Worst-Case Signal Levels with Blocking Level
Semiconductor Group
2401
Package Outlines Plastic-Package, P-DSO-28 (SMD) (Dual-Small-Outlines)
Plastic-Package, P-DSO-28-4 (Shrink) (SMD) (Dual-Small-Outlines)
Sorts Packing Package outlines tubes, trays etc. contained Data Book "Package Information" Surface Mounted Device
Dimensions
Semiconductor Group
GPS05389
GPS05123
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