Seite Infineon Homepage High-Speed ASSPs Bipolar ASICs Please Sel

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Seite Infineon Homepage High-Speed ASSPs Bipolar ASICs Please Sel

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Products High-Speed ASSPs Bipolar ASICs Wirenet Delay
Wirenet Delay
WIND program used prelayout delay calculator. extracts design data calculates wire delays each net. This allows following programs verify design using dynamic input loads additional wire loads. wire delays consist parts:
delay time dynamic input loads, input capacitance (please refer data sheet) delay time wiring load, capacitance resistance metal length
WIND calculates either estimated orthogonal wire delays rising well falling edges writes calculated delays netlist NET.SING. Estimated Wire Delay Calculation WIND takes parameter information dynamic input loads defined library file BBUS calculates delay time dynamic input loads. delay time wiring load WIND calculates estimated value preplacement given. program calculates delays using formulas: TL[nom] Kup/Kdown Fanin) TW[nom] Kup/Kdown
21.06.2000
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where number inputs. Orthogonal Wire Delay Calculation signal connects pins preplaced components WIND will calculate wire delays based orthogonal distances. first step WIND program finds Hamming distances from output each input pin. WIND also calculates estimates) entire length wirenet using lengths orthogonal distances half length surrounding considered signal basis. next step program calculates delays using following formulas: TL[nom] Kup/Kdown (Sum Fanin) 0.042 10E-6 1.43 0.43 Fanin TW[nom] Kup/Kdown 0.042 10E-6 0.71 0.14 Running WIND program executed typing
wind [Options]
With following options [-bbus bbus_file] path name BBUS file default: [-net netlist_file] path name design netlist default: NET.SING [-h[elp]] print this text Before running WIND PREP program must completed successfully.
21.06.2000
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Adding Real Wire Delays Having completed placement routing design system, necessary final logic verification with real propagation delays. final verification, support customer with updated NET.SING file containing final placement real propagation delays each net. IMPORTANT: After installing NET.SING with real delays, NETLISTER executed second time. this happens, your NET.SING will lose information about final placement real wire delays. Simulation with Wire Delays Before running simulator have start program WINE (Wire Delay Extractor). WINE extracts current wire delays from netlist produces output file containing wire delays attached each pin. Depending design development step following wire delays extracted added
estimated wire delays orthogonal wire delays real wire delays
further information about simulation please refer workstation specific chapter this manual.
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1999 2000 Infineon Technologies
21.06.2000

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