GM71C(S)4400C/CL 1,048,576 WORDS 4BIT CMOS DYNAMIC Features

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GM71C(S)4400C/CL 1,048,576 WORDS 4BIT CMOS DYNAMIC Features

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GM71C(S)4400C/CL generation dynamic organized 1,048,576 words bit. GM71C(S)4400C/CL realized higher density, higher performance various functions utilizing advanced CMOS process technology. GM71C(S)4400C/CL offers Fast Page Mode high speed access Mode. Multiplexed address inputs permit GM71C(S)4400C/CL packaged standard 300mil 20(26) plastic standard 300mil 20(26) plastic TSOP package size provides high system densities compatible with widely available automated testing insertion equipment. System oriented features include single power supply 5V+/-10% tolerance, direct interfacing capability with high performance logic families such Schottky TTL.
GM71C(S)4400C/CL
1,048,576 WORDS 4BIT CMOS DYNAMIC
Features
1,048,576 Words Organization Fast Page Mode Capability Single Power Supply (5V+/-10%) Fast Access Time Cycle Time (Unit:
tRAC
GM71C(S)4400C/CL-60 GM71C(S)4400C/CL-70 GM71C(S)4400C/CL-80
tCAC
Configuration (26)
I/O1 I/O2 I/O4 I/O3 I/O1 I/O2
Power Active 605/550/495mW (MAX) Standby 5.5mW (CMOS level MAX) 1.1mW (L-version) Only Refresh, before Refresh, Hidden Refresh Capability inputs outputs Compatible 1024 Refresh Cycles/16ms 1024 Refresh Cycles/128ms (L-version) Battery Back Operation (L-version)
(26) TSOP
I/O4 I/O3
I/O4 I/O3
I/O1 I/O2
NORMAL TYPE
REVERSE TYPE
(Top View)
(Top View)
Semicon
GM71C(S)4400C/CL
Function
Address Inputs Refresh Address Inputs Data Input Data Output Address Strobe Column Address Strobe
A0-A9 A0-A9 I/O1-I/O4
Function
Read/Write Enable Output Enable Power (+5V) Ground
Ordering Information
Type
GM71C(S)4400CJ/CLJ-60 GM71C(S)4400CJ/CLJ-70 GM71C(S)4400CJ/CLJ-80 GM71C(S)4400CT/CLT-60 GM71C(S)4400CT/CLT-70 GM71C(S)4400CT/CLT-80 GM71C(S)4400CR/CLR-60 GM71C(S)4400CR/CLR-70 GM71C(S)4400CR/CLR-80
Access Time
60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
Package
Mil, (26) Plastic Mil, (26) Plastic TSOP (Normal Type) Mil, (26) Plastic TSOP (Reverse Type)
Absolute Maximum Ratings*
Symbol TSTG VIN/VOUT IOUT Parameter
Ambient Temperature under Bias Storage Temperature (Plastic) Voltage Relative Voltage Relative Short Circuit Output Current Power Dissipation
Rating
-1.0 -1.0
Unit
*Note: Operation above Absolute Maximum Ratings adversely affect device reliability.
Recommended Operating Conditions 70C)
Symbol Parameter
Supply Voltage Input High Voltage Input Voltage (I/O Pin) Input Voltage (Others)
-1.0 -2.0
Unit
Semicon
GM71C(S)4400C/CL
Electrical Characteristics (VCC 5V+/-10%, 70C)
Symbol ICC1 Parameter
Output Level Output Level Voltage (IOUT -5mA) Output Level Output Level Voltage (IOUT 4.2mA) Operating Current Average Power Supply Operating Current (RAS, CAS, Address Cycling: min) Standby Current (TTL) Power Supply Standby Current (RAS, CAS= VIH, DOUT High-Z) RAS-Only Refresh Current Average Power Supply Current RAS-Only Refresh Mode (RAS Cycling, VIH, min) Fast Page Mode Current Average Power Supply Current Fast Page Mode (RAS VIL, CAS, Address Cycling: min) Standby Current (CMOS) Power Supply Standby Current (RAS, 0.2V DOUT=High-Z) CAS-before-RAS Refresh Current (tRC min) 60ns 70ns 80ns 60ns 70ns 80ns 60ns 70ns 80ns
Unit Note
60ns 70ns 80ns
ICC2
ICC3
ICC4
ICC5
ICC6
ICC7
Battery Back Current (Standby with Refresh) (tRC=125us, tRAS<=1us, WE=VIH, CAS=VIL, Address DIN=VIH VIL, DOUT=High-Z) Standby Current DOUT Enable Input Leakage Current Input (0V<=VIN<=7V) Output Leakage Current (DOUT Disabled, 0V<=VOUT<=7V)
ICC8
II(L) IO(L)
Note: depends output load condition when device selected. ICC(max) specified output open condition. Address changed once less while VIL. Address changed once less while VIH. L-version. VCC-0.2V<=VIH<=6.5V, 0V<=VIL<=0.2V.
Semicon
GM71C(S)4400C/CL
Parameter
Input Capacitance (Address) Input Capacitance (Clocks) Data Input, Output Capacitance (Data-In, Out)
Capacitance (VCC 5V+/-10%, 25C)
Symbol CI/O
Unit
Note
Note: Capacitance measured with Boonton Meter effective capacitance measuring method. disable DOUT.
Characteristics (VCC 5V+/-10%, 70C, Notes
Test Conditions Input rise fall times: Output load gate Input, output timing reference levels: 0.8V, 2.4V (Including scope jig)
Read, Write, Read-Modify-Write Refresh Cycles (Common Parameters)
Symbol Parameter
Random Read Write Cycle Time Precharge Time Pulse Width Pulse Width Address Set-up Time Address Hold Time Column Address Set-up Time Column Address Hold Time Delay Time Column Address Delay Time Hold Time Hold Time Precharge Time Delay Time Delay Time from Set-up Time from Transition Time (Rise Fall) Refresh Period Refresh Period (L-version) GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
10,000 10,000
tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tODD tDZO tDZC tREF
10,000 10,000
10,000 10,000
Semicon
GM71C(S)4400C/CL
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Read Cycle
Symbol Parameter
Access Time from Access Time from Access Time from Address Access Time from Read Command Setup Time Read Command Hold Time Read Command Hold Time Column Address Lead Time Output Buffer Turn-off Time Output Buffer Turn-off Time from Delay Time Pulse width
Unit
Note
2,3,17
tRAC tCAC tOAC tRCS tRCH tRRH tRAL tOFF1 tOFF2 tCDD tOEP
3,17
Write Cycle
Symbol Parameter
Write Command Setup Time Write Command Hold Time Write Command Pulse Width Write Command Lead Time Write Command Lead Time Data-in Setup Time Data-in Hold Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
tWCS tWCH
tRWL tCWL
Semicon
GM71C(S)4400C/CL
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Read- Modify-Write Cycle
Symbol Parameter
Read-Modify-Write Cycle Time Delay Time Delay Time Column Address Delay Time Hold Time from
Unit
Note
tRWC tRWD tCWD tAWD tOEH
Refresh Cycle
Symbol Parameter
Set-up Time (CAS-before-RAS Refresh Cycle) Hold Time (CAS-before-RAS Refresh Cycle) Precharge Hold Time Precharge Time Normal Mode
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
tCSR tCHR tRPC tCPN
Fast Page Mode Cycle
Symbol Parameter
Fast Page Mode Cycle Time Fast Page Mode Precharge Time Fast Page Mode Pulse Width Access Time from Precharge Hold Time from Precharge Fast Page Mode Read-Modify-Write Cycle Precharge Delay Time Fast Page Mode Read-Modify-Write Cycle Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
100,000
tRASP tACP tRHCP tCPW tPRWC
100,000
100,000
3,13,17
Semicon
GM71C(S)4400C/CL
Test Mode Cycle
Symbol Parameter
Test Mode Setup Time Test Mode Hold Time
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
Counter Test Cycle
Symbol Parameter
Precharge Time Counter Test Cycle
GM71C(S)4400 GM71C(S)4400 GM71C(S)4400 C/CL-60 C/CL-70 C/CL-80
Unit
Note
tCPT
Notes: Measurements assume 5ns. Assumes that tRCD<=tRCD(max) tRAD<=tRAD(max). tRCD tRAD greater than maximum recommended value shown this table, tRAC exceeds value shown. Measured with load circuit equivalent 2TTL loads Assumes that tRCD>=tRCD(max) tRAD<=tRAD(max). Assumes that tRCD<=tRCD(max) tRAD>=tRAD(max). tOFF(max) defines time which output achieves open circuit condition referenced output voltage levels. VIH(min) VIL(max) reference levels measuring timing input signals. Also, transition times measured between VIL. Operation with tRCD(max) limit insures that tRAC(max) met, tRCD(max) specified reference point only; tRCD greater than specified tRCD(max) limit, then access time controlled exclusively tCAC. Operation with tRAD(max) limit insures that tRAC(max) met, tRAD(max) specified reference point only; tRAD greater than specified tRAD(max) limit, then access time controlled exclusively tAA.
Semicon
GM71C(S)4400C/CL
tWCS, tRWD, tCWD tCPW tAWD restrictive operating parameters. They included data sheet electrical characteristics only; tWCS >=tWCS(min), cycle early write cycle data will remain open circuit (high impedance) throughout entire cycle; tRWD>=tRWD(min), tCWD>=tCWD(min), tAWD>=tAWD(min) tCPW>=tCPW(min), cycle readmodify-write data output will contain data read from selected cell; neither above sets conditions satisfied, condition data access time) indeterminate. These parameters referenced leading edge early write cycles leading edge delayed write read modify write cycle. tRASP defines pulse width fast page mode cycles. Access time determined longer tCAC tACP. initial pause 100us required after power followed minimum eight initialization cycles (RAS only refresh cycle before refresh cycle). internal refresh counter used, minimum eight before refresh cycles required. delayed write read-modify-write cycles, must disable output buffer prior applying data device. Test mode operation specified this data sheet 2-bit test function controlled control address bits CA0. This test mode operation performed WE-and-CAS-before-RAS (WCBR) refresh cycle. Refresh during test mode operation will performed normal read cycles WCBR refresh cycles. When state test bits accord each other, condition output data level. order this test mode operation, perform only refresh cycle CAS-before-RAS refresh cycle. test mode read cycle, value tRAC, tAA, tCAC, tOAC tACP delayed specified value. These parameters should specified test mode cycles adding above value specified value this data sheet.
Semicon
GM71C(S)4400C/CL
Unit: Inches (mm)
Package Dimension
(26)
0.025(0.63) 0.039(1.00) 0.305(7.75) 0.340(8.64)
0.260(6.60)
0.275(6.99) 0.008(0.20)
0.295(7.49)
0.330(8.38)
0.661(16.80) 0.669(17.00)
0.085(2.16) 0.103(2.61)
0.128(3.25) 0.148(3.76) 0.050(1.27) 0.015(0.38) 0.021(0. 0.026(0.66) 0.036(0.91)
(26) TSOP
0.308(7.82) 0.292(7.42)
0.012(0.30) 0.028(0.70)
0.009(0.22) 0.667(16.94) 0.690(17.54) 0.041(1.03) 0.048(1.23) 0.012(0.30) 0.020(0.50) 0.050(1.27) 0.001(0.03) 0.009(0.23)
0.371(9.42)
0.355(9.02)

GM71C(S)4400C/CL 1,048,576 WORDS 4BIT CMOS DYNAMIC Features

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