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ASAHI KASEI [AK2358AI Built-in voice filter cordless telepho
Top Searches for this datasheetDepending your printer, need select "Shrink Fit" print dialog ensure that document prints correctly. ASAHI KASEI [AK2358AI Built-in voice filter cordless telephone, MODEM (2400bps), COMPANDOR, scrambler circuit wide operation voltage range (1.9 Built-in COMPANDOR output transient response circuit time constant circuit external component needed COMPANDOR Built-in buffer amplifier ceramic receiver driving. Built-in electronic volume icrophone sensitivity modulator/demodulator sensitivity Receiving level switchable steps (-12 +9dB) Built-in muting function voice transmitting receiving External adjustment limiter levelBuilt-in amplifier transmission reception gain adjustment power CMOS power-down function Built-in 3.58MHz oscillator circuit Scrambler circuit with frequency inversion. inversion frequencies selected. Bypassing scrambler circuit available Built-in frame detection function demodulator Control register MODEM data buffer controlled serial interface external component necessary resulting cost reduction small size. Package: VSOP microphone input Transmission signal output Control data 58MEz frase Receptlnn Receiver Input Recept 0151 E-00 1996 TXHPF +VR1 Compressor TXAFSW Scrambler Limiter ~zl!v TDATA TCLK SCLK D1/O RDF/FD ~a~isj IISK Modulator IISK Demodulator IISKHPF data buffer BUFON DeRXAFSW emphasis Scrambler eiver BUFOP RECSW *:-j \AMp3 Expander RXHPF hJ22.j Operating mode ASAHI KASEI [AK2358AI AK2358A, base-band cordless telephone, built-in voice filters, 2400bps MODEM data communication, frame detection circuit, COMPANDOR noise reduction, scrambler circuits. CMOS process provides power operation. Application VSOP package with feature significant reduction external component provides minimum mounting area. time constant circuit COhlPANDOR output transient response built into LSI. Using 2400bps MODEM data communication realized high data reliability high speed communication same time. This suitable cordless system telephones etc. which requires complicated protocol control. oscillation circuit with 3.58MHz crystal oscillator built other frequency source required MODEM. oscillator also used other DTMF generator etc. scrambler circuit uses simple Inversion method with inversion voice spectrum around carrier frequency. inversion frequencies selected. Built-in electronic volumes provided transmission reception part realize automatic adjustment icrophone sensitivity modulator/demodulator sensitivity external EEPROM icroprocessor. transmission part composed high-pass filter, compressor, pre-emphasis circuit, scrambler, limiter, modulator, splatter filter, electronic volume control, etc. reception part composed band pass filter, de-emphasis circuit, de-scrambler, expander, buffer amplifier, demodulator, frame detection circuit, electronic volume control, etc. Arrangement VSOP AGNDINC TAGNDC TXINC TXINOC LIMLVC MODC Vssc TCLKC TDATA~ DI/Oc RDF/FDc SCLK RAGND RXIN RXINO BUFOP BUFON RXAF RXAFIN EXPOUT XOUT ~DIR 0151 1996 ASAHI KASEI [AK2358AI Block AMP1 TXHPF Compressor Pre-emphasis Scrambler (Tx) Limiter Splatter filter modulator AMP2 RXLPF RXHPF De-emphasis scrambler (Rx) Function operational amplifier voice signal transmission gain adjustment filter eliminate aliasing noise SCF(switched capacitor filter) following stage. external resistor capacitor gain less than 30dB cut-off frequency about 10kHz. circuit eliminate frequency component less than 300Hz from transmission voice signal. circuit compress amplitude transmission voice signal. circuit emphasis high-frequency component transmission voice signal improve modulation signal. circuit inverse transmission voice spectrum regard carrier frequency. Carrier frequency selected from frequencies KEY. PCONT select scrambler pre-emphasis circuit. amplitude-limiting circuit suppress frequency deviation modulation signal. limitation level adjusted applying voltage LIMLV pin. LIMLV open, default limitation level applied. circuit eliminate high frequency component higher than 3kHz from limiter output signal modulator signal. circuit generate 2400bps signal according received digital signal logic from TDATA pin. operational amplifier adjust reception demodulation signal gain filter eliminate aliasing noise following stage. gain less than 30dB cut-off frequency about 10kHz external resister capacitor. circuit eliminate high frequency component higher than 3kHz from limiter output signal modulator signal. circuit eliminate frequency component lower than 300Hz from reception voice signal. circuit de-emphasis emphasized signal pre-emphasis circuit. circuit inverse spectrum scrambled receiving voice signal respect carrier frequency. Carrier frequency selected from candidates KEY. de-scrambler(Rx) de-emphasis circuit selected PCONT. circuit expand signal amplitude compressed compressor. Expander 0151 1996/'12 ASAHI KASEI Block AMP3 [AK2358AI AGND Oscillation circuit Control register data buffer Function operational amplifier used smoothing filter reception output. gain cut-off frequency about 20kHz external resister capacitor. circuit eliminate frequency component lower than 100Hz from reception signal. circuit reproduce 2400bps receiving data clock from received signal RXIN pin. inverting non-inverting buffer amplifier drive ceramic receiver. circuit generate reference voltage internal analog signal. circuit oscillate 3.58 reference clock using external crystal oscillator resistor. volume control input amplitude transmission voice signal. adjustment range -8dB +7dB step. volume control output amplitude. adjustment range -4dB +3.5dB 0.5dB step. volume control input amplitude reception demodulation signal. adjustment range -4dB +3.5dB 0.5dB step. volume control receiving voice amplitude. adjustment range -12dB +9dB step. control register contlols status internal switches internal volumes serial data consists address bits data bits. start power-on-reset circuit works default values control register. (see control register map.) data buffer stores bits receiving data smooth signal interface with CPU. name ACNDIN TAGND TXIN TXINO LIMLV Function Analog ground input pin. Connect capacitor stabilize analog ground. Analog ground transmission system. Connect capacitor stabilize analog ground. Transmission voice input pin. This inverting input AMP1. composes microphone amplifier with ex~ernal resister capacitor. .4i111 output pin. Limitation level adjustment pin. limitation level adjusted applying vollagc' this pin. default limitation level adopted voltage applied. 0151 "E-00 1996 ASAHI KASEI nane [AK2358AI TCLK TDATA DI/O RFD/FD SCLK XOUT EXPOUT RXAFIN RXAF BUFON BUFOP RXINO RXIN RAGND Function Output modulated transmission signal. load impedance larger than 10kQ driven. Negative power supply pin. Clock output data transmission. 2.4kHz clock setting internal register "O". register "l", goes level. transmission data input pin. Data latched synchronizing with TCLK rising edge. Serial data input output pin. signal reception flag output Frame detection signal output pin. This puts types information, depending status internal register FSL. "l", signal reception mode, reaches after bits reception signal have been written data register. "O", frame detection signal output mode, pulse after frame pattern detected. Clock input serial data 1/0. Serial data control pin. Crystal oscillator connection pin. reference clock generated connecting 3.58MHz crystal oscillator parallel resistor between this pin. case external clock operation, connect XOUT apply clock XIN. Crystal oscillator connection pin. Positive power supply pin. Expander output pin. Reception voice input pin. This inverting input AMP3. composes smoothing filter external resistor capacitor. Reception voice output pin. This output AMP3. load impedance more than 10kQ driven. Receiver amplifier output pins. Connect ceramic receiver between these pins. f\MP2 output pin. Demodulated receiving signal input pin. This inverting input AMP2. composes prefilter with external resistor capacitor. \nalog ground reception system. Connecl capacitor stabilize analog ground. 0151 1996:12 ASAHI KASEI VSS=OV; Note Parameter Power supply voltage: (VDD) Input current (except power supply pins) Analog input voltage Digital input voltage Storage temperature Symbol [AK2358AI Maximum Ratings "0.3 Unit VINA -0.3 (VA+)+O.3 V,N~ Tstg -0.3 (VA+)+O. Note voltages with respect pin. Warning: Operation beyond these limits result permanent damage device. Normal operation guaranteed these extremes. VSS=OV; Note Parameter Operation temperature Power supply voltage: (VDD) Analog reference voltage Current consumption Mode Mode Mode Mode Unit Symbol AGND IddO Iddl Idd2 Idd3 l/2VD+ Note voltages with respect pin. 0151-E-00 1996 ASAHI KASEI [AK2358AI f=lkHz, PCONT="l", TC="l", EM="l", VR4=OdB: unless otherwise specified, OdBm=O.775Vrms OdBx=-5dBm AVDD=2V Note system Parameter Standard input level @TXINO Absolute gain TXINO-MOD Note Limiter level JiOD lkHz Note external Adjustment range external Compressor linearity TXINO-MOD Note TXINO=-44dBx TXINO=-50dBx Noise without input TXINO~MOD Note Compressor distortion TXINO+MOD TXINO=-10dBx Transmission @MOD Note signal level 1.2kHz signal output Transmission @MOD Note signal distortion 1.2kHz signal output system Parameter Standard input level @RXINO Absolute gain RXINO-BUFON,BUFOP Note RXINO-BUFON,BUFOP Expander linearity Note RXINO=-25dBx RXINO=-30dBx RXINO-BUFON,BUFOP Noise with input Note Expander distortion RXINO+RXAF RXINO=-5dBx Reception @RXINO signal level 1.2kHz signal output -1.5 -4.5 -2.5 -2.5 -3.5 Unit -17.0 -20.0 -36.5 -4.5 -3.5 -2.5 Unit +1.5 -33.0 -45.0 -30.0 "40. -27.0 -35.0 0151-E-00 1996 ASAHI KASEI Overall characteristics Parameter Absolute gain TXINO~BUFON, BUFOP Note TXINO=-10dBx KEY="O" TXINO~BUFON, BUFOP Note Distortion TXINO=-10dBx KEY="O" Crosstalk @BUFON,BUFOP Note Transmission Reception TC="O" TXINO=OdBx @MOD Crosstalk Note Reception Transmission T.~=?*(j. RXINO=OdBx Filter characteristics Parameter Transmission overall characteristics (See Fig.1) TXINO 100Hz TC=" EM="l" PCONT="l" 300Hz Relative value with gain 5kHz lkHz 3kHz 5kHz Reception overall characteristics (See Fig.2) RXINO EXPOUT 100Hz TC=" EM="l" PCONT="l" 250Hz Relative value with gain 300Hz lkHz 3kHz 5kHz [AK2358AI Unit -56.5 Unit -10.5 13.5 -7.5 -10.5 10.5 Note With external circuit shown application circuit example. Note Relative value with output level time input standard input level (-10dBx) TXINO. Note With C-message filter. Note Relative value with BUFON, BUFOP output level time input standard input level (-10dBx) RXINO. Note With external circuit shown application circuit example. Further, AhlP2 gain should -3.5dB, RXIN should loop connection. Note TC=,T,$$, PCONT="O" Note ~c=~,()*~, PCONT="O" Note standardized unit valid various power supply voltages from 5.5V. voltage OdBx should -5dBm. With other voltage iV], (X2) [dBm]. 0151-E 1996 ASAHI KASEI Filter characteristics IN(dB) [AK2358AI FREQUENCY Fig. Transmission overall characteristics FREQUENCY Fig. Reception overall characteristics ASAHI KASEI [AK2358AI system klodul ator f-lkHz TXAF Pref (AUP1) OS30dB TXINO Cross point -lOdBx H~ddE3+w:i.H Limiter level -ldh "~dB +3.5dB .Scraable O:jdB SdBx(USKs19nsl level) -6.3dBx(referencs level) -23.5dBx -Z6.sdnx system RXINO EXPOUT RXAF `"~PJ:'Ho:~dBH'''4''"r='c:' -b.&t- -44d0x Note) dtlx standardized unit valid various power supply voltages from 5.5V. voltage OdBx should 5dBm. With other voltage [V], OdBx (X/2) [dBml. "'"" 0151-E 1996/'12 ASAHI KASEI [AK2358AI ital Characteristics Parameter High-level input voltage Low-level input voltage Hi~h-level inuut voltage Low-level input voltage V1"'VD+ High-level input current Low-level input current V,,'ov Hizh-level outDut Voltaze I.H'O. lIIIA Low-level outDut voltage ]Svmbol] Unit 70%VD+ 30%VD+ 80!%VDti 20%VD+ (l)(2) (l)(2) 90%VD+ v(-). =0.6mAl Vfi, (l). TDATA. DI/O SCLK, TCLK, RDF, DI/O Characteristics Parameter Master clock frequency modulator timing Falling TCLK Rising TCLK period Rising TXAFSW Falling TDATA time TDATA Hold time TDATA Hold time2 demodulator timing RCLK Period pulse width Serial data input timing Clock pulse width Clock pulse width SDATA time SDATA Hold time time Hold time falling SCLK falling time SCLK;DIR input rising time SCLK;DIR input falling time falling SCLK falling time SCLK rising falling time Svmbol f;lk tvr) 3.579545 208.3 416.7 Unit ,LLS 402.2 416.7 0151-E 199612 [AK2358AI TCLK AFSW Note) Internal registsr Note) rsgister I'DATA Voice signal modulator Voice signal :tb: llJ1 SCLK DI/O ~"""""""""""""""" :tg~ :.-.0. 8DVDD SCLK/DIR input Note) timing rewrite internal registers TXAFSW synchronized with falling edge DIR. o151-f"oo -13- demodulator 1996/12 ASAHI KASEI [AK2358AI Register composition Address Control register Volume register Volume register Control register volume register Reception data register FCLN Data PCONT RECSW TXAF RXAF FRPT MODEM reception data The-reception data register read only register, others write only registers. reception data register address information proceeding Data. bits volume register address "01" "l". they "O", changed test mode, Register Control register Address Data FCLN PCONT (Default) TXAFSW RXAFSW Transmission signal control TXAFSW Transmission output Voice signal Mute signal Reception signal control RXAFSW RECSW RXAF Mute BUFOP/BUFON Mute Mute Scrambler circuit ON/OFF PCONT BvDass (Scrambler OFF) Scrambler works (ON) 0151-E-00 -15- 1996/12 AS.!HI KASEI Frame detection circuit ON/OFF FCLN frame detection function used (OFF). frame detection function used (ON). Note) FCLN automatically changes from when synchronized frame detected. Power-down mode Mode name modeO mode2 mode3 Voice system transmission Reception Oscillator RDF/FD selection signal reception flag (RDF) from RDF/FD pin. frame detection signal (FD) from RDF/FD pin. Control register Address (Default) Data name FRPT Data FRPT Function Carrier inverting frequency 3.107kHz "O": 3.290kHz Frame detector detection pattern "l": 1100010011010110 (base unit) "O": 1001001100110110 (portable unit) Emphasis circuit Passage (ON) "O": Bypass (OFF) COMPANDOR circuit "l": Passage (ON) Volume register Address Data VR23 VR22 \'R21 FRPT VR20 RECSW VR13 VR33 VR42 VR12 VR32 VR41 VR1l VR31 VR40 VR1O VR30 0151-E 1996/12 ASAHI KASEI volume control VR13 VR12 VR1l VRIO Volume gain (dB) [AK2358AI VR2, volume control VR23 VR33 VR22 VR32 VR21 VR31 VR20 VR30 Volume gain (dB) +1.0 +1.5 +2.5 +3.0 +3.5 0151 -EOO 1996i12 ASAHI KASEI volume contro [AK2358AI T242 VR41 VR40 Volume ~ain (dB) Note) reset, gain volumes RECSW changed "o". MODEM reception data Data Data name Function "1":1.2kHz "0":2.4kHz reception data first received data. 0151 E-00 ASAHI KASEI signal transmission flow signal transmission [AK2358AI Modem TDE="O" TXAFSW="l" transmission start transmission data transmitted synchronized TCLK. During transmission Transmission TDE= data transm ssion comp etion TXAFSW= Switching voice signal serial register "TDE" "TXAFSW" "l", that ilSK transmission state provided. 2400Hz clock from TCLK. Synchronizing with rising edge TCLK, AK2358A reads transmission data from TDATA them pin. After transmission necessary number signal bit, "TDE" serial register "l". f\fterwards, before switcl voice signal transmission mode, wait least after "TDE" complete signal final transm ssion. Then TX}\FSW register "o". 0151-E-00 -19" 1996'12 ASAHI KASEI Signal Reception signal reception [AK2358AI "O". that frame detection signal (FD) from RDF/FD pin. Synchronization frame detection? Reception voice mute that signal reception flag (RDF) from RDF/FD pin. Reception data? Reception data read Reading data, change ROF/FD= Waiting next synchronization frame internal register "FCLN" "O", internal nodes RDATA, RCLK fixed After synchronization frame detected, goes during period "T", then RDATA RCLK data following synchronized frame pattern, these After reception data have been entered internal buffer, goes "L". After detect that "L", puts clock bits SCLK, then read With input clock bits SCLK, goes "H". Afterwards, repeating steps necessary data bits read. After necessary data have been read, goes "H", "FCLN" "1". FCLN "l". stored internal buffer. reception data from SDATA pin. serial interface, internal nodes RDAT;\ RCLK "l", then system waits next synchronization frame. 0151"E-00 -20" 1996/12 ASAHI KASEI [AK2358AI Example ZApplication Circuit OAMP transmitting microphone amplifier. gain should less than 30dB. eliminate high frequency noise component over than 100kHz from input signal, order order anti-aliasing filter necessary. following drawing example order anti-aliasing filter, which 30dB gain 10kHz cut-off frequency. TXINO AblPl C1=2200PF TXINR2 C2=33PF Rl=R2=10k R3=330k @Smoothing filter output signal Realize low-pass filter eliminate l12kHz clock signal component from output signal. following example order low-pass filter which 8.7kHz cut-off frequency. 10kQ modulator load resistor provide 3.3dB signal attenuation. R=3.9k cl=4700pF C2=0. RL=lOk (Load resistance MOD) 0AMP2 amplifier receiving gain adjustment anti-aliasing filtering eliminate high frequency noise component over 100kHz. gain should less than 30dB. following example order pass filter, which gain 40kHz cut-off frequency. RXINO C1=560PF C2=27PF AMP2 Rl=lOk R2=9. lkC? R3=100k 0151 1996/12 ASAHI KASEI [AK2358AI OAMP3 smoothing filter eliminate 448kHz clock component from EXPOUT signal Adding provided this amplifier. Also works adjust receiving gain. other pass signal possible. following example order low-pass filter, which gain 19kHz cut-off frequency. IEXPOUT RXAFIN Cl=150pF Rl=R2=56k RXAF AMP3 OAGND stabilizing capacitor stabilize AGND potential, connect capacitors larger than 0.3LLF between TAGND pin, RAGND AVSS pin. Also between AGNDIN AYSS some capacitor necessary reduce ripple power. OVDD stabilizing capacitor reduce noise VDD, connect capacitors between VSS. CI-22,UF (Aluminium Electrolytic Capacitor) C2-O.l,UF (Ceramic Capacitor) 0151 E-00 1996/12 ASAHI KASEI [AK2358AI OCrystal oscillator Crystal resonator resistor capacitors should connected shown Fig.3 on-chip oscillator operation. external clock operation, high(H) level input clock signal amplitude equals greater than 1.5V, low(L) level equals smaller than 0.5V, then connection should shown Fig.4. input clock signal amplitude (peak-to-peak) equals smaller than equals greater than 200mV, then coupling should illustrated Fig.5. Fig.3 Fig.4 O.OIPF l~External clock signal XOUT fig.5 OLimit level adjusting resistor limiting level controled externally applying voltage LIMIV pin. Applied voltage should larger than TAGND, then limiting level shown TAGND*Va(V), while voltage between LIMIV TAGND. Keeping LIMIV open provides default limit level. following example. LIMLV R=50k 0151 1996/12 ASAHI KASEI [AK2358AI Marking HUHIRUNHHHH AK2358A XXXYZ UHNIIHHIIHHH [Contents XXXYZI XXX: Date manufacture Last digit year, week number year digits Production number Assembled place Shape dimensions package VSOP l-t% Note: Dimensions marked include residual (Material] Resin: s[ress type epoxy resin Lead frame: 0151 E-00 0-10. Detail part 1996/'12 IMPORTANT NOTICE These ~roducts andtheir specifications aresubject tochange without notice. Eeforeconsidering anyuseor application, consult Asahi Kasei Microsystems Ltd. (AKMI sales office authorized distributor concerning their current status. assumes liability infringement patent, intellectual property, other right application information contained herein. export these products, devices systems containing therm, require export license other official approval under regulations otthecountry export pertaining customs tariffs, currency exchange, strategic materials. pro&cts neither intended authorized critical components safety, life support, other hazard related device orsystem, assumes responsibility relating such use, except with express written consent Representative Director AKM. used here: hazard related device system designed intended life support maintenance safety applications medicine, aerospace, nuclear energy, orotherfie[ds, which failure function perform reasonably expected result IOSS life significant injury damage person property. critical component whose failure function perform reasonably expected result, whether directly indirectly, loss safety effectiveness device system containing which must therefore meet very high standards performance reliability. responsibility buyer distributor product distributes, disposes otherwise plaCeS product with third party notify that advanCe above content conditions, buyer distributor a!greeS aSSUflle afly responsibility liability hold harrn]ess from CIaiMS ariSiflg frOlll said product absence such notification. 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