Baseband Processing Chipset AD20msp410 SYSTEM ARCHITECTURE A

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Baseband Processing Chipset AD20msp410 SYSTEM ARCHITECTURE A

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FEATURES Passed European Phase Type Approval Complete Baseband Processing Chipset Performs: Speech Coding/Decoding, According 06.XX DTMF Call Progress Tone Generation Equalization with 16-State Viterbi, Soft Decision Channel Coding/Decoding According 05.03 Interface Functions Includes Radio, Auxiliary Voice Interfaces Support Data Services Embedded 16-Bit Microcontroller Layer Software Provided with Chipset Full Phase Protocol Stack Software Available Integrated SIM- Keyboard Interface Ultralow Power Design Operating Voltage Intelligent Power Management Features Hours Standby Time Achievable JTAG-Boundary Scan Full Reference Design Available Three TQFP Devices, Occupying Less than APPLICATIONS GSM/DCS1800 Mobile Radios PCMCIA Cards GENERAL DESCRIPTION
Baseband Processing Chipset AD20msp410
SYSTEM ARCHITECTURE
ALGORITHM SIGNAL PROCESSOR PHYSICAL LAYER PROCESSOR
BASEBAND CONVERTER RADIO SUBSYSTEM
AD20msp410 CHIPSET
512K
128K
DISPLAY
EEPROM
KEYPAD
Analog Devices baseband processing chipset provides competitive solution based mobile radio systems. designed fully integrated, easy use, compatible with wide range product solutions. phones using this chipset accompanying Layer software have passed European full type approval process. chipset consists three highly integrated, sub-micron, power CMOS components that form core baseband signal processing handset. system architecture designed easily integrated into current designs form basis next generation designs. chipset uses operating voltage which coupled with extensive power management features, significantly reduces drain battery power extends handset's talktime standby time.
CHIPSET COMPONENTS Algorithm Signal Processor (ASP)
preprogrammed ROM, user programming required. implements full rate speech transcoding according specifications, including Discontinuous Transmission (DTX) Comfort Noise Insertion (CNI). high performance softdecision Viterbi equalizer also implemented software, embedded ROM.
Physical Layer Processor (PLP)
combines application specific hardware embedded 16-bit microcontroller (Hitachi H8/300H) perform channel coding decoding execute protocol stack user software. embedded processor executes Layer user software. control powerdown functions other chips memory support components achieve maximum power savings.
Baseband Converter (BBC)
application specific variant ADSP-2171 standard from Analog Devices. been optimized meet cost, size power consumption requirements mobile applications. necessary memory specific programs provided on-chip with REV.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties which result from use. license granted implication otherwise under patent patent rights Analog Devices.
performs voiceband baseband analog-todigital digital-to-analog conversions, interfacing digital sections chipset microphone, loudspeaker radio section. addition, contains auxiliary converters burst-ramping, AFC, AGC, battery temperature monitoring. chipset interfaces directly with variety industry standard radio architectures supplies synthesizer timing control signals.
Analog Devices, Inc., 1996 Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 617/329-4700 Fax: 617/326-8703
AD20msp410
Software
required Layer software supplied with chipset. addition, object code license Layers protocol stack available. This exact package Layers 1,2,3 software, coupled with AD20msp410 chipset, today phones that have passed European Final Type Approval.
Architecture Overview
analog voice signal sampled kHz, producing 13-bit linear values corresponding magnitude input. resulting data passed through dedicated serial port.
Speech Encoding (ASP)
standard Handset divided into five functional areas: Analog Digital Baseband Processing Subsystem (Voice Radio) Layer Software (Physical Layer) Protocol Stack Software (Layers Radio Subsystem User Interface Software (MMI) Analog Devices Technology Partnership (TTP) provide cost effective proven method attaining baseband processing subsystem protocol stack software. This data sheet includes functional descriptions baseband processing subsystem Layer software. Technology Partnership provide licenses software reference designs other areas hand-portable terminal. detailed information about individual chipset components, please refer ADSP-2178 (ASP), AD7015 (BBC) ADPLP01 (PLP) data sheets electrical characteristics timing information.
FUNCTIONAL DESCRIPTION
receives voice data stream from encodes data from kb/s kb/s. algorithm used Regular Pulse Excitation, with Long Term Prediction (RPELTP) specified 06-series recommendations. algorithm tested proven bit-exact against test vectors including VAD/DTX functions. After encoding data transferred through parallel port discrete blocks bits intervals.
Channel Coding (PLP)
information received from contains data values filter coefficients that have different levels priority. These subsequently protected different levels within channel coding. encode protection process incorporates block coding convolutional encoding. addition normal speech traffic channels, channel coding function also supports data transmission full rate half rate. After interleave process, necessary, data encrypted using required A5/1 A5/2 encryption algorithm. Data then formatted into bursts, with required timing training sequences sent through dedicated serial port.
GMSK Modulation Conversion (BBC)
Figure functional block diagram baseband processing chipset. chipset viewed functional block that contains number discrete functional units. electrical functional interfaces rest system briefly described this section described detail individual data sheets each component.
BASEBAND
receives data kb/s. on-chip lookup-table modulates spectrally shapes data being sent. pair 10-bit matched differential DACs convert modulated data from digital domain analog domain pass data transmit section radio subsystem.
DOWNLINK
downlink baseband processing functions include following operations:
Analog-to-Digital Conversion (BBC)
receiver signals sampled pair ADCs kHz. resulting digital words transferred through dedicated receive path serial link control.
Equalization (ASP)
VOICE
SPEECH ENCODE
CHANNEL ENCODE
INTERLEAVE
ENCRYPT
VOICE
SPEECH SPEECH DECODE ENCODE
CHANNEL DECODE
DEINTERLEAVE
DECRYPT
EQUALIZER
BASEBAND
CONTROL
Figure Functional Description
UPLINK
equalizer recovers demodulates received signal establishes local timing frequency references mobile unit. equalization algorithm version Maximum Likelihood Sequence Estimation (MLSE) using Viterbi algorithm. confidence bits symbol provide additional information about accuracy each decision channel codec's convolutional decoder. equalizer outputs sequence bits including confidence bits. This data transferred through dedicated parallel port ASP. this point, training sequence trailing bits, contained within burst, discarded.
Channel Decoding (PLP)
uplink baseband processing functions include following operations:
Analog-to-Digital Voice Conversion (BBC)
conventional microphone, connected directly BBC, provides analog input signal ADC. voice function uses sigma-delta converter convert noise shape input signal, achieving Signal-to-Noise Ratio plus Total Harmonic Distortion (SNR+THD) greater than 62.5
A5/1 A5/2 decryption algorithm used, required, recover data that ready deinterleave process. deinterleave process exact inversion interleave process used transmit section. Data pass directly this function, without A5/1 A5/2 decryption, controlled Layer processing. decode function then performs convolutional decoding parity decoding. convolutional decoder uses Viterbi algorithm, with soft REV.
AD20msp410
decision confidence bits supplied equalizer. Once these decoding functions complete, digitized voice data transferred through parallel port. Error control mechanisms used ensure adequate frame indication.
Speech Decoding (ASP)
upconverted applications 1800 applications. dedicated power amplifier increases RF-signal required level. receiver amplifies antenna signal, downconverts intermediate frequency (IF) amplifies there again. After second conversion baseband, components signal into BBC. BBC, provide three auxiliary functions interfacing radio subsystem. These auxiliary functions include AGC, Power Ramping.
Power Ramp Envelope (BBC)
Encoded speech data transferred intervals from blocks bits plus Frame Indicator (BFI). speech decoder supports Comfort Noise Insertion (CNI) function that inserts predefined silence descriptor into decoding process. also implements control talker side-tone short term echo cancellation. resulting data, kb/s, transferred through dedicated serial path.
Voice Digital-to-Analog Conversion
Voice function uses sigma-delta converter convert noise shape signal. 13-bit linear values converted analog domain filtered avoid images. resulting differential signals controlled volume drive directly small earpiece well separate auxiliary output.
AUXILIARY SYSTEM FUNCTIONS
meet spectral time-domain specifications transmitted output signal, burst follow specified power envelope. envelope power profile originates coefficients, down-loaded stored BBC. This envelope profile sent auxiliary DACs with each burst. analog output into power amplifier, controlling power profile absolute level transmitted data.
Automatic Gain Control (AGC)
ASP, perform number auxiliary functions which essential build complete mobile radio. general radio section constitutes three functions transmitter, receiver synthesizer. Figure shows baseband chipset interfaces typical radio architecture. transmitter with baseband analog signals from
mobile radio cope with wide range input signal levels. major part overall gain provided amplifier. incoming signal level analyzed digital gain control signal sent BBC. 10-bit auxiliary generates appropriate analog control signal amplifier. Additionally gain control implemented using output flags ASP.
BASEBAND/AUXILIARY SECTION AD7015
BURST STORE BASEBAND SERIAL INTERFACE GSMSK MODULATOR
DIGITAL FILTER DIGITAL FILTER DIGITAL FILTER
DIGITAL FILTER DIGITAL FILTER
10-BIT AUXILIARY SERIAL INTERFACE 8-BIT 10-BIT VCTCXO
RAMPING
10-BIT
RAMP CONTROL
FLAGS
LOCK SYNTHESIZER CONTROL SIGNALS
PAERROR
VCTCXO
Figure Control Section
REV.
AD20msp410
Automatic Frequency Control (AFC) DATA SERVICES
mobile radio track precisely master clock provided base station. Drift crystal oscillator over time temperature compensated well frequency shifts Doppler effect case moving mobile radio. received signal analyzed digital control signal generated. This signal sent DACs BBC. 10-bit operates coarse 8-bit fine adjust. weighting DACs such, that both DACs yield combined resolution bits. combined analog output signal used control voltage controlled, temperature compensated crystal oscillator (VCTCXO).
Synthesizer Control
Data Services considered essential feature terminals AD20msp410 chipset designed provide flexible cost implementation Data Services supported interface.
HANDSET
APPLICATION LAYER FOREGROUND APPLICATION LAYER BACKGROUND PROTOCOL STACK LAYERS PROTOCOL STACK LAYER AD20msp410 CHIPSET COMMAND INTERPRETER FRAME ROUTER V110' FRAMES
EXTERNAL DATA TERMINAL ADAPTER
DATA TERMINAL ADAPTER
respective parts Layer software control overall timing frequency generation radio subsystem. This includes control signals synthesizers, powerdown control signals power amplifier monitor signals. Detailed information found ADPLP01 data sheet.
Generation Auxiliary Audio Signals
MACHINE INTERFSCE DATA APPLICATION LAYER RELAY (L2R) RADIO LINK PROTOCOL (RLP) RATE ADAPTION
Figure Implementation Data Services
Under control Layer generate variety fixed user-programmable tones. This includes standard DTMF Call Progress tones well user defined tones. tone structure consist four frequency components with individual durations. also generates Talker Sidetone specified recommendations. comparison traditional hardware implementations, this software implementation provides manufacturing flexibility over wide range speaker/microphone sensitivities.
selected system architecture shown Figure provides minimum terminal Bill Materials, lowest possible number interconnection points lowest power consumption when running speech traffic only. However, chipset provides full channel coding decoding Data Services. Parity convolutional encoding interleaving TCH/F9.6, TCH/F4.8 TCH/F2.4 implemented PLP. interface chipset user-configurable, 3-wire serial interface supplying V110 data packets defined 05.03, combined with protocol information control Application Layer. External terminal Data Terminal Adapter (DTA) which runs Data Services Software. Included rate adaptation functions Data Services application. Command Interpreter resident mobile supports serial interface protocol with both traffic data control information communicated. Technology Partnership provide requisite Data Services Software.
SOFTWARE IMPLEMENTATIONS
AUDIO/AUXILIARY SECTION
VOLTAGE REFERENCE LOCK
FILTER VOICEBAND SERIAL INTERFACE
FILTER
AUXILIARY SERIAL INTERFACE
10-BIT TEMP OTHER
full implementation Layer functionality supplied object code module, execution controller, embedded PLP. Functions performed this software include: Initial scan band selection strongest thirty channels required 03.22 05.08 Mobile oscillator adjustment, timing synchronization BCCH decoding from serving cell (camping-on) Base station frequency timing measurements BSIC extraction from neighbor cells under control Layer Frequency hopping according 05.02 Full implementation discontinuous reception (DRX) transmission (DTX) Reporting received level signal quality
Figure Audio-/Auxiliary Section AD7015
Figure shows audio section auxiliary BBC. Input signals come from either directly connected microphone from remote microphone kit. Input gain output signal directly connected small earpiece and, further amplification, external car-kit. output-PGAs programmed
REV.
AD20msp410
Full engineering test mode support Support phase phase handover modes Interface driver Message interfacing Layer (Radio Resources Manager) Layer (data link layer, both signaling data) External functions AGC, synthesizer setting called Layer These allow user configure system wide range radio architectures including reference radio. higher layers protocol stack also reside this embedded processor. Phase compliant, Layer protocol stack available from Technology Partnership.
POWER DISSIPATION CONSIDERATIONS Analog Voice Interface
analog voice interface specified AD7015 data sheet. Several design examples given single-ended differential inputs outputs. voltage reference biasing microphone signal provided BBC. analog output capable driving earpiece directly with impedance optional separate external microphone power amplifier, auxiliary inputs/outputs provided.
Radio Interface
mobile applications, minimizing power consumption devices critical achieving longer standby talk times. handset baseband subsystem dominates current consumption phone standby. design ASP, includes extensive features reduce current consumption give standby times hours. three devices were specifically designed operate from facilitating three four cell NiCad/NiMH single-cell batteries. incorporates intelligent power management, permitting automatic control power consumption peripheral circuitry. Data processing modules switched only when they process data, otherwise they powered down. Additional control signals provided that enable Layer software control external subsystems, such ASP, BBC, radio memory components, that their power intelligently switched PLP. Within different powerdown modes range from simple "wait interrupt" state complete hardware powerdown, with only leakage currents dissipating power. BBC, powerdown functions split separately between receive, transmit auxiliary circuits. This provides optimal analog power performance when operating different modes.
INTERFACES
analog interface between radio subsystem consists differential inputs outputs parts signal three analog control signals AFC, transmit ramp envelope. Details these signals specified AD7015 data sheet. digital interface between radio subsystem consists serial port communicating with synthesizers several control signals specified detail ADPLP01 data sheet.
Digital Card Interface
designed interface directly SIM. However interface logic necessary connect chipset SIM.
Digital Interface Keypad
Keypad interface logic keys provided PLP. This interface provides keyboard scan Rows columns. Additionally extra provided power switch.
Digital Interface Memory Display
External well display controller interfaces directly 21-bit address 16-bit data PLP.
Interface FLASH Memory
large FLASH memory contain programs embedded Control Processor PLP. This includes complete protocol software well User Interface Software. size Mbit Mbit suggested accommodate Protocol software plus typical size User Interface Software. Enhanced features, requiring larger memories supported easily large address space embedded Control Processor. facilitate production programming field upgrades FLASH memories, provides embedded code download software into FLASH memory standard serial port.
Interface SRAM
Figure shows chipset's eight interfaces, which have considered design complete mobile radio. Some these interfaces have meet specifications, others will design specific. Analog Voice Interface Radio Interface Digital Card Interface Digital Interface Keypad Digital Interface from Memory Display Digital Interface from EEPROM Digital Audio Interface (DAI) Digital Interface Data Services
Beside FLASH memory, Control Processor additionally supports static store user defined variables, typically those used Protocol Stack Application Layer. Standard SRAMs interface directly address data PLP.
Interface Display Controller
This interface achieved through address data buses associated read write strobes, well specific enable signal. integrated wait state generator helps interface wide range display controllers. pins with outputs control intensity separate backlights display keypad.
REV.
AD20msp410
Digital Audio Interface (DAI) Table List Components
required specifications, digital audio interface provided allow certain tests audio section during type approval. This interface provided serial between additional control signals from PLP. fully functional "DAI Box" needed process obtained from Analog Devices upon request.
Digital Interface Data Services
Quantity
Description ASP1 PLP1 BBC1 FLASH-PROM2 SRAM EEPROM3 Display Driver
Specification ADSP-2178 ADPLP01 AD7015 256K 128K Design Specific
conventional serial port combined with proprietary protocol used interface external Data Terminal Adapter.
Digital Interface from EEPROM
provides separate pins interface directly external EEPROM serial port. This EEPROM typically used storage calibration user variable parameters like handset identifier (IMEI), language, keypad lock radio calibration parameters. typical size EEPROM bits, this depends individual design handset.
Baseband Processing Parts List
NOTES These components comprise AD20msp410 chipset. size Mbits recommended allow storage Layer programs well typical user interface (MMI). Larger memory used support enhanced user interfaces. omitted parameters stored FLASH memory.
Table lists major hardware components necessary complete baseband processing subsystem. example Bill Material available from Analog Devices. full reference design available through Analog Devices/The Technology Partnership.
BUFFER
CARD
INTERFACE
13MHz VCTCXO
INTERFACE
(AFC)
SERIAL PORT
FLASH MEMORY
CONTROL
VOICEBAND ANALOG
ADDRESS DATA SPORT
VOICEBAND SERIAL PORT (AGC) POWER AMPLIFIER
SRAM
PSRAM CONTROL
INTERFACE
ADDRESS DATA SPORT
DISPLAY CONTROLLER
BASEBAND SERIAL PORT (AGC)
RADIO
AMPLIFIER MODULATOR DEMODULATOR
DISPLAY CONTROL BACKLIGHT CONTROL
CLOCK BASEBAND ANALOG POWER SUBSYSTEM
KEYPAD
KEYPAD INTERFACE EEPROM INTERFACE DATA INTERFACE
POWER CONTROL SYNTHESIZER RADIO CONTROL
KEYPAD DATA INTERFACE
SYNTHESIZER RADIO CONTROL
Figure System Interfaces
REV.
AD20msp410
Mechanical Considerations ORDERING GUIDE
chipset been specifically designed meet only cost power consumption requirements also attention paid physical dimensions. State-of-the-art package technology used achieve smallest possible geometries. Table list main packaging dimensions consult individual data sheets three components further details.
Table Package Dimensions
order parts AD20msp410 chipset, please order each following components. Part Part Number Supply Voltage Range
ADSP-2178-780244 +2.7 AD53/009-9 (Special AD7015) +2.7 ADPLP01 +2.7
Parameter Package Leads Pitch Body Total Height Board
TQFP
TQFP
TQFP 0.65
Unit
evaluation development system ordered this chipset, under part number, AD20msp410-EB03.
three components utilize profile Plastic Quad Flat Packs with lead pitches minimum. Special attention paid possible PCMCIA cards.
REV.
AD20msp410
000000000
REV.
PRINTED U.S.A.

Baseband Processing Chipset AD20msp410 SYSTEM ARCHITECTURE A

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