Interfacing VP5311/VP5511 Video Encoder Application Note AB4518 A

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Interfacing VP5311/VP5511 Video Encoder Application Note AB4518 A

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AB4518
Interfacing VP5311/VP5511 Video Encoder Application Note
AB4518 August 1996
references this document VP5311 equally apply VP5511. Interfacing video encoder complex digital video system requires understanding encoder synchronizes itself rest system. VP5311 simplifies digital analog interface integrating whole composite encoding function single chip. Only small number external components required. digital system interface, however, that several different implementations depending particular system requirements. purpose this application note describe different interfacing options VP5311 well describe genlock closed captioning features.
SYSTEM DATA FLOW SYNCHRONIZATION
typical video system, such cable satellite box, there sources video information. digital consists primary source programming material. other analog sourced screen display-OSD, tuner, external antennae, other analog overlay sources. control synchronization these sources actual television receiver master/slave arrangement required. Analog video arrives asynchronously with respect digital video data, they both need properly synchronized with respect NTSC/PAL timing requirements receiver. master/slave synchronization handled between video encoder MPEG-2 decoder. VP5311 work either master slave mode enable interface MPEG decoders including master slave only mode decoders. driving factor forcing this synchronization timing requirements NTSC television receivers. these receivers, synchronization signals video source material control vertical horizontal timing. There precise number these signals their timing requirements very strict allow compatibility with wide variety sources backwards compatibility with millions televisions purchased over several decades. addition horizontal vertical synchronization, colour televisions require colour burst signal immediately following horizontal sync. This cycle sinusoid specific frequency. receiver needs phase frequency lock this signal order properly extract colour saturation information from video signal source.
SLAVE MODE INTERFACE
video output subsystem shown below Fig.1. this mode, MPEG-2 Video Decoder master while VP5311 slaves this system PIP, OSD, analog video from external source overlaid digital video source. This inserted controlled through switch output VP5311 it's filters. Genlock (the process synchronising colour sub-carrier) only achieved, when video encoder slave mode. this mode MPEG-2 decoder synchronizes digital video analog source then outputs digital video with embedded (Timing Reference Signals) codes. These codes contain blanking information, field identification, active video synchronization which inserted prior beginning active video line data, corresponding CCIR 656. This data stream formats shown Fig.2.
VP5311/VP5511
Fig.1 Video Encoder Slave Interface
byte codes following definitions: during field during field outside field blanking indicates that this field blanking period (Start Active Video) (End Active Video)
protection bits that depend states previous bits. There function allow correction errors detection errors. Fig.2 CCIR Recommendation Data Format 625/50 system
VP5311/VP5511
data consists 1728 8-bit samples line systems while NTSC system 1716 samples line. Each system 1440 active video samples, while more blanking codes give total 1728 samples. video encoder receives this information through 8-bit port. receives data, codes decoded appropriate digital synchronization signals field specific colour subcarrier phase (either 180°) generated. active video consists alternating luma samples separated either sample. seen that there will luma samples line while there will chroma pairs line. chroma pairs will combined with every other luma sample form co-sited sample. CCIR specifies sample clock rate, which means luma data rate 13.5 MHz, while each chroma sample 6.75 rate. Fig. below shows block diagram VP5311:
Fig.3 Block diagram VP5311 VP5311 receives active video, chroma samples filtered interpolated rate where they modulated together colour sub-carrier frequency, luma samples also interpolated MHz. interpolation process both luma chroma paths quite simple. algorithm takes samples, averages them then inserts result between original samples. result interpolation process that output rate doubled from nominal 13.5 MHz, MHz. This helps minimize sinx/x distortion quantizing noise that inherent digital sampling. After interpolation, luma samples combined with synchronization signals coming from video timing generator. luma chroma data then converted analog through three 9bit DACs. DACs used S-Video applications where luma chroma separate. used composite video where luma chroma data numerically summed prior being converted.
MASTER MODE INTERFACE
previous example showed VP5311 operating slave MPEG-2 decoder. Other systems require video encoder operate master control data flow from MPEG-2 decoder's buffer output video monitor. Master Mode, video encoder generates HS/VS/FC outputs, that connect MPEG-2 decoder. When decoder receives Hrizontal Sync control signal, then outputs field after short delay. synchronization between MPEG-2 decoder VP5311 critical television receiver expecting steady stream video along with precise sync signals that embedded This illustrated Fig.4.
VP5311/VP5511
Fig.4 VP5311 Master showing Master Mode Signals
configure VP5311 master mode TRSEL GPSCTL register must `1'. Once this mode, (General Purpose Port) automatically configured produce following outputs: Number Function
start field sync datum, middle equalisation pulses. line sync which used preceding MPEG2 decoder define when output digital video data VP5311.
field count outputs, defined table below: Field
Note that only fields used NTSC, used. fields used. VP5311 asserts signal certain time prior time that television receiver actually requires particular line video. This because there inherent delay through video encoder MPEG decoder. delay through MPEG decoder known pipeline delay will different with each manufacturer's MPEG decoder. accommodate this delay, VP5311 programmed advance timing offset pulse presents MPEG decoder. This illustrated Figure below. programmed value number that represents number 13.5 pixel clocks between time pulse goes active time that decoder puts first sample bus.
VP5311/VP5511
Fig.5 interface with output timing
PROGRAMMING OFFSET
position falling edge relative first data Cb0, programmed HSOFFM-L registers, Figure This done programming number called HSOFF into HSOFFM HSOFFL registers, HSOFFM being most significant bits HSOFFL least significant eight bits. default value 07EH held registers. value program into HSOFF looked table below: NTSC PAL-M: HSOFF Comment normal cks) pulse shortened* normal cks)
PAL-B, HSOFF Comment normal cks) pulse shortened* normal cks)
pulse shortened means that width pulse will less than normal 13.5MHz clock cycles. Where number 13.5MHz clock cycles between falling edge (first data PD7-0), Figure Decreasing HSOFF advances pulse, (numbers decimal). interruption sequence HSOFF values because signal jumping across line boundary previous line offset increased. register default value 7EH, this sets negative edge co-incident NTSC mode. Example offset eight 13.5MHz clock cycles required (pipeline delay 592.6ns) then: HSOFF (76H) NTSC HSOFF (81H)
Example offset 13.5MHz clock cycles required (pipeline delay 22.222us) then: HSOFF (2ACH) NTSC HSOFF (2BDH)
VP5311/VP5511
GENLOCK
When combining video from different sources, Horizontal Sync, Vertical Sync. colour sub-carrier phase need synchronized, shown below:
Fig.6 Synchronization Phase Errors process synchronizing Horizontal Sync (HS), Vertical Sync (VS), colour sub-carrier known Genlock. Synchronizing required that analog video overlay properly positioned video originating from digital video source. this process, genlock circuit needs remove synchronization phase errors. Obtaining colour sub-carrier synchronization required very different reason. Figure above implies that removing phase errors, colour sub-carrier synchronization would occur default. However, colour sub-carrier phase from different sources vary significantly. video receiver aligns colour sub-carrier phase colour burst signal incoming video. colour saturation information would present, receiver were phase locked colour burst digital source, information being displayed from analog source. Thus, colour sub-carrier genlock required maintain saturation accuracy when video information being displayed from source while video receiver synchronized colour sub-carrier another.
VP5311 GENLOCK
VP5311 implements colour sub-carrier genlock. requires external circuit that extracts synchronization signals well providing colour sub-carrier signal, indicated Figure This signal continuous square wave that phase locked colour sub-carrier incoming analog video signal. Horizontal Vertical Sync genlock must performed separate circuit, MPEG-2 decoder being logical location. There several different circuits that perform this HS/VS sync extraction colour sub-carrier generation.
Fig.7 Generic Colour Sub-Carrier extracror
VP5311/VP5511
When genlocking external analog source, digital source needs slave analog signal. analog video arrives asynchronously, MPEG decoder must synchronised extracted analog signals, Fig.7. MPEG decoder will then generate REC656 data stream with embedded synchronisation bytes VP5311 locks these slave mode, effectively locking analog source. subcarrier recovered from analog source converted digital level signal then input REFSQ pin. digital phase locked loop, VP5311, then locks internally generated subcarrier incoming square wave. Once genlock been achieved digital signal overlaid analog vice versa), this useful OSDs, etc. This sync extractor subcarrier circuit variety video decoder products presently available. Several these low-cost high volume, consumer markets; some devices combine into composite sync which need separated externally. colour-subcarrier signal will continuous frequency (particular NSTC system) phase aligned colour sub-carrier source. Since this sinusoidal signal VP5311 expects digital square wave, squaring function needs implemented. comparator with output operation would fulfil this function. VP5311 will then phase lock colour subcarrier generator that external analog source.
CLOSED CAPTIONING
Introduction VP5311 facility generate closed caption data line used NTSC systems USA. Closed captions used means subtitling programs assist people with poor hearing alternative language audio channel. Full screen format text also sent displayed. data displayed needs sent over VP5311 this document describes this software should operate. Closed Caption System This specified EIA-608 Line Data Services NTSC should referred further information. Field used normal caption service while field tends reserved special such second language. bytes data coded line each field, Figure below. data coded data with parity after clock run-in framing code. clock run-in frequency 0.5034965MHz which related nominal line period, 63.55555556 32µs. types data sent, printing non-printing characters. latter byte pairs that transmitted twice successive frames used control purposes, such display position. Printing characters text displayed screen; generally ASCII code used with parity MSB, there some other codes special non-English characters.
Fig.8 Closed Caption format
VP5311/VP5511
Interval Description H-sync clock run-in Clock Clock run-in third start Data Data Horizontal line characters run-in Encoder minimum 10.250µs Encoder nominal 10.500µs 6.5D (12.910µs) 2.0D (3.972µs) 1.0D (1.986µs) 16.0D (31.778µs) 32.0D (63.556) 0.240µs 0.288µs Encoder maximum 10.750µs
Rise fall time data transitions Data high (logic level one) Clock run-in maximum Data (logic level zero) Clock run-in minimum Data differential (high low) Clock run-in differential (max. min)
Notes Horizontal line frequency nominally 15734.26Hz ±0.05Hz. Interval shall adjusted 1/(fH instantaneous line clock run-in signal consists cycles 0.5034965MHz (1/D) sine wave when measured from leading trailing points. sine wave symmetrical about level. negative going midpoints (half amplitude) clock run-in shall coherent with midpoints (half amplitude) Start Data transitions. characters, each consisting data bits parity bit. Bar, measured between amplitude points. clock run-in maximum level shall differ from data high level more than IRE. clock run-in minimum level shall differ from data level more than IRE.
DESCRIPTION VP5311 OPERATION
Five registers used VP5311 closed caption, four store data transmitted (CCREG1 control operation (CCTL). These detailed below: Address Name CCREG1 CCREG2 CCREG3 CCREG4 Description byte encoded onto line field byte encoded onto line field byte encoded onto line field byte encoded onto line field
Note above registers ignored, this parity automatically added VP5311, parity used. CCTL byte encoded onto line field F2EN F1EN
Only bits contained CCTL register, F1EN enables closed captioning onto line field F2EN same field default both bits disabling closed captioning. When byte received into CCREG register encoded next available field, registers then null byte (80H). Null bytes ignored decoder (except non-printing characters, above), gaps transmission characters matter long these filled with null characters. cycles clock run-in parity bits automatically added VP5311 before transmission.
VP5311/VP5511
Software Operation Normally initialisation F1EN from CCTL enable closed caption line field encoding line field required F2EN (both desired). four characters programmed into CCREGs transmission. ensure correct timing data relative field number software should read HANC register, address (shown below). DFI2 DFI1 DFI0 ACTREN
DF2-0 Digital Field Identification, read only. Field Field software should mask bits except bits NTSC mode, field counter runs fields 1-4, this field number should stored. preferable transmit character pair over beginning field line field encoding, beginning field line field encoding. This should ensure that data programmed before relevant encoding field occurs. prevent current data from being overwritten, before next byte pair sent VP5311, software should check that field number incremented from previously read number. Note that non-printing characters used control decoder required sent twice i.e. consecutive frames, this provides some error protection. software interrupted before sending second pair therefore misses next frame necessary repeat control character transmission from start. This really problem with printing characters VP5311 will send `null' character default receives nothing. `null' character ignored decoder. Example caption Coding Information sent shown with corresponding line data bytes) hex, without parity, below: Caption Mode 142c Information Sent data, parity 6672 6f6d 6f73 206f
142c 1420 1420
1140 1140 1429 1429 4845 c4c4c 4f20
2047 5053 6f6e
1240 1240 1429 1429 5650 3533 3220 436c 666f
6564 2043 6170 7469
1540 1540 1429 1429 R14M R14M
7220 4e54 5343
6e80 206c 696e 6520 3231
1440 1440 1429 1429 4861 7665 2061 206e 6963 6520 6461 7921
VP5311/VP5511
Text Mode (same message) 6672 spsp 6f6d Information Sent data, parity 6f6e
142b 142b 4845 c4c4c 4f20
2047 5053 142d 142ad 6f73
142b 142b 5650 3533 3131 2020 436c 666f
6564 2043 6170 7469
142d 142d
206f
142b 142b
7220 4e54 5343
6e80 206c 696e 6520 3231 142d 142d
142b 142b 4861 7665 2061 206e 6963 6520 6461 7921 142d 142d 142d 142d Abrieviations: Erase Non-Displayed Memory Monochrome (Display position where replaced number) Resume Direct Loading Resume Text Show Caption Line NULL SPACE
MASTER MODE TIMINGS
Tsu-fc Thold-hs
15.01ns NTSC/PAL 40.70µs NTSC 41.74µs
Fig.9 VP5311 Field Control Timings referenced pixel clock
VP5311/VP5511
Tsu-hs Thold-hs
14.94ns NTSC/PAL 14.58 NTSC/PAL 4.74 NTSC/PAL 58.81µs NTSC 59.26µs Fig.10 Horizontal Sync Timings
Tsu-vs Thold-vs
15.43ns NTSC/PAL 15.06ns NTSC/PAL Fig.11 Vertical Sync Timings
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Interfacing VP5311/VP5511 Video Encoder Application Note AB4518 A

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