262,144-bit/131,072-bit 2-WIRE SERIAL CMOS EEPROM Power CMOS Tech

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

262,144-bit/131,072-bit 2-WIRE SERIAL CMOS EEPROM Power CMOS Tech

Datasheet Thumbnail

Top Searches for this datasheet

IS24C128-2/3 IS24C256-2/3
262,144-bit/131,072-bit 2-WIRE SERIAL CMOS EEPROM
Power CMOS Technology Standby Current less than (5.5V) Read Current (typical) less than (5.5V) Write Current (typical) less than (5.5V) Voltage Operation IS24C256-2 IS24C128-2: 1.8V 5.5V IS24C256-3 IS24C128-3: 2.5V 5.5V (1.8V), (2.5V) 1MHz (5V) Compatibility Hardware Data Protection Write Protect Sequential Read Feature Filtered Inputs Noise Suppression
ISSI
Self time write cycle with auto clear 2.5V Organization: IS24C256-2 IS24C256-3: 32,768x8 IS24C128-2 IS24C128-3: 16,384x8 64-Byte Page Write Buffer Two-Wire Serial Interface Bi-directional data transfer protocol High Reliability Endurance: 1,000,000 Cycles Data Retention: Years Commercial Industrial temperature ranges 8-pin PDIP, 8-Pin SOIC, 14-pin TSSOP
ADVANCED INFORMATION JULY 2002
PRODUCT OFFERING OVERVIEW
Part IS24C256-2 IS24C256-3 IS24C128-2 IS24C128-3 Voltage 1.8V-5.5V 2.5V-5.5V 1.8V-5.5V 2.5V-5.5V Speed Standby Read Write Temperature
DESCRIPTION
IS24C128-2 1.8V (1.8V-5.5V) 128K-bit (16384 Electrically Erasable PROM, IS24C128-3 2.5V (2.5V5.5V) 128K-bit (16384 Electrically Erasable PROM, IS24C256-2 1.8V (1.8V-5.5V) 256K-bit (32768 Electrically Erasable PROM IS24C256-3 2.5V (2.5V-5.5V) 256K-bit (32768 Electrically Erasable PROM. IS24CXXX (IS24C128-2, IS24C128-3, IS24C256-2 IS24C1256-3) family low-cost voltage 2wire Serial EEPROM. fabricated using ISSI's advanced CMOS EEPROM technology provides power voltage operation. IS24CXXX family features write protection feature, available 8-pin DIP, 8pin SOIC, 14-pin TSSOP packages.
Copyright 2002 Integrated Silicon Solution, Inc. rights reserved. ISSI reserves right make changes this specification products time without notice. ISSI assumes liability arising application information, products services described herein. Customers advised obtain latest version this device specification before relying published information before placing orders products.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
FUNCTIONAL BLOCK DIAGRAM
ISSI
HIGH VOLTAGE GENERATOR, TIMING CONTROL
DECODER
CONTROL LOGIC SLAVE ADDRESS REGISTER COMPARATOR
EEPROM ARRAY
WORD ADDRESS COUNTER
DECODER
Clock DI/O
nMOS
DATA REGISTER
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION Rev. 07/02/02
IS24C128-2/3 IS24C256-2/3
CONFIGURATION 8-Pin SOIC
ISSI
14-pin TSSOP
DESCRIPTIONS
A0-A1 Address Inputs Serial Address/Data Serial Clock Input Write Protect Input Power Supply Ground drain output wire-Ored with other open drain open collector outputs. requires pullup resistor Vcc.
device address inputs that hardwired left connected hardware compatibility with 24C32/64. When pins hardwired, many four 128K/265K devices addressed single system. When pins hardwired, default zero.
This input clock used synchronize data transfer from device.
Write Protect pin. tied entire array becomes Write Protected (Read only). When tied left floating normal read/write operations allowed device.
Bi-directional used transfer addresses data into device. open
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
DEVICE OPERATION
IS24CXXX family features serial communication supports bi-directional 2-wire transmission protocol.
ISSI
2-WIRE
two-wire defined Serial Data line (SDA), Serial Clock Line (SCL). protocol defines device that sends data onto transmitter, receiving devices receiver. controlled MASTER device which generates SCL, controls access generates STOP START conditions. IS24CXXX SLAVE device bus.
128K/256K uses device address bits allow many four devices same bus. These bits must compare their corresponding hardwired input pins. pins internal proprietary circuit that biases them logic condition pins allowed float. last slave address specifies whether Read Write operation performed. When this Read operation selected, when Write operation selected. After MASTER sends START condition SLAVE address byte, IS24CXXX monitors responds with Acknowledge line) when address matches transmitted slave address. IS24CXXX pulls down line during ninth clock cycle, signaling that received eight bits data. IS24CXXX then performs Read Write operation depending state bit.
Protocol:
Data transfer initiated only when busy During data transfer, data line must remain stable whenever clock line high. changes data line while clock line high will interpreted START STOP condition. state data line represents valid data when after START condition, data line stable duration HIGH period clock signal. data line changed during period clock signal. There clock pulse data. Each data transfer initiated with START condition terminated with STOP condition.
WRITE OPERATION Byte Write
Byte Write mode, Master device sends START condition slave address information (with Zero) Slave device. After Slave generates acknowledge, Master sends byte addresses that written into address pointer IS24CXXX. After receiving another acknowledge from Slave, Master device transmits data byte written into address memory location. IS24CXXX acknowledges once more Master generates STOP condition, which time device begins internal programming cycle. While this internal cycle progress, device will respond request from Master device.
START Condition
START condition precedes commands device defined HIGH transition when HIGH. IS24CXXX monitors lines will respond until START condition met.
STOP Condition
STOP condition defined HIGH transition when HIGH. operations must with STOP condition.
Page Write
IS24CXXX capable 64-byte page-WRITE operation. page-WRITE initiated same manner byte write, instead terminating internal write cycle after first data word transferred, master device transmit more bytes. After receipt each data word, IS24CXXX responds immediately with ACKnowledge line, lower order data word address bits internally incremented one, while higher order bits data word address remain constant. master device should transmit more than words, prior issuing STOP condition, address counter will "roll over," previously written data will overwritten. Once bytes received STOP condition been sent Master, internal programming cycle begins. this point, received data written IS24CXXX single write cycle. inputs disabled until completion internal WRITE cycle.
ACKnowledge
After successful data transfer, each receiving device required generate acknowledge. Acknowledging device pulls down line. DEVICE ADDRESSING MASTER begins transmission sending START condition. MASTER then sends address particular slave devices requesting. SLAVE (Fig. address bits. four most significant bits address fixed 1010 IS24CXXX.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION Rev. 07/02/02
IS24C128-2/3 IS24C256-2/3
Acknowledge Polling
disabling inputs used take advantage typical write cycle time. Once stop condition issued indicate host's write operation, IS24CXXX initiates internal write cycle. polling initiated immediately. This involves issuing start condition followed slave address write operation. IS24CXXX still busy with write operation, will returned. IS24CXXX completed write operation, will returned host then proceed with next read write operation.
ISSI
Sequential Read
Sequential Reads initiated either Current Address Read Random Address Read. After IS24CXXX sends initial byte sequence, master device responds with ACKnowledge indicating requires additional data from IS24CXXX. IS24CXXX continues output data each ACKnowledge received. master device terminates sequential READ operation pulling HIGH ACKnowledge) indicating last data word read, followed STOP condition. data output sequential, with data from address followed data from address n+1, etc. address counter increments automatically, allowing entire memory contents serially read during sequential read operation. When memory address boundary (32767 IS24C256-2 IS24C256-3; 16383 IS24C128-2 IS24C128-3) reached, address counter "rolls over" address IS24CXXX-2 continues output data each ACKnowledge received. (Refer Figure Sequential Read Operation Starting with Random Address READ Diagram.)
READ OPERATION
READ operations initiated same manner WRITE operations, except that read/write slave address "1". There three READ operation options: current address read, random address read sequential read.
Current Address Read
IS24CXXX contains internal address counter which maintains address last byte accessed, incremented one. example, previous operation either read write operation addressed address location internal address counter would increment address location n+1. When IS24CXXX receives Device Addressing Byte with READ operation (read/write "1"), will respond ACKnowledge transmit 8-bit data word stored address location n+1. master will acknowledge transfer does generate STOP condition IS24CXXX discontinues transmission. last byte memory, then data from location will transmitted. (Refer Figure Current Address Read Diagram.)
Random Address Read
Selective READ operations allow Master device select random memory location READ operation. Master device first performs 'dummy' write operation sending START condition, slave address word address location wishes read. After IS24CXXX acknowledge word address, Master device resends START condition slave address, this time with one. IS24CXXX then responds with acknowledge sends data requested. master device does send acknowledge will generate STOP condition. (Refer Figure Random Address Read Diagram.)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
Figure Typical System Configuration
ISSI
Master Transmitter/ Receiver
IS24Cxx
Figure Output Acknowledge
from Master
Data Output from Transmitter
Data Output from Receiver
Figure START STOP Conditions
STOP Condition
START Condition
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION Rev. 07/02/02
IS24C128-2/3 IS24C256-2/3
Figure Data Validity Protocol
ISSI
Data Change
Data Stable Data Stable
Figure Slave Address
Figure Byte Write
Device Address
Activity
Word Address Word Address Don't care bits Don't care 24C128
Data
Figure Page Write
Device Address
Activity
Word Address Word Address Don't care bits Don't care 24C128
Data
Data (n+1)
Data (n+63)
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
Figure Current Address Read
Activity
ISSI
Device Address Data
Figure Random Address Read
Activity
Device Address
Word Address
Word Address
Device Address
Data
DUMMY WRITE
Don't care bits Don't care 24C128
Figure Sequential Read
Device Address Activity
Data Byte
Data Byte
Data Byte
Data Byte
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION Rev. 07/02/02
IS24C128-2/3 IS24C256-2/3
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG IOUT Parameter Supply Voltage Voltage Temperature Under Bias Storage Temperature Output Current Value +6.25 -0.5 +150 Unit
ISSI
Notes: Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
OPERATING RANGE (IS24C256-2 IS24C128-2)
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 1.8V 5.5V 1.8V 5.5V
OPERATING RANGE (IS24C256-3 IS24C128-3)
Range Commercial Industrial Ambient Temperature +70°C -40°C +85°C 2.5V 5.5V 2.5V 5.5V
CAPACITANCE(1,2)
Symbol COUT Parameter Input Capacitance Output Capacitance Conditions VOUT Max. Unit
Notes: Tested initially after design process changes that affect these parameters. Test conditions: 25°C, MHz, 5.0V.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
ELECTRICAL CHARACTERISTICS
Symbol VOL1 VOL2 Parameter Output Voltage Output Voltage Input HIGH Voltage Input Voltage Input Leakage Current Output Leakage Current Test Conditions 1.8V, 0.15 2.5V,
ISSI
Min. Max. -1.0 Unit
max.
Notes: reference only tested.
POWER SUPPLY CHARACTERISTICS
Symbol ICC1 ICC2 ISB1 ISB2 Parameter Operating Current Operating Current Standby Current Standby Current Test Conditions READ (Vcc WRITE (Vcc 1.8V, 2.5V 5.5V Min. Max. Unit
ELECTRICAL CHARACTERISTICS
Symbol fSCL tLOW tHIGH tBUF tSU:STA tSU:STO tHD:STA tHD:STO tSU:DAT tHD:DAT Parameter(Test Conditions) Clock Frequency Noise Suppression Time(1) Clock Period Clock HIGH Period Free Time Before Transmission(1) Start Condition Setup Time Stop Condition Setup Time Start Condition Hold Time Stop Condition Hold Time Data Setup Time Data Hold Time Data Hold Time (SCL Data Change) Clock Output (SCL Data Valid) Rise Time(1) Fall Time(1) Write Cycle Time 1.8V Min. Max. 1000 2.5V Min. Max. 5.0V Min. Max. 1000 0.25 0.25 0.25 0.55 Unit
Note: This parameter characterized 100% tested.
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION Rev. 07/02/02
IS24C128-2/3 IS24C256-2/3
WAVEFORMS Figure Timing
ISSI
tHIGH tLOW tSU:STO
tSU:STA tHD:STA tHD:DAT tSU:DAT tBUF
SDAIN
SDAOUT
Figure Write Cycle Timing
WORD
STOP Condition START Condition
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774
ADVANCED INFORMATION 07/02/02 Rev.
IS24C128-2/3 IS24C256-2/3
ORDERING INFORMATION Commercial Range: +70°C
Frequency Voltage Range 1.8V 5.5V 1.8V 5.5V 2.5V 5.5V 2.5V 5.5V Part Number IS24C128-2P IS24C128-2G IS24C128-2Z IS24C256-2P IS24C256-2G IS24C256-2Z IS24C128-3P IS24C128-3G IS24C128-3Z IS24C256-3P IS24C256-3G IS24C256-3Z Package
ISSI
300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP
Industrial Range: -40°C +85°C
Frequency Voltage Range 1.8V 5.5V 1.8V 5.5V 2.5V 5.5V 2.5V 5.5V Part Number IS24C128-2PI IS24C128-2GI IS24C128-2ZI IS24C256-2PI IS24C256-2GI IS24C256-2ZI IS24C128-3PI IS24C128-3GI IS24C128-3ZI IS24C256-3PI IS24C256-3GI IS24C256-3ZI Package 300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP 300-mil Plastic Small Outline (JEDEC STD) TSSOP
ISSI
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, 95054
ADVANCED INFORMATION
Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
Rev. 07/02/02
Integrated Silicon Solution, Inc. www.issi.com 1-800-379-4774

262,144-bit/131,072-bit 2-WIRE SERIAL CMOS EEPROM Power CMOS Tech

Top Searches for this datasheet

Other recent searches