2001 Photobit Technology Corporation. rights reserved. Photobit Techno

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PB-MV40 Megapixel CMOS Active-Pixel Digital Image Sensor
2001 Photobit Technology Corporation. rights reserved. Photobit Technology Corporation wholly owned subsidiary Photobit Corporation. Photobit, wave binary symbol, Behind Every Great Digital Image, TrueBit registered trademarks-and TrueColor, TrueSNAP (Shuttered-Node Active Pixel), Fully Flexible Open Architecture, Serial Host Interface Port, Leading Active Pixel Revolution trademarks-of Photobit Corporation United States other countries. proprietary interface trademark Philips Semiconductors. Other trademarks referenced property their respective owners used identify specific products services. Photobit products protected under U.S. Patents 5,471,515; 5,793,322; 5,841,126; 5,880,691; 5,886,659; 5,887,049; 5,909,026; 5,949,483; 5,952,645; 5,990,506; 5,995,163; 6,005,619; 6,021,172; 6,043,690; 6,049,247; 6,087,970; 6,097,545; 6,101,232; 6,137,100; 6,147,519; 6,166,367; 6,166,768; 6,184,721; 6,191,714; 6,194,696; 6,204,792; 6,211,804; 6,215,428; 6,222,172; 6,222,175; 6,229,134; 6,239,456; 6,255,970. Other U.S. foreign patents pending. Photobit conveys license under patents, copyrights, mask work rights, rights others; does Photobit represent that products shown described herein free from patent infringement from third-party right. Photobit products intended medical radiography life support appliances, devices, systems. Photobit product such applications without written consent Photobit prohibited. Photobit assumes obligation correct errors contained herein advise user this text correction, such made. Photobit assumes liability accuracy correctness engineering software support provided user. Written designed Photobit Technology Corporation, North Robles Avenue, Pasadena, California 91101, USA. Telephone (626) 683-2212. (626) 683-3614. WWW.PHOTOBIT.COM Printed United States America.
PB-MV40 Megapixel CMOS Active-Pixel Digital Image Sensor
September 2001 (Version 1.0)
Contents
Product Specification
Introduction
Introduction
Features. Top-Level Specification Electrical Signal Path Diagram Functional Block Layout External Control Sequence Electronic Shutter 2.4.1 Mode with Exposure Greater than Frame Time 2.4.2 Mode with Exposure Less than Frame Time 2.4.3 Single Shot 2.4.4 Using Pulsed Light. 2.4.5 Partial Scan Examples Descriptions Board Connections Electrical Specification Optical Optical Specification Quantum Efficiency Lens Selection Mechanical Package Views Environmental
Photons-to-bits data stream 2352H 1728V image resolution 7-micron-square active-pixel photodiodes 240+ frames second, progressive-scan Monochrome color Sixteen (16) parallel output ports <700 maximum power dissipation Photobit® TrueColorImage Fidelity On-chip TrueBit® Noise Cancellation On-chip 10-bit analog-to-digital converters 3.3-volt operation
Features
PB-MV40 2352Hx1728V (megapixel) CMOS digital image sensor capable framesper-second (fps) operation. Available monochrome color, on-chip 10-bit analog-to-digital converters (ADCs), which self-calibrating, fully digital input interface. chip's input clock rate fps, compatibility with many off-the-shelf interface components. sensor sixteen (16) 10-bit-wide columnparallel digital output ports. open architecture provides access internal operations. timing pixel-read control integrated on-chip. fps, sensor dissipates <700 operates 3.3V supply. Pixel size microns square digital responsivity about 2,500 bits lux-second.
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Features (continued)
PB-MV40 CMOS image sensor open architecture provide access internal operations. complete camera system built using chip conjunction with following external devices:
FPGA/CPLD/ASIC controller, manage timing signals needed sensor operation. 1-inch lens. Biasing circuits bypass capacitors.
+3.3V
Off-Chip
BIAS
Port Port Port Port Port
D0~D9 D10~D19 D20~D29 D30~D39 D40~D49 D50~D59 D60~D69 D70~D79 D80~D89 D90~D99 D100~D109 D110~D119 D120~D129 D130~D139 D140~D149 D150~D159
Controller
(FPGA, CPLD, ASIC, etc.)
Control Timing
ON-CHIP CONTROL
System Clock
Port Port
Pixel Array
MEMORY
Port Port Port Port Port Port Port Port
Port
System Clock
System Interface
PB-MV40 CMOS Image Sensor
Camera System Using PB-MV40 CMOS Image Sensor
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
Top-Level Specification
Array Format Aspect Ratio Pixel Size Type Sensor Imaging Area Frame Rate Output Data Rate Power Consumption Digital Responsivity Internal Intra-scene Dynamic Range Supply Voltage Operating Temperature Output Color Shutter Package Programmable Controls
2352H 1728V (4,064,256) active-pixel photodiode 16.46mm, 12.10mm, Diagonal: 20.43mm 0-240+ fps, progressive-scan Mbytes/sec. (240 fps) <700 (data dependent) Monochrome: 2,500 bits lux-second reference +3.3 -5°C +60°C 10-bit digital through parallel ports Monochrome color (Bayer RGB) Electronic rolling shutter (ERS) On-chip 10-bit column-parallel 280-pin ceramic Open architecture On-chip: Basic controls
Output multiplexing control calibration
Off-chip: Multiple windowing
Window size location Electronic tilt Frame rate data rate Integration time reference Read/write calibration coefficients
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Electrical
SENSE AMPS MEMORY
ADCs
DIGITAL CONTROL PIXELARRAY
BOTTOM ADCs
Sensor Architecture (not scale)
Signal Path Diagram
Pixel Column Processing Photo Detector
Bias VLN1 Bias VREF2 Calibration VREF1 VREF4
Buffer
Offset (VREF3-VCLAMP3)/10
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
Sample Hold
BIAS VLN2
registers
Functional Block Layout
PIXEL ARRAY Decoder Driver
LogicRST Timing Block
RowSTRT
#2352
Memory Controller
DATA DATA_CLK RE_N WE_N
RowDone Sample Shift 2352 SRAM Output Register Column Decoder
2352 SRAM Register
16x10 Output Ports
Data Shift Read
SRAM Read Control
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
External Control Sequence
PB-MV40 includes on-chip timing control circuitry control most pixel, ADC, output multiplexing operations. However, sensor still requires controller (FPGA, CPLD, ASIC, etc.) guide through full sequence operation. sensor column-parallel architecture that allows array 2,352 analog-to-digital converters chip digitize simultaneously analog data from entire pixel row. following input signals utilized control conversion readout process:
Signal Name ROW_ADDR ROW_STRT_N LD_SHFT_N DATA_READ_EN_N Description Address Start Load shift register Data read enable Input Width 11-bit 1-bit 1-bit 1-bit
PB-MV40 contains pipeline style memory array, which used store data after digitization. This memory also allows data from previous conversion cycle read while conversion taking place. digital readout controlled lowering LD_SHFT_N signal. LD_SHFT_N transfers digitized data from register output register. DATA_READ_EN_N used enable data output from output register. DATA_READ_EN_N kept (enabled) user does want skip output data. output register allows reading digital data from previous performed same time conversion (pipeline mode). This means that total time will only that between when: ROW_STRT_N signal applied ROW_DONE_N returned; LD_SHFT_N applied. pipelined operation means there will always latency start sensor operation. alternative pipeline mode sequential mode which pixel conversion initiated until after output register emptied (and LD_SHFT_N been taken high). ratio line active blanking times adjusted easily match variety display collection formats.
11-bit ROW_ADDR (row address) input selects pixel read each readout cycle. ROW_STRT_N signal starts process reading analog data from pixel row, analog-to-digital conversion, storage digital values registers. When these actions completed, sensor sends response back system controller using ROW_DONE_N. address must valid first half processing time (the period between ROW_START_N ROW_DONE_N).
PB-MV40
Controller
ROW_ADDR
Controls
Column Parallel 10-bit 1176
Even Columns
ROW_STRT_N
On-Chip Control Logic/ Decoders
PIXEL ARRAY
Columns
SYSCLK
Controls
Column Parallel 10-bit 1176
Reads contents pixel specified ROW_ADDR Converts pixel signals digital values Stores digital values register (2352 bit)
Example This example shows MV40 being digitized
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PB-MV40 Product Specification, September 2001 (Version 1.0)
External Control Sequence (continued)
ROW_ADDR address pixel read input externally this 11-bit input bus. Addresses above 1728 invalid. Must valid least SYSCLK cycles, must valid when ROW_STRT_N pulled changed simultaneously with lowering ROW_STRT_N. ROW_STRT_N This signal: i-Reads contents pixel specified ROW_ADDR above) ii-Converts pixel signal digital value iii-Stores digital value register (2352 10-bit) iv-Resets pixel Must valid minimum clock cycles. Should returned high before ROW_DONE_N goes low. ROW_DONE_N SYSCLK cycles after ROW_STRT_N been pulled above) sensor acknowledges completion read operation/digitization sending going pulse this pin. Valid clock cycles. LD_SHFT_N This signal transfers digitized data from register output register (2352 10-bit) gates power sense amplifiers. first data (columns 1-16) available output third rising edge SYSCLK after LD_SHFT_N pulled low. enabled simultaneously with after falling edge ROW_DONE_N. Must remain entire time data being read out. DATA_READ_EN_N This signal used enable data output from output register (2352 10-bit) sixteen, 10-bit output ports. initiated simultaneously with after LD_SHFT_N selected. This control always low. pixel array PB-MV40 image sensor vertically partitioned into groups columns that correspond sensor's sixteen (16) identical output ports.The first column each 16-column always goes Port while last column each goes Port etc. operator access pixels PB-MV40
only using ports (see page Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. Col. CLK147 Col. Col. 2337 Col. Col. 2338 Col. Col. 2339 Col. Col. 2340 Col. Col. 2341 Col. Col. 2342 Col. Col. 2343 Col. Col. 2344 Col. Col. 2345 Col. Col. 2346 Col. Col. 2347 Col. Col. 2348 Col. Col. 2349 Col. Col. 2350 Col. Col. 2351 Col. Col. 2352
Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port Port
output register allows processing performed while digital data from previous operation being read sensor. pixel readout conversion cycle started when LD_SHFT_N pulled low. *Detail timing presented next page. full horizontal resolution mode should last minmum SYSCLK cycles. However, lower resolution modes such 2048x1536 less, data readout stopped (LD_SHFT_N DATA_READ_EN_N returned high) after SYSCLK cycles. This minmum time terms clock cycles needed complete operations.
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
External Control Sequence (continued)
SYSCLK ROW_ADDR ROW_STRT_N ROW_DONE_N LD_SHFT_N DAT_READ_EN_N DATA [159:0]
VALID
2048 columns 2352 columns
Timing diagram
ROW_ADDR ROW_STRT_N ROW_DONE_N LD_SHFT_N DATA_READ_EN_N DATA [159:0]
1727
1726
1727
ROW1727
ROW0
ROW1
ROW1725 ROW1726 ROW1727
Frame Timing
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
External Control Sequence (continued)
PB-MV40 contains special self-calibrating circuitry that enables reduce column-wise fixedpattern noise. This calibration process consists connecting calibration signal (VREF2) each inputs, estimating storing these offsets bits) subtract from subsequent samples. Typical Signal Timing (Initialization Sequence) diagram shows timing sequence calibrate sensor. Calibration occurs automatically after logic reset (LRST_N) also started user, pulling CAL_STRT_N low. When calibration finished, sensor generates active CAL_DONE_N. Significant ambient temperature drift justify re-calibration.
CAL_STRT_N
CAL_DONE_N SYSCLK
LRST_N
CAL_DONE_N SYSCLK
Typical Signal Timing (Initialization Sequence)
CAL_STRT_N two-clock cycle-wide active-low pulse that initiates calibration sequence. pulse must actuated microsecond after either power-up removal sensor from powerdown state. Users find easiest calibrate means logic reset. user should ensure that analog biases settled prior initiating calibration sequence. CAL_DONE_N two-clock cycle-wide active-low output pulse that asserted when calibration complete. device will automatically initiate calibration sequence upon logic reset. Completion this sequence, cases where initiated reset, still with CAL_DONE_N signal. This process complete within SYSCLK cycles CAL_STRT_N. This process complete within SYSCLK cycles LRST_N. LRST_N two-clock cycle-wide active-low pulse that resets digital logic. puts logic into known state (all flip-flops reset). This signal also initiates calibration sequence. While controller busy (performs operations after "start row" calibration commands) insensitive ROW_STRT_N CAL_STRT_N pulse.
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
External Control Sequence (continued)
chip also external read/write access calibration values. shown section calibration values stored SRAM 7-bit digital numbers which used drive 7-bit DACs. Using four-pin serial interface user access calibration data, read them out, optimize write back. interface protocol defined figure below. Recommended frequency serial interface clock MHz.
DATA READ DATA_CLK
Delay<< period/2
RE_N WE_N DATA
Z-state
void c0_b6 c0_b5 c0_b4 c0_b3 c0_b2 c0_b1 c0_b0 void c1_b6 c1_b5
c2351_b0
void
Z-state
DATA WRITE DATA_CLK RE_N WE_N DATA
Z-state void c0_b6 c0_b5 c0_b4 c0_b3 c0_b2 c0_b1 c0_b0 void c1_b6 c1_b5
C2351_b0
void
Z-state
NOTE: c0_b6 column (bit6= MSB); ADCs from 2351
Calibration SRAM Write-Read Convention
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Electronic Shutter
PB-MV40 utilizes electronic rolling shutter (ERS). understand some points must kept mind. First, referring back Section recall that each time selected (e.g., ROW_ADDR ROW_STRT_N applied) pixels read reset. read operation ends integration selected reset operation defines start next exposure. integration time given time between successive resets reads that row. Secondly, should noted that PB-MV40 fast rolling reset mode (enabled with ROL_RST) which each time selected (e.g., ROW_ADDR ROW_STRT_N applied) addition first read reset there second reset allowed second row. This essentially allows doubling read/reset sequence some instances because readout second reset during single processing time. 2.4.1 Mode with Exposure Greater than Frame Time (Single Pointer READ RESET) PB-MV40 operated electronic rolling shutter (ERS) mode control sensor integration time. When user wishes select integration time that equal exceeds frame time (i.e., frame readout time), single READ RESET POINTER* used read data from reset each pixels, shown Figure This done changing address using ROW_ADDR point appropriate sensor. typical application, sequence rows
read repeatedly. integration time time elapsed between successive selection particular selected using ROW_ADDR pulsing ROW_STRT_N), shown Figure Please recall from Section that ROW_STRT_N both reads resets specified ROW_ADDR. integration time simply inverse frame rate (i.e. 60fps msec integration time) this mode. system power-up user should move READ RESET POINTER, along pixel array, row, reset pixels start integration.
*RESET POINTER READ POINTER signals generated sensor rather user-generated constructs utilized here illustrate concept.
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Electronic Shutter
2.4.1 Mode with Exposure Greater than Frame Time (Single Pointer READ RESET) (continued)
READ RESET POINTER
Start expposure. Advance RESET POINTER down through array reset each start integration.
Figure With Single Pointer READ RESET
ROW_ADDR ROW_STRT_N ROW_DONE_N
ROW_ADDR
ROW_ADDR
ROW_ADDR
ROW_ADDR
ROW_ADDR
ROW_ADDR
ROW_ADDR
Integration Time
Figure Reading window rows (starting with array) with single READ RESET pointer
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Electronic Shutter (continued)
2.4.1 Mode with Exposure Greater than Frame Time (Single Pointer READ RESET) (continued)
READ POINTER
RESET POINTER
Advance shutter. Read first array into column processing circuits (ADC). shutter advancing speed matches row-processing speed. (2-column)
RESET POINTER
Both pointers wait here rows intraframe delay (vertical blanking).
READ POINTER read pointer should move down array reset pointer wraps around window.
(2-column)
Figure with Dual RESET READ Pointers
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Electronic Shutter (continued)
2.4.2 Mode with Exposure Less than Frame Time (Dual READ RESET Pointers) When user wishes select integration time that less than frame time, separate pointers used reading resetting row. user still ROW_STRT_N pulse initiate both read reset. However, using ROW_STRT_N initiate reset only time efficient because causes address pointers used each cycle, thus effective frame rate times less compared full-frame integration mode. efficient reset rows through ROL_RST control. When this input HIGH, pixel reset appears twice during time, first time during readout sequence (clocks 1-66), second time during clocks 66-128. recommended that user change address from read address reset address 66th clock. When address switched from current read address current reset address selected gets reset (without read conversion) start integration. Both these address pointers controlled user-supplied ROW_ADDR input. each cycle, first address (READ POINTER) used read data from row. second address (RESET POINTER) used only reset another row. This sets starting point integration that row. read READ POINTER been reset RESET POINTER during previous cycle. difference between value READ POINTER RESET POINTER sets integration time, shown Figure After system power-up, user should move RESET POINTER along pixel array, row, while READ POINTER stays place. When RESET POINTER reaches desired number integration time, READ POINTER should start moving along pixel array. When READ POINTER reaches bottom (last row) pixel array, should wrap around back top. RESET POINTER should never catch with READ POINTER.
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Figure illustrates pictorially. this example, integration time (Address1 Address2) (Row Time). example, Time µsec (~66 clock), user wants msec integration time, Address1 Address2 500. minimum integration time time.
Read Cycle diagram Figure indicates signal relationships. Address1 READ POINTER address. ROW_STRT_N only used read this row. After pixel Address1 read, jump made Address (RESET POINTER). Address2 then reset readout.
2.4.2 Mode with Exposure Less than Frame Time (Dual Pointer READ RESET Pointers) (continued)
Electronic Shutter (continued)
ROW_DONE_N
ROW_STRT_N
Address2 (READ POINTER)
PB-MV40 Product Specification, September 2001 (Version 1.0)
order obtain best performance from initial image, recommended that user reset entire pixel array starting point integration this initial image. timing resetting array should identical frame time subsequent image.
Address1 (RESET POINTER)
ROW_ADDR
SYSCLK
Figure Read Cycle with ROL_RST Enabled
Read Pointer Cycle
Read Pointer Address
Address1
Figure
Clocks
Reset Pointer Cycle
Reset Pointer Address
Address2
Page
Electronic Shutter (continued)
2.4.3 Single Shot Sensor paused some time then user decides capture image. Please note that integration time each ends with read row. provide same integration time rows following procedure recommended: RESET rows, one, initiate integration. Apply ROW_STRT_N pulse every time address changed. LD_SHFT_N DATA_READ_EN_N pulses. READ rows integration read data out. Apply ROW_STRT_N pulse each row. After ROW_DONE_N echo, apply LD_SHFT_N DATA_READ_EN_N pulses read data apply ROW_STRT_N pulse.
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Electronic Shutter (continued)
2.4.4 Using Pulsed Light Achieve Parallel Image Acquisition Sensor with Electronic Rolling Shutter (ERS) typical CMOS active-pixel sensors pixels read reset row. Integration photo- darkcurrent photodetectors starts with photodector reset. particular pixels gets reset during readout. sequential nature addressing provide simultaneous start integration pixels array. Consequently sensors with rolling shutters usually referred sensors that unable "freeze motion". sensor under lighting, possible pulsed light illuminating scene, realize freeze-frame acquisition pulsing light between frames shown below. Integration still starts different times various rows, integration time (duration) same rows includes exposure time.
1727 Integration Time
Exposure
Readout
Exposure
Readout
Time
Read row#N
PB-MV40 Product Specification, September 2001 (Version 1.0)
Read row#N
Read row#0
Read row#0
Page
Electronic Shutter (continued)
2.4.5 Partial Scan Examples PB-MV40 partially scanned sub-sampling rows. user select which rows many rows include partial scan. example, with 66-megahertz clock, time approximately microseconds, resulting following possiblities: frame: ~400,000 frames second rows frame: ~40,000 frames second rows frame: ~4,000 frames second rows frame: ~2,000 frames second rows frame: ~1,000 frames second rows frame: ~500 frames second 1,728 rows frame: ~250 frames second .etc
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Descriptions
Signal Name SYSCLK
Function
Number(s)
ROW_STRT_N
ROW_DONE_N LD_SHFT_N
DATA_READ_EN_N
CAL_STRT_N
CAL_DONE_N VREF2
DATA DATA_CLK WE_N RE_N DARK_OFF_EN_N
Clock input entire chip. Maximum design frequency MHz. Clock duty cycle should ±10% operation speeds <200 fps. operation speeds >200 clock duty cycle (i.e., clock high time time) recommended. Starts conversion pixel (defined address) content. two-clock cycle-wide active-low pulse. two-cycle-wide pulse that indicates that processing currently addressed been completed. active-low signal that places recently converted data into output register output, enables sense amps resets column counter. active-low signal that enables output data multiplexer causes sixteen (16) 10-bit output ports updated with data rising edge system clock. Column counter skips data when this input high. always low. Starts calibration process ADC. This two-clock cycle-wide active-low pulse. This pulse must activated microsecond after either power-up removal sensor from standby state. two-clock cycle-wide active-low pulse that indicates completed calibration operation. reference used calibration operation. Adjustable external voltage from recommended. User voltage source must supply transient current frequency with duty cycle. Decoupling capacitors shown Section usually sufficient filter this required current transient. Serial input/output calibration values. Serial interface clock calibration values. Recommended frequency MHz. active-low envelope signal that enables writing calibration values sensor. active-low envelope signal that enables reading calibration values from sensor. input enables common mode dark offset pixels. value offset defined VREF3 VCLAMP3. Subtracts fixed offset pre-ADC. Signal pulled on-chip.
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Descriptions (continued)
Signal Name VREF3
Function
Number(s)
VCLAMP3
VREF1
VREF4
VLN1
VLN2
LRST_N
Dark offset cancellation positive input reference, tied pedastal voltage added signal. Adjustable external voltage from 3.0V recommended. User voltage source must supply transient current frequency with duty cycle. Decoupling capacitors shown Section usually sufficient filter this required current transient. Dark offset cancellation negative input reference. Adjustable external voltage from 3.0V recommended. User voltage source must supply transient current frequency with duty cycle. Decoupling capacitors shown Section usually sufficient filter this required current transient. reference input voltage that sets maximum N15, N19, J17, input signal level thus sets size least significant (LSB) analog digital conversion process. reference value used like global gain adjustment. Adjustable external voltage from 0.25 recommended. User voltage source must supply transient current frequency with duty cycle. Decoupling capacitors shown Section usually sufficient filter this required current transient. reference input. User voltage source must supply transient current frequency with duty cycle. Decoupling capacitors shown Section usually sufficient filter this required current transient. Bias setting pixel source follower operating current. Generated on-chip. Decoupling capacitor recommended. Range (0.5 1.2V) also adjusted externally better performance. Impedance: 10kOhm, 10pF. Bias setting voltage ADC. Generated on-chip. Decoupling capacitor recommended. Range (0.8 1.1V) also adjusted externally better performance. Impedance: 10kOhm, 10pF. Bias setting voltage column source follower operating current.Generated on-chip. Decoupling capacitor recommended. Range (1.0 2.3V) also adjusted externally better performance. Impedance: 10kOhm, 10pF. Global logic reset function (asynchronous). Active-low pulse. This signal also automatically initiates calibration sequence.
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
Descriptions (continued)
Signal Name STANDBY_N
Function
Number(s)
PIXEL_CLK_OUT ROL_RST ROW_ADDR [10:0]
ROW_ADDR0 ROW_ADDR1 ROW_ADDR2 ROW_ADDR3 ROW_ADDR4 ROW_ADDR5 ROW_ADDR6 ROW_ADDR7 ROW_ADDR8 ROW_ADDR9 ROW_ADDR10 DATA [159:0]
DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16
input sets sensor power mode. (Allow microsecond before calibrating, after coming this mode). Signal pulled on-chip. Data synchronous output. User prefer this data clock instead SYSCLK. active-high envelope signal that enables faster rolling reset array. When unused must grounded. 10-bit 1723, bottom top) that controls which pixel being processed read out. asychronous (unclocked) digital input. Must held valid least SYSCLK cycles. MSB. Pixel data output that sixteen pixels (160 bits) wide. (least significant bit) lowest order pixel. group sixteen pixels being output, (most significant bit).
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Descriptions (continued)
Signal Name DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DATA48 DATA49 DATA50 DATA51 DATA52 DATA53 DATA54 DATA55 DATA56 DATA57 DATA58 DATA59 DATA60 DATA61
Function
Number(s)
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
Descriptions (continued)
Signal Name DATA62 DATA63 DATA64 DATA65 DATA66 DATA67 DATA68 DATA69 DATA70 DATA71 DATA72 DATA73 DATA74 DATA75 DATA76 DATA77 DATA78 DATA79 DATA80 DATA81 DATA82 DATA83 DATA84 DATA85 DATA86 DATA87 DATA88 DATA89 DATA90 DATA91 DATA92 DATA93 DATA94 DATA95 DATA96 DATA97 DATA98 DATA99 DATA100 DATA101 DATA102 DATA103 DATA104 DATA105
Function
Number(s)
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Descriptions (continued)
Signal Name DATA106 DATA107 DATA108 DATA109 DATA110 DATA111 DATA112 DATA113 DATA114 DATA115 DATA116 DATA117 DATA118 DATA119 DATA120 DATA121 DATA122 DATA123 DATA124 DATA125 DATA126 DATA127 DATA128 DATA129 DATA130 DATA131 DATA132 DATA133 DATA134 DATA135 DATA136 DATA137 DATA138 DATA139 DATA140 DATA141 DATA142 DATA143 DATA144 DATA145 DATA146 DATA147 DATA148 DATA149
Function
Number(s)
Page
PB-MV40 Product Specification, September 2001 (Version 1.0)
Descriptions (continued)
Signal Name DATA150 DATA151 DATA152 DATA153 DATA154 DATA155 DATA156 DATA157 DATA158 DATA159 AGND
Function
Number(s)
VRST_PIX
DGND VDD_IO
DGND_IO
SUBSTRATE
Power supply analog processing circuitry T17, N18, L17, (column buffers, ADC, support). Ground analog signal processing circuitry. T18, T19, M16, L19, K16, J18, G16, Power supply pixel array. User voltage source must P16, L15, K17, supply transient current frequency amps, once frame. Recommended range 3.1± 0.2V. Decoupling capacitors shown Section usually sufficient filter this required current transient. Power supply core digital circuitry. U18, Ground core digital circuitry. R16, Power supply digital ring. K3,M3, V5,W7, V10, V12, W15, W18, P15, H19,B19, E14, D14,D12, C11, Digital ground ring. U10, T12, R13, R15, H17, C18, A17, B14, A12, Package cavity contact. Connect AGND. connect. M17, K19, D19, C19, W19, U19, R17, R18,
NOTE: user want allow following changes potential future upgrade PB-MV40: become digital control input sensor; become digital control input sensor; become digital control input sensor; become analog bias input sensor (0-3.3V); become analog bias input sensor (0-3.3V); become analog bias input sensor (0-3.3V); become analog bias input sensor (0-3.3V).
PB-MV40 Product Specification, September 2001 (Version 1.0)
Page
Board Connections
Analog +3.3V Digital Ground
Controller Interface
ROWADDR0 ROWADDR1 ROWADDR2 ROWADDR3 ROWADDR4 ROWADDR5 ROWADDR6 ROWADDR7 ROWADDR8 ROWADDR9 ROWADDR10 SYSCLK DATA_READ_EN_N LD_SHFT_N CAL_DONE_N ROW_DONE_N CAL_STRT_N ROW_STRT_N DARK_OFF_EN_N STANDBY_N LRST_N R0L_RST PIXEL_CLK_OUT DATA DATA_CLK RE_N WE_N
VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 DATA16 DATA17 DATA18 DATA19 DATA20 DATA21 DATA22 DATA23 DATA24 DATA25 DATA26 DATA27 DATA28 DATA29 DATA30 DATA31 DATA32 DATA33 DATA34 DATA35 DATA36 DATA37 DATA38 DATA39 DATA40 DATA41 DATA42 DATA43 DATA44 DATA45 DATA46 DATA47 DATA48 DATA49 DATA50 DATA51 DATA52 DATA53 DATA54 DATA55 DATA56 DATA57 DATA58 DATA59 DATA60 DATA61 DATA62 DATA63 DATA64 DATA65 DATA66 DATA67 DATA68 DATA69 DATA70 DATA71 DATA72 DATA73 DATA74 DATA75 DATA76 DATA77 DATA78 DATA79 DATA80 DATA81 DATA82 DATA83 DATA84 DATA85 DATA86 DATA87 DATA88 DATA89 DATA90 DATA91 DATA92 DATA93 DATA94 DATA95 DATA96 DATA97 DATA98 DATA99 DATA100 DATA101 DATA102 DATA103 DATA104 DATA105 DATA106 DATA107 DATA108 DATA109 DATA110 DATA111 DATA112 DATA113 DATA114 DATA115 DATA116 DATA117 DATA118 DATA119 DATA120 DATA121 DATA122 DATA123 DATA124 DATA125 DATA126 DATA127 DATA128 DATA129 DATA130 DATA131 DATA132 DATA133 DATA134 DATA135 DATA136 DATA137 DATA138 DATA139 DATA140 DATA141 DATA142 DATA143 DATA144 DATA145 DATA146 DATA147 DATA148 DATA149 DATA150 DATA151 DATA152 DATA153 DATA154 DATA155 DATA156 DATA157 DATA158 DATA159
Serial Interface
Analog +3.3V
VCLAMP3
10µF 0.1µF
Analog +3.3V VLN1
10µF 0.1µF
Analog +3.3V
10µF 0.1µF
Analog +3.3V 470µF VREF1 VREF1 VREF1 VREF1
Analog +3.3V 10µF
VREF2
VLN2
0.1µF
10µF
10µF
VREF4
Analog +3.3V
VRST_PIX VRST_PIX VRST_PIX VRST_PIX
10µF 0.1µF
Analog +3.3V VREF3
Pixel Data Output
SUBSTRATE
Digital Ground
Notes:
recommended 470µF electrolytic 0.1µF ceramic capacitors. recommended that capacitors VREF1, VREF2 VREF4 placed physically close possible PB-MV40's package. Alternatively, analog voltages depicted being generated from potentiometers could supplied from DACs. analog voltages VCLAMP3, VREF3, VLN1, VLN2, VLP, VREF4 generated on-chip, user supply voltages override internal biases.
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Analog Ground
AGND AGND AGND AGND AGND AGND AGND AGND
10µF 0.1µF
DGND_IO DGND_IO DGND_IO DGND_IO DGNC_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGNC_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND_IO DGND DGND DGND DGND
Electrical Specification
Electrical Characteristics (Vsupply 3.3V 0.3V) Symbol Tplh Tphl Tsetup Thold Characteristic Data output propagation delay high trans. Data output propogation delay high trans. Setup time input SYSCLK Hold time input SYSCLK Condition Min. Vpwr Vgnd Vpwr=Min,VOH Typ. Max. Unit
Electrical Characteristics (Vsupply 3.3V 0.3V) Symbol VREF1 VREF2 VREF3 VLN1 VLN2 VRST_PIX VCLAMP3 VREF4 Ipwr1 Characteristic Bias Column Buffers Reference Reference Calibration Dark offset (positive) Bias pixel source follower Bias Pixel Array Power Dark offset (negative) Reference Input High Voltage Input Voltage Input Leakage Current, Pullup Resistor Output High Voltage Output Voltage Maximum Supply Current Condition Min. 0.25 Typ. Max. Unit
-0.3 Vpwr Vgnd Vpwr=Min, IOH=-100µA Vpwr=Min, IOL=100µA clock, load outputs Vpwr-0.5
0.15 Open Open (decoupled) 0.25* VREF1 Vpwr+0.3
Ipwr (VDD_IO) (VDD) (VAA)
PB-MV40 Product Specification, September 2001 (Version 1.0)
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Electrical Specification (continued)
Absolute Maximum Ratings Symbol Vpwr Vout Parameter Supply Voltage Input Voltage Output Voltage Current Drain (Any I/O) Current Drain, Vpwr Vgnd Value -0.5 -0.5 Vpwr -0.5 Vpwr ±100 Unit
Maximum Ratings those values beyond which damage device occur. Vpwr=VDD=VAA=VDD_IO (VDD supply digital circuit, analog circuit). Vgnd=DGND=AGND (DGND ground digital circuit, AGND analog circuit).
Recommended Operating Conditions Symbol Vpower
Parameter Supply Voltage Commercial Operating Temperature Junction Temperature
Min. 3.00
Max.
Unit
This device contains circuitry protect inputs against damage from high static voltages electric fields, user advised take precautions avoid application voltage higher than maximum rated.
Power Dissipation (Vpwr 3.3V; 25°C; fps) Symbol Pavg Parameter Average Power Typical <700 Unit
Tplh, Tphl
Tplh, Tphl DOUT(63:0)
Clock Data Propagation Delay
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Optical Optical Specification
Image Sensor Characteristics 25°C)
Symbol PRNU Nsat Vdrk Dyn_I DSNU Kdrk
Parameter Responsivity (ADC VREF1=1V) Photo response non-uniformity Pixel saturation level Output referred dark signal Input referred noise: Overlapped conversion digital readout (240 fps) Internal dynamic range Dark signal non-uniformity Conversion gain Dark current temperature coefficient
Typ. 2,500 25,000
Unit LSB/lux-sec. electrons mV/sec electrons µV/e%/8°C
additional details regarding defect specifications please contact Photobit.
Pixel Array Symbol Resolution Pixel size Pixel pitch Pixel fill factor Parameter Number pixels active image dimensions Center-to-center pixel spacing Area drawn active area Typical 2352 1728 Unit pixels
PB-MV40 Product Specification, September 2001 (Version 1.0)
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Quantum Efficiency
Quantum Efficiency Wavelength (nm) 1000
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Lens Selection
Much specific information this section explained detail Technology section Photobit website. following information applies specifically Photobit PB-MV40 megapixel image sensor. Format diagonal image sensor array 20.43 fits most closely, exactly, within optical format corresponding 1-inch specification. Some 1-inch optical format lenses have been shown work well with this sensor. Typical 1-inch lens examples Computer V2513, V5013, V7514. F-mount lenses provide another possible lens solution their large image circle. Mounting Several lens mounting standards exist that specify threading lens' barrel well distance back flange lens should from image sensor lens properly form image. Typical lens mounting standards PB-MV40 are: Mount Mounting Name Threads Back-Flange-to-Image-Sensor 17.526 12.5 Another option C-mount together with C-to F-mount adapter greater lens flexibility. Field View Focal Length field view imaging system will depend both focal length imaging lens width image sensor. most image information humans attention generally falls within 45-degree horizontal field view, many camera systems attempt imitate this field view. However, some cases telephoto system (with narrow field view, less than degrees), wide angle system (with wide field view, more than degrees) desired. approximate field view that imaging system achieve shown following equation:
where field view, tan-1 trigonometric function arc-tangent, width image sensor, focal length imaging lens. example, imaging system's diagonal field view determined using diagonal image sensor (20.43 particular lens' focal length Alternatively, imaging system's horizontal field view determined using horizontal image sensor (16.46 particular lens' focal length lens with approximately focal length will provide 18-degree horizontal field view with PB-MV40 (keep mind that above equation simplified approximation). F-Number f-number, f/#, imaging lens ratio lens' focal length open aperture diameter. Every doubling f-number reduces light sensor factor four. example, lens f/1.4 lets four times more light than that same lens when f/2.8. f-number lenses capture light delivery image sensor, also require careful focus. Higher f-number lenses capture less light delivery image sensor, require much effort bring imaging system focus. f-number lenses generally cost more than high f-number lenses similar overall performance. Typical f-numbers various imaging systems are: 4.0+ Imaging application Low-light level imaging, manual focus systems Typical other small form cameras Common digital still cameras Often used machine vision applications
PB-MV40 Product Specification, September 2001 (Version 1.0)
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Lens Selection (continued)
Modulation Transfer Function (MTF) technical term that quantifies well particular system propagates information. cameras, "system" lens sensor, "information" picture they capturing. ranges from zero information gets through) (all information gets through), always specified terms information density. most imaging systems, limited performance imaging lens. lens must able transfer enough information image sensor able resolve details image that small pixels image sensor. pixels 7-micron pitch (the center pixel microns from center neighboring pixel). Thus, lens used should able resolve image features small microns. Typically, lens' plotted function number line pairs millimeter lens attempting resolve (more line pairs millimeter mean higher information densities). electronic imaging system, line pair will correspond image sensor pixels (each pixel resolve line). This equated
Infrared Cut-Off Filters most visible imaging situations necessary include filter imaging path that blocks infrared (IR) light from reaching image sensor. This filter called cut-off filter. Various forms cut-off filters available, some absorptive (like Hoya's CM500 Schott's BG18) some reflective (i.e., dielectric stacks). Infrared light poses problem visible imaging because presence blurs decreases images formed lens. Since human vision only extends across narrow range electromagnetic spectrum, camera systems hoping capture images that look like images eyes capture must capture light outside vision range. Silicon-based light detectors (like ones PB-MV40's pixels) detect light from very deep blue near infrared. Thus, filter must exist light's path that keeps infrared from reaching image sensor's pixels. most cases, important that such filter begin blocking light around deep red) continue blocking until least 1100 near IR). most camera systems, cut-off filter included imaging lens.However, this point must verified lens vendor when particular lens chosen with image sensor.
where LP/mm means line pairs millimeter image sensor's pixel pitch, millimeters. PB-MV40, 0.007 such that PB-MV40 LP/mm. Thus, lens should provide acceptable level LP/mm. most lenses, will highst center images they form, gradually drop toward edges images they form. well, MTFs values LP/mm will generally larger than MTFs high values LP/mm. many trade-offs that must decided user high needs particular imaging situation. Generally, near image sensor's LP/mm good MTFs higher than moderate MTFs from poor MTFs less than
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Lens Selection (continued)
C-Mount Lens Shroud PB-MV40 Socket
Note: This shroud designed accommodate PB-MV40 when inserted into socket. These dimensions based MILL #510-93-281-19-081003 socket (www.mill-max.com).
BASE
Threaded holes 4-40 screws places)
2.50"
0.015" Recess
1/8"
0.25"
1/8"
2.50" 0.25" 0.75"
2.50"
1-32 Thread
1.25"
2.50"
1/8" 1.25" 2.50" 0.25"
PB-MV40 Product Specification, September 2001 (Version 1.0)
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Mechanical Package (280-Pin Ceramic PGA)
PB-MV40 CMOS image sensor window-filled package. During manufacture placed into 280-pin ceramic (pin grid array), filled with low-
viscosity epoxy, covered with window appropriate thickness (for focal length), cured. This results physically robust module board installation.
View
1.900±.018 (Square) 1.343±.016 (Square) 1.106±.012 (Square) 1.067±.012 (Square) .840±.009 (Square) .840±.008 (Square)
INDEX
(1727, 2351)
.039 (4X)
19.886±.03mm
.020 (4X)
Column
.020
(4X)
19mils
19.876±.03mm
UNITS: INCHES EXCEPT WHERE NOTED Notes: Gold Plate inches minimum over 50~350m inches nickel. Sensor centered package, pixel array off-center.
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Package (continued)
Side View
.039±.004 .012±.002 .020±.002
.118±.012
(.0235 .047 .005
R.005
BRAZE
Glass
f.018±.002 (281X)
(.008) .039±.005 .150±.008
UNITS: INCHES Notes: thickness 28.5 mils mil. epoxy thickness mil. D-263 glass thickness mils mils. Glass epoxy thickness mil.
PB-MV40 Product Specification, September 2001 (Version 1.0)
f.047±.005 (4X)
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Package (continued)
Bottom View
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PB-MV40 Product Specification, September 2001 (Version 1.0)
Environmental
Absolute Maximum Ratings Symbol Tstorage Tlead Parameter Storage Temperature Range Lead Temperature second soldering) Value Max. Unit
PB-MV40 Product Specification, September 2001 (Version 1.0)
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2001 Photobit Technology Corporation. rights reserved. Photobit Techno

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