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9610 Data Compression Processor Hi/fnsupplies Internet's most important materials: compression encryption. Hi/fn also world's first company both single chip, creating processor that performs compression encryption faster speed than conventional alone could handle, much less than cost Pentium comparable processor. October 1998, address Hi/fn, Inc. University Avenue Gatos, 95032 info@hifn.com http://www.hifn.com Tel: 408-399-3500 Fax: 408-399-3501 Hi/fn Applications Support Hotline: 408-399-3544
Disclaimer Hi/fn reserves right make changes products discontinue semiconductor product service without notice, advises customers obtain latest version relevant information verify, before placing orders, that information being relied current. Hi/fn warrants performance semiconductor products related software specifications applicable time sale accordance with Hi/fn's standard warranty. Testing other quality control techniques utilized extent Hi/fn deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. Certain applications using semiconductor products involve potential risks death, personal injury, severe property environmental damage ("Critical Applications"). HI/FN SEMICONDUCTOR PRODUCTS DESIGNED, INTENDED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT APPLICATIONS, DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. Inclusion Hi/fn products such critical applications understood fully risk customer. Questions concerning potential risk applications should directed Hi/fn through local sales office. order minimize risks associated with customer's applications, adequate design operating safeguards should provided customer minimize inherent procedural hazards. Hi/fn does warrant that products free from infringement patents, copyrights other proprietary rights third parties. event shall Hi/fn liable special, incidental consequential damages arising from infringement alleged infringement patents, copyrights other third party intellectual property rights. "Typical" parameters vary different applications. operating parameters, including "Typicals," must validated each customer application customer's technical experts.
DS-0012-01 (9/98) 1997-1998 Hi/fn, Inc., including more U.S. patents No.: 4,701,745, 5,003,307, 5,016,009, 5,126,739, 5,146,221, 5,414,425, 5,414,850, 5,463,390, 5,506,580, 5,532,694. Other patents pending.
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9610 Data Compression Processor
Table Contents
Product Description System Concept Connections.6 Descriptions.7 Interface.7 Port Interface Port Interface Other Port Signals Miscellaneous Signals Product Overview.10 Source FIFO Data Flow.10 Dest FIFO Data Flow Command/Result Pipeline Register Description Overview Data (0).14 Command Stack Command Termination Conditions Commands.16 Command Stack Fields.19 Result Stack Configuration Interrupt Enable 6.10 Status 6.11 FIFO Status (6).29 6.12 FIFO Configuration Register Summary.31 Timing Description.32 Interface.32 Electrical Specifications Timing Specifications.36
Figures
Figure Tape application.5 Figure Printer application Figure BYTEALIGN locations Figure BYTEALIGN signals Figure Internal Block Diagram Figure Command/Result Pipeline Figure Register list.14 Figure Commands.16 Figure Port Settings Figure Width Figure Absolute Maximum Ratings Figure Recommended Operating Conditions.35 Figure Electrical Characteristics Figure Specification Definition Figure Reset Timing Figure External Clock.36 Figure Asynchronous Timing.36 Figure Asynchronous Timing DATA SHEET DS-0012-01 Page
9610 Data Compression Processor Figure Figure Figure Figure Synchronous Timing.38 Synchronous Timing 144-pin PQFP package.40 144-pin PQFP pinout.41
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9610 Data Compression Processor
Product Description
Hi/fn 9610 very high-performance lossless data compression processor which used high speed applications, including tape drive laser printer applications. This chip implements industry standard Hi/fn LZS® data compression algorithm. This algorithm been standardized many organizations including ANSI (X3.241), (122), IETF (RFC-1967, RFC1974), TIA/EIA (655), Frame Relay Forum (FRF.9). Applications Very High-speed applications Tape drives Laser printers Features Industry standard Hi/fn Compression algorithm Maximum Mbyte/s compression decompression speed In-line architecture (Two 32-bit busses) 16-bit Internal compression Simple operation Part Number 9610-20 9610-50 Package Mbyte/s, 144-pin plastic quad flat pack Mbyte/s, 144-pin plastic quad flat pack
System Concept
9610 SCSI Interface
Tape Formatter
Figure Tape application
Host Interface
Buffer Memory
9610
Print Engine
Figure Printer application
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
144-pin TQFP
Connections
Signal
D15-0 A2-0 R/W# IRQ# CPUMODE CLKC
Type
Description 16-bit data Register select Read/Write Command Strobe Interrupt output mode clock 32-bit Port data Port Parity Port clock 32-bit Port data Port Parity Port clock Port FIFO request Port FIFO acknowledge Port FIFO terminal count Port FIFO request Port FIFO acknowledge Port FIFO terminal count Dest port alignment Reset Main clock Xtal Output volts
Interface 26-29,33-40, 42,44-46 23-25 Port Interface 49-50, 58-65, 69-76, 81-86, 94-97 Port Interface 98-101, 105-112, 116-122, 126, 130-137, 141-144 103, 114, 128,139 Other Port Signals Miscellaneous Signals 102, 113, 123, 127, 104, 115, 125, 129,
DA31-0
PA3-PA0 CLKA
DB31-0
PB3-PB0 CLKB
DREQ0# DACK0# TC0# DREQ1# DACK1# TC1# NOALIGN
RESET# XOUT
Ground
connection
I=TTL-compatible input, SI=schmitt input, CI=CMOS input, O=TTL-compatible output, OC=open collector output.
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9610 Data Compression Processor
Descriptions
Interface
4.1.1 Address (A2-A0) Address input signals Interface. 4.1.2 Data (D15-D0) Bi-directional data Interface. 4.1.3 Command Strobe (CS#) Active input. While this signal active, register access will take place. data direction determined R/W# signal. 4.1.4 Read/Write Command (R/W#) This signal determines direction data during register transfer. this signal high, read transfer will take place. this signal low, write transfer will take place. 4.1.5 Interrupt (IRQ#) Active output. This signal will become active when event occurs that enabled Interrupt Enable register. Interrupt Enable register description further information about when this signal asserted deasserted. This signal open collector output requiring external pull-up resistor 4.1.6 Mode (CPUMODE) This used select timing mode only. CPUMODE tied low, will follow Asynchronous timing specifications. CPUMODE tied high, will follow Synchronous timing specifications.
Port Interface
4.2.1 Port Data (DA31-DA0) Bi-directional data Port Interface. This configured either 16-bit 32-bit operation with WIDTH Configuration Register. While configured 16-bit mode, upper bits (AD31-AD16) will remain tristated. upper bits must tied high) this case prevent these signals from floating. 4.2.2 Port Parity (PA3-PA0) Bi-directional parity Port Interface. Each reflects 8-bits data bus. least-significant corresponds least significant byte DATA SHEET DS-0012-01 Page
9610 Data Compression Processor bus. configured 16-bit operation, only PA1-PA0 significant. other parity signals will remain tri-stated, should tied high) prevent these signals from floating. parity used, i.e. byte "00000000" would result corresponding parity "1".
Port Interface
4.3.1 Port Data (BD31-BD0) Bi-directional data Port Interface. This configured either 8-bit, 16-bit, 32-bit operation with WIDTH field Configuration Register. While configured 8-bit 16-bit mode, unused bits data will remain tri-stated. These unused bits must tied high) this case prevent these signals from floating. 8-bit mode only available port destination. 4.3.2 Port Parity (PB3-PB0) Bi-directional parity Port Interface. Each reflects 8-bits data bus. least-significant corresponds least significant byte bus. configured 16-bit operation, only PB1-PB0 significant. other parity signals will remain tri-stated. configured 8-bit operation, only significant. other signals will remain tristated, should tied high) prevent these signals from floating. parity used, i.e. byte "00000000" would result corresponding parity "1".
Other Port Signals
4.4.1 Request (DREQ0#) Active output. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal indicates when Port FIFO ready accept transfer. This signal will become inactive when Port FIFO longer requires data transfer. Timing section timing details. 4.4.2 Acknowledge (DACK0#) Active input. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal acknowledges transfer. Timing section timing details.
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9610 Data Compression Processor 4.4.3 Terminal Count (TC0#) Active output. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal indicates last transfer current command. further Port activity will next command Command Stack pipeline. Timing section timing details. 4.4.4 Request (DREQ1#) Active output. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal indicates when Port FIFO ready accept transfer. This signal will become inactive when Port FIFO longer requires data transfer. Timing section timing details. 4.4.5 Acknowledge (DACK1#) Active input. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal acknowledges transfer. Timing section timing details. 4.4.6 Terminal Count (TC1#) Active output. Port associated with this signal determined value SOURCE PORT DEST PORT fields Command Stack register. This signal indicates last transfer current command. further Port activity will next command Command Stack pipeline. Timing section timing details. 4.4.7 Align (NOALIGN) Active high output. This signal indicates that last transfer command destination Port contains some extra, undefined data because number valid bytes even multiple width. This signal valid only when corresponding signal asserted. NOALIGN signal active, actual number valid bytes last transfer determined external hardware analyzing BYTEALIGN signals. These signals appear unused most significant byte lane destination Port data bus. Figure determine data signals that BYTEALIGN appears Figure meaning BYTEALIGN signals. Destination port width Endian Little Little BYTEALIGN1,0 signal locations D31, D15,
Figure BYTEALIGN locations
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9610 Data Compression Processor BYTEALIGN1,0 values valid bytes last transfer reserved
Figure BYTEALIGN signals
Miscellaneous Signals
4.5.1 Reset (RESET#) Active input. While this signal active, this chip will immediately stop current activity will into known state. After hardware reset, Compression History will cleared before first use. access chip until clock cycles have occurred after RESET#is deasserted. Since RESET logic propagates through entire chip, clock cycles should slowest clock input chip. 4.5.2 Clock (CLK) This input drives clock internal logic interfaces except configured synchronous operation. clock frequency determines speed Processing Unit. speed Processing Unit directly linear with clock frequency. 4.5.3 Clock (CLKC) This input drives clock configured synchronous operation. clock frequency determines speed bus. configured asynchronous operation, this signal must tied low. 4.5.4 Port Clock (CLKA) This input drives clock Port configured synchronous operation. clock frequency determines speed bus. Port configured asynchronous operation, this signal must tied low. 4.5.5 Port Clock (CLKB) This input drives clock Port configured synchronous operation. clock frequency determines speed bus. Port configured asynchronous operation, this signal must tied low.
Product Overview
Source FIFO Data Flow
source FIFO obtain source data from Port Port Port depending upon setting SOURCE PORT field Command Stack register. following description uses generic term, "source Port" indicate Port used input data, "dest Port" indicate Port used output data. Page DS-0012-01 DATA SHEET
9610 Data Compression Processor source Port will request data unless there active command there room source FIFO additional data. After command issued, source Port will request data. request will remain active until source FIFO becomes full, until command termination conditions listed Command Stack register description occurs. most common command termination condition when Source Counter reaches zero. source Port requests data transfers asserting DREQ# signal source Port setting SOURCE FIFO READY Status register one. source Port Port, there DREQ# signal. Although source FIFO only bytes size, more than bytes could transferred into source FIFO burst because Processing Unit reading data from source FIFO same time making room additional data. Once FIFO becomes full, source Port will stop requesting data. source Port will request data again once number bytes empty space source FIFO greater than value Configure FIFO register. Most command termination conditions affect input side source FIFO. example, when number bytes entering source FIFO matches value SOURCE COUNT field, Stop command issued, last byte source FIFO time termination condition occurs allowed flow through output side source FIFO (and through Processing Unit) before command actually terminates. source Port will stop requesting data when number bytes entering source FIFO matches value SOURCE COUNT field. signal source Port will asserted indicate last data transfer into source Port.
Hanshaking Source Counter Byte Source FIFO Data Data Byte Dest FIFO Hanshaking Dest Counter Processing Unit
Data
Interface
Command Structure
Registers
Figure Internal Block Diagram
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Result Structure
9610 Data Compression Processor command must terminate before command will start. Although commands queued, there will small delay from command start next command until data within FIFOs been completely transferred. When last byte source data given command exits source FIFO enters Processing Unit, trailing bytes that 32-bit 16-bit) aligned will discarded. first byte source data next command will come from next 32-bit 16-bit) aligned value.
Dest FIFO Data Flow
dest FIFO output dest data Port Port Port depending upon setting DEST PORT field Command Stack register. following description uses generic term, "source Port" indicate Port used input data, "dest Port" indicate Port used output data. dest Port will request data transfer unless there data available dest FIFO. After data enters dest FIFO, dest Port will begin requesting data transfers once number bytes residing dest FIFO greater than value Configure FIFO register. request will remain active until dest FIFO becomes empty. dest Port requests data transfers asserting DREQ# signal dest Port setting DEST FIFO READY Status register one. dest Port Port, there DREQ# signal. Although dest FIFO only bytes size, more than bytes could transferred dest FIFO burst because Processing Unit writing data dest FIFO same time, adding additional data. Once FIFO becomes empty, dest Port will stop requesting data transfers. will request data again once number bytes residing dest FIFO greater than value Configure FIFO register. After last byte data from command entered dest FIFO, dest Port will request data transfers, independent FIFO threshold Configure FIFO register, until FIFO empty. signal dest Port will asserted indicate transfer last byte dest FIFO. command must terminate before command will start. Although commands queued, there will small delay from command start next command until data within FIFOs been completely transfered. When last byte data enters dest FIFO from Processing Unit, data padded with dummy data fill entire 32-bit 16-bit) value. value dummy byte undefined. first byte destination data from next command will 32-bit 16-bit) aligned. NOALIGN signal indicates that last data transfer command destination Port contains some extra, undefined data because number valid bytes even multiple width. this signal active, actual number valid bytes last transfer determined external hardware analyzing data BYTEALIGN signals destination Port data bus. Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
Command/Result Pipeline
order eliminate latency while issuing commands reading results, command result registers architected into multi-stage pipeline. Commands results pipelined allow issue commands read results without severe timing constraints. pipeline consists three stages. first stage Command Stack. second stage Processing Unit. third stage Result Stack. When command written chip, written Command Stack pipeline. Processing Unit available command active), command will transferred Processing Unit. When command transferred Processing Unit, Command Stack ready accept another command. COMMAND READY Status register will one. Once Processing Unit completed command, result information will transferred Result Stack. RESULT READY Status register will one. When result transferred Result Stack, Processing Unit ready accept another command from Command Stack. After detecting RESULT READY (via interrupt, polling), read result from Result Stack. three stages allow buffering three operations. pipeline allows ample time issue commands read results without slowing down Processing Unit.
Command
Command
Command
Commands
Command Stack
Processing Engine
Result Stack
Results
Figure Command/Result Pipeline
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9610 Data Compression Processor
Overview
Register Description
9610 uses address locations configuration use. Reserved bits must written zeros ignored when read. Name Address Data Command Stack Result Stack Configuration Interrupt Enable Status FIFO Status FIFO Configuration Figure Register list
Data
Data (D15-D0)
This register read written. used transfer data Source FIFO from Dest FIFO. bytes bits) will transferred each access. ENDIAN Configuration register description byte ordering. write operation will transfer bytes Source FIFO. read operation will transfer bytes from Dest FIFO. During normal operation, interfaces should used transfer data Source FIFO from Dest FIFO. Therefore, this register should only used under special conditions, testing. Transfers from Data register only take place under same conditions that transfer take place. This described Source FIFO Data Flow Dest FIFO Data Flow sections. SOURCE FIFO READY DEST FIFO READY bits Status register determine when valid read write Data register. much data written, much data read, command will terminate, DATA ERROR Result Stack Status register will one. This error will produce undefined results data stream, data must ignored, history must cleared.
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9610 Data Compression Processor
Command Stack
Write Order
Command Ignore Clear Source Ignore Rsrvd Check CRC/ Dest Hist Enable
Reserved
Reserved
Source Align
Dest Align
Source Port
Dest Port
Source Count (D31-D16)
Source Count (D15-D0)
Dest Count (D31-D16)
Dest Count (D15-D0)
This register read written. used specify command executed. addition, several parameters related command here. This register operates stack. write operations required properly start command. COMMAND PROGRESS Status register used verify synchronization write operations. writes must take place unless specified differently command description. command only issued COMMAND READY Status register before first write Command register. Command/Result Pipeline section further details operation Command/Result pipeline. Although normally required, command stack read CPU. This done testing purposes. Reading Command Stack register similar writing words must read. Command Stack should read until words have been written Command Stack. Only last command written Command Stack available read. COMMAND PROGRESS Status register used verify synchronization read operations. Reading command stack does affect state command/result overrun bit.
Command Termination Conditions
commands (except Reset Stop commands) will terminate when following conditions occur: number source bytes read from Source FIFO Processing Unit matches value Source Count field (unless IGNORE SOURCE COUNT one). This will produce normal termination defined below. Result Stack, SOURCE ZERO will one. Read CRAM command different from other commands. will terminate when number bytes written Processing Unit into Dest FIFO matches value Dest Count field. other command operates this way.
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9610 Data Compression Processor Stop command issued. command will terminate when last byte written source FIFO time Stop command issued, enters Processing Unit. This will produce normal termination defined below. Reset command issued. There will Result Stack. Everything stops immediately, data FIFOs will discarded. attempt made write data full source FIFO attempt made read data from empty dest FIFO. Result Stack, DATA ERROR will one. command will terminate when last byte source FIFO time data error occurs, enters Processing Unit. This will produce normal termination defined below. Note: Dest Counter cannot terminate command, except Read CRAM command. Dest Counter decrements below zero during operation command, command will continue process incoming data, additional data will output Dest FIFO. DEST OVERRUN Result Stack will asserted this case. "normal termination" means that after last byte destination data produced command entered destination FIFO, Result Stack register terminated command available, must read.
Commands
COMMAND field specifies command executed. valid values listed Figure other values invalid. Command Command field Compress Decompress Update History Pass-Through Reset Stop Read CRAM Write CRAM
Note: other values command field reserved.
Figure Commands 6.5.1 Compress This command will compress block data termination, Processing Unit will flush internal data, append Marker compressed data stream. compressed data stream after Marker will padded with zeroes round whole byte. This command will optionally append compressed data stream other options this command.
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9610 Data Compression Processor 6.5.2 Decompress This command will decompress block data Marker found before command terminates, source data between Marker last source byte will discarded. Marker present last source byte, then data will discarded. there Marker source data, Decompression History invalid. This condition will cleared automatically next compress decompress operation. This command will optionally analyze compressed data stream verifying other options this command. 6.5.3 Update History This command will pass block uncompressed data from source FIFO dest FIFO without modifying data. Decompression History will updated with uncompressed source data. 6.5.4 Pass-Through This command will pass block data from source FIFO destination FIFO without modifying data. Compression Decompression Histories affected. 6.5.5 Reset This command will cause chip immediately enter known start-up state. This single word command. additional writes Command Stack register will interpreted start next command. affect Reset command identical asserting RESET pin, except that Configuration register will initialized. When this command issued, chip operations will immediately Stop. queued commands will discarded. Source Dest FIFOs will cleared. intermediate information still residing chip will lost. Compress operation stopped this manner, Compression History will corrupt must cleared next time used. This command queued, will operate immediately. COMAND PROGRESS Status register must zero when this command issued. result data generated this command. access chip after Reset command issued until after cycles slowest input clocks have occurred. 6.5.6 Stop This command will cause current Compress, Decompress, Update History, Pass-Through command terminate soon last byte currently source FIFO time Stop command issued, enters Processing Unit. normal termination processing will take place. This single word com-
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9610 Data Compression Processor mand. additional writes Command Stack register will interpreted start next command. Since there source count associated with stop command, four bytes from last source FIFO transfer processed. That there limited control over exactly many bytes processed when utilizing Stop command. number bytes controlled offsetting source data using dest aligned bits Command Stack. This command will affect command residing Command Stack pipeline. there command currently operating, then Stop command will ignored. This command useful terminate command IGNORE SOURCE COUNT set. This command queued, will operate immediately. result data generated this command (except result data command that being stopped). Stop command does affect active Read CRAM command. Read CRAM terminated only dest counter reaching zero. 6.5.7 Read CRAM This command used transfer data directly from CRAM (Compression RAM) destination FIFO. This normally used debugging purposes CRAM memory testing. starting byte address CRAM must SOURCE COUNT field. DEST COUNT field must number bytes read from CRAM. field should zero.The total size CRAM 2Kbytes. Setting DEST COUNT larger value will result address wrapping reading same contents multiple times. Only bits 10:0 SOURCE COUNT used (upper bits ignored).
DESTINATION COUNT
properly terminate ReadCRAM command, IGNORE DEST COUNT must zero. Since source FIFO involved with Read CRAM command, issuing stop command affect Read CRAM command. 6.5.8 Write CRAM This command used transfer data directly CRAM (Compression RAM) from source FIFO. This normally used debugging purposes CRAM memory testing. starting byte address CRAM must DEST COUNT field. SOURCE COUNT field must number bytes write CRAM. total size CRAM 2Kbytes. Setting SOURCE COUNT larger value will result address wrapping writing same CRAM addresses multiple times. Only bits 10:0 DEST COUNT used (upper bits ignored).
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9610 Data Compression Processor
Command Stack Fields
6.6.1 Clear History This significant Compress command only. this one, Compression History will cleared before compress operation begins. This must zero other commands. this zero, Compression History will cleared. compress operation will history information from previous compress operations. Note: This must first compress operation after hardware reset. nature Hi/fn compression format, never necessary clear Decompression History. 6.6.2 Ignore Source Count This significant Compress, Decompress, Update History, PassThrough, Write CRAM commands. this one, source counter will terminate command when counter reaches zero. source counter will wrap from zero FFFFFFFF16. this zero, specified command will terminate when source counter reaches zero. either case, source counter will initialized value SOURCE COUNT field. Also, command terminate from other conditions listed previously. During Read CRAM command, since source FIFO source counter logic involved with operation, source counter value updated from command stack therefore invalid value source counter returned result stack. 6.6.3 Ignore Dest Count This significant Compress, Decompress, Update History, PassThrough, Read CRAM commands. this one, dest counter will cause Processing Unit stop producing data when counter reaches zero. dest counter will wrap from zero FFFFFFFF16. this zero, Processing Unit will stop producing data when dest counter reaches zero. Also, dest counter will decrement further. either case, dest counter will initialized value DEST field.
COUNT
During Read CRAM command, IGNORE DEST COUNT must zero, since Read CRAM terminated only dest counter reaching zero. Stop command does affect active Read CRAM command.
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9610 Data Compression Processor 6.6.4 Check Enable This significant Compressand Decompress commands. enables in-line generation verification check algorithm. this zero, there will in-line check fields generated verified. CHECK ENABLE does affect calculation CHECK FIELD Result Stack register. Compress command, this one, check field will appended compressed destination data stream. Decompress command, this one, check field will verified. check value calculated current block data does match check field embedded data stream, CHECK ERROR Result Stack will one. Also, CHECK ERROR Status register will one. Bits 16-bit appended first datastream, followed bits 15:8. case LCB, only bits appended data stream. 6.6.5 CRC/LCB This significant Compress, Decompress, Update History, PassThrough, Read CRAM, Write CRAM commands. selects between check algorithm. This affects value reported Result Stack well check field optionally inserted checked data stream (check field compress decompress commands only). this zero, 8-bit (Longitudinal Check Byte) will used. exclusive-OR each uncompressed byte. initialized FF16 start each command. this one, 16-bit will used. calculated uncompressed data. initialized FFFF16 start each command. polynomial 6.6.6 Source Align This field significant Compress, Decompress, Update History, PassThrough, Write CRAM commands. first byte source data 32bit 16-bit) aligned, SOURCE ALIGN field used ignore first bytes source data. number bytes ignored this field. ignored bytes counted source counter. source port width configured bits, then SOURCE ALIGN field must zero. Otherwise values three zero valid. 6.6.7 Dest Align This field significant Compress, Decompress, Update History, PassThrough, Read CRAM commands. desired force first byte destination data non-32-bit non-16-bit) alignment, DEST ALIGN field used produce bytes data that will inserted front destination data. value inserted bytes undefined. number bytes inserted this field. Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
inserted bytes counted dest counter. dest port width configured bits, then DEST ALIGN field must zero. Otherwise values three zero valid. 6.6.8 Source Port This field significant commands except Reset, Stop, Read CRAM. This field determines which Port channel will used input source data. Figure details. Source Port field Dest Port field Source Port Port Port Port Port Port Port Port Port Port Dest Port Port Port Port Port Port Port Port Port Port Source DMA0 DMA0 DMA0 DMA1 DMA1 DMA1 none none none Dest DMA1 DMA1 none DMA0 DMA0 none DMA0 DMA1 none
Figure Port Settings 6.6.9 Dest Port This field significant commands except Reset, Stop, Write CRAM. This field determines which Port channel will used output destination data. Figure details.
6.6.10 Source Count This field significant commands except Reset Stop commands. This initial value used Source Counter. Source Counter decremented each source byte processed Processing Unit. Read CRAM command this first CRAM address read. Source Counter will decrement every byte processed, including bytes specified SOURCE ALIGN field, data, input check value enabled). will decrement extra bytes inserted final transfer filling whole word. 6.6.11 Dest Count This field significant commands except Reset Stop commands. This initial value used Dest Counter. Dest Counter decremented each destination byte produced Processing Unit. Write CRAM command this first CRAM address written.
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9610 Data Compression Processor Dest Counter will decrement every byte processed, including bytes specified DEST ALIGN field, data, output check value enabled). will decrement extra bytes inserted final transfer filling whole word.
Result Stack
Read Order
Reserved
Data Dest Check Parity Source Error Overun Error Error Marker Zero Check Value
Reserved
Source Count (D31-D16)
Source Count (D15-D0)
Dest Count (D31-D16)
Dest Count (D15-D0)
This register read only. used read result completed command. This register operates stack. read operations required properly read result. RESULT PROGRESS Status register used verify synchronization read operations. reads must take place even some information will used. Command/Result Pipeline section further details operation Command/Result pipeline. 6.7.1 Data Error This significant commands. This will attempt made write full source FIFO attempt made read data from empty dest FIFO. This error condition will cause automatic execution Stop command. current command will terminate soon source FIFO becomes empty. Stop command description Command Stack additional information. Also, pipelined commands will cleared. commands written until DATA ERROR Status register cleared. This condition reason operation terminated. 6.7.2 Dest Overrun this one, command produced more data than expected. dest counter attempted decrement below zero, IGNORE DEST COUNT zero. This condition does terminate command, however, command continued process incoming data, additional data output dest FIFO. further source data discarded until command terminates. dest counter will remain zero.If this zero, then dest
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9610 Data Compression Processor counter attempt decrement below zero, IGNORE DEST COUNT one. 6.7.3 Check Error This significant Decompress command only, only CHECK ENABLE Decompress command. CHECK ERROR one, check value calculated current block data match check field embedded data stream, check value missing from data stream (due Source Count reaching zero prematurely, example). this zero, check value matched correctly. 6.7.4 Parity Error This significant commands. This will parity error detected (indicating that source data valid). value this will affect operation current command. 6.7.5 Marker This significant Decompress command only. this one, Processing Unit detected Marker source data stream. This condition reason decompress operation terminated. this zero, Marker detected before operation terminated. 6.7.6 Source Zero This significant Compress, Decompress, Update History, Write CRAM, Pass-Through commands. this one, source counter reached zero. This condition reason operation terminated. this zero, source counter reach zero before operation terminated, IGNORE SOURCE COUNT one. 6.7.7 Check Value This field significant Compress, Decompress, Update History, PassThrough, Read CRAM, Write CRAM commands. This calculated CRC/LCB Command Stack) check value. configured LCB, then only bits significant. others unused. configured CRC, then bits significant. This field significant even CHECK ENABLE Command Stack register zero. 6.7.8 Source Count This field significant commands except Reset, Stop, Read CRAM commands. This final value source counter command termination. source counter decremented each source byte processed Processing Unit.
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9610 Data Compression Processor 6.7.9 Dest Count This field significant commands except Reset, Stop, Write CRAM commands. This final value dest counter command termination. dest counter decremented each destination byte produced Processing Unit.
Configuration
Reserved
Port Width
Port Width
Port Port Reserv ChipID Parity Mode Mode Endian
Reserved
This register read written. used configure chip options. default value fields this register after hardware reset zero. 6.8.1 Port Width This field selects Port width. Figure relationship between value this field actual Port width. width field Port width reserved reserved Figure Width 6.8.2 Port Width This selects Port width. Figure relationship between value this field actual Port width. 6.8.3 Port Mode This selects timing mode Port bus. this zero, will follow Asynchronous timing specifications. this one, will follow Synchronous timing specifications. 6.8.4 Port Mode This selects timing mode Port bus. this zero, will follow Asynchronous timing specifications. this one, will follow Synchronous timing specifications. 6.8.5 Endian This selects byte order data transferred interfaces, Data register. this zero, this chip operates were attached Little Endian processor. least significant byte transferred data will enter leave Processing Unit first. Port width reserved
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9610 Data Compression Processor this one, this chip operates were attached Endian processor. most significant byte transferred data will enter leave Processing Unit first. 6.8.6 ChipID This allows ChipID value read from Status register. When this one, ChipID value read once from Status register. After ChipID value read from Status register, this returns zero. This readable. When this one, returns value until after ChipID value read from Status register. After ChipID value read from Status register this read value zero. 6.8.7 Parity This used enable parity. this one, parity will generated checked. this zero, parity will generated checked.
Interrupt Enable
Result Cmnd Source FIFO Ready Ready Ready
Dest FIFO Ready
Cmnd/ Data Dest Check Parity Result Error Error Error Overrn Overun
Reserved
This register read written. used configure chip. default value fields this register after hardware reset zero. 6.9.1 Result Ready Interrupt Enable While this one, IRQ# signal will asserted while RESULT READY Status register one. 6.9.2 Command Ready Interrupt Enable While this one, IRQ# signal will asserted while COMMAND READY Status register one. 6.9.3 Source FIFO Ready Interrupt Enable While this one, IRQ# signal will asserted while SOURCE FIFO READY Status register one. 6.9.4 Dest FIFO Ready Interrupt Enable While this one, IRQ# signal will asserted while DEST FIFO READY Status register one. 6.9.5 Command/Result Overrun Interrupt Enable While this one, IRQ# signal will asserted while COMMAND/RESULT OVERRUN Status register one.
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9610 Data Compression Processor 6.9.6 Data Error Interrupt Enable While this one, IRQ# signal will asserted while DATA ERROR Status register one. 6.9.7 Dest Overrun Interrupt Enable While this one, IRQ# signal will asserted while DEST OVERRUN Status register one. 6.9.8 Check Error Interrupt Enable While this one, IRQ# signal will asserted while CHECK ERROR Status register one. 6.9.9 Parity Error Interrupt Enable While this one, IRQ# signal will asserted while PARITY ERROR Status register one.
6.10
Status
Dest Result Cmnd Source FIFO Cmnd/ Data Dest Check Parity FIFO Result Ready Ready Ready Ready Overun Error Overun Error Error
Reserved
Cmnd Result Prog. Prog.
Reserved
This register read written. used monitor status chip. default value bits this register valid values quiescent chip, listed under each description. 6.10.1 Result Ready This when result ready read from Result Stack. This cleared writing this bit. This also cleared reading first word Result Stack. When cleared, this will again until result next command ready read (after reading words current result). default value this zero. 6.10.2 Command Ready This when Command Stack ready accept command. This cleared writing this bit. This also cleared writing first word Command Stack. When cleared, this will again until chip ready accept another command (after writes current command have been written). default value this one. 6.10.3 Source FIFO Ready This when available space Source FIFO exceeds threshold programmed FIFO Configuration register (when DREQ# signal source FIFO port active). Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
This zero when source FIFO full (when DREQ#signal inactive). Source FIFO Data Flow section more information regarding this bit. This must before FIFO Status Register will contain valid value SOURCE FIFO field. source port, then DREQ# signal used. functional timing SOURCE FIFO READY remains same there were DREQ# signal). This cleared writing this bit. default value this zero. 6.10.4 Dest FIFO Ready This when number bytes Dest FIFO exceeds threshold programmed FIFO Configuration register (when DREQ# signal dest FIFO port active). This zero when dest FIFO empty (when DREQ#signal inactive). Dest FIFO Data Flow section more information regarding this bit. This must before FIFO Status Register will contain valid value DEST FIFO field. dest port, then DREQ# signal used. functional timing DEST FIFO READY remains same there were DREQ# signal). This cleared writing this bit. default value this zero. 6.10.5 Command/Result Overrun This Command Stack written when ready, Result Stack read when ready. This error condition will affect command operation, command successfully queued. However, commands written until this status cleared. This cleared writing this bit. default value this zero. 6.10.6 Data Error This Source FIFO written when ready, Dest FIFO read when ready. This applies Port (Port Port Port). This error condition will cause automatic execution Stop command. current command will terminate soon source FIFO becomes empty. Stop command description Command Stack additional information. Also, queued commands will cleared. commands written until this status cleared. When this set, DATA ERROR Result Stack will also one. DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
This cleared writing this bit. default value this zero. 6.10.7 Dest Overrun This command produced more data than expected. dest counter attempted decrement below zero, IGNORE DEST COUNT zero. When dest counter attempted decrement below zero, command continue process incoming data, additional data output dest FIFO. This cause command terminate. dest counter will remain zero. This cleared writing this bit. default value this zero. 6.10.8 Check Error This check value calculated current block data does match check field embedded data stream. This error also reported CHECK ERROR Result Stack register This cleared writing this bit. default value this zero. 6.10.9 Parity Error This parity error detected. This error also reported PARITY ERROR Result Stack register. This cleared writing this bit. default value this zero. 6.10.10 Command Progress This indicates that command currently middle being written read. This becomes after first access Command Stack register. This returns zero after last (sixth) access Command Stack register. default value this zero. 6.10.11 Result Progress This indicates that result currently middle being read. This becomes after first read from Result Stack register. This returns zero after last (sixth) read from Result Stack register. default value this zero. 6.10.12 Chip When ChipID (bit Configuration register set, this register returns Chip value 0x02XX. upper bits defined product code lower bits reserved.
Page DS-0012-01 DATA SHEET
9610 Data Compression Processor Setting ChipID allows only read this register. ChipID value read again ChipID Configuration register must again.
6.11
FIFO Status
Rsrvd
Source FIFO
Rsrvd
Dest FIFO
This read-only register. used determine number bytes residing source FIFO dest FIFO. During normal operation, interface should used transfer data source FIFO from dest FIFO. Therefore, this register should only used under special conditions, testing. Settling time required between source dest FIFO transfers reading this register. There must clocks between last write source FIFO read SOURCE FIFO field this register, there must clocks between last write dest FIFO read DEST FIFO field this register. These clocks must slowest CLK, CLKC, CLKA CLKB. value this register latched each access 9610. value read always previously latched value. Therefore, unknown when previous access 9610 took place, user should read value this register twice, only second value. Except last transfer, actual number bytes transferred must bytes less than value read register. This will avoid completely filling emptying FIFOs, which negate SOURCE FIFO READY DEST FIFO READY bits generate data error condition. Source FIFO Dest FIFO each bytes size. 6.11.1 Source FIFO This field indicates number bytes available written source FIFO. example, source FIFO empty, this field will indicate default value this field undefined. SOURCE FIFO READY Status register must this register valid. 6.11.2 Dest FIFO This field indicates number bytes residing dest FIFO. example, dest FIFO empty, this field will indicate default value this field undefined. DEST FIFO READY Status register must this register valid.
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
6.12
FIFO Configuration
Reserved
Source FIFO Threshold
Reserved
Dest FIFO Threshold
This register read written. used configure FIFO thresholds which FIFO will begin request data transfer. This threshold used determine when FIFO ready status bits Status register will one. This optionally assert interrupt configured Configuration register. threshold also used determine when Interface logic will begin request block transfers. Product Overview section more information. 6.12.1 Source FIFO Threshold This field sets source FIFO Threshold. When number bytes available written source FIFO greater than value this field, SOURCE FIFO READY Status register will DREQ# signal source interface will become active. Source FIFO Data Flow section more information regarding this field. 9610 assumes minimum value source threshold field bytes 16-bit bus, bytes 32-bit bus. This assures that there least transfers that take place before source FIFO becomes full. 6.12.2 Dest FIFO Threshold This field sets dest FIFO Threshold. When number bytes residing dest FIFO greater than value this field, DEST FIFO READY Status register will DREQ# signal dest interface will become active. Dest FIFO Data Flow section more information regarding this field. 9610 will never assert DEST FIFO READY unless there least full transfer that take place (except last transfer command, which less than full width). addition, dest FIFO always keeps least transaction chip until very command. This give appearance that DEST FIFO READY asserted later than expected.
Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
Register Summary
Data
Data (D15-D0)
Command
Command Ignore Clear Source Ignore Rsrvd Check CRC/ Dest Hist Enable
Reserved
Reserved
Source Align
Dest Align
Source Port
Dest Port
Source Count (D31-D16)
Source Count (D15-D0)
Dest Count (D31-D16)
Dest Count (D15-D0)
Result
Reserved
Data Dest Check Parity Source Error Overun Error Error Marker Zero Check Value
Reserved
Source Count (D31-D16)
Source Count (D15-D0)
Dest Count (D31-D16)
Dest Count (D15-D0)
Configuration
Reserved
Port Width
Port Width
Port Port Reserv ChipID Parity Mode Mode Endian
Reserved
Interrupt Enable
Dest Result Source FIFO Cmnd/ Data Dest Check FIFO Ready Ready Ready Ready Result Error Overun Error Parity Overrn Error
Reserved
Status
Dest Result Source FIFO Cmnd/ Data Dest Check Parity FIFO Result Ready Ready Ready Ready Overun Error Overun Error Error
Reserved
Result Prog. Prog.
Reserved
FIFO Status
Rsrvd
Source FIFO
Rsrvd
Dest FIFO
FIFO Configuration
Reserved
Source FIFO Threshold
Reserved
Dest FIFO Threshold
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
Timing Description
Interface
busses configured Asynchronous Synchronous timing modes. This configured CPUMODE signal bus, PORT MODE PORT MODE bits Configuration register. following discussions (including timing section), signals DREQ# used place signals DREQ0, DREQ1, DACK0, DACK1. Furthermore signal used place signals TC0# TC1#. Generic terms used, because actual signals configured SOURCE PORT DEST PORT bits Command Stack.
DACK#
8.1.1 Asynchronous Mode Interface configured Asynchronous operation, interface driven internally frequency input pin. typical access consists setting ADDR signals prior assertion signal. ADDR signals must remain stable short time after trailing edge CS#. read cycle, 9610 will drive data with valid data after leading edge signal. data will become tri-state after trailing edge CS#. write cycle, data must valid before trailing edge signal. data must remain valid after trailing edge CS#. 8.1.2 Asynchronous Mode Interface configured Asynchronous operation, interface driven internally frequency input pin. typical transfer consists DREQ# being asserted 9610, then more assertions DACK# signal system initiate more transfers. minimum transfer time five cycles. start cycle controlled Controller with assertion DACK# signal. DREQ# signal must asserted previous DACK# being asserted. read cycle, 9610 will drive data with valid data after leading edge DACK# signal. data will become tri-state after trailing edge DACK# write cycle, data must valid before trailing edge DACK# signal. data must remain valid after trailing edge DACK# 9610 will deassert DREQ# signal after leading edge DACK# signal last transfer burst. source signal indicates last transfer Source FIFO current command. 9610 will assert signal after leading edge Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
DACK#
last transfer. 9610 will deassert signal after trailing edge DACK# last transfer.
dest signal indicates last transfer from Dest FIFO current command. 9610 will assert signal after leading edge DACK# last transfer. 9610 will deassert signal after trailing edge DACK# last transfer. NOALIGN BYTEALIGN signals will valid during DACK# last transfer. 8.1.3 Synchronous Mode Interface configured Synchronous operation, interface driven CLKC signal. signals relative rising edge CLKC. typical access consists clock cycles T2), with number wait states (Tw) between cycles. cycle with activity identified Synchronous mode supports minimum transfer time clock cycles. cycle identified assertion signal clock. R/W# Addr signals must valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will There number cycles (including zero). During cycle, data will active. Addr signals longer need valid. following clock cycle will either based value signal following clock cycle. active, then this cycle will inactive, then this cycle will During data transfer remains active. following clock cycle will either based value signal following cycle. active then this cycle will inactive then this cycle will There number cycles (including zero). During cycle, data will inactive. 8.1.4 Synchronous Mode Interface configured Synchronous operation, interface driven CLKA CLKB signals. signals relative rising edge CLKA CLKB. Synchronous mode will support minimum transfer time clock cycles. typical transfer consists clock cycles T2), with number wait states (Tw) between cycles. cycle with activity identified
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor start cycle controlled Controller with assertion DACK# signal. DREQ# signal must valid previous clock same clock) that DACK# signal asserted. There number clock cycles (including zero) between assertion DREQ# signal assertion DACK# signal. These will clock cycles. cycle identified assertion DACK# signal clock. following clock cycle will either based value DACK# signal following cycle. DACK# active, then this cycle will DACK# inactive, then this cycle will There number cycles (including zero). During cycle, data will active. following clock cycle will either based value DACK# signal following cycle. DACK# active, then this cycle will DACK# inactive, then this cycle will During data transfer remains active. following clock cycle will either based value DACK# signal following cycle. DACK# active then this cycle will DACK# inactive then this cycle will There number cycles (including zero). During cycle, data will inactive. 9610 will deassert DREQ# signal during next clock after last transfer burst. source signal indicates last transfer Source FIFO current command. 9610 will assert signal during clock following cycle last transfer. will remain asserted through cycle after cycle last transfer. destination signal indicates last transfer from Dest FIFO current command. 9610 will assert signal during clock following cycle last transfer. will remain asserted through cycle after cycle last transfer. NOALIGN BYTEALIGN signals will valid whenever dest signal active, beyond last cycle
Electrical Specifications
Supply Voltage (VDD) Input Voltage Input Current Operating Temperature Storage Temperature -0.3V +6.V -0.6 0.75V ±10mA -55°C +125°C -65°C +150°C
Caution: Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions affect device reliability.
Figure Absolute Maximum Ratings
Page DS-0012-01 DATA SHEET
9610 Data Compression Processor Supply Voltage Operating Temperature +4.75V +5.25V +70°C
Figure Recommended Operating Conditions Symbol Parameter level input voltage Schmitt negative threshold High level input voltage Schmitt positive threshold Schmitt hysteresis level CMOS input voltage High level CMOS input voltage level input current High level input current level output voltage High level output voltage High impedance leakage current Quiescent supply current Input capacitance Output capacitance Input/Output capacitance Power dissipation Power dissipation Conditions Units
4.75V 5.25V 5.25V 5.25V -4mA 5.25V
VIL(CLK) VIh(CLK)
COUT CI/O
5.25V =50MHz 5.25V =20MHz
0.75
Figure Electrical Characteristics Symbol Parameter Load interface Load Load other port pins Supply voltage Ground potential Ambient operating temperature
Alternate timings, Figure Figure
Conditions +70°C
Figure Specification Definition
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
Number
Timing Specifications
Units Reset width tCLOCK* First access after Reset tCLOCK* tCLOCK represents slowest clock frequency CLK, CLKC, CLKA, CLKB Description
RESET
Figure Reset Timing Number Description Oscillator frequency Clock period (see note Clock width high (see note Clock width (see note Clock rise time from Clock fall time from Units
Note period referred tCLK. CLKC period referred tCLKC. CLKA period referred tCLKA. CLKB period referred tCLKB. asynchronous mode will signal.
CLOCK
Figure External Clock Number Description Addr setup before active Addr hold after inactive R/W# setup before active active width inactive width R/W# hold after inactive Data valid after active (read) Data hold after inactive (read) Data setup before inactive (write) Data hold after inactive (write) tCLKC tCLKC Units
Figure Asynchronous Timing (Diagram next page)
Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
Addr
Read Operation R/W#
Data Write Operation R/W#
Data
Figure Asynchronous Timing Number Description active width DACK# inactive width DREQ# inactive after DACK# active inactive after DACK# inactive active after DACK# active Data valid after DACK# active (read) 50pF load Data hold after DACK# inactive (read) Data setup before DACK# inactive (write) Data hold after DACK# inactive (write)
DACK#
tCLKA tCLKA
tCLKA
Units
Note: References tCLKA apply Port timing. tCLKB Port timing.
DREQ#
DACK#
Read Operation Data Write Operation Data
Figure Asynchronous Timing DATA SHEET DS-0012-01 Page
9610 Data Compression Processor Number Description Addr setup Addr hold setup hold R/w# setup R/w# hold Data output valid delay (read) Data hold (read) Data setup (write) Data hold (write) Units
Requires additional wait state 50MHz clock
Access
Access wait state
CLKC
Addr
Read Operation R/W#
Data Write Operation R/W#
Data
Figure Synchronous Timing
Page DS-0012-01 DATA SHEET
9610 Data Compression Processor
Number
DREQ# output DREQ# hold DACK# setup DACK# hold output hold
Description valid delay
valid delay
Access wait state
Data output valid delay (read) 50pF load Data output valid delay (read) 20pF load Data hold (read) Data setup (write) Data hold (write) Access
Units
CLKA
DREQ#
DACK#
Read Operation Data Write Operation Data
Figure Synchronous Timing
DATA SHEET DS-0012-01 Page
9610 Data Compression Processor
31.9±0.25 28.0±0.1
0.3±0.1 3.32±0.15 0.65
0.8±0.15 1.95TYP units millimeters
Figure 144-pin PQFP package Page DS-0012-01 DATA SHEET
0.25
+0.25 -0.20
31.9±0.25
28.0±0.1
9610 Data Compression Processor
DB24 DB25 DB26 DB27 DB28 DB29 DB30 DB31 DA10 DA11 CLKA DA12 DA13 DA14 DA15
DB23 DB22 DB21 DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 CLKB DB12 DB11 DB10
DA16 DA17 DA18 DA19 DA20 DA21 DA22 DA23 DA24 DA25 DA26 DA27 DA28 DA29 DA30 DA31
XOUT NOALIGN RESET CPUMODE DACK1 DREQ1 DACK0 DREQ0 CLKC
Figure 144-pin PQFP pinout
DATA SHEET DS-0012-01 Page
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