Fast clock speed: 133, 100, Fast Access Times: 4.0/5.0/6.0 Single Cloc

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Fast clock speed: 133, 100, Fast Access Times: 4.0/5.0/6.0 Single Cloc

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DUAL DUAL ADDRESS SYNCHRONOUS SRAM
Fast clock speed: 133, 100, Fast Access Times: 4.0/5.0/6.0 Single Clock Operation Single 3.3V power supply Separate VCCQ output buffer chip enables simple depth expansion Address, Data Input, CE1X#, CE2X, CE1Y#, CE2Y, PTX#, PTY#, WEX#, WEY#, Data Output Registers On-Chip Concurrent Reads Writes Bi-Directional Data Buses Configured Separate Pass-Through Feature Asynchronous Output Enables (OEX#, OEY#) LVTTL Compatible Self-Timed Write Automatic power down 176-Pin TQFP Package
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
256K/128K SRAM
+3.3V SUPPLY, FULLY REGISTERED BI-DIRECTIONAL DATA BUSES
GENERAL DESCRIPTION
GVT81256P36/GVT81128P36 SRAM integrates 262,144x36/131,072x36 SRAM cells with advanced synchronous peripheral circuitry. employs high-speed, power CMOS designs using advanced triple-layer polysilicon, double-layer metal technology. Each memory cell consists four transistors high valued resistors. GVT81256P36/GVT81128P36 allows user concurrently perform reads, writes, pass-through cycles combination data ports. address ports (AX, determine read write locations their respective data ports (DQX, DQY). input pins except output enable pins (OEX#, OEY#) gated registers controlled positive-edge-triggered clock input (CLK). synchronous inputs include addresses, data inputs, depth-expansion chip enables (CE1X#, CE2X, CE1Y# CE2Y), pass-through controls (PTX# PTY#), read-write control (WEX# WEY#). pass-through feature allows data passed from port other, either direction. PTX# input must asserted pass data from port port PTY# will likewise pass data from port port pass-through operation takes precedence over read operation. case when same, certain protocols followed. both ports read, reads occur normally. port written other read, read from array will occur before data written. both ports written, only data will written array. GVT81256P36/GVT81128P36 operate from +3.3V power supply. inputs outputs LVTTL compatible. These dual I/O, dual address synchronous SRAMs well suited ATM, Ethernet switches, routers, cell/frame buffers, switches shared memory applications.
OPTIONS
Timing 4.0ns access/7.5ns cycle 5.0ns access/10.0 cycle 6.0ns access/12.0 cycle Packages 176-pin TQFP
MARKING
-7.5
Galvantech, Inc. 3080 Oakmead Village Drive, Santa Clara, 95051 (408) 566-0688 (408) 566-0699 Site www.galvantech.com
Rev. 12/9
Galvantech, Inc. reserves right chang products specifications without notice.
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
FUNCTIONAL BLOCK DIAGRAM
18/17 18/17
Address Register
256K/128K SRAM Array
Address Register
WEX# Write Register Write Driver Sensing Amplifiers Sensing Amplifiers Write Driver Write Register
WEY#
PTX#
Register
Pass-Through
Register
PTY#
Data Register
Output Register
Output Register
Data Register
CE1X# CE2X Chip Enable Register Chip Enable Register Chip Enable Register Chip Enable Register
CE1Y# CE2Y
OEX#
OEY#
Note: 256K devices, 18-bit wide bus; 128K devices, 17-bit wide bus.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
ASSIGNMENT (Top View)
DQY19 DQX19 VCCQ DQY18 DQX18 CE2Y CE1Y# OEY# OEX# CE2X CE1X# WEY# WEX# PTY# PTX# AX17* AY17* DQX17 DQY17 DQX16 DQY16 DQX20 DQY20 VCCQ DQX21 DQY21 DQX22 DQY22 VCCQ DQX23 DQY23 DQX24 DQY24 VCCQ DQX25 DQY25 DQX26 DQY26 DQY27 DQX27 DQY28 DQX28 VCCQ DQY29 DQX29 DQY30 DQX30 VCCQ DQY31 DQX31 DQY32 DQX32 VCCQ DQY33 DQX33
DQX15 DQY15 VCCQ DQX14 DQY14 DQX13 DQY13 VCCQ DQX12 DQY12 DQX11 DQY11 VCCQ DQX10 DQY10 DQX9 DQY9 DQY8 DQX8 DQY7 DQX7 VCCQ DQY6 DQX6 DQY5 DQX5 VCCQ DQY4 DQX4 DQY3 DQX3 VCCQ DQY2 DQX2
Notes:
AX17 AY17 pins 256K devices only. 128K devices, pins VSS.
September
Rev. 12/9
DQY34 DQX34 VCCQ DQY35 DQX35 AX10 AY10 AX11 AY11 AX12 AY12 AX13 AY13 AX14 AY14 AX15 AY15 AX16 AY16 DQX0 DQY0 VCCQ DQX1 DQY1
Galvantech, Inc. reserves right change products specifications without notice.
DESCRIPTIONS
TQFP PINS
169, 167, 145, 143, 168, 166, 144, 142, 100, 102, 106, 108, 113, 115, 119, 121, 125, 127, 131, 135, 139, 170, 174, 101, 103, 107, 109, 112, 114, 118, 120, 124, 126, 130, 134, 138, 171, 175,
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
SYMBOL
AX17
TYPE
InputSynchronous
DESCRIPTION
Synchronous Address Inputs Port AX17 256K devices only. allow addresses AX17 floating Synchronous Address Inputs Port AY17 256K devices only. allow addresses AY17 floating Read Write Port WEX# signal synchronous input that identifies whether current loaded cycle Read Write operation. Read Write Port WEY# signal synchronous input that identifies whether current loaded cycle Read Write operation. Pass-Through Port PTX# signal synchronous input that enables passing Port input Port output. Pass-Through Port PTY# signal synchronous input that enables passing Port input Port output. Asynchronous Output Enable Port OEX# must read data. When OEX# HIGH, DQXx pins high impedance state. Asynchronous Output Enable Port OEY# must read data. When OEY# HIGH, DQYx pins high impedance state. Data Inputs/Outputs Port Both data input path data output path registered triggered rising edge CLK.
AY17
InputSynchronous
WEX# WEY# OEX# OEY# DQX0 DQX35
InputSynchronous
InputSynchronous
InputSynchronous
InputSynchronous
Input Input Input/ Output
DQY0 DQY35
Input/ Output
Data Inputs/Outputs Port Both data input path data output path registered triggered rising edge CLK.
InputSynchronous
Clock: This clock input this device. Except OEX# OEY#, timing references address, data control signals device made with respect rising edge CLK. Synchronous Active Chip Enable Port CE1X# used with CE2X enable Port this device. CE1X# sampled HIGH rising edge clock initiates deselect cycle Port Synchronous Active High Chip Enable Port CE2X used with CE1X# enable Port this device. CE2X sampled rising edge clock initiates deselect cycle Port Synchronous Active Chip Enable Port CE1Y# used with CE2Y enable Port this device. CE1Y# sampled HIGH rising edge clock initiates deselect cycle Port Synchronous Active High Chip Enable Port CE2Y used with CE1Y# enable Port this device. CE2Y sampled rising edge clock initiates deselect cycle Port Power Supply: +3.3V +5%. Ground: GND.
CE1X#
InputSynchronous
CE2X
inputSynchronous
CE1Y#
InputSynchronous
CE2Y
inputSynchronous
110, 105, 111, 117, 123, 129, 136, 154, 161, 165, 132, 133, 165, 104, 116, 122, 128, 137, 159, 160, 162, 163,
Supply Ground
VCCQ
Ground Supply
Ground: GND. chip current flows through these pins. However, user needs connect these pins. Pins 128K device. Output Buffer Supply: +3.3V Connect: These signals internally connected. User connect them VCC, VSS, signal lines simply leave them floating.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
TRUTH TABLE (1-8)
OPERATION NUMBER
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
INPUT CLOCK
CE1X# CE2X CE1Y# CE2Y WEY# PTX# PTY#
OPERATION
DESELECT CYCLE DESELECT CYCLE WRITE PORT WRITE PORT PASS-THROUGH from PASS-THROUGH from READ PORT READ PORT
Note: means "don't care." means logic HIGH. means logic LOW. inputs except OEX# OEY# must meet setup hold times around rising edge (LOW HIGH) CLK. OEX# OEY# must asserted avoid contention during WRITE PASS-THROUGH cycles. WRITE PASS-THROUGH operation following READ operation, OEX#/OEY# must HIGH before input data required setup time plus High-Z time OEX#/OEY# staying HIGH throughout input data hold time. Operation number used combination. Operation number combined. Operation number combined with operation number because PASS-THROUGH operation higher priority over READ operation. Operation number combined with operation number because PASS-THROUGH operation higher priority over READ operation. This device contains circuitry that will ensure outputs will High-Z during power-up.
tn+1
ADDRESS CONTROL
VALID
PIPELINED READ
DATA INPUT
VALID
PASS-THROUGH
DATA OUTPUT
VALID
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
ABSOLUTE MAXIMUM RATINGS*
Voltage Supply Relative VSS.-0.5V +4.6V .-0.5V VCC+0.5V Storage Temperature (plastic).-55 +125o Temperature Under Bias.-10 Junction Temperature.+125 Power Dissipation.1.6W Short Circuit Output Current.20mA
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
*Stresses greater than those listed under "Absolute Maximum Ratings" cause permanent damage device.This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
ELECTRICAL CHARACTERISTICS RECOMMENDED OPERATING CONDITIONS
70°C; 3.3V unless otherwise noted)
CONDITIONS
Data Inputs (DQxx) Other Inputs
DESCRIPTION
Input High (Logic Voltage Input (Logic Voltage Input Leakage Current Output Leakage Current Output High Voltage Output Voltage Supply Voltage Supply Voltag
SYMBOL
-0.5
VCC+0.5
UNITS
NOTES
Output(s) disabled, -4.0mA 8.0mA 3.3V
3.135 3.135
3.465 3.465
VCCQ
DESCRIPTION
Power Supply Current: Operating CMOS Standby
CONDITIONS
Device selected; inputs IH;VCC =MAX; cycle time MIN; outputs open Device deselected; inputs +0.2 -0.2; MAX; cycle time
ISB1
-7.5
UNITS NOTES
Note: voltages referenced (GND). Overshoot: Undershoot: +6.0V -2.0V
given with output current. increases with greater output loading faster cycle times. "Device Deselected" means device POWER -DOWN mode defined truth table. "Device Selected" means device active.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
ELECTRICAL CHARACTERISTICS
(Note
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
3.3V +5%)
133MHz
DESCRIPTION
Cloc Clock cycle Clock HIGH time Clock Output Times Clock output valid Clock output invalid Clock output Low-Z Clock output High-Z OEX#/OEY# output valid OEX#/OEY# output Low-Z OEX#/OEY# output High-Z Setup Times Addresses, Controls Data Hold Times Addresses, Controls Data
KQLZ tKQH OELZ tOEHZ
100MHz
83MHz
UNITS NOTES
CAPACITANCE
DESCRIPTION
Input Capacitance Input/Output Capacitance (DQ)
CONDITIONS
3.3V
SYMBOL
UNITS
NOTES
THERMAL CONSIDERATIO
DESCRIPTION
Thermal Resistance Junction Ambient lfm) Single-Layer Board Thermal Resistance Junction Ambient lfm) Four-Layer Board Thermal Resistance Junction Board (Bottom) Thermal Resistance Junction Case (Top)
SYMBOL
TQFP
UNITS
NOTES
Note: This parameter sampled. Test conditions specified with output loading shown Fig. unless otherwise noted. Output loading specified with CL=5pF Fig. given temperature voltage condition, tKQHZ less than tKQLZ tOEHZ less than tOELZ. This synchronous device. synchronous inputs must meet specified setup hold time, except "don't care" defined truth table. Capacitance derating applies capacitance different from load capacitance shown Fig.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
TEST CONDITIONS Input pulse levels Input slew rate Input timing reference levels Output reference levels Output load 1.0V/ns 1.5V 1.5V Figures
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
OUTPUT LOADS 1.5V Fig. OUTPUT LOAD EQUIVALENT 3.3v
Fig. OUTPUT LOAD EQUIVALENT
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
READ CYCLE TIMING FROM BOTH PORTS (WEX#, WEY#, PTX#, PTY# HIGH
tOEQ
PORT
OEX#
OEHZ
(See Note)
Q(1)
Q(2)
Q(3)
Q(5)
Q(6)
Q(7)
tOELZ
PORT
OEY#
tKQHZ
tKQLZ
Q(12)
Q(13)
Q(14)
Q(16)
Q(6)
Q(7)
NOTE: Note: means (CE1X# CE1Y#) equals (CE2X CE2Y) equals HIGH. HIGH means (CE1X# CE1Y#) equals HIGH (CE2X CE2Y) equals LOW.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
WRITE CYCLE TIMING BOTH PORTS (PTX#, PTY# HIGH)
WEX# PORT OEX#
(See Note)
D(2)
D(3)
D(4)
D(8)
D(9)
WEY# PORT OEY#
D(14)
D(15)
D(5)
D(6)
D(18)
D(19)
PORT TAKES PRIORITY OVER PORT WHEN AX=AY WRITING BOTH PORTS.
Note:
means (CE1X# CE1Y#) equals (CE2X CE2Y) equals HIGH. HIGH means (CE1X# CE1Y#) equals HIGH (CE2X CE2Y) equals LOW.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
WRITE PORT PASS-THROUGH PORT (SEE NOTE)
WEX#
PORT
OEX#
PTY#
(See Note)
D(2)
D(3)
D(X)
D(Y)
D(6)
WEY#
PORT
OEY#
PTY#
KQHZ
Q(3)
D(X)
D(Y)
Q(17)
Note:NOTE:
means (CE1X# CE1Y#) equals (CE2X CE2Y) equals HIGH. HIGH means (CE1X# CE1Y#) equals HIGH (CE2X CE2Y) equals LOW.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
COMBINATION READ/WRITE WITH SAME ADDRESS EACH PORT
WRITE WRITE READ READ READ READ READ READ
WEX# PORT OEX#
D(ABC) D(DEF)
Q(PQR)
Q(XYZ)
Q(JKL)
WRITE
WRITE
READ
READ
READ
READ
READ
READ
WEY# PORT OEY#
D(PQR)
D(XYZ)
Q(PQR)
D(JKL)
Q(JKL)
PORT TAKES PRIORITY OVER PORT WHEN AX=AY WRITING BOTH PORTS. PTX# PTY# HIGH D(Value) Value input data port. Q(Value) Value output data port.
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
TQFP Package Dimensions
26.00 24.00
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
IDENT
24.00
26.00
1.40 0.05
1.60 Note: dimensions Millimeters
0.50 Basic
0.22 0.05
0.60 0.15
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9
GVT81256P36/GVT81128P36 256K/128K PIPELINED SRAM
Ordering Information 256K 81256P36
Galvantech Prefix Part Number Speed (7.5 4.0ns access/7.5ns cycle 5.0ns access/10.0ns cycle 6.0ns access/12.0ns cycle) Package TQFP)
128K 81128P36
Galvantech Prefix Part Number Speed (7.5 4.0ns access/7.5ns cycle 5.0ns access/10.0ns cycle 6.0ns access/12.0ns cycle) Package TQFP)
September
Galvantech, Inc. reserves right change products specifications without notice.
Rev. 12/9

Fast clock speed: 133, 100, Fast Access Times: 4.0/5.0/6.0 Single Cloc

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