PCnetTM- Home Single-Chip 1/10 Mbps Home Networking Controller DI
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Am79C978A
PCnetTM- Home Single-Chip 1/10 Mbps Home Networking Controller
DISTINCTIVE CHARACTERISTICS
Fully integrated Mbps HomePNA Physical Layer (PHY) defined Home Phoneline Networking Alliance (HomePNA) specification
Optimized home networking applications over ordinary copper telephone wire In-band control features endian little endian byte alignments supported Implements optional power management event (PME)
Adjustable power speed levels bits reserved in-band messaging piggybacked Ethernet packet
Register programmable features
Dual-speed CSMA/CD Mbps Mbps) Media Access Controller (MAC) compliant with IEEE/ANSI 802.3 Ethernet standard Compliant with HomePNA specification Media Independent Interface (MII) connecting external 10/100 Mbps transceivers
IEEE 802.3u compliant Intelligent Auto-Pollexternal status monitor interrupt Supports both auto-negotiable nonauto-negotiable external PHYs Supports 10BASE-T, 100BASETX/FX, 100BASET4, 100BASET2 IEEE 802.3 compliant PHYs full-duplex halfduplex
Power control Performance registers Speed control Major frame timing parameters programmable: ISBI, ISBI, pulse width, inter-symbol time Fully integrated Mbps interface
Comprehensive Auto-Negotiation implementation Full-duplex capability Optimized 10BASE-T applications
Integrated Fast Ethernet controller Peripheral Component Interconnect (PCI)
32-bit glueless host interface Supports clock frequency from independent network clock Supports network operation with clock from High performance mastering architecture with integrated Direct Memory Access (DMA) Buffer Management Unit utilization draft specification revision compliant Supports Subsystem/Subvendor Vendor programming through EEPROM interface Supports both 5.0-V 3.3-V signaling environments Plug Play compatible Supports unlimited burst length
Full-duplex operation supported port with independent Transmit (TX) Receive (RX) channels Supports PC98/PC99 specifications
Implements full OnNow features including pattern matching link status wake-up events Implements Magic Packetmode Magic Packet mode physical address loaded from EEPROM power without requiring clock Supports Power Management Interface specification revision Supports Advanced Configuration Power Interface (ACPI) specification version Supports Network Device Class Power Management specification version 1.0a
Independent internal FIFOs
Programmable FIFO watermarks both operations
Publication# 22399 Rev: Amendment/0 Issue Date: January 2000
Refer AMD's Website (www.amd.com) latest information.
frame queuing high latency host operation Programmable allocation buffer space between queues
allowing protocol analysis begin before receive frame
Includes Programmable Inter Packet (IPG) address less network aggressive controllers Offers Modified Back-Off algorithm address Ethernet Capture Effect IEEE 1149.1-compliant JTAG Boundary Scan test access port interface NAND tree test mode board-level production connectivity test Software compatible with AMD's PCnetFamily LANCE/C-LANCE register descriptor architecture Very power consumption +3.3 power supply along with tolerant I/Os enable broad system compatibility Available 144-pin TQFP 160-pin PQFP packages
Extensive programmable internal/external loopback capabilities EEPROM interface supports jumperless design provides through-chip programming
Supports full programmability half-/fullduplex operation through EEPROM mapping Programmable reset output capable resetting external without need buffering
Extensive programmable status support Look-Ahead Packet Processing (LAPP) data handling technique reduces system overhead
GENERAL DESCRIPTION
Am79C978A controller first series home networking products from AMD. Am79C978A controller fabricated advanced power CMOS process provide operating current power sensitive applications. Am79C978A controller contains Ethernet Controller based Am79C971 Fast Ethernet controller, physical layer device supporting 802.3 standard 10BASE-T, physical layer device data networking speeds Mbps over ordinary residential telephone wiring. integrated Ethernet controller highly integrated 32-bit full-duplex, 10/100 Mbps Ethernet controller solution designed address high-performance system application requirements. flexible busmastering device that used application, including network ready PCs. master architecture provides high data throughput system utilization. integrated Ethernet transceiver physical layer device suppor ting IEEE 802.3 standards 10BASE-T. provides layer functions required support Mbps data transfer speeds. integrated HomePNA transceiver physical layer device that enables data networking speeds Mbps over common residential phone wiring regardless topology without disrupting telephone (POTS) service. 32-bit multiplexed interface unit provides direct interface local bus, simplifying design Ethernet home network node system. device built-in support both little endian byte alignment. integrated home networking controller's advanced CMOS design allows interface connected either +5.0 +3.3 signaling environment. compliant IEEE 1149.1 JTAG test interface board level testing also provided, well NAND tree test structure those systems that support JTAG interface. integrated Am79C978A home networking controller also compliant with PC98, PC99, specifications. includes full implementation Microsoft OnNow ACPI specifications, which backward compatible with Magic Packet technology, compliant with Power Management Interface specification supporting four power management states (D0, D3), optional pin, necessary configuration data registers. integrated Am79C978A home networking controller complete Ethernet home network node integrated into single VLSI device. contains interface unit, Direct Memory Access (DMA) Buffer Management Unit, ISO/IEC 88023 (IEEE 802.3) compliant Media Access Controller (MAC), Transmit FIFO large Receive FIFO, IEEE 802.3u compliant MII. Both IEEE 802.3 compliant full-duplex half-duplex operations supported interface. 10/100 Mbps operation supported through interface. integrated Am79C978A home networking controller register compatible with LANCE (Am7990) C-LANCE (Am79C90) Ethernet controllers Ethernet controllers PCnet Family (except (Am79C960), PCnet-ISA+ (Am79C961), PCnet-ISA (Am79C961A), PCnet-32 (Am79C965A), PCnet-PCI (Am79C970), PCnet-PCI (Am79C970A), PCnet-
Am79C978A
FAST (Am79C971), PCnet-FAST+ (Am79C972). Buffer Management Unit supports LANCE PCnet descriptor software models. integrated Am79C978A controller supports autoconfiguration configuration space. Additional integrated controller configuration parameters, including unique IEEE physical address, read from
external non-volatile memory (EEPROM) immediately following system reset. addition, Am79C978A controller provides programmable on-chip drivers transmit, receive, collision, link integrity, Magic Packet status, speed, activity, power output, address match, full-duplex, Mbps status.
Am79C978A
BLOCK DIAGRAM
XTAL1
XTAL2
RXD(3:0)/TXD(3:0)
Clock Reference
MDIO
1Mbps HomePNA
Interface
Transmit State Machine
Drive Control HRTXRXP/N
AD[31:0] C/BE[3:0] FRAME TRDY IRDY STOP IDSEL DEVSEL PERR SERR INTA
Management
Receive State Machine
Analog Front
Control
Link Monitor
FIFO Interface Unit
FIFO
802.3 Core Interface
Mbps
SRAM
Transmit State Machine BASE-T
FIFO
FIFO
MDIO Management
Receive State Machine
FIFO Control
Network Port Manager
Link Monitor
Auto Negotiation
Buffer Management Unit Control
Control
LED0 LED1 LED2 LED3 LED4 EECS EESK EEDI EEDO
JTAG Port Control
OnNow Power Management Unit
93C46 EEPROM Interface
22399A-1
Am79C978A
TABLE CONTENTS
AM79C978A. DISTINCTIVE CHARACTERISTICS GENERAL DESCRIPTION BLOCK DIAGRAM TABLE CONTENTS RELATED PRODUCTS CONNECTION DIAGRAM (144 TQFP) CONNECTION DIAGRAM (160 PQFP). DESIGNATIONS (PQL144) Listed Number DESIGNATIONS (PQR160) Listed Number DESIGNATIONS (PQL144) Listed Group DESIGNATIONS (PQR160) Listed Group DESIGNATIONS Listed Driver Type. ORDERING INFORMATION Standard Products DESCRIPTIONS Interface Magic Packet Interface Board Interface EEPROM Interface Interface IEEE 1149.1 (1990) Test Access Port Interface. Ethernet Network Interfaces HomePNA Network Interface Clock Interface External Crystal Characteristics. Power Supply. BASIC FUNCTIONS System Interface. Software Interface Network Interfaces Media Independent Interface 10BASE-T JTAG Configuration Information. Slave Interface Unit Slave Configuration Transfers Slave Transfers Expansion Transfers. Slave Cycle Termination Parity Error Response Master Interface Unit Buffer Management Unit Software Interrupt Timer 10/100 Media Access Controller Transmit Operation Receive Operation Loopback Operation PHY/MAC Interface 10BASE-T Physical Layer Auto-Negotiation DETAILED FUNCTIONS
Am79C978A
Mbps HomePNA PHY. HomePNA Medium Interface. Management Interfaces EEPROM Interface Support Power Savings Mode Magic Packet Mode IEEE 1149.1 (1990) Test Access Port Interface. NAND Tree Testing Reset Software Access USER ACCESSIBLE REGISTERS Configuration Registers Register .108 Control Status Registers (CSRs) .109 Configuration Registers (BCRs) .143 10BASE-T Management Registers (TBRs) .177 Mbps HomePNA Internal Registers .187 Initialization Block .195 Receive Descriptors. .197 Transmit Descriptors .200 REGISTER SUMMARY .204 Configuration Registers .204 Control Status Registers .205 Configuration Registers .209 10BASE-T Management Registers .210 Mbps HomePNA Management Registers. REGISTER PROGRAMMING SUMMARY .212 Am79C978A Programmable Registers .212 ABSOLUTE MAXIMUM RATINGS .217 OPERATING RANGES .217 Commercial Devices .217 CHARACTERISTICS OVER COMMERCIAL OPERATING RANGES UNLESS OTHERWISE SPECIFIED .217 SWITCHING CHARACTERISTICS: INTERFACE .219 10BASE-T Mode .221 Power Supply Current .221 External Clock .222 Interface .222 10BASE-T .223 SWITCHING CHARACTERISTICS: MEDIA INDEPENDENT INTERFACE .224 SWITCHING WAVEFORMS .225 Switching Waveforms .225 SWITCHING TEST CIRCUITS .225 SWITCHING WAVEFORMS: SYSTEM INTERFACE .226 SWITCHING WAVEFORMS: MEDIA INDEPENDENT INTERFACE .230 PHYSICAL DIMENSIONS* .232 PQL144 .232 Thin Quad Flat Pack (measured millimeters). .232 PQR160 .233 Plastic Quad Flat Pack (measured millimeters) .233 APPENDIX ALTERNATIVE METHOD INITIALIZATION .A-1 APPENDIX LOOK AHEAD PACKET PROCESSING (LAPP) CONCEPT .B-1 Introduction Outline LAPP Flow. INDEX Index-1
Am79C978A
LIST FIGURES Figure Media Independent Interface Figure Frame Format Interface Connection Figure Slave Configuration Read Figure Slave Configuration Write Figure Slave Read Using Command Figure Slave Write Using Memory Command Figure Expansion Read Figure Disconnect Slave Cycle When Busy Figure Disconnect Slave Burst Transfer Host Wait States Figure Disconnect Slave Burst Transfer Host Inserts Wait States Figure Address Parity Error Response Figure Slave Cycle Data Parity Error Response Figure Acquisition Figure Non-Burst Read Transfer Figure Burst Read Transfer (EXTREQ MEMCMD Figure Non-Burst Write Transfer Figure Burst Write Transfer (EXTREQ Figure Disconnect With Data Transfer Figure Disconnect Without Data Transfer Figure Target Abort Figure Preemption During Non-Burst Transaction Figure Preemption During Burst Transaction Figure Master Abort Figure Master Cycle Data Parity Error Response Figure Initialization Block Read Non-Burst Mode Figure Initialization Block Read Burst Mode Figure Descriptor Ring Read Non-Burst Mode Figure Descriptor Ring Read Burst Mode Figure Descriptor Ring Write Non-Burst Mode Figure Descriptor Ring Write Burst Mode Figure FIFO Burst Write Start Unaligned Buffer Figure FIFO Burst Write Unaligned Buffer Figure 16-Bit Software Model Figure 32-Bit Software Model Figure 8802-3 (IEEE/ANSI 802.3) Data Frame Figure IEEE 802.3 Frame Length Field Transmission Order Figure 10BASE-T Transmit Receive Data Paths Figure HomePNA Framing Figure Symbol Transmit Timing Figure Symbol Receive Timing Figure Transmit Data Symbol Timing Figure Receive Symbol Timing Figure Coding Tree Figure Block Diagram SRAM Configuration Figure Block Diagram Latency Receive Configuration Figure Control Logic Figure OnNow Functional Diagram Figure Pattern Match Figure NAND Tree Circuitry (160 PQFP) Figure NAND Tree Waveform Figure Address Match Logic Figure Clock Timing Figure Interface Timing (PECL) Figure Mbps Transmit (TX±) Timing Diagram Figure Mbps Receive (RX±) Timing Diagram Figure Normal Tri-State Outputs Figure Waveform Signaling Am79C978A
Figure Waveform Signaling .226 Figure Input Setup Hold Timing .226 Figure Output Valid Delay Timing .227 Figure Output Tri-State Delay Timing .227 Figure EEPROM Read Functional Timing .227 Figure Automatic PREAD EEPROM Timing .228 Figure JTAG (IEEE 1149.1) Waveform Signaling .228 Figure JTAG (IEEE 1149.1) Test Signal Timing .229 Figure Transmit Timing .230 Figure Receive Timing .230 Figure Waveform .230 Figure Management Data Setup Hold Timing .231 Figure Management Data Output Valid Delay Timing .231 Figure B-1. LAPP Timeline Figure B-2. LAPP Buffer Grouping Figure B-3. LAPP Timeline Two-Interrupt Method Figure B-4. LAPP Buffer Grouping Two-interrupt Method B-10 LIST TABLES Table Interrupt Flags Table External Clock/Crystal Select Table Crystal Characteristics Table Device Table Software Configuration Table Slave Commands Table Slave Configuration Transfers Table Master Commands Table Descriptor Read Sequence Table Descriptor Write Sequence Table Receive Address Match Table Auto-Negotiation Capabilities Table HomePNA Pulse Parameters Table Access Symbol Pulse Positions Encoding Table Blanking Interval Speed Settings Table Master Station Control Word Functions Table Slave Station Control Word Status Conditions Table Control Frame Format Table EEPROM Table Default Configuration Table IEEE 1149.1 Supported Instruction Summary Table Mode Operation Table Device Register Table NAND Tree Sequence (160 PQFP) Table NAND Tree Sequence (144 TQFP) Table Configuration Space Layout Table Word Mode (DWIO Table Legal Accesses Word Mode (DWIO Table DWord Mode (DWIO Table Legal Accesses Double Word Mode (DWIO Table Loopback Configuration .125 Table Software Styles .133 Table Receive Watermark Programming .136 Table Transmit Start Point Programming .136 Table Transmit Watermark Programming .137 Table Registers .144 Table ROMTNG Programming Values .154 Table Select Programming .157
Am79C978A
Table EEDET Setting .159 Table Interface Assignment .159 Table Software Styles .161 Table SRAM_BND Programming .163 Table EBCS Values .164 Table CLK_FAC Values .165 Table FMDC Values .168 Table APDW Values .168 Table Am79C978A 10BASE-T Management Register .177 Table TBR0: 10BASE-T Control Register (Register .178 Table TBR1: 10BASE-T Status Register (Register .179 Table TBR2: 10BASE-T Identifier (Register .180 Table TBRM0BASE-T Identifier (Register .180 Table TBR4: 10BASE-T Auto-Negotiation Advertisement Register (Register .181 Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Base Page Format .182 Table TBR5: 10BASE-T Auto-Negotiation Link Partner Ability Register (Register Next Page Format .182 Table TBR6: 10BASE-T Auto-Negotiation Expansion Register (Register .183 Table TBR7: 10BASE-T Auto-Negotiation Next Page Register (Register .183 Table TBR16: 10BASE-T INTERRUPT Status Enable Register (Register .184 Table TBR17: 10BASE-T Control/Status Register (Register .185 Table TBR19: 10BASE-T Management Extension Register (Register .186 Table TBR24: 10BASE-T Summary Status Register (Register .186 Table HPR0: HomePNA Control (Register .187 Table HPR1: HomePNA Status (Register .188 Table HPR2 HPR3: HomePNA (Registers .189 Table HPR4-HPR7: HomePNA Auto-Negotiation (Registers .189 Table HPR16: HomePNA Control (Register .190 Table HPR18 HPR19: HomePNA TxCOMM (Registers .191 Table HPR20 HPR21: HomePNA RxCOMM (Registers .191 Table HPR22: HomePNA (Register .192 Table HPR23: HomePNA Noise Control (Register .192 Table HPR24: HomePNA Noise Control (Register .192 Table HPR25: HomePNA Noise Statistics (Register .193 Table HPR26: HomePNA Event Status (Register .193 Table HPR27: HomePNA Event Status (Register .194 Table HPR8: HomePNA ISBI Control (Register .194 Table HPR29: HomePNA Control (Register .194 Table Initialization Block (SSIZE32 .195 Table Initialization Block (SSIZE32 .195 Table R/TLEN Decoding (SSIZE32 .196 Table R/TLEN Decoding (SSIZE32 .196 Table Receive Descriptor (SWSTYLE .197 Table Receive Descriptor (SWSTYLE .197 Table Receive Descriptor (SWSTYLE .197 Table Transmit Descriptor (SWSTYLE .200 Table Transmit Descriptor (SWSTYLE .200 Table Transmit Descriptor (SWSTYLE .200 Table Configuration Registers .204 Table 10BASE-T Management Registers (TBRs) .210 Table Mbps HomePNA Management Registers (HPRs) .211 Table Control Status Registers .212 Table Configuration Registers .214 Table A-1. Registers Alternative Initialization Method (Note
Am79C978A
RELATED PRODUCTS
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Integrated Repeater/Hub Devices Am79C981 Am79C982 Am79C983A Am79C984A Am79C985 Am79C987 Integrated Multiport Repeater Plus (IMR+) Basic Integrated Multiport Repeater (bIMR) Integrated Multiport Repeater (IMR2TM) Enhanced Integrated Multiport Repeater (eIMRTM) Enhanced Integrated Multiport Repeater Plus (eIMR+TM) Hardware Implemented Management Information Base (HIMIBTM)
Am79C978A
CONNECTION DIAGRAM (PQL 144)
IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12
C/BE3 AD24 AD25 VSSB AD26 VDD_PCI AD27 AD28 AD29 AD30 VSSB AD31 VDD_PCI PCI_CLK INTA VSSB VAUXDET EECS VSSB EESK/LED1 LED2 VDDB EEDI/LED0 EEDO/LED3
Am79C978A PCnet-Home
RXDVDDRX DVSSX TXDVDDTX DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 XCLK/XTAL LED4 MDIO VSSB RXD3 RXD2 VDDB RXD1 RXD0
AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV
22399A-2
Am79C978A
CONNECTION DIAGRAM (160 PQFP)
IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12
C/BE3 AD24 AD25 VSSB AD26 VDD_PCI AD27 AD28 AD29 AD30 VSSB AD31 VDD_PCI PCI_CLK INTA VSSB VAUXDET EECS VSSB EESK/LED1 LED2 VDDB EEDI/LED0 EEDO/LED3
Am79C978A PCnet-Home
RXDVDDRX DVSSX TXDVDDTX DVDDD IREF DVSSD DVSSA DVDDA PHY_RST DVDDA_HR VSSB VDDB HRTRXP VDDHR HRTRXN VSSHR VDDCO XTAL1 XTAL2 XCLK/XTAL LED4 MDIO VSSB RXD3 RXD2 VDDB RXD1 RXD0
AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV
22399A-3
Am79C978A
DESIGNATIONS (PQL144) Listed Number
Name IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12 Name AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV Name RXD0 RXD1 VDDB RXD2 RXD3 VSSB MDIO LED4 XCLK/XTAL XTAL2 XTAL1 VDDCO VSSHR HRTRXN VDDHR HRTRXP VDDB VSSB DVDDA_HR PHY_RST DVDDA DVSSA DVSSD IREF DVDDD DVDDTX TXDVSSX DVDDRX RXPin Name EEDO/LED3 EEDI/LED0 VDDB LED2 EESK/LED1 VSSB EECS VAUXDET VSSB INTA PCI_CLK VDD_PCI AD31 VSSB AD30 AD29 AD28 AD27 VDD_PCI AD26 VSSB AD25 AD24 C/BE3
Am79C978A
DESIGNATIONS (PQR160) Listed Number
Name IDSEL AD23 VSSB AD22 VDD_PCI AD21 AD20 AD19 AD18 VSSB AD17 VDD_PCI AD16 C/BE2 FRAME IRDY VSSB TRDY VDD_PCI DEVSEL STOP PERR SERR VSSB VDD_PCI C/BE1 AD15 AD14 AD13 VSSB AD12 Name AD11 VDD_PCI AD10 C/BE0 VSSB VDD_PCI VSSB VDD_PCI VSSB TXD3 TXD2 TXD1 VDDB TXD0 TX_EN TX_CLK VSSB RX_ER RX_CLK RX_DV Name RXD0 RXD1 VDDB RXD2 RXD3 VSSB MDIO LED4 XCLK/XTAL XTAL2 XTAL1 VDDCO VSSHR HRTRXN VDDHR HRTRXP VDDB VSSB DVDDA_HR PHY_RST DVDDA DVSSA DVSSD IREF DVDDD DVDDTX TXDVSSX DVDDRX RXPin Name EEDO/LED3 EEDI/LED0 VDDB LED2 EESK/LED1 VSSB EECS VAUXDET VSSB INTA PCI_CLK VDD_PCI AD31 VSSB AD30 AD29 AD28 AD27 VDD_PCI AD26 VSSB AD25 AD24 C/BE3
Am79C978A
DESIGNATIONS (PQL144) Listed Group
Pins
Name HomePNA Network Ports HRTXRXP/N XTAL1 XTAL2 XCLK/XTAL IREF PHY_RST TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDIO Magic Packet Host Interface PCI_CLK C/BE[3:0] AD[31:0] DEVSEL FRAME IDSEL INTA IRDY PERR SERR Clock Transmit Clock Transmit Data Transmit Enable Receive Clock Receive Data Receive Error
Function Receive/Transmit Data Crystal Input XTAL/60 CLK) Crystal Output XTAL) Oscillator/Crystal Select Serial Transmit Data Serial Receive Data Tied resistor Buffered signal
Type
Voltage 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
Driver XTAL OMII1 OMII1 OMII1 OMII2 TSMII STS6 STS6 STS6 STS6 STS6
10BASE-T Network Ports
Receive Data Valid Management Data Clock Management Data Carrier Sense Collision Power Management Event Power Good
Command Byte Enable Address/Data Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Parity Parity Error Request Reset System Error
Am79C978A
Name STOP TRDY EECS EEDI/LED0 EESK/LED1 LED2 EEDO/LED3 LED4 TCLK Power/Ground DVDDTX DVDDRX VDD_PCI VDDB VDDHR DVDDA DVDDD VDDCO DVDDA_HR DVSSD DVSSA DVSSX VSSB VSSHR Stop Target Ready Chip Select Data In/LED0 Serial Clock/LED1 LED2 Data Out/LED3 LED4 Test Clock Test Mode Select Test Data Test Data
Function
Type
Voltage 3.3/5 3.3/5
Driver STS6 STS6
Pins
EEPROM/LED Interface
Test Access Port Interface (JTAG)
Transceiver Digital Power Transceiver Digital Power Digital Power Digital Power Digital Power Digital Power HomePNA Transceiver Analog Power Transceiver Digital Power Crystal Oscillator Power Transceiver Analog Power Transceiver Digital Ground Transceiver Analog Ground Transceiver Ground Digital Ground Digital Ground HomePNA Analog Ground
Am79C978A
DESIGNATIONS (PQR160) Listed Group
Pins
Name HomePNA Network Ports HRTXRXP/N XTAL1 XTAL2 XCLK/XTAL IREF PHY_RST TX_CLK TXD[3:0] TX_EN RX_CLK RXD[3:0] RX_ER RX_DV MDIO Magic Packet Host Interface PCI_CLK C/BE[3:0] AD[31:0] DEVSEL FRAME IDSEL INTA IRDY PERR SERR Clock Transmit Clock Transmit Data Transmit Enable Receive Clock Receive Data Receive Error
Function Receive/Transmit Data Crystal Input XTAL/60 CLK) Crystal Output XTAL) Oscillator/Crystal Select Serial Transmit Data Serial Receive Data Tied resistor Buffered signal
Type
Voltage 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5 3.3/5
Driver XTAL OMII1 OMII1 OMII1 OMII2 TSMII STS6 STS6 STS6 STS6 STS6
10BASE-T Network Ports
Receive Data Valid Management Data Clock Management Data Carrier Sense Collision Power Management Event Power Good
Command Byte Enable Address/Data Device Select Cycle Frame Grant Initialization Device Select Interrupt Initiator Ready Parity Parity Error Request Reset System Error
Am79C978A
Name STOP TRDY EECS EEDI/LED0 EESK/LED1 LED2 EEDO/LED3 LED4 TCLK Power/Ground DVDDTX DVDDRX VDD_PCI VDDB VDDHR DVDDA DVDDD VDDCO DVDDA_HR DVSSD DVSSA DVSSX VSSB VSSHR Stop Target Ready Chip Select Data In/LED0 Serial Clock/LED1 LED2 Data Out/LED3 LED4 Test Clock Test Mode Select Test Data Test Data
Function
Type
Voltage 3.3/5 3.3/5
Driver STS6 STS6
Pins
EEPROM/LED Interface
Test Access Port Interface (JTAG)
Transceiver Digital Power Transceiver Digital Power Digital Power Digital Power Digital Power Digital Power HomePNA Transceiver Analog Power Transceiver Digital Power Crystal Oscillator Power Transceiver Analog Power Transceiver Digital Ground Transceiver Analog Ground Transceiver Ground Digital Ground Digital Ground HomePNA Analog Ground
Am79C978A
DESIGNATIONS Listed Driver Type
following table describes various types output drivers used Am79C978A controller. values shown table apply signaling.
sustained tri-state signal active signal that driven high clock period before left floating. differential output driver. characteristics those XTAL2 output described CHARACTERISTICS section.
Driver Name STS6 OMII1 OMII2 TSMII Totem Pole Open Drain Tri-State Tri-State
Type
(mA)
(mA)
Load (pF)
Sustained Tri-State Tri-State Tri-State Tri-State
Am79C978A
ORDERING INFORMATION Standard Products
standard products available several packages operating ranges. order number (Valid Combination) formed combination elements below.
AM79C978A
ALTERNATE PACKAGING OPTION Trimmed formed tray TEMPERATURE RANGE Commercial (0°C +70°C) PACKAGE TYPE Plastic Quad Flat Pack (PQR160) Thin Quad Flat Pack (PQL144) SPEED OPTION applicable
DEVICE NUMBER/DESCRIPTION AM79C978A PCnet-Home Single-Chip 1/10 Mbps Home Networking Controller
Valid Combinations AM79C978A KC\W VC\W
Valid Combinations Valid Combinations list configurations planned supported volume this device. Consult local sales office confirm availability specific valid combinations check newly released combinations.
Am79C978A
DESCRIPTIONS Interface AD[31:0]
Address Data Input/Output Address data multiplexed same interface pins. During first clock transaction, AD[31:0] contain physical address bits). During subsequent clocks, AD[31:0] contain data. Byte ordering little endian default. AD[7:0] defined least significant byte (LSB) AD[31:24] defined most significant byte (MSB). FIFO data transfers, Am79C978A controller programmed endian byte ordering. CSR3, (BSWP) more details. During address phase transaction, when Am79C978A controller master, AD[31:2] will address active Double Word (DWord). Am79C978A controller always drives AD[1:0] "00" during address phase indicating linear burst order. When Am79C978A controller master, AD[31:0] lines continuously monitored determine address match exists slave transfers. During data phase transaction, AD[31:0] driven Am79C978A controller when performing master write slave read operations. Data AD[31:0] latched Am79C978A controller when performing master read slave write operations. When active, AD[31:0] inputs NAND tree testing.
networ king demands. Am79C978A controller will suppor clock frequency after certain precautions taken ensure data integrity. This clock derivation used drive network functions. When active, PCI_CLK input NAND tree testing.
DEVSEL
Device Select Input/Output Am79C978A controller drives DEVSEL when detects transaction that selects device target. device samples DEVSEL detect target claims transaction that Am79C978A controller initiated. When active, DEVSEL input NAND tree testing.
FRAME
Cycle Frame Input/Output FRAME driven Am79C978A controller when master indicate beginning duration transaction. FRAME asserted indicate transaction beginning. FRAME asserted while data transfers continue. FRAME deasserted before final data phase transaction. When Am79C978A controller slave mode, samples FRAME determine address phase transaction. When active, FRAME input NAND tree testing.
C/BE[3:0]
Command Byte Enables Input/Output command byte enables multiplexed same interface pins. During address phase transaction, C/BE[3:0] define command. During data phase, C/BE[3:0] used byte enables. byte enables define which physical byte lanes carry meaningful data. C/BE0 applies byte (AD[7:0]) C/BE3 applies byte (AD[31:24]). function byte enables independent byte ordering mode (BSWP, CSR3, When active, C/BE[3:0] inputs NAND tree testing.
Grant Input This signal indicates that access been granted Am79C978A controller. Am79C978A controller supports parking. When idle system arbiter Am79C978A controller, device will drive AD[31:0], C/BE[3:0], lines. When active, input NAND tree testing.
IDSEL
Initialization Device Select Input Am79C978A controller during configuration read write transactions. When active, IDSEL input NAND tree testing.
PCI_CLK
Clock Input This clock used drive system interface internal buffer management unit. signals sampled rising edge PCI_CLK parameters defined with respect this edge. Am79C978A controller normally operates over frequency range
Am79C978A
INTA
Interrupt Request Output attention signal which indicates that more following status flags set: EXDINT, IDON, MERR, MISS, MFCO, MPINT, RCVCCO, RINT, SINT, TINT, TXSTRT, UINT, MCCINT, MPDTINT, MAPINT, MREINT, STINT. Each status flag either mask enable which allows suppression INTA assertion. Table shows flag descriptions. default INTA open-drain output. applications that need high-active edge-sensitive interrupt signal, INTA configured this mode setting INTLEVEL (BCR2, Table When active, INTA output NAND tree testing. Table
Name EXDINT IDON MERR MISS MFCO MPINT RCVCCO RINT SINT TINT TXSTRT UINT Description Excessive Deferral Initialization Done Memory Error
IRDY
Initiator Ready Input/Output IRDY indicates ability initiator transaction complete current data phase. IRDY used conjunction with TRDY. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C978A controller master, asserts IRDY during write data phases indicate that valid data present AD[31:0]. During read data phases, device asserts IRDY indicate that ready accept data. When Am79C978A controller target transaction, checks IRDY during write data phases determine valid data present AD[31:0]. During read data phases, device checks IRDY determine initiator ready accept data. When active, IRDY input NAND tree testing.
Interrupt Flags
Mask CSR5, CSR3, CSR3, Interrupt CSR5, CSR0, CSR0, CSR0, CSR4, CSR5, CSR4, CSR0, CSR5, CSR0, CSR4, CSR4,
Parity Input/Output Parity even parity across AD[31:0] C/BE[3:0]. When Am79C978A controller master, generates parity during address write data phases. checks parity during read data phases. When Am79C978A controller operates slave mode, checks parity during every address phase. When target cycle, checks parity during write data phases generates parity during read data phases. When active, input NAND tree testing.
Missed Frame CSR3, Missed Frame CSR4, Count Overflow Magic Packet Interrupt CSR5,
Receive Collision Count CSR4, Overflow Receive Interrupt System Error Transmit Interrupt Transmit Start User Interrupt Management Command Complete Interrupt CSR3, CSR5, CSR3, CSR4, CSR4,
PERR
Parity Error Input/Output During slave write transaction master read transaction, Am79C978A controller asserts PERR when detects data parity error reporting error enabled setting PERREN (PCI Command register, During master write transaction, Am79C978A controller monitors PERR target reports data parity error. When active, PERR input NAND tree testing.
MCCINT
CSR7,
CSR7,
MPDTINT MAPINT
Detect CSR7, Transition Interrupt Auto-Poll Interrupt CSR7,
CSR7, CSR7,
Request Input/Output Am79C978A controller asserts signal that wishes become master. driven high when Am79C978A controller does request bus. Power Management mode, will driven.
MREINT
Management CSR7, Frame Read Error Interrupt Software Timer CSR7, Interrupt
CSR7,
STINT
CSR7,
Am79C978A
When active, input NAND tree testing.
Reset Input When asserted HIGH, then Am79C978A controller performs internal system reset type H_RESET (HARDWARE_RESET, section RESET). must held minimum clock periods. While H_RESET state, Am79C978A controller will disable deassert outputs. asynchronous clock when asserted deasserted. When LOW, disables pins except pin. When HIGH, NAND tree testing enabled.
When Am79C978A controller target transaction, asserts TRDY during read data phases indicate that valid data present AD[31:0]. During write data phases, device asserts TRDY indicate that ready accept data. When active, TRDY input NAND tree testing.
Magic Packet Interface
Power Management Event Output, Open Drain output that used indicate that power management event Magic Packet, OnNow pattern match, change link state) been detected. asserted when either PME_STATUS PME_EN both PME_EN_OVR MPMAT both PME_EN_OVR LCDET both
SERR
System Error Output During slave transaction, Am79C978A controller asserts SERR when detects address parity error, reporting error enabled setting PERREN (PCI Command register, SERREN (PCI Command register, default SERR open-drain output. component test, programmed active-high totem-pole output. When active, SERR input NAND tree testing.
signal asynchronous with respect clock. Power Saving Mode section detailed description.
VAUXDET
Auxiliary Power Detect Input VAUXDET used sense presence auxiliary power correctly report capability asserting signal cold. VAUXDET should connected auxiliary power supply ground through resistor. power used power device, pull-down resistor required. systems that provide auxiliary power, VAUXDET should tied auxiliary power through pull-up resistor.
STOP
Stop Input/Output slave mode, Am79C978A controller drives STOP signal inform master stop current transaction. master mode, Am79C978A controller checks STOP determine target wants disconnect current transaction. When active, STOP input NAND tree testing.
Power Good Input functions: puts device into Magic Packet mode, blocks resets when power off. When either MPPEN MPMODE device enters Magic Packet mode. When LOW, assertion will only cause interface pins (except PME) high impedance state. internal logic will ignore assertion RST. When HIGH, assertion causes controller logic reset configuration information loaded from EEPROM. Note: input should kept high during NAND tree testing.
TRDY
Target Ready Input/Output TRDY indicates ability target transaction complete current data phase. Wait states inserted until both IRDY TRDY asserted simultaneously. data phase completed clock when both IRDY TRDY asserted. When Am79C978A controller master, checks TRDY during read data phases determine valid data present AD[31:0]. During write data phases, device checks TRDY determine target ready accept data.
Am79C978A
Board Interface
Note: Before programming pins, description LEDPE BCR2,
LED0
LED0 Output This output designed directly drive LED. default, LED0 indicates active link connection. This also programmed indicate other network status (see BCR4). LED0 polarity programmable, default active LOW. When LED0 polarity programmed active LOW, output open drain driver. When LED0 polarity programmed active HIGH, output totem pole driver. Note: LED0 multiplexed with EEDI pin.
status (see BCR6). LED2 polarity programmable, default active LOW. When LED2 polarity programmed active LOW, output open drain driver. When LED2 polarity programmed active HIGH, output totem pole driver.
LED3
LED3 Output This output designed directly drive LED. default, LED3 indicates transmit activity network. This also programmed indicate other network status (see BCR7). LED3 polarity programmable, default active LOW. When LED3 polarity programmed active LOW, output open drain driver. When LED3 polarity programmed active HIGH, output totem pole driver. Special attention must given external circuitry attached this pin. When this used drive while EEPROM used system, then buffering required between LED3 circuit. circuit were directly attached this pin, create requirement that could serial EEPROM attached this pin. EEPROM included system design current LEDs used, then LED3 signal directly connected without buffering. more details regarding connection, section Support. Note: LED3 multiplexed with EEDO pin.
LED1
LED1 Output This output designed directly drive LED. default, LED1 indicates receive activity network. This also programmed indicate other network status (see BCR5). LED1 polarity programmable, default, active LOW. When LED1 polarity programmed active LOW, output open drain driver. When LED1 polarity programmed active HIGH, output totem pole driver. Note: LED1 multiplexed with EESK pin. LED1 also used during EEPROM AutoDetection determine whether EEPROM present Am79C978A controller interface. last rising edge while active LOW, LED1 sampled determine value EEDET BCR19. important maintain adequate hold time around rising edge this time ensure correctly sampled value. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pullup pull-down resistor must attached instead order ground EEDET setting. WARNING: input signal level LED1 must insured correct EEPROM detection before deassertion RST.
LED4
LED4 Output This output designed directly drive LED. This programmed indicate various network status (see BCR48). LED4 polarity programmable, default active LOW. When LED4 polarity programmed active LOW, output open drain driver. When LED4 polarity programmed active HIGH, output totem pole driver.
EEPROM Interface EECS
EEPROM Chip Select Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EECS connected EEPROM's chip select pin. controlled either Am79C978A controller during command portions read entire EEPROM, indirectly host system writing BCR19,
LED2
LED2 Output This output designed directly drive LED. This programmed indicate various network
Am79C978A
EEDI
EEPROM Data Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDI connected EEPROM's data input pin. controlled either Am79C978A controller during command portions read entire EEPROM, indirectly host system writing BCR19, Note: EEDI multiplexed with LED0 pin.
RX_ER signals into Am79C978A device. RX_CLK must provide nibble rate clock (25% network data rate). Hence, when Am79C978A device operating Mbps, provides RX_CLK frequency MHz, Mbps provides RX_CLK frequency MHz.
RXD[3:0]
Receive Data Input RXD[3:0] nibble-wide MII-compatible receive data bus. Data RXD[3:0] sampled every rising edge RX_CLK while RX_DV asserted. RXD[3:0] ignored while RX_DV de-asserted.
EEDO
EEPROM Data Input This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EEDO connected EEPROM's data output pin. controlled either Am79C978A controller during command portions read entire EEPROM, indirectly host system reading from BCR19, Note: EEDO multiplexed with LED3 pin.
RX_DV
Receive Data Valid Input RX_DV input used indicate that valid received data being presented RXD[3:0] pins RX_CLK synchronous receive data. order frame fully received Am79C978A device, RX_DV must asserted prior RX_CLK rising edge, when first nibble Start Frame Delimiter driven RXD[3:0], must remain asserted until after rising edge RX_CLK, when last nibble driven RXD[3:0]. RX_DV must then deasserted prior RX_CLK rising edge which follows this final nibble. RX_DV transitions synchronous RX_CLK rising edges.
EESK
EEPROM Serial Clock Output This designed directly interface serial EEPROM that uses 93C46 EEPROM interface protocol. EESK connected EEPROM's clock pin. controlled either Am79C978A controller directly during read entire EEPROM, indirectly host system writing BCR19, Note: EESK multiplexed with LED1 pin. EESK also used during EEPROM AutoDetection determine whether EEPROM present Am79C978A controller interface. rising edge last edge while asserted, EESK sampled determine value EEDET BCR19. sampled HIGH value means that EEPROM present, EEDET will sampled value means that EEPROM present, EEDET will EEPROM Auto-Detection section more details. circuit attached this pin, then pull-up pull-down resistor must attached instead resolve EEDET setting. WARNING: input signal level EESK must valid correct EEPROM detection before deassertion RST.
Receive Carrier Sense Input input that indicates that non-idle medium, either transmit receive activity, been detected.
Collision Input input that indicates that collision been detected network medium.
RX_ER
Receive Error Input RX_ER input that indicates that transceiver device detected coding error receive data frame currently being transferred RXD[3:0] pins. RX_ER asserted while RX_DV asserted, error will indicated receive descriptor incoming receive frame. RX_ER ignored while RX_DV deasserted. Special code groups generated while RX_DV deasserted ignored (e.g., idle T4). RX_ER transitions synchronous RX_CLK.
Interface RX_CLK
Receive Clock Input RX_CLK clock input that provides timing reference transfer RX_DV, RXD[3:0],
Am79C978A
TX_CLK
Transmit Clock Input TX_CLK clock input that provides timing reference transfer TXD[3:0] TX_ER signals into Am79C978A device. TX_CLK must provide nibble rate clock (25% network data rate). Hence, when Am79C978A device operating Mbps, provides TX_CLK frequency MHz, Mbps provides RX_CLK frequency MHz.
MDIO should externally pulled with resistor.
IEEE 1149.1 (1990) Test Access Port Interface
Test Clock Input clock input boundary scan test mode operation. operate frequency to10 MHz. internal pull-up resistor.
TXD[3:0]
Transmit Data Output TXD[3:0] nibble-wide MII-compatible transmit data bus. Valid data generated TXD[3:0] every rising edge TX_CLK while TX_EN asserted. While TX_EN deasserted, TXD[3:0] values driven TXD[3:0] transitions synchronous rising edges TX_CLK
Test Data Input test data input path Am79C978A controller. internal pull-up resistor.
Test Data Output test data output path from Am79C978A controller. tri-stated when JTAG port inactive.
TX_EN
Transmit Enable Output TX_EN indicates when Am79C978A device presenting valid transmit nibbles TXD[3:0] bus. While TX_EN asserted, Am79C978A device generates TXD[3:0] TX_ER TX_CLK rising edges. TX_EN asserted with first nibble preamble remains asserted throughout duration packet until deasserted prior first TX_CLK following final nibble frame. TX_EN transitions synchronous TX_CLK.
Test Mode Select Input serial input stream used define specific boundary scan test executed. internal pull-up resistor.
Ethernet Network Interfaces
Serial Transmit Data Output These pins carry transmit output data connected transmit side magnetics module.
Management Data Clock Output non-continuous clock output that provides timing reference bits MDIO pin. During management port operations, runs nominal frequency MHz. When management operations progress, driven LOW. port selected, left floating.
Serial Receive Data Input These pins accept receive input data from magnetics module.
IREF
Internal Current Reference Input This serves current reference integrated 1/10 PHY. must connected through resistor (1%).
MDIO
Management Data Input/Output Input/Output MDIO bidirectional management port data pin. MDIO output during header portion management frame transfers during data portion write operations. MDIO input during data portion read operations. attached port physical connector then MDIO should externally pulled down with resistor. directly attached pins then
PHY_RST
Reset Output This output used reset external PHY. This output eliminates need fanout buffer reset (RST) signal, provided polarity control specific used, prevents resetting when input LOW. output polarity determined RST_POL (CRS116, bit0).
Am79C978A
HomePNA Network Interface HRTXRXP/HRTXRXN
Serial Receive Data Input/Output These pins accept receive input data from magnetics module carry transmit output data. 100-W resistor should placed between these pins.
Table
Parameter Parallel Resonant Frequency
Crystal Characteristics
0.022 Units
Resonant Frequency Error Change Resonant Frequency With Respect Temperature (0-70°C)*
Clock Interface XCLK/XTAL
External Clock/Crystal Select Input When HIGH, external 60-MHz clock source selected bypassing crystal circuit clock trippler. When LOW, 20-MHz crystal used instead. following table illustrates this works.
Crystal Load Capacitance Motional Crystal Capacitance (C1) Internal Equivalent Series Resistance Shunt Capacitance
Table
Input XTAL1 XTAL1
External Clock/Crystal Select
XCLK/XTAL Clock Source 20-MHz Crystal 60-MHz Oscillator/ External Source
Output XTAL2 Don't Care
Note: *Requires trimming specification; trimmed total.
Power Supply VDDB
Buffer Power Pins) +3.3 Power These pins power supply pins that used input/output buffer drivers. VDDB pins must connected +3.3 supply.
XTAL1
Crystal Oscillator Input internal clock generator utilizes either 20-MHz crystal that attached pins XTAL1 XTAL2 60-MHz clock source connected XTAL1. This tolerant, clock source should from source, clock source.
VDD_PCI
Buffer Power Pins) +3.3 Power These pins power supply pins that used input/output buffer drivers (except driver). VDD_PCI pins must connected +3.3 supply.
XTAL2
Crystal Oscillator Output internal clock generator utilizes either 20-MHz crystal that attached pins XTAL1 XTAL2 60-MHz clock source connected XTAL1.
VSSB
Buffer Ground Pins) Ground These pins ground pins that used input/output buffer drivers.
External Crystal Characteristics
When using crystal drive oscillator, following crystal specification Table used ensure less than ±0.5 jitter DO±.
Digital Power Pins) +3.3 Power These pins power supply pins that used internal digital circuitry. pins must connected +3.3 supply.
Digital Ground Pins) Ground There seven ground pins that used internal digital circuitry.
Am79C978A
DVDDD
10BASE-T Block Power +3.3 Power This supplies power Mbps Transceiver block. must connected +3.3 source. This requires careful decoupling ensure proper device performance.
DVSSD
10BASE-T Digital Ground Ground This ground connection digital logic within block.
VDDCO
Crystal +3.3 Power This supplies power crystal circuit.
DVDDRX, DVDDTX
10BASE-T Buffer Power +3.3 Power These pins supply power 10BASE-T input/output buffers. They must connected +3.3 source. These pins require careful decoupling ensure proper device performance.
VDDHR
HomePNA Digital Power +3.3 Power These pins digital power supply pins that used internal digital circuitry HomePNA block. They must connected +3.3 source.
DVDDA
Analog Power +3.3 Power This supplies power IREF current reference circuit 10BASE-T analog PLL. They must connected +3.3 source. These pins require careful decoupling ensure proper device performance.
VSSHR
HomePNA Analog Ground Ground This ground connection analog section within HomePNA block.
DVDDA_HR
HomePNA Analog Power +3.3 Power This supplies power analog section HomePNA block. must connected +3.3 source. This requires careful decoupling ensure proper device performance.
DVSSX, DVSSA
10BASE-T Analog Ground Ground These pins ground connection analog section within Physical Data Transceiver (PDX) block.
Am79C978A
BASIC FUNCTIONS System Interface
Am79C978A controller designed operate master during normal operations. Some slave accesses Am79C978A controller required operations well. Initialization Am79C978A controller achieved through combination Configuration Space accesses, slave accesses, master accesses, optional read EEPROM that perfor Am79C978A controller. EEPROM read operation performed through 93C46 EEPROM interface. 8802-3 (IEEE/ANSI 802.3) Ethernet Address reside within serial EEPROM. Some controller configuration registers also programmed EEPROM read operation. Address PROM, on-chip board-configuration registers, Ethernet controller registers occupy bytes address space. memory mapped accesses supported. Base Address registers configuration space allow locating address space wide variety starting addresses.
change during normal network operations. There descriptor area receive activity, there separate area transmit activity. descriptor space contains relocatable pointers network frame data, used transfer frame status from Am79C978A controller software. buffer areas locations that hold frame data transmission that accept frame data that been received.
Network Interfaces
Am79C978A controller provides layer functions Mbps (10BASE-T) Mbps. Am79C978A controller supports both half-duplex full-duplex operation network interface.
Media Independent Interface
Am79C978A controller fully supports according IEEE 802.3 standard. This Reconciliation Sublayer interface allows variety PHYs (100BASE-TX, 100BASE-FX, 100BASE-T4, 100BASE-T2, 10BASE-T, etc.) attached Am79C978A device without future upgrade problems. interface 4-bit (nibble) wide data path interface that runs 100-Mbps networks 10-Mbps networks. interface consists independent data paths, receive (RXD(3:0)) transmit (TXD(3:0)), control signals each data path (RX_ER, RX_DV, TX_EN), network status signals (COL, CRS), clocks (RX_CLK, TX_CLK) each data path, two-wire management interface (MDC MDIO). Figure Transmit Interface transmit clock generated external sent Am79C978A controller TX_CLK input pin. clock MHz, depending speed network which external attached. data nibble-wide bits) data path, TXD(3:0), from Am79C978A controller exter synchronous ising edge TX_CLK. transmit process star when Am79C978A controller asserts TX_EN, which indicates exter that data TXD(3:0) valid. Normally, unrecoverable errors signaled through external with TX_ER output pin. external will respond this error generating coding error current transmitted frame. Am79C978A controller does this method rans Am79C978A controller will invert last byte generating invalid FCS. TX_ER should tied GND.
Software Interface
software interface Am79C978A controller divided into three parts. part configuration registers used identify Am79C978A controller setup configuration device. setup information includes memory mapped base address, mapping Expansion ROM, routing Am79C978A controller interrupt channel. This allows jumperless implementation. second portion software interface direct access resources Am79C978A controller. Am79C978A controller occupies bytes address space that must begin 32-byte block boundary. address space mapped into memory space (memory mapped I/O). Base Address Register Configuration Space controls start address address space mapped space. Memory Mapped Base Address Register controls start address address space mapped memory space. 32-byte address space used software program Am79C978A controller operating mode, enable disable various features, monitor operating status, request particular functions executed Am79C978A controller. third portion software interface descriptor buffer areas that shared between software Am79C978A controller during normal network operations. descriptor area boundaries software
Am79C978A
RXD(3:0) RX_DV RX_ER RX_CLK Receive Signals
Interface
TXD(3:0) TX_EN TX_CLK Management Port Signals MDIO Transmit Signals Network Status Signals
Am79C978A
22399A-4
Figure
Media Independent Interface
Receive Interface receive clock also generated external sent Am79C978A controller RX_CLK input pin. clock will same frequency TX_CLK will phase MHz, depending speed network which external attached. RX_CLK continuous clock during reception frame, stopped RX_CLK periods beginning frames, that external sync network data traffic necessary recover receive clock. During this time, external switch TX_CLK maintain stable clock receive interface. Am79C978A controller will handle this situation with loss data. data nibble-wide bits) data path, RXD(3:0), from exter Am79C978A controller synchronous rising edge RX_CLK. receive process starts when RX_DV asserted. RX_DV will remain asserted until receive frame. Am79C978A controller requires (Carrier Sense) toggle between frames order receive them properly. Errors currently received frame signaled across RX_ER pin. RX_ER used signal special conditions band when RX_DV asserted. defined out-of-band conditions this 100BASE-TX signaling Start Frame Delimiter 100BASE-T4 indication illegal code group before receiver synched incoming data. Am79C978A controller will respond these conditions. band conditions currently treated NULL events. Certain band non-IEEE 802.3u-compliant flow control sequences cause erratic behavior Am79C978A controller.
Network Status Interface also provides signals that consistent necessary IEEE 802.3 IEEE 802.3u operation. These signals (Carrier Sense) (Collision Sense). Carrier Sense used detect non-idle activity network. Collision Sense used indicate that simultaneous transmission occurred half-duplex network. Management Interface provides two-wire management interface that Am79C978A controller control receive status from external devices. Network Port Manager copies PHYAD after Am79C978A controller reads EEPROM uses communicate with external PHY. address must programmed into EEPROM prior starting Am79C978A controller. This necessary that internal management controller work autonomously from software driver always know where access external PHY. Am79C978A controller unique offering direct hardware support external device without software support. address reserved should used. access external PHYs, software driver must have knowledge external PHY's address when multiple PHYs present before attempting address Management Interface uses Control, Address, Data registers (BCR32, control communicate external PHYs. Am79C978A controller generates management frames external through MDIO synchronous rising edge Management Data Clock (MDC) based combination writes reads these registers.
Am79C978A
Management Frames management frames automatically generated Am79C978A controller conform clause IEEE 802.3u standard. start frame preamble ones guarantees that external PHYs synchronized same interface. Figure Loss synchronization possible hot-plugging capability exposed MII.
IEEE 802.3 specification allows drop preamble, after reading Status Register from external determine that external will support Preamble Suppression (BCR34, After having valid Status Register read, Am79C978A controller will then drop creation preamble stream until reset occurs, receives read error, external disconnected.
Preamble 1111.1111 Bits
Bits
Bits
Address
Register Address
Bits
Data
Idle
22399A-5
Bits
Bits
Bits
Figure
Frame Format Interface Connection 2.5-MHz clock rate, available user. intended applications that 10-MHz clock rate used single external adapter card motherboard. 5-MHz clock rate used exposed with external attached. 2.5-MHz clock rate intended used when multiple external PHYs connected Management Port compliance IEEE 802.3u standard required. Auto-Poll External Status Polling defined IEEE 802.3 standard, external attached Am79C978A controller's communicating important timely status information back Am79C978A controller. Am79C978A controller knowing that external undergone change status without polling status register. prevent problems from occurring with inadequate host software polling, Am79C978A controller will Auto-Poll when APEP (BCR32, insure that most current information available. 10BASE-T Management Registers descriptions Status Register. contents latest read from external will stored shadow register Auto-Poll block. first read Status Register will just stored, subsequent reads will compared contents already stored shadow register. there been change contents Status Register, MAPINT (CSR7, interrupt will generated INTA MAPINTE (CSR7, Auto-Poll features disabled software driver polling required.
This followed start field (ST) operation field (OP). operation field (OP) indicates whether Am79C978A controller initiating read write operation. This followed external address (PHYAD) register address (REGAD) programmed BCR33. address reserved should used. external have larger address space starting 1Fh. This address range aside IEEE vendor usable address space will vary from vendor vendor. This field followed turnaround field. During read operation, turnaround field used determine external responding correctly read request not. Am79C978A controller will tri-state MDIO both cycles. During second cycle, external synchronized Am79C978A controller, external will drive external does drive Am79C978A controller will signal MREINT (CSR7, interrupt, MREINTE (CSR7, indicating Am79C978A controller management frame read error that data BCR34 valid. data field to/from external read written into BCR34 register. last field IDLE field that necessary give ample time drivers turn before next access. Am79C978A controller will drive tristate MDIO anytime Management Port active. help speed reading writing management frames external PHY, sped setting FMDC bits BCR32. IEEE 802.3 specification requires
Am79C978A
Auto-Poll's frequency generating management frames adjusted setting APDW bits (BCR32, bits 10-8). delay adjusted from periods 2048 periods. Auto-Poll default will only read Status register external PHY. Network Port Manager external present active, Network Port Manager will request status from external generating management frames. These frames will sent roughly every These frames necessary that Network Port Manager monitor current active link select different network port current link goes down.
Slave Interface Unit
slave Interface Unit (BIU) controls accesses configuration space, Control Status Registers (CSR), Configuration Registers (BCR), Address PROM (APROM) locations, Expansion ROM. Table shows response Am79C978A controller each commands slave mode.
Table Slave Commands
C[3:0] 0000 0001 0010 0011 0100 0101 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Memory mapped read CSR, BCR, APROM, Reset registers. Read Expansion Memory mapped write CSR, BCR, APROM used used Read CSR, BCR, APROM, Reset registers Write CSR, BCR, APROM
10BASE-T
10BASE-T transceiver incorporates physical layer function, including both clock recovery (ENDEC) transceiver function. Data transmission over 10BASE-T medium requires integrated 10BASE-T MAU. transceiver will meet electrical requirements 10BASE-T specified IEEE 802.3i. transmit signal filtered transceiver reduce harmonic content IEEE 802.3i. Since filtering performed silicon, external filtering modules needed. 10BASE-T transceiver receives Mbps data from across internal million nibbles second (parallel), million bits second (serial) 10BASE-T. then Manchester encodes data before transmission network. pins differential twisted-pair receivers. When properly terminated, each receiver will meet electrical requirements 10BASE-T specified IEEE 802.3i. Each receiver internal filtering does require external filter modules. 10BASE-T transceiver receives Manchester coded 10BASE-T data stream from medium. then recovers clock decodes data. data stream presented internal interface either parallel serial format.
0110
Memory Read
0111 1000 1001 1010 1011 1100 1101 1110
Memory Write Reserved Reserved Configuration Read Configuration Write Memory Read Multiple Dual Address Cycle Memory Read Line Memory Write Invalidate
Read Configuration Space Write Configuration Space Aliased Memory Read used Aliased Memory Read Aliased Memory Write
JTAG Configuration Information
device software configuration information follows Table Table
Table
Vendor 1022
Device
(offset 0x08)
1111
Device 2001
Slave Configuration Transfers
host access configuration space with Am79C978A controller will assert DEVSEL during address phase when IDSEL asserted, AD[1:0] both access configuration cycle. AD[7:2] select DWord location configuration space. Am79C978A controller ignores AD[10:8], because
Table Software Configuration
CSR89 00002262 CSR88 00006003h JTAG 2262 6003h
Am79C978A
single function device. AD[31:11] "don't cares." Table
Table Slave Configuration Transfers
AD31 AD11 Don't care AD10 Don't care DWord Index
active bytes within DWord determined byte enable signals. Eight-bit, 16-bit, 32-bit transfers supported. DEVSEL asserted clock Am79C978A controller will assert TRDY third clock data phase. Am79C978A controller does support burst transfers access configuration space. When host keeps FRAME asserted second data phase, Am79C978A controller will disconnect transfer. When host tries access configuration space while automatic read EEPROM after H_RESET (see section RESET) on-going, Am79C978A controller will terminate access with disconnect/retry response. Am79C978A controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C978A controller capable detecting configuration cycle even when address phase immediately follows data phase transaction different target without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C978A controller asserts DEVSEL second clock after FRAME asserted (medium timing).
Am79C978A controller asserts DEVSEL detects address match access cycle. configured memory mapped mode, Am79C978A controller will look address that falls within bytes memory address space (starting from memory mapped base address). Am79C978A controller asser DEVSEL detects address match access memory cycle. DEVSEL asserted clock cycles after host asserted FRAME. Figure Figure Am79C978A controller will assert DEVSEL detects address match command correct type. memory mapped mode, Am79C978A controller aliases accesses resources command types Memory Read Multiple Memory Read Line basic Memory Read command. accesses type Memory Write Invalidate aliased basic Memory Write command. Eight-bit, 16-bit, 32-bit nonburst transactions supported. Am79C978A controller decodes address lines determine which resource accessed. typical number wait states added slave memory mapped read write access part Am79C978A controller seven clock cycles, depending upon relative phases internal Buffer Management Unit clock signal, since internal Buffer Management Unit clock divide-by-two version signal. Am79C978A controller does support burst transfers access resources. When host keeps FRAME asserted second data phase, Am79C978A controller will disconnect transfer. Am79C978A controller supports fast back-to-back transactions different targets. This indicated Fast Back-To-Back Capable (PCI Status register, which hardwired Am79C978A controller capable detecting memorymapped cycle even when address phase immediately follows data phase transaction different target, without idle state in-between. There will contention DEVSEL, TRDY, STOP signals, since Am79C978A controller asserts DEVSEL second clock after FRAME asserted (medium timing). Figure Figure
Slave Transfers
After Am79C978A controller configured device setting IOEN (for regular mode) MEMEN (for memory mapped mode) Command register, starts monitoring access CSR, BCR, EEPROM locations. configured regular mode, Am79C978A controller will look address that falls within bytes address space (starting from base address).
Am79C978A
FRAME
FRAME
ADDR DATA
ADDR
DATA
C/BE
1010
C/BE
1011
IRDY
IRDY
TRDY
TRDY
DEVSEL
DEVSEL
STOP
STOP
IDSEL
IDSEL
DEVSEL sampled
22399A-6
22399A-7
Figure
Slave Configuration Read
Figure
Slave Configuration Write
FRAME
ADDR
DATA
C/BE
0010
IRDY
TRDY
DEVSEL
STOP
22399A-8
Figure
Slave Read Using Command
Am79C978A
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
STOP
22399A-9
Figure Slave Write Using Memory Command
Expansion Transfers
host must initialize Expansion Base Address register offset configuration space with valid address before enabling access device. Am79C978A controller will react access Expansion until both MEMEN (PCI Command register, ROMEN (PCI Expansion Base Address register, After Expansion enabled, Am79C978A controller will assert DEVSEL memory read accesses with address between ROMBASE ROMBASE Am79C978A controller aliases accesses Expansion command types Memory Read Multiple Memory Read Line basic Memory Read command. Eight-bit, 16-bit, 32-bit read transfers supported. Since setting MEMEN also enables memory mapped access resources, attention must given Memory Mapped Base Address register before enabling access Expansion ROM. host must Memory Mapped Base Address register value that prevents Am79C978A controller from claiming memory cycles intended
Am79C978A controller will always read four bytes every host Expansion read access. TRDY will asserted until four bytes loaded into internal scratch register. cycle TRDY asserted depends programming Expansion interface timing. Figure assumes that ROMTMG (BCR18, bits 15-12) default value. Note: Expansion should read only during configuration time system. When host tries write Expansion ROM, Am79C978A controller will claim cycle asserting DEVSEL. TRDY will asserted clock cycle later. write operation will have effect. Writes Expansion done through BCR30 Expansion Data Port. Expansion Interface section more details. During boot procedure, system will find Expansion ROM. system assumes that Expansion present when reads signature (byte (byte
Slave Cycle Termination
There three scenarios besides normal completion transaction where Am79C978A controller target slave cycle will terminate access.
Am79C978A
FRAME
ADDR
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22399A-10
Figure Expansion Read
Disconnect When Busy Am79C978A controller cannot service slave access while reading contents EEPROM. Simultaneous access allowed order avoid conflicts, since EEPROM used initialize some configuration space locations most BCRs CSR116. EEPROM read operation will always happen automatically after deassertion pin. addition, host start read operation setting PREAD (BCR19, 14). While EEPROM read on-going, Am79C978A controller will disconnect slave access where target asserting STOP together with DEVSEL, while driving TRDY high. STOP will stay asserted until cycle. Note that memory slave accesses will only disconnected they enabled setting IOEN MEMEN Command register. Without enable set, cycles will claimed all. Since H_RESET clears IOEN MEMEN bits automatic EEPROM read after H_RESET, disconnect only applies configuration cycles. second situation where Am79C978A controller will generate disconnect/retry cycle when host tries access resources right after having
read Reset register. Since access generates internal reset pulse about length, further slave accesses will deferred until internal reset operation completed. Figure Disconnect Burst Transfer Am79C978A controller does support burst access configuration space, resources, Expansion Bus. host indicates burst transaction keeping FRAME asserted during data phase. When Am79C978A controller sees FRAME IRDY asserted clock cycle before wants assert TRDY, also asserts STOP same time. transfer first data phase still successful, since IRDY TRDY both asserted. Figure host ready when Am79C978A controller asserts TRDY, device will wait host assert IRDY. When host asserts IRDY FRAME still asserted, Am79C978A controller will finish first data phase deasserting TRDY clock later. same time, will assert STOP signal disconnect host. STOP will stay asserted until host removes FRAME. Figure
Am79C978A
FRAME
FRAME
ADDR
DATA
DATA
DATA
C/BE
C/BE
IRDY
IRDY
TRDY
TRDY
DEVSEL
DEVSEL STOP
STOP
22399A-11
22399A-13
Figure
Disconnect Slave Cycle When Busy
Figure
Disconnect Slave Burst Transfer Host Inserts Wait States
FRAME
Parity Error Response
When Am79C978A controller current master, samples AD[31:0], C/BE[3:0], lines during address phase command parity error. When detects address parity error, Am79C978A controller sets PERR (PCI Status register, When reporting that error enabled setting SERREN (PCI Command register, PERREN (PCI Command register, Am79C978A controller also drives SERR signal clock cycle sets SERR (PCI Status register, assertion SERR follows Am79C978A controller will assert DEVSEL transaction that address parity error when PERREN SERREN Figure
DATA
DATA
C/BE
IRDY
TRDY
DEVSEL
STOP
22399A-12
Figure
Disconnect Slave Burst Transfer Host Wait States
Am79C978A
FRAME
ADDR
DATA
C/BE
During data phase write, memory-mapped write, configuration write command that selects Am79C978A controller target, device samples AD[31:0] C/BE[3:0] lines parity clock edge, data transferred indicated assertion IRDY TRDY. sampled following clock cycle. parity error detected reporting that error enabled setting PERREN (PCI Command register, PERR asserted clock later. parity error will always PERR (PCI Status register, even when PERREN cleared Am79C978A controller will finish transaction that data parity error normal asserting TRDY. corrupted data will written addressed location. Figure shows transaction that suffered parity error time data transferred (clock IRDY TRDY both asserted). PERR driven high beginning data phase then drops parity error clock clock cycles after data transferred. After PERR driven low, Am79C978A controller drives PERR high clock cycle, since PERR sustained tri-state signal.
SERR
DEVSEL
22399A-14
Figure
Address Parity Error Response
FRAME
ADDR
DATA
C/BE
PERR
IRDY
TRDY
DEVSEL
22399A-15
Figure Slave Cycle Data Parity Error Response
Am79C978A
Master Interface Unit
master Interface Unit (BIU) controls acquisition accesses initialization block, descriptor rings, receive transmit buffer memory. Table shows usage commands Am79C978A controller master mode. Table Master Commands
C[3:0] 0000 0001 0010 0011 0100 0101 Command Interrupt Acknowledge Special Cycle Read Write Reserved Reserved Read initialization block descriptor rings Read transmit buffer non-burst mode Write descriptor rings receive buffer
FRAME
ADDR
used used used used
C/BE
IRDY
0110
Memory Read
Figure Acquisition
22399A-16
0111 1000 1001 1010 1011 1100 1101 1110 1111
Memory Write Reserved Reserved
Configuration Read used Configuration Write Memory Read Multiple used Read transmit buffer burst mode Read transmit buffer burst mode used
burst mode, deassertion depends setting EXTREQ (BCR18, EXTREQ cleared deasserted same time FRAME asserted. (The Am79C978A controller never performs more than burst transaction within single mastership period.) EXTREQ Am79C978A controller does deassert until starts last data phase transaction. Once asserted, remains active until become active independent subsequent setting STOP (CSR0, SPND (CSR5, assertion H_RESET S_RESET, however, will cause inactive immediately. Master Transfers There four primary types transfers. Am79C978A controller uses non-burst well burst cycles read write access main memory. Basic Non-Burst Read Transfer default, Am79C978A controller uses nonburst cycles master read operations. controller non-burst read accesses command type Memory Read (type Note that during non-burst read operation, byte lanes will always active. Am79C978A controller will internally discard unneeded bytes. Am79C978A controller typically performs more than non-burst read transaction within single mastership period. FRAME dropped between consecutive non-burst read cycles. stays asserted until FRAME asserted last transaction.
Dual Address Cycle used Memory Read Line Memory Write Invalidate
Acquisition microcode will determine when transfer should initiated. first step master transfer acquire ownership bus. This task handled synchronous logic within BIU. ownership requested with signal ownership granted arbiter through signal. Figure shows Am79C978A controller acquisition. asserted arbiter returns while another master transferring data. Am79C978A controller waits until idle (FRAME IRDY deasserted) before starts driving AD[31:0] C/BE[3:0] clock FRAME asserted clock indicating valid address command AD[31:0] C/BE[3:0]. Am79C978A controller does address stepping which reflected ADSTEP (bit Command register being hardwired
Am79C978A
Am79C978A controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. Figure shows non-burst read transactions. first transaction zero wait states. second transaction, target extends cycle asserting TRDY clock later. Basic Burst Read Transfer Am79C978A controller supports burst mode master read operations. burst mode must enabled setting BREADE (BCR18, allow burst transfers descriptor read operations, Am79C978A controller must also programmed SWSTYLE (BCR20, bits 7-0). burst read accesses initialization block descriptor ring command type Memory Read (type Burst read accesses transmit buffer typically longer than data phases. When MEMCMD (BCR18, cleared burst read accesses transmit buffer command type Memory Read Line (type 14). When MEMCMD (BCR18, burst read accesses transmit buffer command type Memory Read Multiple (type 12).
AD[1:0] will both during address phase indicating linear burst order. Note that during burst read operation, byte lanes will always active. Am79C978A controller will internally discard unneeded bytes. Am79C978A controller will always perform only single burst read transaction mastership period, where transaction defined address Am79C978A controller supports zero wait state read cycles. asserts IRDY immediately after address phase same time starts sampling DEVSEL. FRAME deasserted when next last data phase completed. Figure shows typical burst read access. Am79C978A controller arbitrates bus, granted access, reads three 32-bit words (DWord) from system memory, then releases bus. example, memory system extends data phase each access wait state. example assumes that EXTREQ (BCR18, cleared therefore, deasserted same cycle FRAME asserted.
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-17
Figure Non-Burst Read Transfer
Am79C978A
FRAME
ADDR
DATA
DATA
DATA
C/BE
1110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-18
Figure Burst Read Transfer (EXTREQ MEMCMD Basic Non-Burst Write Transfer default, Am79C978A controller uses nonburst cycles master write operations. controller non-burst write accesses command type Memory Write (type byte enable signals indicate byte lanes that have valid data. Am79C978A controller typically performs more than non-burst write transaction within single mastership period. FRAME dropped between consecutive non-burst write cycles. stays asserted until FRAME asserted last transaction. Am79C978A controller supports zero wait state write cycles except with descriptor write transfers. (See Descriptor Transfers section only exception.) asserts IRDY immediately after address phase. Figure shows non-burst write transactions. first transaction wait states. target inserts wait state asserting DEVSEL clock late another wait state also asserting TRDY clock late. second transaction shows zero wait state write cycle. target asserts DEVSEL TRDY same cycle Am79C978A controller asserts IRDY. Basic Burst Write Transfer Am79C978A controller supports burst mode master write operations. burst mode must enabled setting BWRITE (BCR18, allow burst transfers descriptor write operations, Am79C978A controller must also programmed SWSTYLE (BCR20, bits 7-0). controller burst write transfers command type Memory Write (type AD[1:0] will both during address phase indicating linear burst order. byte enable signals indicate byte lanes that have valid data. Am79C978A controller will always perform single burst write transaction mastership period, where transaction defined address phase multiple data phases. Am79C978A controller supports zero wait state write cycles except with case descriptor write transfers. (See Descriptor Transfers section only exception.) device asserts IRDY immediately after address phase same time star sampling DEVSEL. FRAME deasserted when next last data phase completed.
Am79C978A
FRAME
ADDR
DATA
ADDR
DATA
C/BE
0111
0111
IRDY
TRDY
DEVSEL
22399A-19
DEVSEL sampled
Figure Non-Burst Write Transfer
Figure shows typical burst write access. Am79C978A controller arbitrates bus, granted cess, ites four 32-bit (DWords) system memory then releases bus. this example, memory system extends data phase first access wait state. following three data phases take clock cycle each, which determined timing TRDY. example assumes that EXTREQ (BCR18, therefore, deasserted until next last data phase finished. Target Initiated Termination When Am79C978A controller master, cycles produces terminated target three different ways: disconnect
with data transfer, disconnect without data transfer, target abort. Disconnect With Data Transfer Figure shows disconnection which last data transfer occurs after target asserted STOP. STOP asserted clock start termination sequence. Data still transferred during this cycle, since both IRDY TRDY asserted. Am79C978A controller terminates current transfer with deassertion FRAME clock IRDY clock later. finally releases clock wants transfer more data, Am79C978A controller will again request after clock cycles. starting address transfer will address next non-transferred data.
Am79C978A
FRAME
ADDR
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-20
Figure
Burst Write Transfer (EXTREQ
Am79C978A
FRAME
ADDRi
DATA
DATA
ADDRi+8
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
22399A-21
DEVSEL sampled
Figure
Disconnect With Data Transfer
Disconnect Without Data Transfer Figure shows target disconnect sequence during which data transferred. STOP asserted clock without TRDY being asserted same time. Am79C978A controller terminates access with deassertion FRAME clock IRDY clock cycle later. finally releases clock Am79C978A controller will again request after clock cycles retry last transfer. starting address transfer will address last non-transferred data. Target Abort Figure shows target abort sequence. target asserts DEVSEL clock. then deasserts DEVSEL asserts STOP clock target target abort sequence indicate that cannot service data transfer that does want transaction retr ied. Additionally, Am79C978A controller cannot make assumption
about success previous data transfers current transaction. Am79C978A controller terminates current transfer with deassertion FRAME clock IRDY clock cycle later. finally releases clock Since data integrity guaranteed, Am79C978A controller cannot recover from target abort event. TheAm79C978A controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station.
Am79C978A
FRAME
ADDRi
DATA
ADDRi
C/BE
0111
0000
0111
IRDY
TRDY
DEVSEL
STOP
DEVSEL sampled
22399A-22
Figure Disconnect Without Data Transfer
RTABORT (PCI Status register, will indicate that Am79C978A controller received target abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Master Initiated Termination There three scenarios besides normal completion transaction where Am79C978A controller will terminate cycles produces bus. Preemption During Non-Burst Transaction When Am79C978A controller performs multiple non-burst transactions, keeps asserted until assertion FRAME last transaction. When removed, Am79C978A controller will finish current transaction then release bus. last transaction,
will remain asserted regain ownership soon possible. Figure Preemption During Burst Transaction When Am79C978A controller operates burst mode, only performs single transaction mastership period, where transaction defined address phase multiple data phases. central arbiter remove time during transaction. TheAm79C978A controller will ignore deassertion continue with data transfers, long Latency Timer expired. When Latency Timer deasserted, Am79C978A controller will finish current data phase, deassert FRAME, finish last data phase, release bus. EXTREQ (BCR18, cleared will immediately assert regain ownership soon possible. EXTREQ will stay asserted.
Am79C978A
ADDR
DATA
C/BE
0111
0000
Am79C978A controller will reset locations their STOP_RESET values. configuration registers will cleared. on-going network transmission terminated orderly sequence. less than bits have been transmitted onto network, transmission will terminated immediately, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. RMABORT Status register, will indicate that Am79C978A controller terminated transaction with master abort. addition, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. Figure Parity Error Response During every data phase read operation, when target indicates that data valid asserting TRDY, Am79C978A controller samples AD[31:0], C/BE[3:0], lines data parity error. When detects data parity error, Am79C978A controller sets PERR (PCI Status register, When reporting that error enabled setting PERREN (PCI Command register, Am79C978A controller also drives PERR signal sets DATAPERR (PCI Status register, assertion PERR follows corrupted data/byte enables clock cycles clock cycle. Figure shows transaction that parity error data phase. TheAm79C978A controller asserts PERR clock clock cycles after data valid. data clock checked parity, because read access, only required valid clock after target asser TRDY. TheAm79C978A controller then drives PERR high clock cycle, since PERR sustained tri-state signal. During every data phase write operation, Am79C978A controller checks PERR input target reports parity error. When sees PERR input asserted, Am79C978A controller sets PERR (PCI Status register, When PERREN (PCI Command register, Am79C978A controller also sets DATAPERR (PCI Status register,
IRDY
TRDY
VSEL
DEVSEL sampled
22399A-23
Figure Target Abort
When preemption occurs after counter counted down Am79C978A controller will finish current data phase, deassert FRAME, finish last data phase, release bus. Note that important host program Latency Timer according bandwidth requirement Am79C978A controller. host determine this bandwidth requirement reading MAX_LAT MIN_GNT registers. Figure assumes that Latency Timer counted down clock Master Abort TheAm79C978A controller will terminate cycle with Master Abort sequence DEVSEL asserted within clocks after FRAME asserted. Master Abort treated fatal error Am79C978A controller.
Am79C978A
FRAME
ADDR
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-24
Figure
Preemption During Non-Burst Transaction
FRAME
ADDR
DATA
DATA
DATA
DATA
DATA
C/BE
0111
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-25
Figure Preemption During Burst Transaction
Am79C978A
FRAME
ADDR
DATA
C/BE
0111
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-26
Figure
Master Abort
FRAME
ADDR
DATA
C/BE
0111
PERR
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-27
Figure Master Cycle Data Parity Error Response
Am79C978A
Whenever Am79C978A controller current master data parity error occurs, SINT (CSR5, will When SINT set, INTA asserted enable SINTE (CSR5, This mechanism used inform driver system error. host read Status register determine exact cause interrupt. setting SINT data parity error dependent setting PERREN (PCI Command register, default, data parity error does affect state engine. TheAm79C978A controller treats data master transfers that have parity error nothing happened. network activity continues. Advanced Parity Error Handling cycles, Am79C978A controller provides second, more advanced level parity error handling. This mode enabled setting APERREN (BCR20, When APERREN bits (RMD1 TMD1, used indicate parity error data transfers receive transmit buffers. Note that since advanced parity error handling uses additional descriptor, SWSTYLE (BCR20, bits 7-0) must program Am79C978A controller 32-bit software structures. TheAm79C978A controller will react following when data parity error occurs:
trans nate tely, generating runt packet. bits more have been transmitted, message will have current inverted appended next byte boundary guarantee error detected receiving station. APERREN does affect reporting address parity errors data parity errors that occur when Am79C978A controller target transfer. Initialization Block Transfers During execution Am79C978A controller master initialization procedure, microcode will repeatedly request transfers from BIU. During each these initialization block transfers, will perform data transfer cycles reading DWord transfer then will relinquish bus. When SSIZE32 (BCR20, (i.e., initialization block organized 32-bit software structures), there seven DWords transfer during master initialization procedure, four mastership periods needed order complete initialization sequence. Note that last DWord transfer last mastership period initialization sequence accesses unneeded location. Data from this transfer discarded internally. When SSIZE32 cleared (i.e., initialization block organized 16-bit software structures), then three mastership periods needed complete initialization sequence. Am79C978A device supports transfer modes reading initialization block: non-burst burst mode, with burst mode being preferred mode when Am79C978A controller used application. Figure Figure When BREADE cleared (BCR18, initialization block read transfers will executed non-burst mode. There address phase every data phase. FRAME will dropped between transfers. phases within mastership period will have addresses ascending contiguous order. When BREADE (BCR18, initialization block read transfers will executed burst mode. AD[1:0] will during address phase indicating linear burst order.
Initialization block read: STOP (CSR0, causes STOP_RESET device. Descriptor ring read: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device. Descriptor ring write: on-going network activity terminated orderly sequence then STOP (CSR0, cause STOP_RESET device. Transmit buffer read: (TMD1, current transmit descriptor. on-going network transmission terminated orderly sequence. Receive buffer write: (RMD1, last receive descriptor associated with frame.
Terminating on-going network transmission order sequence means that less than bits have been transmitted onto network,
Am79C978A
FRAME
IADDi
DATA
IADDi+4
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
22399A-28
DEVSEL sampled
Figure
Initialization Block Read Non-Burst Mode
FRAME
IADDi 0110
DATA
DATA
C/BE
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-29
Figure Initialization Block Read Burst Mode
Am79C978A
Descriptor Transfers Am79C978A microcode will determine when descriptor access required. descriptor read will consist data transfers. descriptor write will consist data transfers. descriptor transfers within single mastership period will always same type (either read write). During descriptor read accesses, byte enable signals will indicate that byte lanes active. Should some bytes needed, then Am79C978A controller will internally discard extraneous information that gathered during such read. settings SWSTYLE (BCR20, bits 7-0) BREADE (BCR18, affect Am79C978A controller performs descriptor read operations. When SWSTYLE descriptor read operations performed non-burst mode. setting BREADE effect this configuration. Figure When SWSTYLE descriptor entries ordered allow burst transfers. TheAm79C978A controller will perform descriptor read operations burst mode, BREADE Figure Table shows descriptor read sequence. During descriptor write accesses, only byte lanes which need written enabled. buffer chaining used, accesses descriptors intermediate buffers consist only data transfer return ownership buffer system. When SWSTYLE (BCR20, bits 7-0) cleared (i.e., descriptor entries organized 16-bit software structures), descriptor access will write single byte. When SWSTYLE (BCR20, bits 7-0) (i.e., descriptor entries organized 32-bit software structures), descriptor access will write single word. single buffer transmit receive descriptors, well last buffer chain, writes descriptor consist data transfers. first data transfer writes DWord containing status information. second data transfer writes byte (SWSTYLE cleared otherwise word containing additional status ownership (i.e., MD1[31]). settings SWSTYLE (BCR20, bits 7-0) Am79C978A controller performs descriptor write operations. When SWSTYLE descriptor write operations performed non-burst mode.
setting BWRITE effect this configuration. Figure When SWSTYLE descriptor entries ordered allow burst transfers. TheAm79C978A controller will perform descriptor write operations burst mode, BWRITE Figure Table descriptor write sequence. write transaction descriptor ring entries only case where Am79C978A controller inserts wait state when being master. Every data phase non-burst burst mode extended clock cycle, during which IRDY deasserted. Note that Figure assumes that Am79C978A controller programmed 32-bit software structures (SWSTYLE byte enable signals second data transfer would 0111b, device programmed 16-bit software structures (SWSTYLE
Table
SWSTYLE BCR20[7:0]
Descriptor Read Sequence
Sequence Address XXXX XX00h Turn around cycle Data MD1[31:24], MD0[23:0]
BREADE BCR18[6]
Idle Address XXXX XX04h Turn around cycle Data MD2[15:0], MD1[15:0] Address XXXX XX04h Turn around cycle Data MD1[31:0]
Idle Address XXXX XX00h Turn around cycle Data MD0[31:0] Address XXXX XX04h Turn around cycle Data MD1[31:0]
Idle Address XXXX XX08h Turn around cycle Data MD0[31:0] Address XXXX XX04h
Turn around cycle Data MD1[31:0] Data MD0[31:0]
Am79C978A
FRAME
DATA
DATA
C/BE
0110
0000
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-30
Figure Descriptor Ring Read Non-Burst Mode
FRAME
DATA
DATA
C/BE
0110
0000
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-31
Figure
Descriptor Ring Read Burst Mode
Am79C978A
FRAME
DATA
DATA
C/BE
0111
0000
0111
0011
IRDY
TRDY
DEVSEL
DEVSEL sampled
22399A-32
Figure
Descriptor Ring Write Non-Burst Mode
FRAME
DATA
DATA
C/BE
0110
0000
0011
IRDY
TRDY
DEVSEL
22399A-33
DEVSEL sampled
Figure
Descriptor Ring Write Burst Mode
Am79C978A
Table
SWSTYLE BCR20[7:0]
Descriptor Write Sequence
BWRITE BCR18[5] Sequence Address XXXX XX04h Data MD2[15:0], MD1[15:0]
Idle Address XXXX XX00h Data MD1[31:24] Address XXXX XX08h Data MD2[31:0]
Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h Data MD2[31:0]
Idle Address XXXX XX04h Data MD1[31:16] Address XXXX XX00h
mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system Am79C978A controller's request, speed operation preemption events. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period and, thereby, increase number transfers that period. general rule that longer Grant latency, slower transfer operations; slower clock speed, higher transmit watermark; higher receive watermark, longer mastership period will Note: Latency Timer significant during non-burst transfers. Burst FIFO Transfers Bursting only performed Am79C978A controller BREADE and/or BWRITE bits BCR18 set. These bits individually enable/disable ability Am79C978A controller perform burst accesses during master read operations master write operations, respectively. burst transaction will start with address phase, followed more data phases. AD[1:0] will always during address phase indicating linear burst order. During FIFO read operations, byte lanes will always active. TheAm79C978A controller will internally discard unused bytes. During first last data phases FIFO burst write operation, more byte enable signals inactive. other data phases will always write complete DWord. Figure shows beginning FIFO write with beginning buffer aligned DWord boundary. TheAm79C978A controller starts writing only three bytes during first data phase. This operation aligns address other data transfers 32-bit boundary that Am79C978A controller continue bursting full DWords. receive buffer does DWord boundary, Am79C978A controller will perform non-DWord write last transfer buffer. Figure shows final three FIFO transfers receive buffer. Since there were only nine bytes space left receive buffer, Am79C978A controller bursts three data phases. first data phases write full DWord, last only writes single byte.
Data MD2[31:0] Data MD1[31:16]
FIFO Transfers Am79C978A microcode will determine when FIFO transfer required. This transfer mode will used transfers data from FIFOs. Once been granted mastership, will perform series consecutive transfer cycles before relinquishing bus. transfers within master cycle will either read write cycles, transfers will contiguous, ascending addresses. Both nonburst burst cycles used, with burst mode being preferred mode when device used application. Non-Burst FIFO Transfers default mode, Am79C978A controller uses non-burst transfers read write data when accessing FIFOs. Each non-burst transfer will performed sequentially with issue address transfer corresponding data with appropriate output signals indicate selection active data bytes during transfer. FRAME will deasserted after every address phase. Several factors will affect length mastership period. possibilities follows: cycles will continue until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers). exact number total transfer cycles
Am79C978A
Note that Am79C978A controller will always perform DWord transfer long owns buffer space, even when there less than four bytes write. example, there only byte left current receive frame, Am79C978A controller will write full DWord, containing last byte receive frame least significant byte position (BSWP cleared CSR3, content other three bytes undefined. message byte count receive descriptor always reflects exact length received frame.
FRAME
DATA
DATA
DATA
C/BE
0111
0000
1110
FRAME
IRDY
TRDY
DATA
DATA
DATA
DEVSEL
C/BE
0111
0001
0000
DEVSEL sampled
IRDY
22399A-35
TRDY
Figure FIFO Burst Write Unaligned Buffer
DEVSEL
DEVSEL sampled
22399A-34
Figure
FIFO Burst Write Start Unaligned Buffer
TheAm79C978A controller will continue transferring FIFO data until transmit FIFO filled high threshold (read transfers) receive FIFO emptied threshold (write transfers), Am79C978A controller preempted Latency Timer expired. host should values MIN_GNT MAX_LAT registers determine value Latency Timer.
exact number total transfer cycles mastership period dependent following variables: settings FIFO watermarks, conditions FIFOs, latency system Am79C978A controller's request, speed operation. TRDY response time memory device will also affect number transfers, since speed accesses will affect state FIFO. During accesses, FIFO filling emptying network end. example, receive operation, slower TRDY response will allow additional data accumulate inside FIFO. accesses slow enough, complete DWord become available before mastership period and, thereby, increase number transfers that period. general rule that longer Grant latency, slower transfer operations; slower clock speed, higher transmit watermark; lower receive watermark, longer total burst length will When FIFO burst operation preempted, Am79C978A controller will relinquish ownership until Latency Timer expires.
Am79C978A
Buffer Management Unit
Buffer Management Unit (BMU) microcoded state machine which implements initialization procedure manages descriptors buffers. buffer management unit operates half speed input. Initialization Initialization includes reading initialization block memory obtain operating parameters. initialization block organized ways. When SSIZE32 (BCR20, default value initialization block entries logically 16bits wide backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. When SSIZE32 (BCR20, initialization block entries logically 32-bits wide. Note that Am79C978A controller always performs 32-bit transfers read initialization block entries. initialization block read when INIT CSR0 set. INIT should before concurrent with STRT insure correct operation. Once initialization block been completely read internal registers have been updated, IDON will CSR0, generating interrupt IENA set). TheAm79C978A controller obtains start address initialization block from contents CSR1 (least significant bits address) CSR2 (most significant bits address). host must write CSR1 CSR2 before setting INIT bit. initialization block contains user defined conditions operation, together with base addresses length information transmit receive descriptor rings. Ther alter nate method initialize Am79C978A controller. Instead initialization initialization block memory, data written directly into appropriate registers. Either method combination used discretion programmer. Refer Appendix Alternative Method Initialization details this alternate method. Re-Initialization Am79C978A controller turned initialization block (DTX, DRX, CSR15, bits 1-0). states transmitter receiver monitored host through CSR0 (RXON, TXON bits). TheAm79C978A controller should re-initialized transmitter and/or receiver were turned during original initialization subsequently required activate them, either section shut detection error condition (MERR, UFLO, BUFF error).
Re-initialization done initialization block setting STOP CSR0, followed writing CSR15, then setting START CSR0. Note that this form restart will perform same Am79C978A controller C-LANCE device. particular, upon restart, Am79C978A controller reloads transmit receive descriptor pointers with their respective base addresses. This means that software must clear descriptor bits reset descriptor ring pointers before restarting Am79C978A controller. reload descriptor base addresses performed C-LANCE device only after initialization, that restart CLANCE without initialization leaves C-LANCE pointing same descriptor locations before restart. Suspend TheAm79C978A controller offers suspend modes that allow easy updating registers without going through full re-initialization device. suspend modes also allow stopping device with orderly termination network activity. host requests Am79C978A controller enter suspend mode setting SPND (CSR5, host must poll SPND until reads back determine that Am79C978A controller entered suspend mode. When host sets SPND procedure taken Am79C978A controller enter suspend mode depends setting fast suspend enable (FASTSPND, CSR7, 15). When fast suspend requested (FASTSPND Am79C978A controller performs quick entry into suspend mode. time SPND set, Am79C978A controller will continue process transmit and/or receive packets that have already begun activity until network activity been completed. addition, transmit packet that started transmission will fully transmitted receive packet that begun reception will fully received. However, additional packets will transmitted received additional transmit receive activity will begin after network activity ceased. Hence, Am79C978A controller enter suspend mode with transmit and/or receive packets still FIFOs SRAM. This offers worst case suspend time maximum length packet over possibility completely emptying SRAM. Care must exercised this mode, because entire memory subsystem Am79C978A controller suspended. changes either descriptor rings SRAM cause Am79C978A controller start unknown condition could cause data corruption.
Am79C978A
When FASTSPNDE SPND set, Am79C978A controller take longer before entering suspend mode. time SPND set, Am79C978A controller will complete process transmit packet already begun, Am79C978A controller will completely receive receive packet already begun. TheAm79C978A controller will receive packets after completion current reception. Additionally, transmit packets stored transmit FIFOs transmit buffer area SRAM present) will transmitted, receive packets stored receive FIFOs receive buffer area SRAM selected) will transferred into system memory. Since FIFO SRAM contents flushed, take much longer before Am79C978A controller enters suspend mode. amount time that takes depends many factors including size SRAM, latency, network traffic level. Upon completion described operations, Am79C978A controller sets read-version SPND enters suspend mode. suspend mode, registers accessible. long Am79C978A controller reset while suspend mode H_RESET, S_RESET, setting STOP bit), re-initialization device required after device comes suspend mode. When SPND Am79C978A controller will leave suspend mode will continue transmit receive descriptor ring locations where when entered suspend mode. section Magic Packet technology details that affects suspension integrated Ethernet controller. Buffer Management Buffer management accomplished through message descriptor entries organized ring structures memory. There descriptor rings, transmit receive. Each descriptor describes single buffer. frame occupy more buffers. multiple buffers used, this referred buffer chaining. Descriptor Rings Each descriptor ring must occupy contiguous area memory. During initialization, user-defined base address transmit receive descriptor rings, well number entries contained descriptor rings programming software style (SWSTYLE, BCR20, bits 7-0) affects descriptor rings their entries arranged. When SWSTYLE default value descriptor rings backwards compatible with Am79C90 C-LANCE Am79C96x PCnet-ISA family. descriptor ring base addresses must aligned 8-byte boundary maximum
ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry contains subset three 32-bit transmit receive message descriptors (TMD, RMD) that organized four 16-bit structures (SSIZE32 (BCR20, Note that even though Am79C978A controller treats descriptor entries 16-bit structures, will always perform 32-bit transfers access descriptor entries. value CSR2, bits 15-8, used upper 8-bits memory addresses during master transfers. When SWSTYLE descriptor ring base addresses must aligned 16-byte boundary, maximum ring entries allowed when ring length through TLEN RLEN fields initialization block. Each ring entry organized three 32-bit message descriptors (SSIZE32 (BCR20, fourth DWord reserved. When SWSTYLE order message descriptors optimized allow read write access burst mode. software style, ring lengths beyond this range 65535) writing transmit receive ring length registers (CSR76, CSR78) directly. Each ring entry contains following information:
address actual message data buffer user host memory length message buffer Status information indicating condition buffer
permit queuing de-queuing message buffers, ownership each buffer allocated either Am79C978A controller host. within descriptor status information, either RMD, used this purpose. When signifies that Am79C978A controller currently ownership this ring descriptor associated buffer. Only owner permitted relinquish ownership write field descriptor entry. device that current owner descriptor entry cannot assume ownership change field entry. device may, however, read from descriptor that does currently own. Software should always read descriptor entries sequential order. When software finds that current descriptor owned Am79C978A controller, then software must read ahead next descriptor. software should wait descriptor does until Am79C978A controller sets release ownership software. When LAPPEN (CSR3, this rule modified. LAPPEN description. initialization, Am79C978A controller reads base address both transmit
Am79C978A
receive descriptor rings into CSRs Am79C978A controller during subsequent operations. Figure illustrates relationship between initialization base address, initialization block, receive transmit descriptor ring base addresses, receive transmit descriptors, receive transmit data buffers, when SSIZE32 cleared
Note that value CSR2, bits 15-8, used upper 8-bits memory addresses during master transfers. Figure illustrates when SSIZE32 relationship between initialization base address, initialization block, receive transmit descriptor ring base addresses, receive transmit descriptors, receive transmit data buffers.
Descriptor Ring CSR2
IADR[31:16]
CSR1
IADR[15:0]
desc. start
desc.
RMD0
Initialization Block
PADR[15:0] PADR[31:16] PADR[47:32] LADRF[15:0] LADRF[31:16] LADRF[47:32] LADRF[63:48] RDRA[15:0] RDRA[23:16] TDRA[15:0] TDRA[23:16]
Buffers
Data Buffer
Data Buffer
Data Buffer
Descriptor Ring
desc. start desc.
Buffers
Data Buffer
Data Buffer
Data Buffer
22399A-36
Figure 16-Bit Software Model
Am79C978A
CSR2
IADR[31:16]
CSR1
IADR[15:0]
desc. start
Descriptor Ring
desc. start
Initialization Block
MODE PADR[31:0] PADR[47:32] LADRF[31:0] LADRF[63:32] RDRA[31:0] TDRA[31:0]
Buffers
Data Buffer
Data Buffer
Data Buffer
desc. start
Descriptor Ring
desc. start
TMD0
TMD0 TMD1 TMD2 TMD3
Buffers
Data Buffer
Data Buffer
Data Buffer
22399A-37
Figure 32-Bit Software Model
Polling there network channel activity there pre- post-receive pre- post-transmit activity bein
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