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COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules

COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules

COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules
PRELIMINARY
August 1996
COP888GW 8-Bit Microcontroller with Pulse Train Generators and Capture Modules
General Description
I / O Features
n Memory mapped I / O n Software selectable I / O options ( TRI-STATE ® Output, Push-Pull Output, Weak Pull-Up Input, High Impedance Input) n Schmitt trigger inputs on port G n Package: 68-pin PLCC
CPU / Instruction Set Features
n 1 µs instruction cycle time n Fourteen multi-source vectored interrupts servicing: - External Interrupt with selectable edge - Idle Timer T0 - Two Timers (each with 2 interrupts) - MICROWIRE / PLUS - Multi-Input Wake-Up - Software Trap - UART (2) - Capture Timers - Counters (one vector for all four counters) - Default VIS (default interrupt) n Versatile and easy-to-use instruction set n 8-bit Stack Pointer SP - (stack in RAM) n Two 8-bit register indirect data memory pointers (B and X)
Key Features
Two 16-bit input capture modules with 8-bit prescalers Four Pulse Train Generators with 16-bit prescalers Full duplex UART Two 16-bit timers, each with two 16-bit registers supporting: - Processor independent PWM mode - External event counter mode - Input capture mode n Quiet design (low radiated emissions) n 16 kbytes on-board ROM n 512 bytes on-board RAM n n n n
Fully Static CMOS
Development Support
Additional Peripheral Features
n Idle Timer
TRI-STATE ® is a registered trademark of National Semiconductor Corporation. M2CMOSTM, MICROWIRE / PLUSTM, COPSTM, MICROWIRE and WATCHDOG are trademarks of National Semiconductor Corporation. IBM ® , PC ® , PC-AT ® and PC / XT ® are registered trademarks of International Business Machines Corporation. iceMASTER is a trademark of MetaLink Corporation.
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COP888GW
Block Diagram
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FIGURE 1. COP888GW Block Diagram
Connection Diagram
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Top View Order Number COP888GW-XXX / V See NS Package Number V68A
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Absolute Maximum Ratings (Note 1)
SuppIy Voltage (VCC) Voltage at Any Pin Total Current into VCC Pin (Source) 7V -0.3V to VCC +0.3V 100 mA
Total Current out of GND Pin (Sink) Storage Temperature Range
110 mA -65°C to +150°C
Note 1: Absolute maximum ratings indicate limits beyond which damage to the device may occur. DC and AC electrical specifications are not ensured when operating the device at absolute maximum ratings.
DC Electrical Characteristics
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AC Electrical Characteristics
COP888GW: -40°C TA 85°C unless otherwise specified Parameter Instruction Cycle Time (tc) Crystal, Resonator Ceramic CKI Clock Duty Cycle (Note 6) Rise Time (Note 6) Fall Time (Note 6) Inputs tSETUP tHOLD Output Propagation Delay (Note 9) tPD1, tPD0 SO, SK All Others MICROWIRE Setup Time (tUWS) (Note 7) MICROWIRE Hold Time (tUWH) (Note 7) MICROWIRE Output Propagation Delay (tUPD) Input Pulse Width (Note 8) Interrupt Input High Time Interrupt Input Low Time Timer 1, 2 Input High Time Timer 1, 2 Input Low Time Capture Timer High Time Capture Timer Low Time Reset Pause Width
Min 2.5 1.0 40
µs µs µs µs ns ns ns tc tc tc tc CKI CKI tc
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FIGURE 2. MICROWIRE / PLUS Timing
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Typical Performance Characteristics
Port D Source Current Port D Sink Current
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Ports C / G / L / E / F Source Current
Ports C / G / L / E / F Sink Current
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Ports C / G / L / E / F Weak Pull-Up Source Current
Dynamic - IDD vs VCC
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Idle - IDD vs VCC
HALT - IDD vs VCC
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Pin Descriptions
VCC and GND are the power supply pins. All VCC and GND pins must be connected. CKI is the clock input. This comes from an R / C generated oscillator, or a crystal oscillator (in conjunction with CKO). See Oscillator Description section. RESET is the master reset input. See Reset description section. The device contains five bidirectional 8-bit I / O ports (C, E, F, G and L), where each individual bit may be independently configured as an input (Schmitt trigger inputs on ports L and G), output or TRI-STATE under program control. Three data memory address locations are allocated for each of these I / O ports. Each I / O port has two associated 8-bit memory mapped registers, the CONFIGURATION register and the output DATA register. A memory mapped address is also reserved for the input pins of each I / O port. (See the memory map for the various addresses associated with the I / O ports.) Figure 3 shows the I / O port configurations. The DATA and CONFIGURATION registers allow for each port bit to be individually configured under software control as shown below: Configuration Register 0 0 1 1 Data Register 0 1 0 1 Hi-Z Input (TRI-STATE Output) Input with Weak Pull-Up Push-Pull Zero Output Push-Pull One Output Port Set-Up
PORT L is an 8-bit I / O port. All L-pins have Schmitt triggers on the inputs. The Port L supports Multi-Input Wake Up on all eight pins. L1 is used for the UART external clock. L2 and L3 are used for the UART transmit and receive. L4 and L5 are used for the timer input functions T2A and T2B. L6 and L7 are used for the capture timer input functions CAP1 and CAP2. The Port L has the following alternate features: L0 MIWU L1 MIWU or CKX L2 MIWU or TDX L3 MIWU or RDX L4 MIWU or T2A L5 MIWU or T2B L6 MIWU or CAP1 L7 MIWU or CAP2 Port G is an 8-bit port with 6 I / O pins (G0-G5), an input pin (G6), and a dedicated output pin (G7). Pins G0-G6 all have Schmitt Triggers on their inputs. Pin G7 serves as the dedicated output pin for the CKO clock output. There are two registers associated with the G Port, a data register and a configuration register. Therefore, each of the 6 I / O bits (G0-G5) can be individually configured under software control.
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Pin Descriptions
(Continued)
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Port G has the following alternate features: G0 INTR (ExternaI Interrupt Input) G2 T1B (Timer T1 Capture Input) G3 T1A (Timer T1 I / O) G4 SO (MICROWIRE Serial Data Output) G5 SK (MICROWIRE SeriaI Clock) G6 SI (MICROWIRE Serial Data Input) Port G has the following dedicated functions: G7 CKO OsciIlator dedicated output Ports C and F are 8-bit I / O ports. Port E is an 8-bit I / O port. It has the following alternate features: E0 CT1 (Output for counter1, PuIse Train Generator) E1 CT2 (Output for counter2, Pulse Train Generator) E2 CT3 (Output for counter3, PuIse Train Generator) E3 CT4 (Output for counter4, Pulse Train Generator) Port I is an eight-bit Hi-Z input port. Port D is an 8-bit output port that is preset high when RESET goes Iow. The user can tie two or more D port outputs (except D2) together in order to get a higher drive.
Functional Description
The architecture of the device is modified Harvard architecture. With the Harvard architecture, the control store program memory (ROM) is separated from the data store
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Functional Description
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The data memory consists of 512 bytes of RAM. Sixteen bytes of RAM are mapped as "registers" at addresses 0F0 to 0FF Hex. These registers can be loaded immediately, and also decremented and tested with the DRSZ (decrement register and skip if zero) instruction. The memory pointer registers X, SP, B and S are memory mapped into this space at address locations 0FC to 0FF Hex respectively, with the other registers being available for general usage.
Note: RAM contents are undefined upon power-up.
Data Memory Segment RAM Extension
Data memory address 0FF is used as a memory mapped location for the Data Segment Address Register (S). The data store memory is either addressed directly by a single-byte address within the instruction, or indirectly relative to the reference of the B, X, or SP pointers (each contains a single-byte address). This single-byte address allows an addressing range of 256 locations from 00 to FF hex. The upper bit of this single-byte address divides the data store memory into two separate sections as outlined previously. With the exception of the RAM register memory from address locations 00F0 to 00FF, all RAM memory is memory mapped with the upper bit of the single-byte address being equal to zero. This allows the upper bit of the single-byte address to determine whether or not the base address range (from 0000 to 00FF) is extended. If this upper bit equals one (representing address range 0080 to 00FF), then address extension does not take place. Alternatively, if this upper bit equals zero, then the data segment extension register S is used to extend the base address range (from 0000 to 007F) from XX00 to XX7F, where XX represents the 8 bits from the S register. Thus the 128-byte data segment extensions are located from addresses 0100 to 017F for data segment 1, 0200 to 027F for data segment 2, etc., up to FF00 to FF7F for data segment 255. The base address range from 0000 to 007F represents data segment 0.
Figure 4 illustrates how the S register data memory extension is used in extending the lower half of the base address range (00 to 7F hex) into 256 data segments of 128 bytes each, with a total addressing range of 32 kbytes from XX00 to XX7F. This organization allows a total of 256 data segments of 128-bytes each with an additional upper base segment of 128 bytes. Furthermore, all addressing modes are availabIe for all data segments. The S register must be changed under program control to move from one data segment (128 bytes) to another. However, the upper base segment (containing the 16 memory registers, I / O registers, controI registers, etc.) is always available regardless of the contents of the S register, since the upper base segment (address range 0080 to 00FF) is independent of data segment extension. The instructions that utilize the stack pointer (SP) always reference the stack as part of the base segment (Segment 0), regardless of the contents of the S register. The S register is not changed by these instructions. Consequently, the stack (used with subroutine linkage and interrupts) is always located in the base segment. The stack pointer will be initialized to point at data memory location 006F as a result of reset. The 128 bytes of RAM contained in the base segment are split between the Iower and upper base segments. The first 112 bytes of RAM are resident from address 0000 to 006F in the Iower base segment, while the remaining 16 bytes of RAM represent the 16 data memory registers located at addresses 00F0 to 00FF of the upper base segment. No RAM is located at the upper sixteen addresses (0070 to 007F) of the lower base segment. Additional RAM beyond these initial 128 bytes, however, will always be memory mapped in groups of 128 bytes (or less) at the data segment address extensions (XX00 to XX7F) of the lower base segment. The additional 384 bytes of RAM in this device are memory mapped at address locations 0100 to 017F° 0200 to 027F, and 0300 to 037F hex.
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Data Memory Segment RAM Extension
(Continued)
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Note 10: Reads as all ones.
FIGURE 4. RAM Organization
Reset
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Reset
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WKEN, WKEDG: CLEARED WKPND: RANDOM S Register: CLEARED SP (Stack Pointer): Loaded with 6F Hex B and X Pointers: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on RAM: UNAFFECTED after RESET with power already applied RANDOM after RESET at power-on The external RC network shown in Figure 5 should be used to ensure that the RESET pin is held low until the power supply to the chip stabilizes.
Control Registers
T1C3 Bit 7 T1C2 T1C1 T1C0 MSEL IEDG SL1 SL0 Bit 0
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FIGURE 5. Recommended Reset Circuit
Oscillator Circuits
The chip can be driven by a clock input on the CKI input pin which can be between DC and 10 MHz. The CKO output clock is on pin G7 (crystal configuration), The CKI input frequency is divided down by 10 to produce the instruction cycle clock (tc).
Figure 6 shows the Crystal diagram
HC Bit 7 C T1PNDA T1ENA EXPND BUSY EXEN GIE Bit 0
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FIGURE 6. Crystal Diagram CRYSTAL OSCILLATOR CKI and CKO can be connected to make a closed loop crystal (or resonator) controlled oscillator.
Table 1 shows the component values required for various standard crystal values.
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Control Registers
T0EN T0PND LPEN
(Continued)
Timer T0 Interrupt Enable (Bit 12 toggle) Timer T0 Interrupt pending L Port Interrupt Enable (Multi-Input Wake up / Interrupt)
Bit 7 could be used as a flag
Unused Bit 7 LPEN T0PND T0EN WPND WEN T1PNDB T1ENB Bit 0
T2C3 Bit 7 T2C2 T2C1 T2C0 T2PNDA T2ENA T2PNDB T2ENB Bit 0
Each timer block consists of a 16-bit timer, Tx, and two supporting 16-bit autoreload / capture registers, RxA and RxB. Each timer block has two pins associated with it, TxA and TxB. The pin TxA supports I / O required by the timer block, while the pin TxB is an input to the timer block. The powerful and flexible timer block allows the device to easily perform all timer functions with minimal software overhead. The timer block has three operating modes: Processor Independent PWM mode, External Event Counter mode, and Input Capture mode. The control bits TxC3, TxC2, and TxC1 allow selection of the different modes of operation. Mode 1. Processor Independent PWM Mode As the name suggests, this mode allows the device to generate a PWM signal with very minimal user intervention. The user only has to define the parameters of the PWM signal (ON time and OFF time). Once begun, the timer block will continuously generate the PWM signal completely independent of the microcontroller. The user software services the timer block only when the PWM parameters require updating. In this mode the timer Tx counts down at a fixed rate of tc. Upon every underflow the timer is alternately reloaded with the contents of supporting registers, RxA and RxB. The very first underflow of the timer causes the timer to reload from the register RxA. Subsequent underflows cause the timer to be reloaded from the registers alternately beginning with the register RxB. The Tx Timer control bits, TxC3, TxC2 and TxC1 set up the timer for PWM mode operation.
Timers
The device contains a very versatile set of timers (T0, T1, T2). All timers and associated autoreload / capture registers power up containing random data. TIMER T0 (IDLE TIMER) The device supports applications that require maintaining reaI time and Iow power with the IDLE mode. This IDLE mode support is furnished by the IDLE timer T0, which is a 16-bit timer. The Timer T0 runs continuously at the fixed rate of the instruction cycle cIock, tc. The user cannot read or write to the IDLE Timer T0, which is a count down timer. The Timer T0 supports the following functions:
TIMER T1 AND TIMER T2 The device has a set of two powerful timer / counter blocks, T1 and T2. The associated features and functioning of a timer block are described by referring to the timer block Tx. Since the two timer blocks, T1 and T2 are identical, all comments are equally applicable to either of the two timer blocks.
Figure 7 shows a block diagram of the timer in PWM mode. The underfIows can be programmed to toggle the TxA output pin. The underfIows can also be programmed to generate interrupts. UnderfIows from the timer are alternately latched into two pending flags, TxPNDA and TxPNDB. The user must reset these pending fIags under software control. Two control enabIe fIags, TxENA and TxENB, alIow the interrupts from the timer underflow to be enabled or disabled. Setting the timer enable flag TxENA wilI cause an interrupt when a timer underflow causes the RxA register to be reloaded into the timer. Setting the timer enable flag TxENB will cause an interrupt when a timer underflow causes the RxB register to be reloaded into the timer. Resetting the timer enable flags will disable the associated interrupts. Either or both of the timer underflow interrupts may be enabled. This gives the user the flexibility of interrupting once per PWM period on either the rising or falling edge of the PWM output. Alternatively, the user may choose to interrupt on both edges of the PWM output.
Mode 2. ExternaI Event Counter Mode This mode is quite similar to the processor independent PWM mode described above. The main difference is that the timer, Tx, is cIocked by the input signal from the TxA pin. The Tx timer control bits, TxC3, TxC2 and TxC1 allow the timer to be clocked either on a positive or negative edge from the TxA pin. Underflows from the timer are Iatched into the TxPNDA pending flag. Setting the TxENA control flag will cause an interrupt when the timer underflows.
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Timers
(Continued)
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FIGURE 7. Timer in PWM Mode
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FIGURE 8. Timer in External Event Counter Mode
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Timers
(Continued)
In this mode the input pin TxB can be used as an independent positive edge sensitive interrupt input if the TxENB control flag is set. The occurrence of a positive edge on the TxB input pin is latched into the TxPNDB flag.
The trigger conditions can also be programmed to generate interrupts. The occurrence of the specified trigger condition on the TxA and TxB pins will be respectively Iatched into the pending flags, TxPNDA and TxPNDB. The control flag TxENA allows the interrupt on TxA to be either enabled or disabled. Setting the TxENA flag enables interrupts to be generated when the selected trigger condition occurs on the TxA pin. Similarly, the flag TxENB controls the interrupts from the TxB pin. Underflows from the timer can also be programmed to generate interrupts. Underflows are latched into the timer TxC0 pending flag (the TxC0 control bit serves as the timer underflow interrupt pending flag in the Input Capture mode). Consequently, the TxC0 control bit should be reset when entering the Input Capture mode. The timer underflow interrupt is enabled with the TxENA control flag. When a TxA interrupt occurs in the Input Capture mode, the user must check both the TxPNDA and TxC0 pending flags in order to determine whether a TxA input capture or a timer underflow (or both) caused the interrupt.
Figure 8 shows a block diagram of the timer in External Event Counter mode.
Note: The PWM output is not available in this mode since the TxA pin is being used as the counter input clock.
Mode 3. Input Capture Mode The device can precisely measure external frequencies or time external events by placing the timer block, Tx, in the input capture mode. In this mode, the timer Tx is constantly running at the fixed tc rate. The two registers, RxA and RxB, act as capture registers. Each register acts in conjunction with a pin. The register RxA acts in conjunction with the TxA pin and the register RxB acts in conjunction with the TxB pin. The timer value gets copied over into the register when a trigger event occurs on its corresponding pin. Control bits, TxC3, TxC2 and TxC1, allow the trigger events to be specified either as a positive or a negative edge. The trigger condition for each input pin can be specified independently.
Figure 9 shows a block diagram of the timer in Input Capture mode.
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Capture Timer
This device contains two independent capture timers, Capture Timer 1 and Capture Timer 2. Each capture timer contains an 8-bit programmable prescaler register, a 16-bit down counter, a 16-bit input capture register, and capture edge select Iogic. The 16-bit down counter is clocked at a specific frequency determined by the value loaded into the prnscaler register. A selected positive or negative edge transition on the capture input causes the contents of the down counter to be latched into the capture register. The values captured in the registers reflect the eIapsed time between two positive or two negative transitions on the capture input. The time between a positive and negative edge (a pulse width) may be measured if the selected capture edge is switched after the first edge is captured. Each capture timer
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Capture Timer
(Continued)
Figure 10 shows the capture timer 1 block diagram.
may be stopped / started under software control, and each capture timer may be configured to interrupt the microcontroller on an underflow or input capture. TABLE 2. Timer Mode Control TxC3 0 0 1 1 0 TxC2 0 0 0 0 1 TxC1 0 1 1 0 0 Timer Mode MODE 2 (External Event Counter) MODE 2 (External Event Counter) MODE 1 (PWM) TxA Toggle MODE 1 (PWM) No TxA Toggle MODE 3 (Capture) Captures: TxA Positive Edge TxB Positive Edge 1 1 0 MODE 3 (Capture) Captures: TxA Positive Edge TxB Negative Edge 0 1 1 MODE 3 (Capture) Captures: TxA Negative Edge TxB Positive Edge 1 1 1 MODE 3 (Capture) Captures: TxA Negative Edge TxB Negative Edge Negative TxA Edge or Timer Underflow Negative TxB Edge tc Negative TxA Edge or Timer Underflow Positive TxB Edge tc Positive TxA Edge or Timer Underflow Negative TxB Edge tc Interrupt A Source Timer Underflow Timer Underflow Autoreload RA Autoreload RA Positive TxA Edge or Timer Underflow Interrupt B Source Positive TxB Edge Positive TxB Edge Autoreload RB Autoreload RB Positive TxB Edge Timer Counts On TxA Positive Edge TxA Negative Edge tc tc tc
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FIGURE 10. Capture Timer 1 Block Diagram
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Capture Timer
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Capture Timer
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interrupts should not be disabIed prior to stopping the timer. If interrupts are not being used, the user should poll the capture timer pending bits after stopping the timer. If the user wishes to ignore this capture and interrupts are being used, the capture timer interrupt service routine should check that the timer is still running prior to processing capture interrupts. If the user is polling the pending flags, these flags should be cleared after the timer is stopped. The contents of the prescaler and down counter remain unchanged while the capture timer is stopped. The capture edge detect logic is disabled, and no capture takes place even if an external capture signal occurs. The capture timer may be restarted under software control by writing a "1" to the start / stop bit. This causes the prescaler and down counter to be re-initialized. The prescaler is loaded from the prescaler register, and the down counter is loaded with 0FFFF Hex. RESET STATE A reset signal applied to the counter block during normal operation has the following effects:
WARNING In order to avoid erroneous interrupts, the capture timer interrupts must be disabled prior to setting / resetting the capture edge control bits (CMxEC). In addition, after selecting the interrupt edge, the pending flags must be reset before the capture interrupts are enabled or re-enabled. If the initialization sequence outlined above is followed each time the user aIters the edge control bits, the user is guaranteed to avoid erroneous interrupts.
CM1PSC, CMICRL, CM1CRH, CM2PSC, CM2CRL and CM2CRH are unaffected. (At power-on, the contents of these registers are undefined.) The bi-directional port pins are initialized during reset as HI-Z inputs. Setting the start / stop bits connects the pins to the capture timers. INITIALIZATION The user should perform the following initialization prior to starting the capture timer: 1. Reset the CMxRUN bit
Clear CCMR1 register Clear CCMR2 register
Pulse Train Generators
Figure 11 shows the pulse train generator 1 block diagram.
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FIGURE 11. Pulse Train Generator 1 Block Diagram
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Pulse Train Generators
(Continued)
C4 IPND
C4 IEN
C4 RUN
C3 IPND
C3 IEN
C3 RUN Bit 0
C2 Bit 7 C2 IPND C2 IEN C2 RUN C1 C1 IPND C1 IEN C1 RUN Bit 0
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Pulse Train Generators
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erated before the output is toggled. The user may also choose to alter the logic level on the port pin before restarting. This is done by initializing the associated port pin data register bit. A counter underflow may occur before the start / stop bit is physically cleared by software. The user must ensure that the software handles this situation correctly. If the user wishes to process this underflow and interrupts are being used, the counter interrupts should not be disabled prior to stopping the timer. If interrupts are not being used, the user should poll the counter pending bits after stopping the timer. If the user wishes to ignore this underflow and interrupts are being used, the counter interrupt should be disabled prior to stopping the timer. If the user is polling the pending flags, these flags should be cleared after the timer is stopped. If the default level of the output pin is high (associated port data register bit is set to "1") and the counter is stopped during a low level, the low level becomes the default level. The software must reinitialize the port pin to a high level before restarting if necessary. The programmer may also have to adjust the counter value (See Figure 12). RESET STATE A reset signal applied to the pulse train generator block during normal operation has the following effects:
Divide-by-2 counter is reset The bi-directional port pins are initialized during reset as HI-Z inputs. The appropriate bits must be initialized as outputs, in order to route the Counter OUT signals to the port pins.
INITIALIZATION The user should perform the following initialization prior to starting the counter: 1. Load PRL register 2. Load PRH register 3. Load CTL register 4. Load CTH register 5. Reset CxIPND bit 6. Set CxIEN (if interrupt is to be used) 7. Configure the associated port bit as an output (if OUT is to be used) 8. Set the Global Interrupt Enable (GIE) bit (if interrupt is to be used) 9. Set CxRUN bit to start counter
Multiply / Divide
This device contains a multiply / divide block. This block supports a 1 byte x 2 bytes (3 bytes result) multiply or a 3 bytes / 2 bytes (2 bytes result) divide operation. The multiply or divide operation is executed by setting control bits located in the multiply / divide control register. The multiply or divide operands must be placed into the appropriate memory mapped locations before the operation is initiated.
Counting stops immediately Interrupt enable bit is reset to zero Counter start / stop bit is reset to zero Interrupt pending bit is reset to zero Test mode controI bit is reset to zero PRL, PRH, CTL and CTH are unaffected (At power-on reset, the contents of the prescaler and count register are undefined.)
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Multiply / Divide
Register Name (Address) MDR1 (xx98) MDR2 (xx99) MDR3 (xx9A) MDR4 (xx9B) MDR5 (xx9C)
(Continued) TABLE 3. Multiply / Divide Registers Multiplication Assignment Before Operation Unused Multiplier After Operation Unchanged Low byte of result Middle byte of result High byte of result Unchanged Division Assignment Before Operation Low byte of dividend Middle byte of dividend High byte of dividend Low byte of divisor High byte of divisor After Operation Low byte of result High byte of result Undefined Low byte of divisor High byte of divisor
Low byte of multiplicand High byte of multiplicand
bit is set in the multiply / divide control register. The dividend and the divisor are left unchanged. The divide operation always causes the DIVOVF flag to be set or reset as appropriate. The DIVOVF flag is cleared following a multiply operation. RESET STATE A reset signal applied to the device during normal operation has the following affects: MDCR is cleared, and any operation in progress is stopped. MDR1 through MDR5 are undefined.
Power Save Modes
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Power Save Modes
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The user can enter the IDLE mode with the Timer T0 interrupt enabled. In this case, when the T0PND bit gets set, the device will first execute the Timer T0 interrupt service routine and then return to the instruction following the "Enter Idle Mode" instruction. Alternatively, the user can enter the IDLE mode with the IDLE Timer T0 interrupt disabled. In this case, the device will resume normal operation with the instruction immediately following the "Enter IDLE Mode" instruction.
Note: It is necessary to program two NOP instructions following both the set HALT mode and set IDLE mode instructions. These NOP instructions are necessary to allow clock resynchronization following the HALT or IDLE modes.
Multi-Input Wakeup
The Multi-Input Wake Up feature is used to return (wake up) the device from either the HALT or IDLE modes. Alternately Multi-Input Wake Up / Interrupt feature may also be used to generate up to 8 edge selectable external interrupts.
Figure 13 shows the Multi-Input Wake Up logic.
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FIGURE 13. Multi-Input Wake Up Logic The Multi-Input Wake Up feature utilizes the L Port. The user selects which particular L port bit (or combination of L Port bits) will cause the device to exit the HALT or IDLE modes. The selection is done through the register WKEN. The register WKEN is an 8-bit read / write register, which contains a control bit for every L port bit. Setting a particular WKEN bit enables a Wake Up from the associated L port pin. The user can select whether the trigger condition on the selected L Port pin is going to be either a positive edge (low to high transition) or a negative edge (high to low transition).
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Multi-Input Wakeup
(Continued)
This selection is made via the register WKEDG, which is an 8-bit control register with a bit assigned to each L Port pin. Setting the control bit will select the trigger condition to be a negative edge on that particular L Port pin. Resetting the bit selects the trigger condition to be a positive edge. Changing an edge select entails several steps in order to avoid a Wake Up condition as a result of the edge change. First, the associated WKEN bit should be reset, followed by the edge select change in WKEDG. Next, the associated WKPND bit should be cleared, followed by the associated WKEN bit being reenabled. An example may serve to clarify this procedure. Suppose we wish to change the edge select from positive (low going high) to negative (high going low) for L Port bit 5, where bit 5 has previously been enabled for an input interrupt. The program would be as follows: RBIT 5, WKEN SBIT 5, WKEDG RBIT 5, WKPND SB1T 5, WKEN If the L port bits have been used as outputs and then changed to inputs with Multi-Input Wake Up / lnterrupt, a safety procedure should also be followed to avoid wakeup conditions. After the selected L port bits have been changed from output to input but before the associated WKEN bits are enabled, the associated edge select bits in WKEDG should be set or reset for the desired edge selects, followed by the associated WKPND bits being cleared, This same procedure should be used following reset, since the L port inputs are left floating as a result of reset. The occurrence of the selected trigger condition for Multi-Input Wake Up is latched into a pending register called WKPND. The respective bits of the WKPND register will be set on the occurrence of the selected trigger edge on the corresponding Port L pin. The user has the responsibility of clearing these pending flags. Since WKPND is a pending register for the occurrence of selected wake up conditions, the device will not enter the HALT mode if any Wake Up bit is both enabled and pending. Consequently, the user must clear the pending flags before attempting to enter the HALT mode. WKEN, WKPND and WKEDG are all read / write registers, and are cleared at reset. PORT L INTERRUPTS Port L provides the user with an additional eight fully selectable, edge sensitive interrupts which are all vectored into the same service subroutine.
The interrupt from Port L shares logic with the wake up circuitry. The register WKEN allows interrupts from Port L to be individually enabled or disabled. The register WKEDG specifies the trigger condition to be either a positive or a negative edge. Finally, the register WKPND latches in the pending trigger conditions. The GIE (Global Interrupt Enable) bit enables the interrupt function. A control flag, LPEN, functions as a global interrupt enable for Port L interrupts. Setting the LPEN flag will enable interrupts and vice versa. A separate global pending flag is not needed since the register WKPND is adequate. Since Port L is also used for waking the device out of the HALT or lDLE modes, the user can elect to exit the HALT or IDLE modes either with or without the interrupt enabled. If he elects to disable the interrupt, then the device will restart execution from the instruction immediately following the instruction that placed the microcontroller in the HALT or IDLE modes. In the other case, the device will first execute the interrupt service routine and then revert to normal operation. (See HALT MODE for clock option wake up information.)
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FIGURE 14. UART Block Diagram UART CONTROL AND STATUS REGISTERS The operation of the UART is programmed through three registers: ENU, ENUR and ENUI. The function of the individual bits in these registers is as follows: ENU-UART Control and Status Register (Address at 0BA)
PEN PSEL1 XBIT9 / PSEL0 0RW Bit 7 0RW 0RW 0RW 0RW 0R 0R IR Bit 0 CHL1 CHL0 ERR RBFL TBMT
ENUR-UART Receive Control and Status Register (Address at 0BB)
DOE 0RD Bit 7 FE 0RD PE 0RD SPARE 0RW RBlT9 0R ATTN 0RW XMTG 0R RCVG 0R Bit 0
ENUI-UART Interrupt and Clock Source Register (Address at 0BC)
STP2 0RW Bit 7 STP78 0RW ETDX 0RW SSEL 0RW XRCLK 0RW XTCLK 0RW ERI 0RW ETI 0RW Bit 0
Bit is not used. Bit is cleared on reset. Bit is set to one on reset. Bit is read-only it cannot be written by software. Bit is read / write. Bit is cleared on read when read by software as a one, it is cleared automatically. Writing to the bit does not affect its state.
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PEN: This bit enables / disables Parity (7- and 8-bit modes only). Parity disabled. Parity enabled.
Associated I / O Pins
Data is transmitted on the TDX pin and received on the RDX pin. TDX is the alternate function assigned to Port L pin L2 it is selected by setting ETDX (in the ENUI register) to one. RDX is an inherent function of Port L pin L3, requiring no setup. The baud rate clock for the UART can be generated on-chip, or can be taken from an external source. Port L pin L1 (CKX) is the external clock I / O pin. The CKX pin can be either an input or an output, as determined by Port L Configuration and Data registers (Bit 1). As an input, it accepts a clock signal which may be selected to drive the transmitter and / or receiver. As an output, it presents the internal Baud Rate Generator output.
UART Operation
The UART has two modes of operation: asynchronous mode and synchronous mode. ASYNCHRONOUS MODE This mode is selected by resetting the SSEL (in the ENUI register) bit to zero. The input frequency to the UART is 16 times the baud rate. The TSFT and TBUF registers double-buffer data for transmission. While TSFT is shifting out the current character on the TDX pin, the TBUF register may be loaded by software with the next byte to be transmitted. When TSFT finishes transmitting the current character the contents of TBUF are transferred to the TSFT register and the Transmit Buffer Empty Flag (TBMT in the ENU register) is set. The TBMT flag is automatically reset by the UART when software loads a new character into the TBUF register. There is also the XMTG bit which is set to indicate that the UART is transmitting. This bit gets reset at the end of the last frame (end of last Stop bit). TBUF is a read / write register. The RSFT and RBUF registers double-buffer data being received. The UART receiver continually monitors the signal on the RDX pin for a low level to detect the beginning of a Start bit. Upon sensing this low level, it waits for half a bit time and samples again. If the RDX pin is still low, the receiver considers this to be a valid Start bit, and the remaining bits in the character frame are each sampled a single time, at the mid-bit position. Serial data input on the RDX pin is shifted into the RSFT register. Upon receiving the complete character, the contents of the RSFT register are copied into the RBUF register and the Received Buffer Full Flag (RBFL) is set. RBFL is automatically reset when software reads the character from the RBUF register. RBUF is a read only register. There is also the RCVG bit which is set high when a framing error occurs and goes low once RDX goes high. TBMT, XMTG, RBFL and RCVG are read only bits.
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UART Operation
SYNCHRONOUS MODE
(Continued)
In this mode data is transferred synchronously with the clock. Data is transmitted on the rising edge and received on the falling edge of the synchronous clock. This mode is selected by setting SSEL bit in the ENUI register. The input frequency to the UART is the same as the baud rate. When an external clock input is selected at the CKX pin, data transmit and receive are performed synchronously with this clock through TDX / RDX pins. If data transmit and receive are selected with the CKX pin as clock output, the device generates the synchronous clock output at the CKX pin. The internal baud rate generator is used to produce the synchronous clock. Data transmit and receive are performed synchronously with this clock. FRAMING FORMATS The UART supports several serial framing formats (Figure 15). The format is selected using control bits in the ENU, ENUR and ENUI registers.
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FIGURE 15. Framing Formats For any of the above framing formats, the last Stop bit can be programmed to be 7 / 8th of a bit in length. If two Stop bits are selected and the 7 / 8th bit is set (selected), the second Stop bit will be 7 / 8th of a bit in length. The parity is enabled / disabled by PEN bit located in the ENU register. Parity is selected for 7- and 8-bit modes only. If
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UART Operation
(Continued)
with nine data bits per frame. There is no parity selection in this framing format. For other framing formats XBIT9 is not needed and the bit is PSEL0 used in conjunction with PSEL1 to select parity. The frame formats for the receiver differ from the transmitter in the number of Stop bits required. The receiver only requires one Stop bit in a frame, regardless of the setting of the Stop bit selection bits in the control register. Note that an implicit assumption is made for full duplex UART operation that the framing formats are the same for the transmitter and receiver. UART INTERRUPTS The UART is capable of generating interrupts. Interrupts are generated on Receive Buffer Full and Transmit Buffer Empty. Both interrupts have individual interrupt vectors. Two bytes of program memory space are reserved for each interrupt vector. The two vectors are located at addresses 0xEC to 0xEF Hex in the program memory space. The interrupts can be individually enabled or disabled using Enable Transmit Interrupt (ETl) and Enable Receive Interrupt (ERl) bits in the ENUI register.
The interrupt from the Transmitter is set pending, and remains pending, as long as both the TBMT and ETl bits are set. To remove this interrupt, software must either clear the ETI bit or write to the TBUF register (thus clearing the TBMT bit). The interrupt from the receiver is set pending, and remains pending, as long as both the RBFL and ERI bits are set. To remove this interrupt, software must either clear the ERl bit or read from the RBUF register (thus clearing the RBFL bit).
Baud Clock Generation
The clock inputs to the transmitter and receiver sections of the UART can be individually selected to come either from an external source at the CKX pin (port L, pin L1) or from a source selected in the PSR and BAUD registers. Internally, the basic baud clock is created from the oscillator frequency through a two-stage divider chain consisting of a 1-16 (increments of 0.5) prescaler and an 11-bit binary counter (Figure 16). The divide factors are specified through two read / write registers shown in Figure 17. Note that the 11-bit Baud Rate Divisor spills over into the Prescaler Select Register (PSR). PSR is cleared upon reset.
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FIGURE 16. UART BAUD Clock Generation
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FIGURE 17. UART BAUD Clock Divisor Registers
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Baud Clock Generation
(Continued)
TABLE 5. Prescaler Factors Prescaler Select 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Prescaler Factor NO CLOCK 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 6 6.5 7 7.5 8 8.5 9 9.5 10 10.5 11 11.5 12 12.5 13 13.5 14 14.5 15 15.5 16
As shown in Table 5, a Prescaler Factor of 0 corresponds to NO CLOCK. This condition is the UART power down mode where the UART clock is turned off for power saving purpose. The user must also turn the UART clock off when a different baud rate is chosen. The correspondences between the 5-bit Prescaler Select and Prescaler factors are shown in Table 5. There are many ways to calculate the two divisor factors, but one particularly effective method would be to achieve a 1.8432 MHz frequency coming out of the first stage. The 1.8432 MHz prescaler output is then used to drive the software programmable baud rate counter to create a 16x clock for the following baud rates: 110, 134.5, 150, 300, 600, 1200, 1800, 2400, 3600, 4800, 7200, 9600, 19200 and 38400 (Table 4). Other baud rates may be created by using appropriate divisors. The 16x clock is then divided by 16 to provide the rate for the serial shift registers of the transmitter and receivers. TABLE 4. Baud Rate Divisors (1.8432 MHz PrescaIer Output) Baud Rate 110 (110.03) 134.5 (134.58) 150 300 600 1200 1800 2400 3600 4800 7200 9600 19200 38400 Baud Rate Divisor - 1 (N-1) 1046 855 767 383 191 95 63 47 31 23 15 11 5 2
Note 11: The entries in Table 4 assume a prescaIer output of 1.8432 MHz. In asynchronous mode the baud rate could be as high as 625k.
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Baud Clock Generation
(Continued)
Note: In the Synchronous Mode, the divisor 16 is replaced by two.
The idle timer (T0) generates a fixed (256 tc) delay to ensure that the oscillator has indeed stabilized before allowing the device to execute code. The user has to consider this delay when data transfer is expected immediately after exiting the HALT mode.
Diagnostic
Bits CHARL0 and CHARL1 in the ENU register provide a Ioopback feature for diagnostic testing of the UART. When these bits are set to one, the following occur: The receiver input pin (RDX) is internally connected to the transmitter output pin (TDX) the output of the Transmitter Shift Register is "looped back" into the Receive Shift Register input. In this mode, data that is transmitted is immediately received. This feature allows the processor to verify the transmit and receive data paths of the UART. Note that the framing format for this mode is the nine bit format one Start bit, nine data bits, and 7 / 8, one or two Stop bits. Parity is not generated or verified in this mode.
Attention Mode
The UART Receiver section supports an alternate mode of operation, referred to as ATTENTION Mode. This mode of operation is selected by the ATTN bit in the ENUR register. The data format for transmission must also be selected as having nine Data bits and either 7 / 8, one or two Stop bits. The ATTENTION mode of operation is intended for use in networking the device with other processors. Typically in such environments the messages consists of device addresses, indicating which of several destinations should receive them, and the actual data. This Mode supports a scheme in which addresses are flagged by having the ninth bit of the data field set to a 1. If the ninth bit is reset to a zero the byte is a Data byte. While in ATTENTION mode, the UART monitors the communication flow, but ignores all characters until an address character is received. Upon receiving an address character, the UART signals that the character is ready by setting the RBFL flag, which in turn interrupts the processor if UART Receiver interrupts are enabled. The ATTN bit is also cleared automatically at this point, so that data characters as well as address characters are recognized. Software examines the contents of the RBUF and responds by deciding either to accept the subsequent data stream (by leaving the ATTN bit reset) or to wait until the next address character is seen (by setting the ATTN bit again). Operation of the UART Transmitter is not affected by selection of this Mode. The value of the ninth bit to be transmitted is programmed by setting XBIT9 appropriately. The value of the ninth bit received is obtained by reading RBIT9. Since this bit is located in ENUR register where the error flags reside, a bit operation on it will reset the error flags.
Effect of HALT / IDLE
The UART logic is reinitialized when either the HALT or IDLE modes are entered. This reinitialization sets the TBMT flag and resets all read only bits in the UART control and status registers. Read / Write bits remain unchanged. The Transmit Buffer (TBUF) is not affected, but the Transmit Shift register (TSFT) bits are set to one. The receiver registers RBUF and RSFT are not affected. The device will exit from the HALT / IDLE modes when the Start bit of a character is detected at the RDX (L3) pin. This feature is obtained by using the Multi-Input Wakeup scheme provided on the device. Before entering the HALT or IDLE modes the user program must select the Wakeup source to be on the RDX pin. This selection is done by setting bit 3 of WKEN (Wakeup Enable) register. The Wakeup trigger condition is then selected to be high to low transition. This is done via the WKEDG register (Bit 3 is "one"). If the device is halted and crystal oscillator is used, the Wake Up signal will not start the chip running immediately because of the finite start up time requirement of the crystal oscillator.
Interrupts
The devices supports a vectored interrupt scheme. It supports a total of fourteen interrupt sources. Table 6 lists all the possible device interrupt sources, their arbitration rankings and the memory locations reserved for the interrupt vector for each source. Two bytes of program memory space are reserved for each interrupt source. All interrupt sources except the software interrupt are maskable. Each of the maskable interrupts have an Enable bit and one or more Pending bits. A maskable interrupt is active it its associated enable and
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Interrupts
(Continued)
Thus, if an interrupt with a higher rank than the one which caused the interruption becomes active before the decision of which interrupt to service is made by the VIS, then the interrupt with the higher rank will override any lower ones and will be acknowledged. The lower priority interrupt(s) are still pending, however, and will cause another interrupt immediately following the completion of the interrupt service routine associated with the higher priority interrupt just serviced. This lower priority interrupt will occur immediately following the RETI (Return from Interrupt) instruction at the end of the interrupt service routine just completed. Inside the interrupt service routine, the associated pending bit has to be cleared by software. The RETI (Return from Interrupt) instruction at the end of the interrupt service routine will set the GIE (Global Interrupt Enable) bit, allowing the processor to be interrupted again if another interrupt is active and pending. The VIS instruction looks at all the active interrupts at the time it is executed and performs an indirect jump to the beginning of the service routine of the one with the highest rank. The addresses of the different interrupt service routines, called vectors, are chosen by the user and stored in ROM in a table starting at 01E0 (assuming that VIS is located between 00FF and 01DF). The vectors are 15-bit wide and therefore occupy 2 ROM locations.
TABLE 6. Interrupt Vector Table ARBITRATION RANKING (1) Highest (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) (13) (14) (15) (16) Lowest Software Reserved External Timer T0 Timer T1 Timer T1 Microwire / PIus Counters UART UART Timer T2 Timer T2 Capture Timer 1 and 2 Unused Port L / Wakeup Default VIS Reserved Receive Transmit T2A / Underflow T2B G0 Underflow T1A / Underflow T1B Busy Low SOURCE DESCRIPTION VECTOR (Note 12) ADDRESS (Hi-Low Byte) 0yFE-0yFF 0yFC-0yFD 0yFA-0yFB 0yF8-0yF9 0yF6-0yF7 0yF4-0yF5 0yF2-0yF3 0yF0-0yF1 0yEE-0yEF 0yEC-0yED 0yEA-0yEB 0yE8-0yE9 0yE6-0yE7 0yE4-0yE5 0yE2-0yE3 0yE0-0yE1
Note 12: y is a variable which represents the VIS block. VIS and the vector table must be located in the same 256-byte block except if VIS is located at the last address of a block, In this case, the table must be in the next block.
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Interrupts
(Continued)
VIS and the vector table must be located in the same 256-byte block (0y00 to 0yFF) except if VIS is located at the last address of a block. In this case, the table must be in the next block. The vector table cannot be inserted in the first 256-byte block (y 0). The vector of the maskable interrupt with the lowest rank is located at 0yE0 (Hi-Order byte) and 0yE1 (Lo-Order byte) and so forth in increasing rank number. The vector of the maskable interrupt with the highest rank is located at 0yFA (Hi-Order byte) and 0yFB (Lo-Order byte). The Software Trap has the highest rank and its vector is located at 0yFE and 0yFF. If, by accident, a VIS gets executed and no interrupt is active, then the PC (Program Counter) will branch to a vector located at 0yE0-0yE1. Warning: A Default VIS interrupt handler routine must be present. As a minimum, this handler should confirm that the GIE bit is cleared (this indicates that the interrupt sequence has been taken), take care of any required housekeeping, restore context and return. Some sort of Warm Restart procedure should be implemented. These events can occur without any error on the part of the system designer or programmer.
Note: There is always the possibility of an interrupt occurring during an instruction which is attempting to reset the GIE bit or any other interrupt enable bit. If this occurs when a single cycle instruction is being
used to reset the interrupt enable bit, the interrupt enable bit will be reset but an interrupt may still occur. This is because interrupt processing is started at the same time as the interrupt bit is being reset. To avoid this scenario, the user should always use a two-, three- or four-cycle instruction to reset interrupt enable bits.
Figure 18 shows the Interrupt block diagram.
SOFTWARE TRAP The Software Trap (ST) is a special kind of non-maskable interrupt which occurs when the INTR instruction (used to acknowledge interrupts) is fetched from ROM and placed inside the instruction register. This may happen when the PC is pointing beyond the available ROM address space or when the stack is over-popped. When an ST occurs, the user can re-initialize the stack pointer and do a recovery procedure (similar to reset, but not necessarily containing all of the same initialization procedures) before restarting. The occurrence of an ST is latched into the ST pending bit. The GIE bit is not affected and the ST pending bit (not accessible by the user) is used to inhibit other interrupts and to direct the program to the ST service routine with the VIS instruction. The RPND instruction is used to clear the software interrupt pending bit. This pending bit is also cleared on reset. The ST has the highest rank among all interrupts. Nothing (except another ST) can interrupt an ST being serviced.
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FIGURE 18. Interrupt Block Diagram
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Detection of Illegal Conditions
Where tc is the instruction cycle clock
MICROWIRE / PLUS
MICROWIRE / PLUS is a serial synchronous communications interface. The MICROWIRE / PLUS capability enables the
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FIGURE 19. MICROWIRE / PLUS Block Diagram
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MICROWIRE / PLUS
(Continued)
TABLE 8. MICROWIRE Mode Settings
G4 (SO) Config. Bit 1 0 1 0 G5 (SK) Config. Bit 1 1 0 0 G4 Fun. SO TRISTATE SO TRlSTATE G5 Fun. Int. SK Int. SK Ext. SK Ext. SK MICROWIRE / PLUS Master MICROWlRE / PLUS Master MlCROWlRE / PLUS Slave MICROWlRE / PLUS Slave Operation
MICROWIRE / PLUS OPERATION Setting the BUSY bit in the PSW register causes the MICROWIRE / PLUS to start shifting the data. It gets reset when eight data bits have been shifted. The user may reset the BUSY bit by software to allow less than 8 bits to shift. If enabled, an interrupt is generated when eight data bits have been shifted. The device may enter the MICROWIRE / PLUS mode either as a Master or as a Slave. Figure 20 shows how two devices, microcontrollers and several peripherals may be interconnected using the MICROWIRE / PLUS arrangements. Warning: The SIO register should only be loaded when the SK clock is low. Loading the SIO register while the SK clock is high will resuIt in undefined data in the SIO register. SK clock is normally low when not shifting. Setting the BUSY flag when the input SK clock is high in the MICROWIRE / PLUS slave mode may cause the current SK clock for the SIO shift register to be narrow. For safety, the BUSY flag should only be set when the input SK clock is low. MICROWIRE / PLUS Master Mode Operation In the MICROWIRE / PLUS Master mode of operation the shift clock (SK) is generated internally by the device. The MICROWIRE Master always initiates all data exchanges. The MSEL bit in the CNTRL register must be set to enable the SO and SK functions onto the G Port. The SO and SK pins must also be selected as outputs by setting appropriate bits in the Port G configuration register. Table VIII summarizes the bit settings required for Master mode of operation. MICROWIRE / PLUS Slave Mode Operation In the MICROWIRE / PLUS Slave mode of operation the SK clock is generated by an external source. Setting the MSEL bit in the CNTRL register enables the SO and SK functions onto the G Port. The SK pin must be selected as an input and the SO pin is selected as an output pin by setting and resetting the appropriate bits in the Port G configuration register. Table VIII summarizes the settings required to enter the Slave mode of operation.
This table assumes that the control flag MSEL is set. The user must set the BUSY flag immediately upon entering the Slave mode. This will ensure that all data bits sent by the Master will be shifted properly. After eight clock pulses the BUSY flag will be cleared and the sequence may be repeated. Alternate SK Phase Operation The device allows either the normal SK clock or an alternate phase SK clock to shift data in and out of the SIO register. in both the modes the SK is normally low. In the normal mode data is shifted in on the rising edge of the SK clock and the data is shifted out on the falling edge of the SK clock. The SIO register is shifted on each falling edge of the SK clock. In the alternate SK phase operation, data is shifted in on the falling edge of the SK clock and shifted out on the rising edge of the SK clock. A control flag, SKSEL, allows either the normal SK clock or the alternate SK clock to be selected. Resetting SKSEL causes the MICROWIRE / PLUS logic to be clocked from the normal SK signal. Setting the SKSEL flag selects the alternate SK clock. The SKSEL is mapped into the G6 configuration bit. The SKSEL flag will power up in the reset condition, selecting the normal SK signal.
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FIGURE 20. MICROWIRE / PLUS Application
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Memory Map
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Memory Map
(Continued) ADDRESS S / ADD REG CONTENTS UART Control and Status Register (ENU) UART Receive Control and Status Register (ENUR) UART Interrupt and Clock Source Register (ENUI) UART Baud Register (BAUD) UART Prescaler Select Register (PSR) Reserved for UART Timer T2 Lower Byte Timer T2 Upper Byte Timer T2 Autoload Register T2RA Lower Byte Timer T2 Autoload Register T2RA Upper Byte Timer T2 Autoload Register T2RB Lower Byte Timer T2 Autoload Register T2RB Upper Byte Timer T2 Control Register Reserved MIWU Edge Select Register (WKEDG) MlWU Enable Register (WKEN) MlWU Pending Register (WKPND) Reserved Reserved Reserved Port L Data Register Port L Configuration Register Port L Input Pins (Read Only) Reserved for Port L Port G Data Register Port G Configuration Register Port G Input Pins (Read Only) Port l Input Pins (Read Only) Port C Data Register Port C Configuration Register Port C Input Pins (Read Only) Reserved for Port C Port D Reserved for Port D Reserved for EE Control Registers Timer T1 Autoload Register T1RB Lower Byte Timer T1 Autoload Register T1RB Upper Byte ICNTRL Register MICROWIRE Shift Register Timer T1 Lower Byte Timer T1 Upper Byte Timer T1 Autoload Register T1RA Lower Byte Timer T1 Autoload Register T1RA Upper Byte CNTRL Control Register PSW Register On-chip RAM Mapped as Registers X Register SP Register
xxBA xxBB xxBC xxBD xxBE xxBF xxC0 xxC1 xxC2 xxC3 xxC4 xxC5 xxC6 xxC7 xxC8 xxC9 xxCA xxCB xxCC xxCD to xxCF xxD0 xxD1 xxD2 xxD3 xxD4 xxD5 xxD6 xxD7 xxD8 xxD9 xxDA xxDB xxDC xxDD to xxDF xxE0 to xxE5 xxE6 xxE7 xxE8 xxE9 xxEA xxEB xxEC xxED xxEE xxEF xxF0 to xxFB xxFC xxFD
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Memory Map
(Continued) ADDRESS S / ADD REG CONTENTS B Register S Register On Chip RAM Bytes (384 Bytes)
xxFE xxFF 0100 to 017F 0200 to 027F 0300 to 037F
Reading memory locations 0070H-007FH (Segment 0) will return all ones. Reading unused memory locations between 0080H-00F0 Hex (Segment 0) will return undefined data. Reading memory locations from other segments (i.e., segment 4, segment 5, etc.) will return all ones.
ADDRESSING MODES There are ten addressing modes, six for operand addressing and four for transfer of control. OPERAND ADDRESSING MODES Register Indirect This is the "normal" addressing mode. The operand is the data memory addressed by the B pointer or X pointer. Register Indirect (with auto post Increment or decrement of pointer) This addressing mode is used with the LD and X instructions. The operand is the data memory addressed by the B pointer or X pointer. This is a register indirect mode that automatically post increments or decrements the B or X register after executing the instruction. Direct The instruction contains an 8-bit address field that directly points to the data memory for the operand. ImmedIate The instruction contains an 8-bit immediate field as the operand. Short Immediate This addressing mode is used with the Load B Immediate instruction. The instruction contains a 4-bit immediate field as the operand. Indirect This addressing mode is used with the LAID instruction. The contents of the accumuiator are used as a partial address (lower 8 bits of PC) for accessing a data operand from the program memory. TRANSFER OF CONTROL ADDRESSING MODES Relative This mode is used for the JP instruction, with the instruction field being added to the program counter to get the new program location. JP has a range from -31 to +32 to allow a 1-byte relative jump (JP + 1 is implemented by a NOP instruction). There are no "pages" when using JP, since all 15 bits of PC are used. Absolute This mode is used with the JMP and JSR instructions, with the instruction field of 12 bits replacing the lower 12 bits of the program counter (PC). This allows jumping to any location in the current 4k program memory segment.
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Absolute Long This mode is used with the JMPL and JSRL instructions, with the instruction field of 15 bits replacing the entire 15 bits of the program counter (PC). This allows jumping to any location up to 32k in the program memory space. Indirect This mode is used with the JID instruction. The contents of the accumulator are used as a partial address (lower 8 bits of PC) for accessing a location in the program memory. The contents of this program memory location serve as a partial address (lower 8 bits of PC) for the jump to the next instruction.
Note: The VIS is a special case of the Indirect Transfer of Control addressing mode, where the double byte vector associated with the interrupt is transferred from adjacent addresses in the program memory into the program counter (PC) in order to jump to the associated interrupt service routine.
Instruction Set
Register and Symbol Definition Registers A B X SP PC PU PL C HC GIE VU VL 8-Bit Accumulator Register 8-Bit Address Register 8-Bit Address Register 8-Bit Stack Pointer Register 15-Bit Program Counter Register Upper 7 Bits of PC Lower 8 Bits of PC 1 Bit of PSW Register for Carry 1 Bit of PSW Register for Half Carry 1 Bit of PSW Register for Global Interrupt Enable Interrupt Vector Upper Byte Interrupt Vector Lower Byte
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Instruction Set
B X MD Mem Meml
(Continued) Imm Symbols Reg Bit
Symbols 8-Bit Immediate Data Register Memory: Addresses F0 to FF (Includes B, X and SP) Bit Number (0 to 7) Loaded with Exchanged with
Memory Indirectly Addressed by B Register Memory Indirectly Addressed by X Register Direct Addressed Memory Direct Addressed Memory or B Direct Addressed Memory or B or Immediate Data
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#, Mem #, Mem #, Mem
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Instruction Set
IFNC POP PUSH VIS JMPL JMP JP JSRL JSR JID RET RETSK RETI INTR NOP Addr. Addr. Disp. Addr. Addr A A