2003 Revision GeodeSC2200 Thin Client Chip GeodeSC2200 Thin
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GeodeSC2200 Thin Client Chip
2003 Revision
GeodeSC2200 Thin Client Chip
GeodeSC2200 Thin Client Chip device member National Semiconductor® (Information Appliance) Chip family fully integrated system chips. Geode SC2200 includes: Geode processor module combines advanced performance with Intel support, fully accelerated graphics, 64-bit synchronous DRAM (SDRAM) interface, controller, display controller. low-power Video Processor module with Video Input Port (VIP), hardware video accelerator scaling, filtering, color space conversion. Core Logic module includes: PC/AT functionality, interface, interface, interface, interface, Advanced Configuration Power Interface (ACPI) version compliant power management, audio codec interface. SuperI/O module has: three Serial Ports (UART1, UART2, UART3 with fast infrared), Parallel Port, ACCESS.bus (ACB) interfaces, Real-Time Clock (RTC). block diagram shows relationships between modules. These features, combined with device's small form factor power consumption, make ideal core thin client application.
Block Diagram
Memory Controller Graphics Accelerator Controller Display Controller Video Scaling Config. Block Video Input Port (VIP) Host Interface Fast-PCI Clock Reset Logic Fast X-Bus Video Mixer
Video Processor
Core
Bridge PCI/Sub-ISA GPIO Audio Codec X-Bus
Core Logic
DMAC Mgmnt Configuration
Parallel Port ACB1
SuperI/O
ACB2 UART1 UART2
UART3
National Semiconductor Virtual System Architecture registered trademarks National Semiconductor Corporation. Geode trademarks National Semiconductor Corporation. complete listing National Semiconductor trademarks, please visit www.national.com/trademarks.
2003 National Semiconductor Corporation
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GeodeSC2200
Features
General Features
32-Bit processor, MHz, with Memory Controller:
instruction support
Memory controller with 64-bit SDRAM interface graphics accelerator controller with hardware video accelerator CCIR-656 video input port with direct video full
64-Bit SDRAM interface frequency range Direct interface with CPU/cache, display controller graphic accelerator Supports clock suspend power-down/selfrefresh banks SDRAM devices total) SODIMM
Display Controller:
screen display
PC/AT functionality controller interface, channels USB, three ports, OHCI (OpenHost Controller Interface)
Hardware graphics frame buffer compress/decompress Hardware cursor, 32x32 pixels Video Processor Module
Video Accelerator:
version compliant
Audio, AC97/AMC97 version compliant Virtual System Architecture® (VSATM) technology
Flexible video scaling support (horizontally vertically) Bilinear interpolation filters (with taps, eight phases) smooth output video
Video/Graphics Mixer:
support
Power management, ACPI (Advanced Configuration
Power Interface) version compliant
Package:
8-bit value alpha blending Three blending windows with constant alpha value Color
Video Input Port (VIP):
432-Terminal EBGA (Enhanced Ball Grid Array) 481-Terminal TEPBGA (Thermally Enhanced Plastic Ball Grid Array) Processor Module
Core:
32-Bit x86, MHz, with compatible instruction support unified cache Integrated Floating Point Unit (FPU) Re-entrant (System Management Mode) enhanced
Graphics Accelerator:
Video capture display CCIR-656 format VESA Video Interface Port compliant Lock display timing video input timing (GenLock) Able transfer video data into main memory Direct video transfer full screen display Separate memory location
Interface:
Uses three 8-bit DACs Supports 1280x1024 non-interlaced bpp, 1024x768 non-interlaced bpp,
Accelerates BitBLTs, line draw text Supports raster operations Supports transparent BLTs Runs core clock frequency
Interface:
Direct connection panels 800x600 non-interlaced graphics, 1024x768 non-interlaced graphics, Connects Geode CS9211 companion DSTN panel support IDE: FPCLK Parallel Port: FPCLK
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GeodeSC2200
Features (Continued)
Core Logic Module
Audio Codec Interface: Interface:
AC97/AMC97 (Rev. 2.0) codec interface channels
PC/AT Functionality:
channels four external devices Supports ATA-33 synchronous mode transfers, MB/s
Universal Serial (USB):
Programmable Interrupt Controller (PIC), 8259A-equivalent Programmable Interval Timer (PIT), 8254-equivalent Controller (DMAC), 8237-equivalent
Power Management:
OpenHCI compliant Three ports SuperI/O Module
Real-Time Clock (RTC):
ACPI compliant state control three power planes Cx/Sx state control clocks PLLs Thermal event input Wakeup event support: Three general-purpose events AC97 codec event UART2 signal Infrared (IR) event
DS1287, MC146818 PC87911 compatible Multi-century calendar
ACCESS.bus (ACB) Interface:
interface ports
Parallel Port:
compliant IEEE 1284 compliant, including level
Serial Port (UART):
General Purpose I/Os (GPIOs):
multiplexed GPIO signals
Count (LPC) Interface:
UART1, 16550A compatible (SIN, SOUT, BOUT pins), used SmartCard interface UART2, 16550A compatible Enhanced UART with fast Infrared (IR) Other Features
High-Resolution Timer:
Specification version compatible
Interface:
version compliant with wakeup capability 32-Bit data path, Glueless interface external device Fixed priority 3.3V signal support only
32-Bit counter with count interval
WATCHDOG Timer:
Interfaces INTR, SMI, Reset
Clocks:
Sub-ISA Interface:
addressing Supports chip select Flash EPROM boot device Supports either: M-Systems DiskOnChip DOC2000 Flash file system NAND EEPROM Supports chip selects external devices 8-Bit (optional 16-bit) data width Shares balls with signals subtractive agent
Input (external crystals): 32.768 (internal clock oscillator) (internal clock oscillator) Output: AC97 clock (24.576 MHz) Memory controller clock MHz) clock MHz)
JTAG Testability:
Bypass, Extest, Sample/Preload, IDcode, Clamp,
Voltages:
Internal logic: 233/266 1.8V 2.1V Battery: I/O: 3.3V Standby: 3.3V
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GeodeSC2200
Table Contents
Architecture Overview
MODULE 1.1.1 Memory Controller 1.1.2 Fast-PCI 1.1.3 Display VIDEO PROCESSOR MODULE 1.2.1 Module Interface 1.2.2 Video Input Port 1.2.3 Core Logic Module Interface 1.2.4 CORE LOGIC MODULE 1.3.1 Other Interfaces Core Logic Module SUPERI/O MODULE CLOCK, TIMERS, RESET LOGIC 1.5.1 Reset Logic
1.5.1.1 1.5.1.2 Power-On Reset System Reset
Signal Definitions
BALL ASSIGNMENTS STRAP OPTIONS MULTIPLEXING CONFIGURATION SIGNAL DESCRIPTIONS 2.4.1 System Interface 2.4.2 Memory Interface Signals 2.4.3 Video Port Interface Signals 2.4.4 CRT/TFT Interface Signals 2.4.5 ACCESS.bus Interface Signals 2.4.6 Interface Signals 2.4.7 Sub-ISA Interface Signals 2.4.8 Count (LPC) Interface Signals 2.4.9 Interface Signals 2.4.10 Universal Serial (USB) Interface Signals 2.4.11 Serial Ports (UARTs) Interface Signals 2.4.12 Parallel Port Interface Signals 2.4.13 Fast Infrared (IR) Port Interface Signals 2.4.14 AC97 Audio Interface Signals 2.4.15 Power Management Interface Signals 2.4.16 GPIO Interface Signals 2.4.17 Debug Monitoring Interface Signals 2.4.18 JTAG Interface Signals 2.4.19 Test Measurement Interface Signals 2.4.20 Power, Ground Connections
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GeodeSC2200
Table Contents (Continued) General Configuration Block
CONFIGURATION BLOCK ADDRESSES MULTIPLEXING, INTERRUPT SELECTION, BASE ADDRESS REGISTERS WATCHDOG 3.3.1 Functional Description
3.3.1.1 WATCHDOG Timer Usage Hints
3.3.2
WATCHDOG Registers
3.3.2.1
HIGH-RESOLUTION TIMER 3.4.1 Functional Description 3.4.2 High-Resolution Timer Registers
3.4.2.1 Usage Hints
CLOCK GENERATORS PLLS 3.5.1 Crystal Oscillator 3.5.2 Module Core Clock 3.5.3 Internal Fast-PCI Clock 3.5.4 SuperI/O Clocks 3.5.5 Core Logic Module Clocks 3.5.6 Video Processor Clocks 3.5.7 Clock Registers
SuperI/O Module
FEATURES MODULE ARCHITECTURE CONFIGURATION STRUCTURE/ACCESS 4.3.1 Index-Data Register Pair 4.3.2 Banked Logical Device Registers 4.3.3 Default Configuration Setup 4.3.4 Address Decoding STANDARD CONFIGURATION REGISTERS 4.4.1 Control Configuration Registers 4.4.2 Logical Device Control Configuration
4.4.2.1 4.4.2.2 4.4.2.3 4.4.2.4 4.4.2.5 4.4.2.6 Real-Time Clock System Wakeup Control Infrared Communication Port Serial Port Serial Ports ACCESS.bus Ports Parallel Port
REAL-TIME CLOCK (RTC) 4.5.1 Interface 4.5.2 Clock Generation
4.5.2.1 4.5.2.2 4.5.2.3 4.5.2.4 4.5.2.5 4.5.2.6 4.5.2.7 4.5.2.8 4.5.2.9 4.5.2.10 Internal Oscillator External Oscillator Timing Generation Timekeeping Alarms Power Supply System Power States Oscillator Activity Interrupt Handling Battery-Backed RAMs Registers
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GeodeSC2200
Table Contents (Continued)
4.5.3 Registers
4.5.3.1 Usage Hints
4.5.4 General-Purpose SYSTEM WAKEUP CONTROL (SWC) 4.6.1 Event Detection
4.6.1.1 4.6.1.2 Audio Codec Event CEIR Address
4.6.2 Registers ACCESS.BUS INTERFACE 4.7.1 Data Transactions 4.7.2 Start Stop Conditions 4.7.3 Acknowledge (ACK) Cycle 4.7.4 Acknowledge After Every Byte Rule 4.7.5 Addressing Transfer Formats 4.7.6 Arbitration 4.7.7 Master Mode
4.7.7.1 Master Stop
4.7.8 Slave Mode 4.7.9 Configuration 4.7.10 Registers LEGACY FUNCTIONAL BLOCKS 4.8.1 Parallel Port
4.8.1.1 Parallel Port Register Maps UART Mode Register Bank Overview Register Maps UART Functionality IR/SP3 Mode Register Bank Overview IRCP/SP3 Register Maps
4.8.2
UART Functionality (SP1 SP2)
4.8.2.1 4.8.2.2
4.8.3
Communications Port (IRCP) Serial Port (SP3) Functionality
4.8.3.1 4.8.3.2
Core Logic Module
FEATURE LIST MODULE ARCHITECTURE 5.2.1 Fast-PCI Interface External
5.2.1.1 5.2.1.2 5.2.1.3 5.2.1.4 5.2.1.5 Processor Mastered Cycles External Mastered Cycles Core Logic Internal Sub-ISA Mastered Cycles External Master Request Priority Video Retrace Interrupt Configuration Registers Mode Master Mode UltraDMA/33 Mode
5.2.2 5.2.3
PSERIAL Interface
5.2.2.1 5.2.3.1 5.2.3.2 5.2.3.3 5.2.3.4
Controller
5.2.4 5.2.5
Universal Serial Sub-ISA Interface
5.2.5.1 5.2.5.2 5.2.5.3 5.2.5.4 5.2.5.5 5.2.5.6 5.2.5.7 Sub-ISA Cycles Sub-ISA Support Delayed Transactions Sub-ISA Data Steering Recovery Delays Interface Sub-ISA Signal Cycle Multiplexing
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GeodeSC2200
Table Contents (Continued)
5.2.6 Compatibility Logic
5.2.6.1 5.2.6.2 5.2.6.3 Controller Programmable Interval Timer Programmable Interrupt Controller Port 092h System Control Port 061h System Control Generation Fast Keyboard Gate Address Reset States Sleep States Power Planes Control Power Management Events Usage Hints Support Power Management Peripheral Power Management Power Management Programming Summary
5.2.7
Ports 092h 061h System Control
5.2.7.1 5.2.7.2 5.2.7.3
5.2.8 5.2.9
Keyboard Support
5.2.8.1 5.2.9.1 5.2.9.2 5.2.9.3 5.2.9.4 5.2.9.5
Power Management Logic
5.2.10
Power Management Programming
5.2.10.1 5.2.10.2 5.2.10.3 5.2.10.4
5.2.11 5.2.12
GPIO Interface Integrated Audio
5.2.12.1 5.2.12.2 5.2.12.3 5.2.12.4 5.2.12.5 5.2.12.6 5.2.12.7 5.2.12.8 Data Transport Hardware AC97 Codec Interface Technology Support Hardware Configuration Registers Interface Interface Signal Definitions Cycle Types Interface Support
REGISTER DESCRIPTIONS 5.3.1 Configuration Space Access Methods 5.3.2 Register Summary CHIPSET REGISTER SPACE 5.4.1 Bridge, GPIO, Registers Function
5.4.1.1 5.4.1.2 GPIO Support Registers Support Registers Status Support Registers ACPI Support Registers Controller Support Registers Audio Support Registers X-Bus Expansion Support Registers
5.4.2
Status ACPI Registers Function
5.4.2.1 5.4.2.2
5.4.3 5.4.4 5.4.5 5.4.6 5.4.7
Controller Registers Function
5.4.3.1 5.4.4.1 5.4.5.1
Audio Registers Function X-Bus Expansion Interface Function Controller Registers PCIUSB Legacy Register Space
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GeodeSC2200
Table Contents (Continued) Video Processor Module
MODULE ARCHITECTURE FUNCTIONAL DESCRIPTION 6.2.1 Video Input Port (VIP)
6.2.1.1 6.2.1.2 6.2.1.3 Direct Video Mode Capture Video Mode Capture Mode Video Input Formatter Horizontal Downscaler with 4-Tap Filtering Line Buffers Formatter 2-Tap Vertical Horizontal Upscalers Video Data Path Gamma Correction Color/Chroma Color/Chroma Mixer/Blender
6.2.2
Video Block
6.2.2.1 6.2.2.2 6.2.2.3 6.2.2.4 6.2.2.5
6.2.3
Mixer/Blender Block
6.2.3.1 6.2.3.2 6.2.3.3 6.2.3.4
6.2.4 VESA DDSC2B DPMS Support 6.2.5 Integrated DACs 6.2.6 Interface 6.2.7 Integrated REGISTER DESCRIPTIONS 6.3.1 Register Summary 6.3.2 Video Processor Registers Function
6.3.2.1 6.3.2.2 Video Processor Support Registers F4BAR0 Support Registers F4BAR2
Debugging Monitoring
TESTABILITY (JTAG) 7.1.1 Mandatory Instruction Support 7.1.2 Optional Instruction Support 7.1.3 JTAG Chain
Electrical Specifications
GENERAL SPECIFICATIONS 8.1.1 Power/Ground Connections Decoupling 8.1.2 Absolute Maximum Ratings 8.1.3 Operating Conditions 8.1.4 Current
8.1.4.1 8.1.4.2 8.1.4.3 8.1.4.4 Power State Parameter Definitions Definition Measurement Techniques SC2200 Current Parameters Definition System Conditions Measuring Parameters Current Measurements
8.1.5 8.1.6
Ball Capacitance Inductance Pull-Up Pull-Down Resistors
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Table Contents (Continued)
CHARACTERISTICS 8.2.1 INAB Characteristics 8.2.2 INBTN Characteristics 8.2.3 INPCI Characteristics 8.2.4 INSTRP Characteristics 8.2.5 Characteristics 8.2.6 INTS Characteristics 8.2.7 INTS1 Characteristics 8.2.8 INUSB Characteristics 8.2.9 OAC97 Characteristics 8.2.10 Characteristics 8.2.11 ODPCI Characteristics 8.2.12 Op/n Characteristics 8.2.13 OPCI Characteristics 8.2.14 OUSB Characteristics 8.2.15 TSp/n Characteristics
8.2.15.1 Exceptions
CHARACTERISTICS 8.3.1 Memory Controller Interface 8.3.2 Video Port 8.3.3 Interface 8.3.4 ACCESS.bus Interface 8.3.5 Interface
8.3.5.1 Measurement Test Conditions
8.3.6 8.3.7 8.3.8 8.3.9 8.3.10 8.3.11 8.3.12 8.3.13 8.3.14 8.3.15 8.3.16
Sub-ISA Interface Interface Interface Universal Serial (USB) Interface Serial Port (UART) Fast Port Parallel Port Interface
8.3.12.1 Extended Capabilities Port (ECP)
Audio Interface (AC97) Power Management Interface Power-Up Sequencing JTAG Interface
Package Specifications Support Documentation
Appendix
ORDER INFORMATION DATASHEET REVISION HISTORY
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GeodeSC2200
Architecture Overview
Core Logic Module: Includes PC/AT functionality, interface, Universal Serial (USB) interface, ACPI compliant power management, audio codec interface. SuperI/O Module: Includes Serial Ports, Infrared (IR) Port, Parallel Port, ACCESS.bus interfaces, Real-Time Clock (RTC).
illustrated Figure 1-1, SC2200 contains following modules integrated device: Module: Combines advanced performance with support, fully accelerated graphics, 64-bit synchronous DRAM (SDRAM) interface controller. Integrates silicon revision 8.1.1. Video Processor Module: low-power support module with video input port, hardware video accelerator scaling, filtering color space conversion.
Memory Controller Graphics Accelerator Controller Display Controller
Video Processor
Config. Block Video Input Port (VIP) Host Interface Fast-PCI Clock Reset Logic Fast X-Bus
Core
Video Scaling
Video Mixer
Bridge PCI/Sub-ISA GPIO Audio Codec X-Bus
Core Logic
DMAC Mgmnt Configuration
Parallel Port ACB1
SuperI/O
ACB2 UART1 UART2
UART3
Figure 1-1. SC2200 Block Diagram
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Architecture Overview (Continued)
MODULE
There some differences SC2200's memory controller stand-alone processor's memory controller: There drive strength/slew control SC2200 that GX1. bits that control this function MC_MEM_CNTRL1 MC_MEM_CNTRL2 registers. processor, these bits marked reserved. SC2200 supports banks memory. supports four banks memory. addition, SC2200 supports maximum eight devices supports devices. With this difference, MC_BANK_CFG register different. processor (silicon revision 8.1.1) central module SC2200. detailed information regarding module, refer Geode Processor Series datasheet Geode Processor Series Silicon Revision 8.1.1 errata. SC2200's device contained module. Software detect revision reading DIR0 DIR1 Configuration registers (see Configuration registers Geode Processor Series datasheet). SC2200 device errata contains specific values. 1.1.1 Memory Controller module connected external SDRAM devices. more information Section 2.4.2 "Memory Interface Signals" page "Memory Controller" chapter Processor Series datasheet.
Table summarizes 32-bit registers contained SC2200's memory controller. Table gives detailed register/bit formats.
Table 1-1. SC2200 Memory Controller Register Summary
GX_BASE+ Memory Offset 8400h-8403h 8404h-8407h 8408h-840Bh 840Ch-840Fh 8414h-8417h 8418h-841Bh 841Ch-841Fh Width (Bits) Type Name/Function MC_MEM_CNTRL1. Memory Controller Control Register MC_MEM_CNTRL2. Memory Controller Control Register MC_BANK_CFG. Memory Controller Bank Configuration MC_SYNC_TIM1. Memory Controller Synchronous Timing Register MC_GBASE_ADD. Memory Controller Graphics Base Address Register MC_DR_ADD. Memory Controller Dirty Address Register MC_DR_ACC. Memory Controller Dirty Access Register Reset Value 248C0040h 00000801h 41104110h 2A733225h 00000000h 00000000h 0000000xh
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Architecture Overview (Continued)
Table 1-2. SC2200 Memory Controller Registers
Description MC_MEM_CNTRL1 (R/W) Reset Value: 248C0040h
GX_BASE+ 8400h-8403h 31:30 28:27 25:24 23:22 20:18
MDCTL (MD[63:0] Drive Strength). strongest, weakest. RSVD (Reserved) Write MABACTL (MA[12:0] BA[1:0] Drive Strength). strongest, weakest. RSVD (Reserved). Write MEMCTL (RASA#, CASA#, WEA#, CS[1:0]#, CKEA, DQM[7:0] Drive Strength). strongest, weakest. RSVD (Reserved). Write RSVD (Reserved). Must written Wait state X-Bus x_data during read cycles debug only. SDCLKRATE (SDRAM Clock Ratio). Selects SDRAM clock ratio. 000: Reserved 001: 010: 011: (Default) 100: 101: 110: 111:
Ratio does take effect until SDCLKSTRT (bit this register) transitions from SDCLKSTRT (Start SDCLK). Start operating SDCLK using ratio shift value (selected bits [20:18] this register). Clear. Enable. This must transition from zero (written zero) (written one) order start SDCLK change shift value. 16:8 RFSHRATE (Refresh Interval). This field determines number processor core clocks multiplied between refresh cycles DRAM. default, refresh interval 00h. Refresh turned default. RFSHSTAG (Refresh Staggering). This field determines number clocks between RFSH commands each four banks during refresh cycles: SDRAM clocks SDRAM clocks (Default) SDRAM clocks SDRAM clocks Staggering used help reduce power spikes during refresh refreshing bank time. only bank installed, this field must written 2CLKADDR (Two Clock Address Setup). Assert memory address extra clock before asserted. Disable. Enable. This used compensate address setup high frequencies and/or high loads. RFSHTST (Test Refresh). This bit, when high, generates refresh request. This only used testing purposes. XBUSARB (X-Bus Round Robin). When enabled, processor, graphics pipeline non-critical display controller requests arbitrated same priority level. When disabled, processor requests arbitrated higher priority level. High priority display controller requests always have highest arbitration priority. Enable. Disable. SMM_MAP (SMM Region Mapping). Maps memory region GX_BASE+400000 physical address A0000 BFFFF SDRAM. Disable. Enable. RSVD (Reserved). Write SDRAMPRG (Program SDRAM). When this set, memory controller will program SDRAM register using LTMODE MC_SYNC_TIM1. This must transition from zero (written zero) (written one) order program SDRAM devices.
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Architecture Overview (Continued)
Table 1-2. SC2200 Memory Controller Registers (Continued)
Description MC_MEM_CNTRL2 (R/W) Reset Value: 00000801h
GX_BASE+8404h-8407h 31:14 13:12 RSVD (Reserved). Write
SDCLKCTL (SDCLK High Drive/Slew Control). Controls high drive slew rate SDCLK[3:0] SDCLK_OUT. strongest, weakest. RSVD (Reserved). Write SDCLKOMSK# (Enable SDCLK_OUT). Turns output. Enable. Disable.
SDCLK3MSK# (Enable SDCLK3). Turns output. Enable. Disable.
SDCLK2MSK# (Enable SDCLK2). Turns output. Enable. Disable.
SDCLK1MSK# (Enable SDCLK1). Turns output. Enable. Disable.
SDCLK0MSK# (Enable SDCLK0). Turns output. Enable. Disable.
SHFTSDCLK (Shift SDCLK). This function allows shifting SDCLK meet SDRAM setup hold time requirements. shift function will take effect until SDCLKSTRT (bit MC_MEM_CNTRL1) transitions from 000: shift 001: Shift core clock 010: Shift core clock 011: Shift core clock 100: Shift core clocks 101: Shift core clocks 110: Shift core clocks 111: Reserved
RSVD (Reserved). Write (Read Data Phase). Selects read data latched core clock after rising edge SDCLK. Core clock. Core clocks.
FSTRDMSK (Fast Read Mask). allow core reads bypass request FIFO. Disable. Enable.
GX_BASE+8408h-840Bh 31:16 RSVD (Reserved). Write 0070h RSVD (Reserved). Write
MC_BANK_CFG (R/W)
Reset Value: 41104110h
SODIMM_MOD_BNK (SODIMM Module Banks Banks Selects number module banks installed SODIMM SODIMM: Module bank (Bank only). Module banks (Bank
RSVD (Reserved). Write SODIMM_COMP_BNK (SODIMM Component Banks Banks Selects number component banks module bank SODIMM: Component banks. Component banks. Banks must have same number component banks.
10:8
RSVD (Reserved). Write SODIMM_SZ (SODIMM Size Banks Selects size SODIMM: 000: 001: 010: 011: 100: 101: 110: 111:
This size total both banks Also, banks must same size. RSVD (Reserved). Write
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Architecture Overview (Continued)
Table 1-2. SC2200 Memory Controller Registers (Continued)
Description SODIMM_PG_SZ (SODIMM Page Size Banks Selects page size SODIMM: 000: 001: 010: 011: 1xx: 111: SODIMM installed
Both banks must have same page size. RSVD (Reserved). Write MC_SYNC_TIM1 (R/W) Reset Value: 2A733225h
GX_BASE+840Ch-840Fh 30:28 RSVD (Reserved). Write
LTMODE (CAS Latency). latency delay, SDRAM clock cycles, between registration read command availability first piece output data. This parameter significantly affects system performance. Optimal setting should used. SODIMM used, BIOS interrogate EEPROM across ACCESS.bus interface determine this value: 000: Reserved 001: Reserved 010: 011: 100: 101: 110: 111:
This field will take effect until SDRAMPRG (bit MC_MEM_CNTRL1) transitions from 27:24 (RFSH RFSH/ACT Command Period, tRC). Minimum number SDRAM clock between RFSH RFSH/ACT commands: 0000: Reserved 0001: 0010: 0011: 23:20 0000: Reserved 0001: 0010: 0011: 18:16 0100: 0101: 0110: 0111: 0100: 0101: 0110: 0111: 1000: 1001: 1010: 1011: 1000: 1001: 1010: 1011: 1100: 1101: 1110: 1111: 1100: 1101: 1110: 1111:
(ACT Command Period, tRAS). Minimum number SDRAM clocks between commands:
RSVD (Reserved). Write (PRE Command Period, tRP). Minimum number SDRAM clocks between commands: 000: Reserved 001: 010: 011: 100: 101: 110: 111:
14:12
RSVD (Reserved). Write (Delay Time READ/WRT Command, tRCD). Minimum number SDRAM clock between READ/WRT commands. This parameter significantly affects system performance. Optimal setting should used: 000: Reserved 001: 010: 011: 100: 101: 110: 111:
10:8
RSVD (Reserved). Write (ACT(0) ACT(1) Command Period, tRRD). Minimum number SDRAM clocks between command different component banks within same module bank. memory controller does perform back-to-back Activate commands different component banks without READ WRITE command between them. Hence, this field should written 001. RSVD (Reserved). Write (Data-in command period, tDPL). Minimum number SDRAM clocks from time last write datum sampled till bank precharged: 000: Reserved 001: 010: 011: 100: 101: 110: 111:
Note:
RSVD (Reserved). Leave unchanged. Always returns 101h. Refer SDRAM manufacturer's specification more information component banks.
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Architecture Overview (Continued)
Table 1-2. SC2200 Memory Controller Registers (Continued)
Description MC_GBASE_ADD (R/W) Reset Value: 00000000h
GX_BASE+8414h-8417h 31:18 RSVD (Reserved). Write (Test Enable TEST[3:0]).
TEST[3:0] driven (normal operation). TEST[3:0] pins used output test information. TECTL (Test Enable Shared Control Pins). RASB#, CASB#, CKEB, WEB# (normal operation). RASB#, CASB#, CKEB, WEB# used output test information. 15:12 10:0 (Select). This field used debug purposes only should left zero normal operation. RSVD (Reserved). Write GBADD (Graphics Base Address). This field indicates graphics memory base address, which programmable boundaries. This field corresponds address bits [29:19]. Note that BC_DRAM_TOP must value lower than Graphics Base Address. GX_BASE+8418h-841Bh 31:10 RSVD (Reserved). Write DRADD (Dirty Address). This field address index that used access Dirty with MC_DR_ACC register. This field does auto increment. MC_DR_ACC (R/W) Reset Value: 0000000xh MC_DR_ADD (R/W) Reset Value: 00000000h
GX_BASE+841Ch-841Fh 31:2 RSVD (Reserved). Write
(Dirty Bit). This read/write accessible. (Valid Bit). This read/write accessible.
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Architecture Overview (Continued)
1.1.2 Fast-PCI module communicates with Core Logic module Fast-PCI that work MHz. Fast-PCI internal SC2200 connected General Configuration Block. This supports seven masters. requests (REQs) fixed priority. seven masters order priority are: Channel Channel Audio External REQ0# External REQ1# 1.2.1 Module Interface Video Processor connected module following way: Video Processor DOTCLK output signal used module's DCLK input signal. module's PCLK output signal used GFXCLK input signal Video Processor. 1.2.2 Video Input Port Video Input Port (VIP) within Video Processor contains standard interface that typically connected media processor encoder. clock supplied externally connected device; typically MHz. Video input sent module's video frame buffer (Capture Video mode) used directly (Direct Video mode). 1.2.3 Core Logic Module Interface Video Processor interfaces Core Logic module accessing function configuration registers. 1.2.4 Video Processor drives three DACs with 135M pixels second. interface these DACs monitored external balls SC2200. more information, Section 2.4.4 "CRT/TFT Interface Signals" page
1.1.3 Display module generates display timing, controls internal signals CRT_VSYNC CRT_HSYNC Video Processor module. module interfaces with Video Processor video data graphics data bus. Video data. module uses core clock, divided (typically MHz). drives video data using this clock. Internal signals VID_VAL VID_RDY used data-flow handshake signals between module Video Processor. Graphics data. module uses internal signal DCLK, supplied Video Processor, drive 18-bit graphics-data Video Processor. Each bits this define different color. Each these six-bit color definitions expanded adding zero lines) form eight-bit bus, Video Processor. more information about module's interface Video Processor, "Display Controller" chapter Processor Series datasheet.
CORE LOGIC MODULE
Core Logic module described detail Section "Core Logic Module" page 150. Core Logic module connected Fast-PCI bus. uses signal AD28 IDSEL configuration functions except which uses AD29. 1.3.1 Other Interfaces Core Logic Module following interfaces Core Logic module implemented external balls SC2200. Each interface listed below with reference descriptions relevant balls. IDE: Section 2.4.9 "IDE Interface Signals" page AC97: Section 2.4.14 "AC97 Audio Interface Signals" page PCI: Section 2.4.6 "PCI Interface Signals" page USB: Section 2.4.10 "Universal Serial (USB) Interface Signals" page function uses signal AD29 IDSEL configuration.
VIDEO PROCESSOR MODULE
Video Processor provides high resolution graphics TFT/DSTN interface. following paragraphs provide summary this Video Processor interfaces with other modules SC2200. detailed information about Video Processor, Section "Video Processor Module" page 316.
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Architecture Overview (Continued)
LPC: Section 2.4.8 "Low Count (LPC) Interface Signals" page Sub-ISA: Section 2.4.7 "Sub-ISA Interface Signals" page Section 5.2.5 "Sub-ISA Interface" page 156, Section "Multiplexing, Interrupt Selection, Base Address Registers" page GPIO: Section 2.4.16 "GPIO Interface Signals" page More detailed information about each these interfaces provided Section "Module Architecture" page 151. Super/IO Block Interfaces: Section "Multiplexing, Interrupt Selection, Base Address Registers" page Section 2.4.5 "ACCESS.bus Interface Signals" page Section 2.4.13 "Fast Infrared (IR) Port Interface Signals" page Section 2.4.12 "Parallel Port Interface Signals" page Core Logic module interface module consists seven miscellaneous connections, interface signals, plus display controller connections. Note that PC/AT legacy signals NMI, WM_RST, A20M virtual functions executed (System Management Mode) BIOS. PSERIAL one-way serial from Core Logic module used communicate powermanagement states VSYNC information emulation. IRQ13 input from processor indicating that floating point error detected that INTR should asserted. INTR level output from integrated 8259A PICs asserted unmasked interrupt request (IRQn) sampled active. SMI# level-sensitive interrupt that configured assert number different system events. After SMI# assertion, entered program execution begins base address space. Once asserted, SMI# remains active until source cleared. SUSP# SUSPA# handshake signals implementing Clock Stop clock throttling. CPU_RST resets asserted approximately after negation POR#. interface signals.
SUPERI/O MODULE
SuperI/O (SIO) module member National Semiconductor's SuperI/O family integrated peripherals. PC98 ACPI compliant that offers single-cell solution most commonly used peripherals. module incorporates: Serial Ports, Infrared Communication Port that supports FIR, MIR, HP-SIR, Sharp-IR, Consumer Electronics-IR, full IEEE 1284 Parallel Port, ACCESS.bus Interface (ACB) ports, System Wakeup Control (SWC), Real-Time Clock (RTC) that provides timekeeping.
CLOCK, TIMERS, RESET LOGIC
addition four main modules (i.e., GX1, Core Logic, Video Processor SIO) that make SC2200, following blocks logic have also been integrated into SC2200: Clock Generators described Section "Clock Generators PLLs" page Configuration Registers described Section "Multiplexing, Interrupt Selection, Base Address Registers" page WATCHDOG timer described Section "WATCHDOG" page High-Resolution timer described Section "High-Resolution Timer" page 1.5.1 Reset Logic This section provides description reset flow SC2200. 1.5.1.1 Power-On Reset Power-On reset triggered assertion POR# signal. Upon power-on reset, following things happen: Strap balls sampled. PLL4, PLL5, PLL6 reset, disabling their output. When POR# signal negated, clocks lock then each outputs clock. PLL6 last clock generator output clock. Section "Clock Generators PLLs" page Certain WATCHDOG High-Resolution Timer register bits cleared. 1.5.1.2 System Reset System reset causes signal PCIRST# issued, thus triggering reset agents. system reset triggered following events: Power-on, indicated POR# signal assertion. WATCHDOG reset event (see Section 3.3.2 "WATCHDOG Registers" page 89). Software initiated system reset.
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Signal Definitions
according ball number alphabetically signal name. Section "Strap Options": Several balls read power-up that state SC2200. This section provides details regarding those balls. Section "Multiplexing Configuration": Lists multiplexing options their configurations. Section "Signal Descriptions": Detailed descriptions each signal according functional group.
This section defines signals describes external interface SC2200. Figure shows signals organized their functional groups. Where signals multiplexed, default signal name listed first separated plus sign (+). slash signal name means that function always enabled available (i.e., cycle multiplexed). remaining subsections this chapter describe: Section "Ball Assignments": Provides ball assignment diagram tables listing signals sorted
System Interface
POR# X32I X32O X27I X27O PCIRST# BOOT16+ROMCS# LPC_ROM+PCICLK1 TFT_PRSNT+SDATA_OUT FPCI_MON+PCICLK0 DID0+GNT0#, DID1+GNT1# MD[63:0] MA[12:0] BA[1:0] CS[1:0]# RASA# CASA# WEA# DQM[7:0] CKEA SDCLK[3:0] SDCLK_IN SDCLK_OUT
HSYNC VSYNC VREF SETRES RED, GREEN, BLUE
Interface
Straps
Memory Interface
GeodeSC2200
ACCESS.bus Interface
AB1C+GPIO20+DOCCS# AB1D+GPIO1+IOCS1# GPIO12+AB2C GPIO13+AB2D ACK#+TFTDE AFD#/DSTRB#+TFTD2 BUSY/WAIT#+TFTD3 ERR#+TFTD4 INIT#+TFTD5 PD7+TFTD13 PD6+TFTD1 PD[5:0]+TFTD[11:6] PE+TFTD14 SLCT+TFTD15 SLIN#/ASTRB#+TFTD16 STB#/WRITE#+TFTD17 VPD[7:0] VPCKIN
IDE_ADDR2+TFTD4 IDE_ADDR1+TFTD2 IDE_ADDR0+TFTD3 IDE_DATA15+TFTD7 IDE_DATA14+TFTD17 IDE_DATA13+TFTD15 IDE_DATA12+TFTD13 IDE_DATA11+GPIO41 IDE_DATA10+DDC_SCL IDE_DATA9+DDC_SDA IDE_DATA8+GPIO40 IDE_DATA7+INTD# IDE_DATA6+IRQ9 IDE_DATA5+CLK27M IDE_DATA4+FP_VDD_ON IDE_DATA3+TFTD12 IDE_DATA2+TFTD14 IDE_DATA1+TFTD16 IDE_DATA0+TFTD6 IDE_IOR0#+TFTD10 IDE_IOW0#+TFTD9 IDE_CS0#+TFTD5 IDE_CS1#+TFTDE IDE_IORDY0+TFTD11 IDE_DREQ0+TFTD8 IDE_DACK0#+TFTD0 IDE_RST#+TFTDCK IRQ14+TFTD1
IDE/TFT Interface
Parallel Port/ Interface
Video Port Interface
Note:
Straps default signal, shown with system signals reader convenience. However, they also listed with appropriate functional group.
Figure 2-1. Signal Groups
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Signal Definitions (Continued)
Interface
POWER_EN OVER_CUR# DPOS_PORT1 DNEG_PORT1 DPOS_PORT2 DNEG_PORT2 DPOS_PORT3 DNEG_PORT3
Serial Ports (UARTs)/IDE Interface
Port Interface
AC97 Audio Interface
Power Management Interface
JTAG Interface
PCICLK0+FPCI_MON PCICLK1+LPC_ROM PCICLK INTA#, INTB# FRAME# GeodeLOCK# SC2200 PERR# SERR# REQ[1:0]# GNT0#+DID0 SIN1 GNT1#+DID1 SIN2+SDTEST3 A[23:0]/AD[23:0] SOUT1+CLKSEL1 D[7:0]/AD[31:24] SOUT2+CLKSEL2 D[11:8]/C/BE[3:0]# GPIO7+RTS2#+IDE_DACK1#+SDTEST0 D12/PAR GPIO8+CTS2#+IDE_DREQ1+SDTEST4 D13/TRDY# GPIO18+DTR1#/BOUT1 D14/IRDY# D15/STOP# GPIO11+RI2#+IRQ15 BHE#/DEVSEL# GPIO9+DCD2#+IDE_IOW1#+SDTEST2 GPIO17+TFTDCK+IOCS0# GPIO10+DSR2#+IDE_IORDY1+SDTEST1 GPIO1+IOCS1+TFTD12 ROMCS#/BOOT16 GPIO20+DOCCS#+TFTD0 IRRX1+SIN3 RD#+CLKSEL0 IRTX+SOUT3 GPIO14+DOCR#+IOR# BIT_CLK GPIO15+DOCW#+IOW# SDATA_OUT+TFT_PRSNT GPIO0+TRDE# SDATA_IN GPIO19+INTC#+IOCHRDY SDATA_IN2 SYNC+CLKSEL3 AC97_CLK GPIO32+LAD0 AC97_RST# GPIO33+LAD1 GPIO16+PC_BEEP GPIO34+LAD2 GPIO35+LAD3 GPIO36+LDRQ# CLK32 GPIO37+LFRAME# GPWIO[2:0] GPIO38+IRRX2+LPCPD LED# GPIO39+SERIRQ ONCTL# PWRBTN# PWRCNT[1:2] PLL6B+TEST1 PLL2B+TEST0 THRM# GXCLK+FP_VDD_ON+TEST3 PLL5B+TEST2 GTEST TDP, TRST#
Sub-ISA/PCI Interface
GPIO/LPC Interface
Test Measurement Interface
Figure 2-1.
Signal Groups (Continued)
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Signal Definitions (Continued)
BALL ASSIGNMENTS Table 2-1. Signal Definitions Legend
Mnemonic AVSS AVCC Definition Analog Ground ball: Analog Power ball: Analog General Configuration Block registers. Refer Section "General Configuration Block" page Location General Configuration Block cannot determined software. SC2200 Thin Client Chip device errata. MCR[x] Input ball Bidirectional ball Miscellaneous Configuration Register register, located GCB. Refer Section "Configuration Block Addresses" page further details. Output ball Open-drain Pull-down Multiplexing Register register, located GCB, used configure balls with multiple functions. Refer Section "Configuration Block Addresses" page further details. Pull-up TRI-STATE Power ball: 1.2V Power ball: 3.3V Ground ball symbol signal name indicates that active asserted state occurs when signal voltage level. Otherwise, signal asserted when high voltage level. signal name indicates both functions always enabled (i.e., cycle multiplexed). signal name indicates function available ball, that either strapping options register programming required select desired function. SC2200 highly configurable illustrated Figure page Strap options register programming used various modes operation specific signals specific balls. This section describes which signals available which balls provides configuration information: Figure page Figure page Illustrations EBGA TEPBGA ball assignments. Table page Table page Lists signals according ball number. Power Rail, Signal Type, Buffer Type and, where relevant, Pull-Up PullDown resistors indicated each ball this table. multiplexed balls, necessary configuration each signal listed well. Table page Table page Quick reference signal list sorted alphabetically listing signal names ball numbers.The tables this chapter several common abbreviations. Table lists mnemonics their meanings Notes: each GPIO signal, there optional pull-up resistor relevant ball. After system reset, pull-up present. This pull-up resistor disabled registers Core Logic module. configuration without regard selected ball function (except GPIO12, GPIO13, GPIO16). Alternate functions GPIO12, GPIO13, GPIO16 control pull-up resistors. more information, Section 5.4.1 "Bridge, GPIO, Registers Function page 199. Configuration settings listed this table with regard Multiplexing Register (PMR). Section "Multiplexing, Interrupt Selection, Base Address Registers" page detailed description this register. VCORE PMR[x]
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Signal Definitions (Continued)
IDAT13 IDAT10 IDAT8 IRST# IDAT5 IDAT1 IORDY0 IAD0 ICS0# GP18
AD29 AD26 AD22 AD19 AD16 CBE3# SERR# CBE1# AD14 AD12 CBE0# AD31 AD27 DVSL#
X27I
VPLL3 LED#
TRDY# PERR# AD15
IDAT15 IDAT12
IDAT7 IDAT4 IDAT0
SOUT1 PWRE PLL5B X32I
RQ0# AD30
AD28 AD24 AD21 AD17 IRDY# LOCK#
AD13 AD11 AD10
ICS1# IAD2 IDAT14 IDAT11 IDAT9 IIOR0# IDAT6 IDAT3 IDRQ0 IDCK0# IAD1 OVCR# PLL6B VCORE VCORE
PRST# GNT1# PCK0 GNT0# AD25 AD20 AD18 CBE2# STP#
VCORE VCORE VCORE VCORE
IDAT2 IIOW0# IRQ14 SIN1 X27O PLL2B X32O VBAT
FRM# PCLK REQ1# PCK1
AVSSP3 PBTN# OCTL# GPW0 THRM# GPW1 GPW2 PCNT1 PCNT2
IOR#
AD23
IOW# RMCS# GP20 GP19
TRDE#
VSBL CK32 GP11 SDIN2 IRRX1 POR# DQM0
HSYN VSYN IRTX GP17 VSSCRT VCCCRT AVSSCRT AVCCCRT VCORE VCCCRT GREEN AVCCCRT BLUE AVSSCRT VCORE VREF STRS AVSSCRT VPLL2 AVSSP2 VCORE SLCT
GeodeSC2200 Thin Client Chip
(Top View)
VPCKI VPD4 VPD0 VCORE VCORE VCORE SDCK1 VCORE VCORE VCORE
VCORE
VCORE WEA# CASA# RASA# CS0#
VCORE MA10
DQM4 VCORE VCORE MD33 MD32
ACK# VCORE
MD36 MD35 MD34
SLIN#
VCORE INIT#
VCORE MD39 MD38 MD37 MD46 MD47 MD45
ERR# VCORE
VCORE MD44
STB# AFD# INTB#
MD41 MD42 MD43
CKEA SDCK0 DQM5 MD40 DQM1
INTA# D+P3 D-P3 AVCCUSB SIN2
MD14 MD15 MA11
AVSSUSB D-P2 D-P1 D+P2 D+P1 GP10
MD13
MD28 MD55 MD51 MD48 MD23 SDCKO MA12 MD11 MD10 SDCKI MD12
VPD7 VPD6 VPD2 GP38 GP35 GP32 GP12 AB1C ACCK ACRT# SDCK3 MD56 MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6 MD22 MD19
SOUT2 TRST#
VPD1 GP37 GP34
SDATO SDATI
MD59 MD62
MD26 MD30 MD53
MD21 MD18 CS1#
GTST VPD5 VPD3 GP39 GP36 GP33 GP13 AB1D SYNC BITCK GP16 GXCK MD57 MD60 MD63 SDCK2 MD24 MD27 MD31 MD52 MD49 DQM2 MD20 MD17 MD16
Note:
Signal names have been abbreviated this figure space constraints. Ball Ball Strap Option Ball Multiplexed Ball
Figure 2-2. 432-EBGA Ball Assignment Diagram
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Signal Definitions (Continued)
Table 2-2. 432-EBGA Ball Assignment Sorted Ball Number
Ball Signal Name AD29 AD26 AD22 AD19 AD16 C/BE3# SERR# C/BE1# AD14 AD12 C/BE0# Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed TFTD16 IDE_IORDY0 TFTD11 IDE_ADDR0 TFTD3 IDE_CS0# TFTD5 GPIO18 DTR1#/BOUT1 Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed X27I AD31 AD27 Cycle Multiplexed DEVSEL# BHE# Cycle Multiplexed Cycle Multiplexed TRDY# Cycle Multiplexed PERR# (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) Cycle Multiplexed CLK27M IDE_DATA1 Cycle Multiplexed Cycle Multiplexed -VIO -Cycle Multiplexed A202 TFTD15 IDE_DATA10 DDC_SCL IDE_DATA8 GPIO40 IDE_RST# TFTDCK IDE_DATA5 Ball Signal Name IDE_DATA13 Buffer1 Power Rail Configuration (PU/PD) Type INTS1, TS1/4 O1/4 INTS1, TS1/4 INTS1, TS1/4 INTS1, O1/4 O1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1 O1/4 O1/4 O1/4 O1/4 O1/4 INTS, O8/8 O8/8 WIRE -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -INPCI, OPCI INPCI, OPCI INPCI, OPCI -VIO -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed -VIO PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[16] PMR[16] -Cycle Multiplexed
INPCI, (PU22.5) ODPCI (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI
Cycle Multiplexed
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Signal Definitions (Continued)
Table 2-2.
Ball Signal Name AD15 IDE_DATA15 TFTD7 IDE_DATA12 TFTD13 IDE_DATA7 INTD# IDE_DATA4 FP_VDD_ON IDE_DATA0 TFTD6 SOUT1 CLKSEL1 POWER_EN PLL5B TEST2 REQ0# AD30
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name AD28 -VIO -Cycle Multiplexed AD24 Cycle Multiplexed -VIO -PMR[24] PMR[24] PMR[24] PMR[24] -VIO -D12 -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -VIO -Strap (See Table page 51.) -PMR[29] PMR[29] -VIO -TFTD17 Cycle Multiplexed IDE_DATA11 GPIO41 IDE_CS1# TFTDE IDE_ADDR2 TFTD4 IDE_DATA14 AD13 AD11 AD10 (PU22.5) LOCK# IRDY# (PU22.5) (PU22.5) (PU22.5) (PU22.5) AD17 AD21 Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI O1/4 O1/4 O1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 INTS1, O1/4 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed -Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI OPCI -INPCI, OPCI OPCI INPCI, OPCI OPCI -INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -INTS1, TS1/4 INTS INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -O8/8 Cycle Multiplexed
INSTRP (PD100) O1/4 INT, TS2/5 O2/5
INPCI (PU22.5) INPCI, OPCI INPCI, OPCI
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Signal Definitions (Continued)
Table 2-2.
Ball C202 Signal Name IDE_DATA9 DDC_SDA IDE_IOR0# TFTD10 IDE_DATA6 IRQ9 IDE_DATA3 TFTD12 IDE_DREQ0 TFTD8 IDE_DACK0# TFTD0 IDE_ADDR1 TFTD2 OVER_CUR# PLL6B TEST1 X32I VPLL3 PCIRST# GNT1# DID1 PCICLK0 FPCI_MON GNT0# DID0 AD25 AD20 AD18 C/BE2#
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name STOP# PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[29] PMR[29] -VBAT -VIO -Strap (See Table page 51.) -Strap (See Table page 51.) -Strap (See Table page 51.) Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed E304, ONCTL# GPWIO0 AVSSPLL3 PWRBTN# PCICLK1 LPC_ROM VCORE VCORE VCORE VCORE VCORE VCORE IDE_DATA2 TFTD14 IDE_IOW0# TFTD9 IRQ14 TFTD1 SIN1 X27O PLL2B TEST0 X32O VBAT LED# FRAME# PCICLK REQ1# Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI -INPCI, OPCI OPCI -INTS1, TS1/4 O1/4 O1/4 O1/4 INTS1 O1/4 INTS WIRE INT, TS2/5 O2/5 WIRE -OD14 INPCI, OPCI INPCI OPCI VBAT -VSB -VIO -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[29] PMR[29] -Strap (See Table page 51.) -VSB -VIO -Cycle Multiplexed Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type INTS1, TS1/4 INT, O1/4 O1/4 INTS1, TS1/4 INTS1 INTS1, TS1/4 O1/4 INTS1 O1/4 O1/4 O1/4 O1/4 O1/4 INTS INTS, TS2/5 O2/5 -WIRE -OPCI OPCI PMR[24] PMR[24] PMR[24] PMR[24] PMR[24]
INSTRP (PD100) OPCI
INSTRP (PD100) OPCI
INSTRP (PD100) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI
INSTRP (PD100) (PU100) (PU100) -INBTN OD14 INTS, TS2/14
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Signal Definitions (Continued)
Table 2-2.
Ball Signal Name IOR# DOCR# GPIO14 CLKSEL0 AD23 F314, THRM# PWRCNT1 IOW# DOCW# GPIO15 ROMCS# BOOT16 GPWIO1 GPWIO2
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name VSBL CLK32 GPIO11 RI2# IRQ15 -VSB -VIO -PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] -VSB -Strap (See Table page 51.) -PMR[12] PMR[12] PMR[23]3 PMR[13] PMR[23]3 PMR[13] PMR[23]3 PMR[23]3 PMR[7] PMR[23]3 PMR[7] PMR[23]3 PMR[9] PMR[4] PMR[9] PMR[4] PMR[9] PMR[4]
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) O3/5 O3/5 INTS, O3/5 -O3/5 -VIO PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] -Strap (See Table page 51.) Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) -O2/5 INTS, O8/8 INTS INTS1 INTS O1/4 O1/4 O8/8 O8/8 INTS, O3/5 O3/5 O1/4 INTS INTS INTS INT, TS2/5 INT, TS2/5 WIRE -INT, TS2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 -INT, TS2/5 -WIRE AVCCCRT -VIO -VIO -VIO -AVCCCRT
-VSB
-PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
INSTRP (PD100) (PU22.5) INPCI, OPCI OPCI INTS -OD14 O3/5 -O3/5 O3/5 INTS, O3/5 O3/5
SDATA_IN2 HSYNC VSYNC IRTX SOUT3
F3BAR0+Memory Offset 08h[21] -PMR[6] PMR[6]
GPIO17 IOCS0# TFTDCK
PMR[23]3 PMR[5] PMR[23]3 PMR[5] PMR[23]3 PMR[6] PMR[6]
IRRX1 SIN3
POR# VSSCRT VCCCRT AVSSCRT AVCCCRT VCORE VCORE
J314
INSTRP (PD100) (PU100) (PU100) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTs, TS2/14 INTS, TS2/14 -OD14 O3/5 INTS, O3/5 INT, O3/5 O3/5 O1/4 INT, O3/5 O3/5 O1/4 INTS, O3/5 INTS INTS1
G314, PWRCNT2 TRDE# GPIO0 GPIO1 IOCS1# TFTD12 GPIO20 DOCCS# TFTD0 GPIO19 INTC# IOCHRDY
K304 K314 L294
AVCCCRT GREEN
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Signal Definitions (Continued)
Table 2-2.
Ball
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball T34, Signal Name Buffer1 Power (PU/PD) Type Rail Configuration (PU22.5 PD22.5) PMR[23]3 (PMR[27] FPCI_MON (PU/PD under software control.) PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Signal Name DQM0 AVCCCRT BLUE AVSSCRT VCORE VCORE WEA# CASA# RASA# VREF SETRES AVSSCRT CS0# VPLL2 AVSSPLL2 VCORE VCORE MA10 BUSY/WAIT#
Buffer1 Power Rail Configuration (PU/PD) Type -INT, TS2/5 -O2/5 -WIRE -O2/5 O2/5 O2/5 WIRE WIRE -O2/5 O2/5 O2/5 -O2/5 -O2/5 -VIO -VIO -AVCCCRT -VIO AVCCCRT AVCCCRT -VIO -VIO -VIO
TFTD14
O1/4
F_C/BE2#
O1/4
T44,
SLCT
TFTD15
O1/4
F_C/BE3#
O1/4
-T31
DQM4 VCORE
O2/5 O2/5 -O2/5 INT, O14/14 O1/4
U14,
TFTD13
F_AD7
O14/14
ACK#
-INT
TFTDE -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON U314 V14,
O1/4
FPCICLK
O1/4
TFTD3
O1/4
VCORE VCORE MD33 MD32
-INT, TS2/5 -INT, TS2/5 INT, O14/14 O1/4
F_C/BE1#
O1/4
TFTD10
F_AD4
O14/14
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Signal Definitions (Continued)
Table 2-2.
Ball V24, Signal Name
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball W314 Y14, Signal Name MD37 Buffer1 Power (PU/PD) Type Rail Configuration INT, TS2/5 INT, O14/14 O1/4 -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -INT, TS2/5 INT, O14/14 O1/4 -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -VIO
Buffer1 Power Rail Configuration (PU/PD) Type INT, O14/14 O1/4 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO
TFTD11
TFTD7
F_AD5
O14/14
F_AD1
V34,
INT, O14/14 O1/4
O14/14
Y34,
TFTD1
INIT#
-O14/14
F_AD6
O14/14
TFTD5
O1/4
V294
MD36 MD35 MD34 SLIN#/ASTRB#
-INT, TS2/5 INT, TS2/5 INT, TS2/5 O14/14
SMI_O
O14/14
-Y30 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -AA4 AA28 AA29 AA30 AA31
MD46 MD47
-INT, TS2/5
Y294
V314 W14,
Y314
TFTD16
O1/4
AA14,
F_IRDY#
O14/14
TFTD6
W24,
INT, O14/14 O1/4
F_AD0
O14/14
TFTD9
AA34,
ERR#
-INT, O1/4 O1/4
F_AD3
O14/14
TFTD4
W34,
INT, O14/14 O1/4
F_C/BE0#
O1/4
TFTD8
VCORE VCORE MD44 MD45
-INT, TS2/5 -INT, TS2/5
F_AD2
O14/14
VCORE VCORE MD39 MD38
-INT, TS2/5 INT, TS2/5
W304
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GeodeSC2200
Signal Definitions (Continued)
Table 2-2.
Ball Signal Name
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball AE29 AE30 AE31 AF34 AF28
Buffer1 Power Rail Configuration (PU/PD) Type O14/14 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
Signal Name INTB# DNEG_PORT3 AVCCUSB MD14 MD15 DQM1 AVSSUSB DNEG_PORT2 DNEG_PORT1 GPIO9 DCD2# IDE_IOW1# SDTEST2
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) O2/5 -O2/5 INPCI -INUSB, OUSB -INT, TS2/5 INT, TS2/5 -O2/5 -INUSB, OUSB INUSB, OUSB INTS, O1/4 INTS O1/4 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INUSB, OUSB INUSB, OUSB INTS, O1/4 O1/4 O1/4 O2/5 AVCCUSB AVCCUSB -VIO -AVCCUSB
AB14, STB#/WRITE#
-PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
TFTD17
O1/4
F_FRAME#
O14/14
AB24, AFD#/DSTRB#
O14/14
-VIO -VIO -AVCCUSB AVCCUSB
TFTD2
O1/4
AF294 AF30 AF31 AG24 AG34
INTR_O
O14/14
AB28 AB294 AB304 AB314 AC28 AC29 AC30 AC31 AD28 AD29 AD30 AD31 AE44 AE28
MD41 MD42 MD43 CKEA SDCLK0 DQM5 MD40 INTA# DPOS_PORT3
-GND -PWR -PWR (PU22.5)
-INT, TS2/5 INT, TS2/5 INT, TS2/5 -O2/5 O2/5 O2/5 INT, TS2/5 -O2/5 O2/5 O2/5 O2/5 -INPCI INUSB, OUSB O2/5
-VIO
-VIO
AG28 AG29
MA11 MD13 DPOS_PORT2 DPOS_PORT1 GPIO6 DTR2#/BOUT2 IDE_IOR1# SDTEST5
AG304 AG314
-AH3 -AH24 AH14
-VIO AVCCUSB
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GeodeSC2200
Signal Definitions (Continued)
Table 2-2.
Ball Signal Name GPIO7 RTS2# IDE_DACK1# SDTEST0 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH234 AH244 AH254 AH264 AH274 AH28 AH29 AH304 AH314 VPCKIN VPD4 VPD0 VCORE VCORE VCORE SDCLK1 VCORE VCORE VCORE MD28 MD55 MD51 MD48 MD23 SDCLK_OUT MA12 MD11 MD10 GPIO10 DSR2# IDE_IORDY1 SDTEST1
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GPIO8 CTS2# IDE_DREQ1 SDTEST4 SIN2 SDTEST3 VPD7 VPD6 VPD2 GPIO38/IRRX2 Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTS, O8/8 INTS INTS1 O2/5 -INTS O2/5 INPCI INPCI, OPCI -VIO PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] -PMR[28] PMR[28] -PMR[14]6 PMR[22]6 IRRX2 input connected input path GPIO38. There logic required enable IRRX2, just simple connection. Hence, when GPIO38 selected function, IRRX2 also selected. PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[19] PMR[19] PMR[23]3 PMR[23]3 PMR[7] PMR[23]3 PMR[7] PMR[25] FPCI_MON FPCI_MON
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INTS, O1/4 O1/4 O1/4 O2/5 Diode OPCI -O2/5 -INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INTS, O8/8 INTS INTS1 O2/5 -VIO -VIO -VIO PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8]
LPCPD# AJ10 GPIO35 LAD3
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB, INAB, INT, O3/5 O3/5 O2/5 O2/5 O2/5 O2/5 INT, TS2/5
-AJ11 -LAD0 -AJ12 -AJ13 -GPIO20 PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] AJ14 AJ15 DOCCS# AC97_CLK AC97_RST# F_STOP# AJ16 AJ174 SDCLK3 MD56 AB1C AB2C GPIO12 GPIO32
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Signal Definitions (Continued)
Table 2-2.
Ball AJ184 AJ194 AJ20 AJ21 AJ22
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball AK17 AK184 -VIO -VIO -AK194 -AK234 -AK244 -AK25 -Strap (See Table page 51.) -VIO -PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 -VIO -Strap (See Table page 51.) FPCI_MON FPCI_MON -IOCS1# GPIO1 AL11 GPIO13 AB2D AL12 AB1D (PU22.5) (PU22.5) (PU22.5) (PU22.5) AL10 SERIRQ GPIO36 LDRQ# GPIO33 LAD1 AK26 AK274 AK284 AK29 AK30 AK31 -INT INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI -OAC97 MD21 MD18 CS1# GTEST VPD5 VPD3 GPIO39 (PU22.5) (PD22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) MD53 MD30 AK20 AK21 AK224 MD26 MD62 Signal Name MD59 Buffer1 Power Rail Configuration (PU/PD) Type -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 -WIRE INPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB, INAB, INT, O3/5 O3/5 -VIO -VIO -VIO -VIO -PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[14]6 PMR[22]6 PMR[19] PMR[19] PMR[23]3 PMR[23]3 1and PMR[13] PMR[23]3 PMR[13]
Signal Name MD58 MD61 DQM7 DQM3 MD25 MD29 MD54 MD50 DQM6 MD22 MD19 SDCLK_IN MD12 SOUT2 CLKSEL2
Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 INT, TS2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 INT, TS2/5 -INT INT, TS2/5 -O8/8
AJ234 AJ244 AJ254 AJ26 AJ274 AJ284 AJ29 AJ30 AJ314
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI INPCI
TRST# VPD1 GPIO37 LFRAME#
AK10
GPIO34 LAD2
AK11 AK12 AK13
SDATA_OUT TFT_PRSNT
INSTRP (PD100) O2/5
AK14
SDATA_IN F_GNT0#
AK15 AK16
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GeodeSC2200
Signal Definitions (Continued)
Table 2-2.
Ball AL13 Signal Name SYNC CLKSEL3 AL14 BIT_CLK F_TRDY# AL15 GPIO16 PC_BEEP F_DEVSEL# AL16 GXCLK FP_VDD_ON TEST3 AL174 AL184 AL194 AL20 AL214 AL224 AL234 AL244 MD57 MD60 MD63 SDCLK2 MD24 MD27 MD31 MD52
432-EBGA Ball Assignment Sorted Ball Number (Continued)
Ball AL254 AL26 AL274 AL284 AL294 AL30 AL31 Signal Name MD49 DQM2 MD20 MD17 MD16 Buffer1 Power Rail Configuration (PU/PD) Type INT, TS2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 -VIO
Buffer1 Power Rail Configuration (PU/PD) Type OAC97 -Strap (See Table page 51.) FPCI_MON FPCI_MON PMR[0] FPCI_MON PMR[0] FPCI_MON FPCI_MON PMR[23]3 PMR[29] PMR[23]3 PMR[23]3 PMR[29]
INSTRP (PD100) (PU22.5) O1/4 INT, O2/5 O2/5 O2/5 O2/5 O1/4 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5
Buffer Type definitions, refer Table "Buffer Types" page 365. need tolerant protection system level (DDC_SCL, DDC_SDA). TFT_PRSNT strap determines power-on reset (POR) state PMR[23]. back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). LPC_ROM strap determines power-on reset (POR) state PMR[14] PMR[22].
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Signal Definitions (Continued)
Table 2-3. 432-EBGA Ball Assignment Sorted Alphabetically Signal Name
Signal Name AB1C AB1D AB2C AB2D AC97_CLK AC97_RST# ACK# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Ball AJ13 AL12 AJ12 AL11 AJ14 AJ15 Signal Name AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AFD#/DSTRB# AVCCCRT AVCCUSB AVSSCRT AVSSPLL2 AVSSPLL3 AVSSUSB BHE# BIT_CLK BLUE BOOT16 BUSY/WAIT# C/BE0# C/BE1# C/BE2# C/BE3# CASA# CKEA CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 CS0# CS1# CTS2# Ball AL14 Signal Name DCD2# DDC_SCL DDC_SDA DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# DOCCS# DOCR# DOCW# DPOS_PORT1 DPOS_PORT2 DPOS_PORT3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DSR2# DTR1#/BOUT1 DTR2#/BOUT2 ERR# F_AD0 F_AD1 F_AD2 F_AD3 F_AD4 F_AD5 F_AD6 F_AD7 F_C/BE0# F_C/BE1# Ball AJ13 AF31 AL26 AJ21 AC30 AJ26 AJ20
AC28 AL13 AK29
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GeodeSC2200
Signal Definitions (Continued)
Table 2-3.
Signal Name F_C/BE2# F_C/BE3# F_DEVSEL# F_FRAME# F_GNT0# F_IRDY# F_STOP# F_TRDY# FP_VDD_ON FPCI_MON FPCICLK FRAME# GNT0# GNT1# GPIO0 GPIO1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2 GREEN GTEST GXCLK HSYNC IDE_ADDR0
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AL15 AK14 AJ15 AL14 B23, AL16 AL12 AJ12 AL11 AL15 AJ13 AJ11 AL10 AK10 AJ10 AL16 Signal Name IDE_ADDR1 IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0 IDE_DREQ1 IDE_IOR0# IDE_IOR1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_RST# INIT# INTA# INTB# INTC# INTD# INTR_O IOCHRDY IOCS0# IOCS1# IOCS1# IOR# IOW# IRDY# IRQ9 IRQ14 IRQ15 IRRX1 IRTX Ball AL12 Signal Name LAD0 LAD1 LAD2 LAD3 LDRQ# LED# LFRAME# LOCK# LPC_ROM LPCPD# MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 Ball AJ11 AL10 AK10 AJ10 AE28 AE29 AE31 AD28 AD29 AD30 AD31 AG28 AH29 AG30 AG29 AH31 AH30 AJ31 AG31 AF28 AF29 AL29 AL28 AK28 AJ28 AL27 AK27 AJ27 AH27 AL21 AJ22
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Signal Definitions (Continued)
Table 2-3.
Signal Name MD26 MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 (Total
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AK22 AL22 AH23 AJ23 AK23 AL23 AC31 AB29 AB30 AB31 AA29 AA31 AH26 AL25 AJ25 AH25 AL24 AK24 AJ24 AH24 AJ17 AL17 AJ18 AK18 AL18 AJ19 AK19 AL19 AB3, AC1, AC2, AD1, AD2, AD3, AD4, AL15 Signal Name PERR# PLL2B PLL5B PLL6B POR# POWER_EN PWRBTN# PWRCNT1 PWRCNT2 RASA# REQ0# REQ1# RI2# ROMCS# RTS2# SDATA_IN SDATA_IN2 SDATA_OUT SDCLK_IN SDCLK_OUT SDCLK0 SDCLK1 SDCLK2 SDCLK3 SDTEST0 SDTEST1 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SETRES SIN1 SIN2 SIN3 SLCT SLIN#/ASTRB# Ball AK14 AK13 AJ30 AH28 AC29 AH16 AL20 AJ16 Signal Name SMI_O SOUT1 SOUT2 SOUT3 STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT TFTD0 TFTD1 TFTD10 TFTD11 TFTD12 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD9 TFTDCK TFTDE THRM# TRDE# TRDY# TRST# VBAT VCCCRT Ball AL13 AL16 AK13 C25, D25, C21, A25, C23, B19, D23, A19, A24, C18, C26, A26, C17, A27, B24, B18, C24, D24, A22, C16,
ONCTL# OVER_CUR# PC_BEEP PCICLK PCICLK0 PCICLK1 PCIRST#
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GeodeSC2200
Signal Definitions (Continued)
Table 2-3.
Signal Name VCORE (Total
432-EBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball D11, D13, D15, D17, D19, D21, L28, N28, R28, T30, U28, W28, AA4, AA28, AH11, AH13, AH15, AH17, AH19, AH21 A30, B11, B16, B20, B25, B31, C29, G30, M30, Y30, AC3, AE2, AE30, AJ3, AJ29, AK1, AK6, AK11, AK16, AK20, AK25, AK31, AL2, AL30 VSSCRT VSYNC WEA# X27I X27O X32I X32O Signal Name VREF VSBL (Total Ball A31, B12, B15, B17, B21, B26, B30, D10, D12, D14, D18, D20, D22, F30, K28, L30, M28, P28, R30, U30, V28, Y28, AA2, AA30, AB4, AB28, AC4, AF2, AF30, AH10, AH12, AH14, AH18, AH20, AH22, AK2, AK7, AK12, AK15, AK17, AK21, AK26, AK30, AL1, AL31,
(Total
VPCKIN VPD0 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VPLL2 VPLL3
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Signal Definitions (Continued)
VPLL2 STB# D+P3 D-P3 D+P1 D-P1 D+P2 D-P2 GP10
AD30 PCK0 REQ1# PRST# PCICK IOW# GP20 GP17 HSNC AVCCCT GREEN BLUE
AD29 AD28 REQ0# AD23
VSNC
AVSSCT STRES
BUSY ACK#
SLIN# INIT#
AD26 AD24
AD25 GNT0# GNT1# RMCS# GP19 FRM# IOR#
IRTX VSSCT AVCCCT AVSSCTAVSSCT AVSSP2 SLCT AVCCCT VREF
INTB# AVSSUSB
AD21 AD22 AD20 AD27 AD31 PCK1 AD16 AD19 AD18 DVSL# TRDY# IRDY# CBE2# AD17 STOP#
TRDE# VCCCT
ERR# AFD#
INTA# AVCCUSB SOUT SIN2 TRST#
GTST VPCKI VPD7
SRR# PRR# LOCK# CBE3# AD13 CBE1# AD15 AD11 AD14
VPD6 VPD5 VPD4 VPD3
CBE0#
AD10 AD12
GeodeVCORE VCORE VCORE VCORE VCORE VCORE VCORE VCORE
VPD2 VPD1 VPD0 GP39 GP38 GP37
GP36 GP35 GP34 GP33 GP32 GP13
GP12 AB1D AB1C
ICS1#
VCORE
VCORE SYNC ACCK
VCORE VCORE VCORE VCORE IAD2 VCORE
VCORE VCORE VCORE VCORE VCORE ACRST# BITCK SDCK3 GXCK GP16 MD57 SDCK1
IDAT15 IDAT14 IDAT13 IDAT12 IDAT11
VCORE VCORE VCORE VCORE
VCORE VCORE VCORE VCORE
IDAT10 IDAT9 IDAT8 IIOR0# IRST# IDAT7 IDAT6 IDAT5 IDAT4 IDAT3
IDAT1 IDAT2 IDAT0 IDRQ0 IIORY0 IIOW0# IAD0 IDACK0# IAD1
SC2200 Thin Client Chip
(Top View)
CK32 POR# GP11 WEA# MD34 MD37 MD41 DQM1 MD13 CASA# RASA# MA10 MD32 MD33 MD36 MD47 MD45 MD42 SDCK0 MD35 MD46 MD38 MD39 MD43 DQM5
MD58 MD59 MD60 MD56 SDCK2 MD61 MD62 MD63 MD24 DQM7
MD25 MD26 MD27 DQM3 MD52 MD29 MD30 MD31 MD28
IRQ14 ICS0# SOUT1 OVRCUR# GP18 SIN1 X27I PLL6B PBTN# GPW0
MD50 MD49 MD54 MD53 MD21 DQM6 DQM2 MD55 MA11 CS1# MD18 MD48 MD20 MD51 MD11 SDCKI MD19 MD22 MD17
PWRE X27O PLL2B PLL5B X32I
X32O VPLL3 ONCT# GPW2
AVSSP3 THRM#GPW1 PCNT1 IRRX1 VBAT LED# VSBL PCNT2 SDATI2
MD15
MD14 MD12 SDCKO MD16
DQM0 CS0#
DQM4
MD44 MD40 CKEA
MD10 MA12 MD23
Note:
Signal names have been abbreviated this figure space constraints. Ball Ball Strap Option Ball Multiplexed Ball
Figure 2-3. 481-TEPBGA Ball Assignment Diagram
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4. 481-TEPBGA Ball Assignment Sorted Ball Number
Ball Signal Name AD30 PCICLK0 FPCI_MON REQ1# PCIRST# PCICLK IOW# DOCW# GPIO15 GPIO20 DOCCS# TFTD0 GPIO17 IOCS0# TFTDCK HSYNC AVCCCRT GREEN BLUE VPLL2 Buffer1 Power Rail Configuration (PU/PD) Type -INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 51.) -TFTD7 OPCI O3/5 O3/5 INTS, O3/5 INT, O3/5 O3/5 O1/4 INTS, O3/5 O3/5 O1/4 O1/4 -WIRE WIRE -INT, O14/14 O1/4 -AVCCCRT AVCCCRT -VIO -F_AD1 PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] PMR[23]3 PMR[7] PMR[23]3 PMR[7] PMR[23]3 PMR[23] PMR[5] PMR[23]3 PMR[5]
Ball A206,
Signal Name
Buffer1 Power Rail Configuration (PU/PD) Type INT, O14/14 O1/4 PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -AVCCUSB
-VIO
-Cycle Multiplexed
TFTD1
F_AD6
O14/14
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI
A216,
INT, O14/14 O1/4
O14/14
A226,
STB#/WRITE#
O14/14
TFTD17
O1/4
F_FRAME#
O14/14
A266 A276 A286 A296
DPOS_PORT3 DNEG_PORT3 DPOS_PORT1 DNEG_PORT1 AD29
-I/O
-INUSB, OUSB INUSB, OUSB INUSB, OUSB INUSB, OUSB -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI
-Cycle Multiplexed
PMR[23]3 -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
AVCCUSB AVCCUSB AVCCUSB -VIO
A186,
TFTD13
AD28
Cycle Multiplexed
F_AD7
O14/14
REQ0#
INPCI (PU22.5)
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Signal Definitions (Continued)
Table 2-4.
Ball Signal Name AD23 CLKSEL0
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball B276 -VIO -Strap (See Table page 51.) -VIO AVCCCRT
Buffer1 Power Rail Configuration (PU/PD) Type INPCI, OPCI OPCI -O3/5 Cycle Multiplexed
Signal Name DPOS_PORT2 DNEG_PORT2 GPIO10 DSR2# IDE_IORDY1 SDTEST1
Buffer1 Power Rail Configuration (PU/PD) Type -I/O (PU22.5) (PU22.5) (PU22.5) (PU22.5) -INUSB, OUSB INUSB, OUSB INTS, O8/8 INTS INTS1 O2/5 -INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 51.) -Strap (See Table page 51.) -VIO -Strap (See Table page 51.) PMR[9] PMR[4] PMR[9] PMR[4] PMR[9] PMR[4] -VIO -PMR[6] PMR[6] -VIO -Cycle Multiplexed Cycle Multiplexed -VIO -AVCCUSB
-PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] -Cycle Multiplexed
B286
AVCCUSB
INSTRP (PD100) O3/5 -O1/4 WIRE -WIRE -INT
VSYNC AVSSCRT SETRES BUSY/WAIT#
-PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23] (PMR[27] FPCI_MON
-AVCCCRT
AD26
-VIO
TFTD3
O1/4
AD24
F_C/BE1#
O1/4
AD25
B186,
ACK#
PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
TFTDE
O1/4
GNT0# DID0
FPCICLK
O1/4
PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
INSTRP (PD100) OPCI
GNT1# DID1
B206,2
SLIN#/ASTRB#
-O14/14
INSTRP (PD100) -O3/5
ROMCS# BOOT16
TFTD16
O1/4
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) INTS, O3/5 INTS INTS1 -O8/8 O8/8
F_IRDY#
O14/14
GPIO19 INTC# IOCHRDY
B216,2
INIT#
O14/14
TFTD5
O1/4
IRTX SOUT3
SMI_O
O14/14
VSSCRT AVCCCRT AVSSCRT AVSSCRT
-GND
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball C176,2 Signal Name AVSSPLL2 SLCT
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GPIO7 RTS2# IDE_DACK1# SDTEST0 GPIO8 CTS2# IDE_DREQ1 SDTEST4 AD21 AD22 AD20 AD27 AD31 PCICLK1 LPC_ROM FRAME# IOR# DOCR# GPIO14 GPIO1 IOCS1# TFTD12 PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8] TRDE# GPIO0 VCCCRT Buffer1 Power (PU/PD) Type Rail Configuration (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) -INTS, O1/4 O1/4 O1/4 O2/5 INTS, O8/8 INTS INTS1 O2/5 INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -Strap (See Table page 51.) -VIO -PMR[21] PMR[2] PMR[21] PMR[2] PMR[21] PMR[2] -PMR[23]3 PMR[13] PMR[23]3 PMR[13] PMR[23]3 PMR[12] PMR[12] -VIO Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed Cycle Multiplexed -VIO -PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] PMR[17] PMR[8] Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type -INT -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23] (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON
TFTD15
O1/4
F_C/BE3#
O1/4
INT, O14/14 O1/4
TFTD10
F_AD4
O14/14
C196,2
INT, O14/14 O1/4
TFTD11
F_AD5
O14/14
C206,2
INT, O14/14 O1/4
TFTD9
F_AD3
O14/14
C216,2
INT, O14/14 O1/4
TFTD6
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) -INPCI, OPCI O3/5 O3/5 INTS, O3/5 INT, O3/5 O3/5 O1/4 O3/5 INTS, O3/5
F_AD0
O14/14
INTB# AVSSUSB GPIO9 DCD2# IDE_IOW1# SDTEST2
-PWR (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
-INPCI -INTS, O1/4 INTS O1/4 O2/5
-VIO -VIO
-PMR[18] PMR[8]
Revision
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball D176, Signal Name AVCCCRT VREF
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name SOUT2 CLKSEL2 PMR[23]3 (PMR[27] FPCI_MON (PU/PD under software control.) AD16 AD19 AD18 DEVSEL# BHE# SIN2 SDTEST3 TRST# TRDY# IRDY# C/BE2# AD17 GTEST VPCKIN STOP# O2/5 PMR[18] PMR[8] Buffer1 Power (PU/PD) Type Rail Configuration O8/8 -Strap (See Table page 51.) -VIO -Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5 PD22.5) -WIRE -AVCCCRT
INSTRP (PD100) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PD22.5) (PU22.5) (PU22.5) Diode WIRE INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INTS O2/5 INPCI OPCI INPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI INPCI INPCI, OPCI INPCI, OPCI -VIO
Cycle Multiplexed
TFTD14
O1/4
PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON PMR[23]3 (PMR[27] FPCI_MON -VIO -VIO -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
F_C/BE2#
O1/4
Cycle Multiplexed
-INT, O14/14 O1/4
Cycle Multiplexed
D206,
PMR[28] PMR[28] -Cycle Multiplexed
TFTD8
F_AD2
O14/14
D216, ERR#
INT, O1/4 O1/4
TFTD4
Cycle Multiplexed
F_C/BE0#
O1/4
D226, AFD#/DSTRB#
O14/14
Cycle Multiplexed
TFTD2
O1/4
Cycle Multiplexed
INTR_O
O14/14
INTA# AVCCUSB GPIO6 DTR2#/BOUT2 IDE_IOR1# SDTEST5
-GND (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
-INPCI -INTS, O1/4 O1/4 O1/4
-Cycle Multiplexed
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball Signal Name VPD7 SERR# PERR# LOCK# C/BE3# VPD6 VPD5 VPD4 VPD3 AD13 C/BE1# AD15 VPD2 VPD1 VPD0 GPIO39 SERIRQ AD11 AD14
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GPIO38/IRRX2 Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) INPCI, OPCI PMR[14]4 PMR[22]4 IRRX2 input connected input path GPIO38. There logic required enable IRRX2, just simple connection. Hence, when GPIO38 selected function, IRRX2 also selected. PMR[14]4 PMR[22]4 -VIO -PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type -INT -VIO -Cycle Multiplexed
INPCI, (PU22.5) ODPCI (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI -INPCI, OPCI OPCI
LPCPD# -Cycle Multiplexed C/BE0# AD10 AD12 -PMR[14] PMR[22]4 PMR[14] PMR[22]4 Cycle Multiplexed GPIO34 LAD2 GPIO33 LAD1
(PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5)
OPCI -INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI INPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI INPCI, OPCI -INPCI, OPCI OPCI -VIO
GPIO37 LFRAME#
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
Cycle Multiplexed
GPIO36 LDRQ#
PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 -Cycle Multiplexed
GPIO35 LAD3
-VIO
-Cycle Multiplexed
Revision
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball Signal Name GPIO32 LAD0 GPIO13 AB2D VCORE VCORE VCORE VCORE GPIO12 AB2C AB1D GPIO1 IOCS1# AB1C GPIO20 DOCCS#
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name IDE_CS1# TFTDE PMR[14]4 PMR[22]4 PMR[14]4 PMR[22]4 -VIO PMR[19] PMR[19] -Cycle Multiplexed Cycle Multiplexed VCORE VCORE VCORE VCORE VCORE VCORE SDATA_OUT TFT_PRSNT Cycle Multiplexed -VIO -PMR[19] PMR[19] PMR[23]3 PMR[23] PMR[13] PMR[23]3 PMR[13] PMR[23]3 PMR[23]3 PMR[7] PMR[23]3 PMR[7] Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) (PU22.5) INPCI, OPCI OPCI INPCI, OPCI INPCI, OPCI INAB, O8/8 INAB, -INPCI, OPCI OPCI INPCI, OPCI OPCI INPCI, OPCI OPCI -INAB, O8/8 INAB, INAB, INT, O3/5 O3/5 INAB, INT, O3/5 O3/5 INPCI, OPCI OPCI Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type O1/4 O1/4 INPCI, OPCI OPCI -OAC97 -VIO -Strap (See Table page 51.) -Strap (See Table page 51.) -PMR[25] -VIO PMR[24] PMR[24] Cycle Multiplexed
INSTRP (PD100) OAC97
SYNC CLKSEL3 AC97_CLK VCORE VCORE VCORE VCORE
INSTRP (PD100) O2/5
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball Signal Name VCORE VCORE VCORE VCORE IDE_ADDR2 TFTD4 VCORE VCORE AC97_RST# F_STOP# BIT_CLK F_TRDY# SDATA_IN F_GNT0# IDE_DATA15 TFTD7 IDE_DATA14 TFTD17 IDE_DATA13 TFTD15 VCORE VCORE VCORE VCORE SDCLK3
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name GXCLK FP_VDD_ON TEST3 GPIO16 PC_BEEP PMR[24] PMR[24] Cycle Multiplexed -VIO -FPCI_MON FPCI_MON FPCI_MON FPCI_MON FPCI_MON FPCI_MON PMR[24] PMR[24] PMR[24] DDC_SCL PMR[24] PMR[24] DDC_SDA PMR[24] -VIO -Y306 Y316 MD60 MD56 Y296 MD59 Y286 GPIO40 IDE_IOR0# TFTD10 MD58 IDE_DATA8
Buffer1 Power Rail Configuration (PU/PD) Type -INPCI, OPCI OPCI O1/4 O1/4 INPCI, OPCI OPCI -O2/5 O2/5 O1/4 O2/5 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 -O2/5 -VIO -Cycle Multiplexed
Buffer1 Power Rail Configuration (PU/PD) Type (PU22.5) O2/5 O1/4 O2/5 INT, O2/5 O2/5 O2/5 -INTS1, TS1/4 O1/4 INTS1, TS1/4 INTS1, O1/4 -INT, TS2/5 O2/5 -INTS1, TS1/4 INTS1, TS1/4 INT, INTS1, TS1/4 INTS1, O1/4 O1/4 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 -VIO -VIO -VIO PMR[23]3 PMR[29] PMR[23]3 PMR[23]3 PMR[29] PMR[0] FPCI_MON PMR[0] FPCI_MON FPCI_MON -PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24]
F_DEVSEL# IDE_DATA12 TFTD13 IDE_DATA11 GPIO41 W286 VCORE VCORE VCORE VCORE MD57 SDCLK1 IDE_DATA10
IDE_DATA9
Revision
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball Signal Name IDE_RST# TFTDCK IDE_DATA7 INTD# IDE_DATA6 IRQ9 IDE_DATA5 CLK27M AA28 AA296 AA306 AA316 SDCLK2 MD61 MD62 MD63 IDE_DATA4 FP_VDD_ON IDE_DATA3 TFTD12 AB286 AB29 AB30 AB31 MD24 DQM7 IDE_DATA1 TFTD16 IDE_DATA2 TFTD14 IDE_DATA0 TFTD6 IDE_DREQ0 TFTD8 AC286 AC296 AC306 AC31 MD25 MD26 MD27 DQM3 IDE_IORDY0 TFTD11
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball Signal Name IDE_IOW0# TFTD9 IDE_ADDR0 TFTD3 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24] -VIO -PMR[24] PMR[24] -VIO -AF2 -PMR[24] PMR[24] PMR[24] AF296 PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24] AG28 AG29
Buffer1 Power Rail Configuration (PU/PD) Type O1/4 O1/4 INTS1, TS1/4 INTS INTS1, TS1/4 INTS1 INTS1, TS1/4 O1/4 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INTS1, TS1/4 O1/4 -INTS1, TS1/4 O1/4 INT, TS2/5 -O2/5 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1, TS1/4 O1/4 INTS1 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INTS1 O1/4 PMR[24] PMR[24] PMR[24]
Buffer1 Power Rail Configuration (PU/PD) Type O1/4 O1/4 O1/4 O1/4 O1/4 O1/4 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O1/4 O1/4 -INT, TS2/5 INTS1 O1/4 O1/4 O1/4 O8/8 -VIO PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] PMR[24] -PMR[24] PMR[24] -PMR[24] PMR[24] PMR[24] PMR[24] -Strap (See Table page 51.) -PMR[16] PMR[16] -PMR[29] PMR[29]
IDE_DACK0# TFTD0
AD286 AD296 AD306 AD316
MD52 MD29 MD30 MD31 IDE_ADDR1 TFTD2
AE28 AE29 AE30 AE316
MD28 IRQ14 TFTD1 IDE_CS0# TFTD5
SOUT1 CLKSEL1 OVER_CUR# MD50 MD49 MD54 MD53 GPIO18 DTR1#/BOUT1
INSTRP (PD100) (PU22.5) (PU22.5) INTS INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INTS, O8/8 O8/8 INTS WIRE INTS, TS2/5 O2/5 INT, TS2/5 O2/5
AF286
AF306 AF316
SIN1 X27I PLL6B TEST1 MD21 DQM6
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GeodeSC2200
Signal Definitions (Continued)
Table 2-4.
Ball AG30 AG316 Signal Name DQM2 MD55 POWER_EN X27O PLL2B TEST0 AH106 AH116 AH12 AH13 AH14 AH15 AH166 AH176 AH18 AH19 AH206 AH21 AH22 AH23 AH246 AH25 AH26 AH27 AH286 AH29
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball -PMR[29] PMR[29] -VSB -VSB -VIO -VIO -VIO -IRQ15 INTS, TS2/14 -O2/5 INTS INT, TS2/5 INT, TS2/5 O2/5 -O2/5 INT, TS2/5 INT, TS2/5 -INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 -O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 WIRE VBAT -AJ96 -AJ186 -AJ196 -AJ21 -AJ29 -PMR[29] PMR[29] -AJ306 AJ316 MD22 MD17 AVSSPLL3 THRM# GPWIO1 (PU100) AJ27 AJ286 SDCLK_IN MD19 AJ22 AJ23 AJ24 AJ25 AJ266 SDCLK0 MD11 AJ206 MD42 MD45 MD47 AJ166 AJ176 MD33 MD36 AJ10 AJ116 AJ12 AJ13 AJ14 AJ15
Buffer1 Power Rail Configuration (PU/PD) Type (PU100) (PU100) O2/5 INT, TS2/5 O1/4 WIRE INT, TS2/5 O2/5 -INBTN
Signal Name X32O VPLL3 ONCTL# GPWIO2 GPIO11 RI2#
Buffer1 Power (PU/PD) Type Rail Configuration (PU100) (PU22.5) (PU22.5) (PU22.5) WIRE -OD14 INTS, TS2/14 -INTS, O8/8 INTS INTS1 INT, TS2/5 -INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 -O2/5 O2/5 -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 -INTS INTs, TS2/14 -VIO -VIO -VIO -VIO -VSB VBAT -VSB -VIO -PMR[18] PMR[8] PMR[18] PMR[8] PMR[18] PMR[8]
PWRBTN# GPWIO0 CLK32 POR# WEA# MD34 MD37 MD41 DQM1 MD13 MA11 CS1# MD18 MD48 MD20 MD51 PLL5B TEST2
CASA# MA10 MD32
AH306 AH316
X32I
Revision
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Signal Definitions (Continued)
Table 2-4.
Ball Signal Name
481-TEPBGA Ball Assignment Sorted Ball Number (Continued)
Ball AL12 AL13 AL14 AL15 AL16 AL17 -VIO -VIO -INT, TS2/5 INT, TS2/5 -INT, TS2/5 O2/5 -O2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 -OD14 -OD14 INTS INT, TS2/5 INT, TS2/5 O2/5 -VIO -VIO -VIO -VSB -VSB -AL29 -AL30 -F3BAR0+Memory Offset 08h[21] Buffer Type definitions, refer Table "Buffer Types" page 365. tolerant (ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). TFT_PRSNT strap determines power-on reset (POR) state PMR[23]. LPC_ROM strap determines power-on reset (POR) state PMR[14] PMR[22]. need tolerant protection system level (DDC_SCL, DDC_SDA). back-drive protected (MD[63:0], DPOS_PORT1, DNEG_PORT1, DPOS_PORT2, DNEG_PORT2, DPOS_PORT3, DNEG_PORT3, ACK#, AFD#/DSTRB#, BUSY/WAIT#, ERR#, INIT#, PD[7:0], SLCT, SLIN#/ASTRB#, STB#/WRITE#, ONCTL#, PWRCNT[2:1]). AL31 AL266 AL276 AL28
Buffer1 Power Rail Configuration (PU/PD) Type OD14 -INTS INTS INT, TS2/5 -INT, TS2/5 O2/5 -O2/5 O2/5 -VSB -PMR[6] PMR[6]
Signal Name CS0# DQM4 MD38 MD39
Buffer1 Power Rail Configuration (PU/PD) Type O2/5 -O2/5 O2/5 -INT, TS2/5 INT, TS2/5 -INT, TS2/5 INT, TS2/5 O2/5 O2/5 O2/5 INT, TS2/5 INT, TS2/5 INT, TS2/5 O2/5 INT, TS2/5 -VIO -VIO -VIO -VIO
AK66, PWRCNT1 IRRX1 SIN3 AK96 AK10 AK116 AK12 AK13 AK14 AK15 AK16 AK17
RASA# MD35 MD46 MD43 DQM5 MD15 MD14 MD12 SDCLK_OUT MD16 VBAT LED# VSBL PWRCNT2 SDATA_IN2 DQM0
AL186 AL19 AL20
MD44 MD40 CKEA MD10 MA12 MD23
AL216 AL22 AL23 AL24 AL256
AK186 AK19 AK206 AK21 AK22 AK23 AK246 AK25 AK266 AK276 AK28 AK296 AK30 AK31 AL76, AL96 AL106 AL11
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Signal Definitions (Continued)
Table 2-5. 481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name
Signal Name AB1C AB1D AB2C AB2D AC97_CLK AC97_RST# ACK# AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 Ball Signal Name AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 AFD#/DSTRB# AVCCCRT AVCCUSB AVSSCRT AVSSPLL2 AVSSPLL3 AVSSUSB BHE# BIT_CLK BLUE BOOT16 BUSY/WAIT# C/BE0# C/BE1# C/BE2# C/BE3# CASA# CKEA CLK27M CLK32 CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 CS0# CS1# CTS2# Ball A12, C13, B14, C14, AJ13 AK14 AJ12 AL22 AL12 AH27 Signal Name DCD2# DDC_SCL DDC_SDA DEVSEL# DID0 DID1 DNEG_PORT1 DNEG_PORT2 DNEG_PORT3 DOCCS# DOCR# DOCW# DPOS_PORT1 DPOS_PORT2 DPOS_PORT3 DQM0 DQM1 DQM2 DQM3 DQM4 DQM5 DQM6 DQM7 DSR2# DTR1#/BOUT1 DTR2#/BOUT2 ERR# F_AD0 F_AD1 F_AD2 F_AD3 F_AD4 F_AD5 F_AD6 F_AD7 F_C/BE0# F_C/BE1# F_C/BE2# Ball AL11 AH23 AG30 AC31 AL15 AK21 AG29 AB31
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Signal Definitions (Continued)
Table 2-5.
Signal Name F_C/BE3# F_DEVSEL# F_FRAME# F_GNT0# F_IRDY# F_STOP# F_TRDY# FP_VDD_ON FPCI_MON FPCICLK FRAME# GNT0# GNT1# GPIO0 GPIO1 GPIO6 GPIO7 GPIO8 GPIO9 GPIO10 GPIO11 GPIO12 GPIO13 GPIO14 GPIO15 GPIO16 GPIO17 GPIO18 GPIO19 GPIO20 GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 GPIO40 GPIO41 GPWIO0 GPWIO1 GPWIO2 GREEN GTEST GXCLK HSYNC IDE_ADDR0 IDE_ADDR1
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball V30, D10, Signal Name IDE_ADDR2 IDE_CS0# IDE_CS1# IDE_DACK0# IDE_DACK1# IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_DREQ0 IDE_DREQ1 IDE_IOR0# IDE_IOR1# IDE_IORDY0 IDE_IORDY1 IDE_IOW0# IDE_IOW1# IDE_RST# INIT# INTA# INTB# INTC# INTD# INTR_O IOCHRDY IOCS0# IOCS1# IOCS1# IOR# IOW# IRDY# IRQ9 IRQ14 IRQ15 IRRX1 IRTX LAD0 Ball Signal Name LAD1 LAD2 LAD3 LDRQ# LED# LFRAME# LOCK# LPC_ROM LPCPD# MA10 MA11 MA12 MD10 MD11 MD12 MD13 MD14 MD15 MD16 MD17 MD18 MD19 MD20 MD21 MD22 MD23 MD24 MD25 MD26 Ball AL14 AH15 AK15 AJ24 AL24 AK23 AJ23 AL23 AH22 AH21 AJ14 AH26 AL28 AH10 AL10 AH11 AJ11 AK11 AL25 AL27 AL26 AJ26 AK27 AH24 AK26 AK24 AK29 AJ31 AH28 AJ28 AH30 AG28 AJ30 AL29 AB28 AC28 AC29
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Signal Definitions (Continued)
Table 2-5.
Signal Name MD27 MD28 MD29 MD30 MD31 MD32 MD33 MD34 MD35 MD36 MD37 MD38 MD39 MD40 MD41 MD42 MD43 MD44 MD45 MD46 MD47 MD48 MD49 MD50 MD51 MD52 MD53 MD54 MD55 MD56 MD57 MD58 MD59 MD60 MD61 MD62 MD63 (Total
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball AC30 AE31 AD29 AD30 AD31 AJ15 AJ16 AH16 AK17 AJ17 AH17 AL17 AL18 AL21 AH20 AJ20 AK20 AL20 AJ19 AK18 AJ18 AH29 AF29 AF28 AH31 AD28 AF31 AF30 AG31 AA29 AA30 AA31 A23, A24, A25, B23, B26, C23, C24, Signal Name PERR# PLL2B PLL5B PLL6B POR# POWER_EN PWRBTN# PWRCNT1 PWRCNT2 RASA# REQ0# REQ1# RI2# ROMCS# RTS2# SDATA_IN SDATA_IN2 SDATA_OUT SDCLK_IN SDCLK_OUT SDCLK0 SDCLK1 SDCLK2 SDCLK3 SDTEST0 SDTEST1 SDTEST2 SDTEST3 SDTEST4 SDTEST5 SERIRQ SERR# SETRES SIN1 SIN2 SIN3 SLCT SLIN#/ASTRB# SMI_O SOUT1 Ball AK12 AJ27 AK28 AJ21 AA28 Signal Name SOUT2 SOUT3 STB#/WRITE# STOP# SYNC TEST0 TEST1 TEST2 TEST3 TFT_PRSNT TFTD0 TFTD1 TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD9 TFTD10 TFTD11 TFTD12 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 TFTDCK TFTDE THRM# TRDE# TRDY# TRST# VBAT VCCCRT VCORE (Total Ball A20, D22, B17, D21, B21, C21, A21, D20, C20, C18, C19, D10, A18, D17, C17, B20, A22, A10, B18, N13, N14, N18, N19, P13, P14, P18, P19, P28, T28, T29, T30, T31, U28, V13, V14, V18, V19, W13, W14, W18,
ONCTL# OVER_CUR# PC_BEEP PCICLK PCICLK0 PCICLK1 PCIRST#
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Signal Definitions (Continued)
Table 2-5.
Signal Name (Total
481-TEPBGA Ball Assignment Sorted Alphabetically Signal Name (Continued)
Ball A30, B13, B16, B19, B31, C10, C22, C25, C29, D14, D18, D23, G29, K29, M30, W31, AB3, AB29, AE3, AE29, AH4, AH14, AH18, AJ7, AJ10, AJ22, AJ25, AJ29, AK1, AK13, AK16, AK19, AK31, AL2, AL30 VSSCRT VSYNC Signal Name (Total Ball A13, A16, A19, A31, B10, B22, B24, B25, B30, D13, D19, D25, G28, G30, K30, M31, N15, N16, N17, N28, P15, P16, P17, R13, R14, R15, R16, R17, R18, R19, R28, R29, R30, R31, T13, T14, T15, T16, T17, T18, T19, U13, U14, U15, U16, U17, U18, U19, V15, V16, V17, V28, W15, W16, W17, W30, AB2, AB30, AE2, AE4, AE28, AE30, AH7, AH13, AH19, AH25, AK2, AK7, AK10, AK22, AK25, AK30, AL1, AL13, AL16, AL19, AL31 Signal Name WEA# X27I X27O X32I X32O Ball AH12
VPCKIN VPD0 VPD1 VPD2 VPD3 VPD4 VPD5 VPD6 VPD7 VPLL2 VPLL3 VREF VSBL
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Signal Definitions (Continued)
STRAP OPTIONS
placed balls listed Table 2-6. value resistor important ensure that proper state read during power-up sequence. ball read correctly power-up, SC2200 default state that causes function improperly, possibly resulting application failure. Several balls read power-up that state SC2200. These balls typically multiplexed with other functions that outputs after power-up sequence complete. SC2200 must read state balls power-up internal resistors guarantee correct state will read. Therefore, required that external resistor with value
Table 2-6. Strap Options
Ball Strap Option CLKSEL0 CLKSEL1 CLKSEL2 CLKSEL3 Muxed With SOUT1 SOUT2 SYNC EBGA AL13 TEPBGA Nominal Internal PD100 PD100 PD100 PD100 External PU/PD Strap Settings Strap (PD) Strap (PU) Register References GCB+I/O Offset 1Eh[9:8] (aka CCFC register bits [9:8]) (RO): Value programmed reset CLKSEL[1:0]. GCB+I/O Offset 10h[3:0] (aka MCCM register bits [3:0]) (RO): Value programmed reset CLKSEL[3:0]. GCB+I/O Offset 1Eh[3:0] (aka CCFC register bits [3:0]) (R/W, write recommended): Value programmed reset CLKSEL[3:0]. Note: Values GCB+I/O Offset 10h[3:0] 1Eh[3:0] same. BOOT16 ROMCS# PD100 Enable boot from 8-bit Enable boot from 16-bit GCB+I/O Offset 34h[3] (aka register (RO): Reads back strap setting. GCB+I/O Offset 34h[14] (R/W): Used allow ROMCS# width changed under program control. TFT_PRSNT SDATA_OUT AK13 PD100 muxed onto Parallel Port Disable boot from Disable FastPCI, INTR_O, SMI_O monitoring signals. muxed onto Parallel Port Enable boot from Enable FastPCI, INTR_O, SMI_O monitoring signals. (Useful during debug.) GCB+I/O Offset 30h[23] (aka register (R/W): Reads back strap setting. F0BAR1+I/O Offset 10h[15] (R/W): Reads back strap setting allows changed under program control. GCB+I/O Offset 34h[30] (aka register (RO): Reads back strap setting. Note: normal operation, strap this signal using resistor. GCB+I/O Offset 34h[31,29] (aka register bits (RO): Reads back strap setting. Note: GNT0# must have resistor GNT1# must have resistor Note: Accuracy internal PU/PD resistors: 250K. Location (General Configuration Block) cannot determined software. SC2200 Thin Client Chip device errata document.
Table page CLKSEL strap options.
LPC_ROM
PCICLK1
PD100
FPCI_MON
PCICLK0
PD100
DID0 DID1
GNT0# GNT1#
PD100 PD100
Defines system-level chip
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Signal Definitions (Continued)
MULTIPLEXING CONFIGURATION
system reset, pull-up present. This pull-up resistor disabled writing Core Logic registers. configuration without regard selected ball function. above applies pins multiplexed with GPIO, except GPIO12, GPIO13, GPIO16. tables that follow list multiplexing options their configurations. Certain multiplexing options chosen signal; others available only group signals. Where ever GPIO multiplexed with another function, there optional pull-up resistor this pin; after
Table 2-7. Two-Signal/Group Multiplexing
Default EBGA TEPBGA Signal IDE_ADDR0 IDE_ADDR1 IDE_ADDR2 IDE_DATA0 IDE_DATA1 IDE_DATA2 IDE_DATA3 IDE_DATA4 IDE_DATA5 IDE_DATA6 IDE_DATA7 IDE_DATA8 IDE_DATA9 IDE_DATA10 IDE_DATA11 IDE_DATA12 IDE_DATA13 IDE_DATA14 IDE_DATA15 IDE_IOR0# IDE_IORDY0 IDE_DREQ0 IDE_IOW0# IDE_CS0# IDE_CS1# IDE_DACK0# IDE_RST# IRQ14 Sub-ISA TRDE# PMR[12] GPIO0 PMR[24] TFTD3 TFTD2 TFTD4 TFTD6 TFTD16 TFTD14 TFTD12 FP_VDD_ON CLK27M IRQ9 INTD# GPIO40 DDC_SDA DDC_SCL GPIO41 TFTD13 TFTD15 TFTD17 TFTD7 TFTD10 TFTD11 TFTD8 TFTD9 TFTD5 TFTDE TFTD0 TFTDCK TFTD1 GPIO PMR[12] Configuration Signal Alternate Configuration
Ball
TFT, CRT, PCI, GPIO, System PMR[24]
Ball
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Signal Definitions (Continued)
Table 2-7. Two-Signal/Group Multiplexing (Continued)
Default EBGA TEPBGA Signal GPIO GPIO12 GPIO13 GPIO GPIO18 PMR[16] Infrared IRTX IRRX1 GPIO GPIO32 GPIO33 GPIO34 GPIO35 GPIO36 GPIO37 GPIO38/IRRX2 GPIO39 UART SIN2 PMR[28] AC97 AC97_RST# SDATA_IN BIT_CLK Internal Test PLL6B PLL5B PLL2B PMR[29] TEST1 TEST2 TEST0 FPCI_MON F_STOP# F_GNT0# F_TRDY# Internal Test PMR[29] SDTEST3 PMR[14] PMR[22] LAD0 LAD1 LAD2 LAD3 LDRQ# LFRAME# LPCPD# SERIRQ Internal Test PMR[28] FPCI Monitoring FPCI_MON PMR[6] SOUT3 SIN3 PMR[14] PMR[22] DTR1#/BOUT1 PMR[19] AB2C AB2D UART PMR[16] UART PMR[6] Configuration Signal Alternate Configuration ACCESS.bus PMR[19]
Ball AJ12 AL11
Ball
Ball Ball AJ11 AL10 AK10 AJ10
Ball
Ball AJ15 AK14 AL14
Ball
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Signal Definitions (Continued)
Table 2-8. Three-Signal/Group Multiplexing
Default EBGA TEPBGA Signal Configuration Sub-ISA IOR# IOW# PMR[21] PMR[2] GPIO GPIO16 PMR[0] FPCI_MON GPIO GPIO19 PMR[9] PMR[4] Parallel Port ACK# PMR[23] AFD#/DSTRB# (PMR[27] FPCI_MON BUSY/WAIT# ERR# INIT# SLCT SLIN# /ASTRB# STB#/WRITE# GPIO GPIO17 GPIO20 GPIO1 PMR[23] PMR[5] PMR[23] PMR[7] PMR[23] PMR[13] AB1C AB1D PMR[23] PMR[23] GPIO GPIO11 PMR[18] PMR[8] RI2# GPIO20 GPIO1 IOCS0# DOCCS# IOCS1# TFTDE TFTD2 TFTD3 TFTD4 TFTD5 TFTD6 TFTD7 TFTD8 TFTD9 TFTD10 TFTD11 TFTD1 TFTD13 TFTD14 TFTD15 TFTD16 TFTD17 Sub-ISA PMR[23] PMR[5] PMR[23] PMR[7] PMR[23] PMR[13] GPIO PMR[23] PMR[7] PMR[23] PMR[13] UART2 PMR[18] PMR[8] IRQ15 DOCCS# IOCS1# TFTDCK TFTD0 TFTD12 INTC# PC_BEEP DOCR# DOCW# Signal Alternate1 Configuration Sub-ISA1 PMR[21] PMR[2] AC97 PMR[0] FPCI_MON PCI2 PMR[9] PMR[4] TFT3 PMR[23] (PMR[27] FPCI_MON IOCHRDY GPIO14 GPIO15 Signal Alternate2 Configuration GPIO PMR[21] PMR[2] FPCI Monitoring F_DEVSEL FPCI_MON Sub-ISA PMR[9] PMR[4]
Ball
Ball AL15
Ball
Ball
FPCI Monitoring FPCI_CLK INTR_O F_C/BE1# F_C/BE0# SMI_O F_AD0 F_AD1 F_AD2 F_AD3 F_AD4 F_AD5 F_AD6 F_AD7 F_C/BE2# F_C/BE3# F_IRDY F_FRAME# TFT3 PMR[23] PMR[23] PMR[23] Sub-ISA PMR[23] PMR[7] PMR[23] PMR[13] IDE2 PMR[18] PMR[8] PMR[23] (PMR[27] FPCI_MON
Ball
Ball AJ13 AL12
Ball
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Signal Definitions (Continued)
Table 2-8. Three-Signal/Group Multiplexing (Continued)
Default EBGA TEPBGA Signal Configuration Internal Test GXCLK PMR[23] PMR[29] TEST3 Signal Alternate1 Configuration Internal Test PMR[23] PMR[29] FP_VDD_ON Signal Alternate2 Configuration PMR[23]
Ball AL16
combination PMR[21] PMR[2] undefined should used. combination PMR[9] PMR[4] undefined should used. These outputs reset POR# TFT_PRSNT strap pulled high PMR[10] This relates signals TFTD[17:0], TFTDE, TFTDCK.
Table 2-9. Four-Signal/Group Multiplexing
TEPBGA EBGA Default Signal Configuration GPIO GPIO7 GPIO8 GPIO6 GPIO9 GPIO10 PMR[17] RTS2# PMR[8] CTS2# PMR[18] DTR2#/BOUT2 PMR[8] DCD2# DSR2# Signal Alternate1 Configuration UART2 PMR[17] IDE_DACK1# PMR[8] IDE_DREQ1 PMR[18] IDE_IOR1# PMR[8] IDE_IOW1# IDE_IORDY1 Signal Alternate2 Configuration IDE2 Signal Alternate3 Configuration
Ball
Internal Test PMR[17] PMR[8] PMR[18] PMR[8]
PMR[17] SDTEST0 PMR[8] SDTEST4 PMR[18] SDTEST5 PMR[8] SDTEST2 SDTEST1
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Signal Definitions (Continued)
SIGNAL DESCRIPTIONS
Information tables that follow have duplicate information multiple tables. Multiple references contain identical information. 2.4.1 System Interface Ball Signal Name CLKSEL1 CLKSEL0 EBGA TEPBGA Type Description Fast-PCI Clock Selects. These strap signals used internal Fast-PCI clock. 33.3 66.7 33.3 During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used. CLKSEL3 CLKSEL2 AL13 Maximum Core Clock Multiplier. These strap signals used maximum allowed multiplier value core clock. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used. BOOT16 Boot Bits Wide. This strap signal enables optional 16-bit wide Sub-ISA bus. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used. LPC_ROM LPC_ROM. This strap signal forces selecting sets F0BAR1+I/O Offset 10h[15], Addressing Enable. enables SC2200 boot from connected bus. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used. TFT_PRSNT AK13 Present. strap used select multiplexing signals power-up. Enables using instead Parallel Port, ACB1, GPIO17. During system reset, internal pull-down resistor exists these balls. external pull-up pull-down resistor must used. FPCI_MON Fast-PCI Monitoring. strap this ball forces selection Fast-PCI monitoring signals. normal operation, strap this signal using resistor. value this strap read MCR[30]. PCICLK0 SDATA_OUT PCICLK1 ROMCS# SYNC SOUT2 SOUT1
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Signal Definitions (Continued)
2.4.1 System Interface (Continued) Ball Signal Name DID1 DID0 EBGA TEPBGA Type Description Device Together, straps these signals define system-level chip value DID1 read MCR[29]. value DID0 read MCR[31]. DID0 must have pull-up resistor DID1 must have pull-down resistor POR# Power Reset. POR# system reset signal generated from power supply indicate that system should reset. Crystal Connections. Connected directly 32.768 crystal. This clock input required even internal being used. Some internal clocks derived from this clock. external clock used, should connected X32I, using voltage level volts VCORE +10% maximum. X32O should remain unconnected. Crystal Connections. Connected directly 27.000 crystal. Some internal clocks derived from this clock. external clock used, should connected X27I, using voltage level volts X27O should remain unconnected. Output Clock. Output crystal oscillator. System Reset. PCIRST# reset signal system. asserted approximately after POR# negated. -Mux GNT1# GNT0#
X32I X32O
X27I X27O
CLK27M PCIRST#
IDE_DATA5
2.4.2
Memory Interface Signals Ball
Signal Name MD[63:0]
EBGA Table page Table page
TEPBGA Table page Table page AK14 AJ13
Type
Description Memory Data Bus. data lines driven to/from system memory.
MA[12:0]
Memory Address Bus. multiplexed row/column address lines driven system memory. Supports 256-Mbit SDRAM. Bank Address Bits. These bits used select component bank within SDRAM.
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Signal Definitions (Continued)
2.4.2 Memory Interface Signals (Continued) Ball Signal Name CS1# CS0# EBGA AK29 TEPBGA AH27 AL12 Type Description Chip Selects. These bits used select module bank within system memory. Each chip select corresponds specific module bank. high, bank(s) respond RAS#, CAS#, until bank selected again. Address Strobe. RAS#, CAS#, encoded support different SDRAM commands. RASA# used with CS[1:0]#. Column Address Strobe. RAS#, CAS#, encoded support different SDRAM commands. CASA# used with CS[1:0]#. Write Enable. RAS#, CAS#, encoded support different SDRAM commands. WEA# used with CS[1:0]#. Data Mask Control Bits. During memory read cycles, these outputs control whether SDRAM output buffers driven not. signals asserted during read cycles. During memory write cycles, these outputs control whether data written into SDRAM. DQM[7:0] connect directly [DQM7:0] pins each DIMM connector. Clock Enable. These signals used enter Suspend/power-down mode. CKEA used with CS[1:0]#. goes when read write cycle progress, SDRAM enters powerdown mode. ensure that SDRAM data remains valid, self-refresh command executed. exit this mode, return normal operation, drive high. These signals should have external pulldown resistor SDCLK3 SDCLK2 SDCLK1 SDCLK0 SDCLK_IN AJ16 AL20 AH16 AC29 AJ30 AA28 AJ21 AJ27 SDRAM Clocks. SDRAM uses these clocks sample control, address, data lines. ensure that Suspend mode functions correctly, SDCLK3 SDCLK1 should used with CS1#. SDCLK2 SDCLK0 should used together with CS0#. SDRAM Clock Input. SC2200 samples memory read data this clock. Works conjunction with SDCLK_OUT signal. -Mux
RASA#
AK12
CASA#
AJ12
WEA#
AH12
DQM7 DQM6 DQM5 DQM4 DQM3 DQM2 DQM1 DQM0 CKEA
AJ20 AJ26 AC30 AJ21 AL26 AF31 AC28
AB31 AG29 AK21 AL15 AC31 AG30 AH23 AL11 AL22
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Signal Definitions (Continued)
2.4.2 Memory Interface Signals (Continued) Ball Signal Name SDCLK_OUT EBGA AH28 TEPBGA AK28 Type Description SDRAM Clock Output. This output routed back SDCLK_IN. board designer should vary length board trace control skew between SDCLK_IN SDCLK.
2.4.3
Video Port Interface Signals Ball
Signal Name VPD7 VPD6 VPD5 VPD4 VPD3 VPD2 VPD1 VPD0 VPCKIN
EBGA
TEPBGA
Type
Description Video Port Data. data input from CCIR-656 video decoder.
Video Port Clock Input. clock input from video decoder.
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Signal Definitions (Continued)
2.4.4 CRT/TFT Interface Signals Ball Signal Name DDC_SCL EBGA TEPBGA Type Description Serial Clock. This serial clock VESA Display Data Channel interface. used monitor communications. DDC2B standard supported this interface. Serial Data. This bidirectional serial data signal VESA Display Data Channel interface. used monitor communications. DDC2B standard supported this interface. Horizontal Sync Vertical Sync Voltage Reference. Reference voltage DAC. This signal reflects internal voltage reference. internal voltage reference used (recommended), leave this ball disconnected. external voltage reference used, this input tied 1.235V reference. Resistor. This signal sets current level RED/GREEN/BLUE analog outputs. Typically, 464, resistor connected between this ball AVSSCRT. IDE_DATA10
DDC_SDA
IDE_DATA9
HSYNC VSYNC VREF
SETRES
On-Chip RAMDAC GREEN BLUE Analog Red, Green Blue
(External DAC) Interface TFTDCK TFTDE FP_VDD_ON AL16 TFTD[17:0] Table page Table page Clock. Clock external DACs TFT. Data Enable. used blank signal external DACs. Power Control. Used enable power Flat Panel display, with power sequence timing. IDE_RST# GPIO17+ IOCS0# IDE_CS1# ACK#+FPCICLK IDE_DATA4 GXCLK+TEST3
Digital Data TFT. interface TFTD[5:0] Connect BLUE inputs. muxed with TFTD[11:6] Connect GREEN inputs. interface ParTFTD[17:12] Connect inputs. allel Port. Table page Table page details.
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Signal Definitions (Continued)
2.4.5 ACCESS.bus Interface Signals Ball Type Signal Name AB1C EBGA AJ13 TEPBGA Description ACCESS.bus Serial Clock. This serial clock interface. Note: AB1D AL12 selected AB1C function used, AB1C high. GPIO1+IOCS1# GPIO20+DOCCS#
ACCESS.bus Serial Data. This bidirectional serial data signal interface. Note: AB1D function selected used, AB1D high.
AB2C
AJ12
ACCESS.bus Serial Clock. This serial clock interface. Note: AB2C function selected used, AB2C high.
GPIO12
AB2D
AL11
ACCESS.bus Serial Data. This bidirectional serial data signal interface. Note: AB2D function selected used, AB2D high.
GPIO13
2.4.6
Interface Signals BalL
Signal Name PCICLK
EBGA
TEPBGA
Type
Description Clock. PCICLK provides timing transactions bus. other signals sampled rising edge PCICLK, timing parameters defined with respect this edge. Clock Outputs. PCICLK0 PCICLK1 provide clock drives system MHz. These clocks asynchronous signals. There skew between outputs. these clock signals should connected PCICLK input. clock users system (including PCICLK) should receive clock with skew possible. Multiplexed Address Data. transaction consists address phase cycle which FRAME# asserted followed more data phases. During address phase, AD[31:0] contain physical 32-bit address. I/O, this byte address. configuration memory, DWORD address. During data phases, AD[7:0] contain least significant byte (LSB) AD[31:24] contain most significant byte (MSB).
PCICLK0 PCICLK1
FPCI_MON (Strap) LPC_ROM (Strap)
AD[31:24] AD[23:0]
Table page
Table page
D[7:0] A[23:0]
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Signal Definitions (Continued)
2.4.6 Interface Signals (Continued) BalL Signal Name C/BE3# C/BE2# C/BE1# C/BE0# EBGA TEPBGA Type Description Multiplexed Command Byte Enables. During address phase transaction when FRAME# active, C/BE[3:0]# define command. During data phase, C/BE[3:0]# used byte enables. byte enables valid entire data phase determine which byte lanes carry meaningful data. C/BE0# applies byte (LSB) C/BE3# applies byte (MSB). Interrupts. SC2200 provides inputs optional "level-sensitive" interrupts (also known industry terms PIRQx#). These interrupts mapped IRQs internal 8259A interrupt controllers using Interrupt Steering Registers Index 5Dh). Note: selected INTC# INTD# function(s) used, INTC# INTD# high.
INTA# INTB# INTC# INTD#
-GPIO19+IOCHRDY IDE_DATA7
Parity. Parity generation required agents. master drives address- write-data phases. target drives read-data phases. Parity even across AD[31:0] C/BE[3:0]#. address phases, stable valid clock after address phase. same timing AD[31:0] delayed clock. data phases, stable valid clock after either IRDY# asserted write transaction after TRDY# asserted read transaction. Once valid, remains valid until clock after completion data phase. (Also PERR#.)
FRAME#
Frame Cycle. Frame driven current master indicate beginning duration access. FRAME# asserted indicate beginning transaction. While FRAME# asserted, data transfers continue. FRAME# de-asserted when transaction final data phase. This signal internally connected pullup resistor.
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Signal Definitions (Continued)
2.4.6 Interface Signals (Continued) BalL Signal Name IRDY# EBGA TEPBGA Type Description Initiator Ready. IRDY# asserted indicate that master able complete current data phase transaction. IRDY# used conjunction with TRDY#. data phase completed clock which both IRDY# TRDY# sampled asserted. During write, IRDY# indicates that valid data present AD[31:0]. During read, indicates that master prepared accept data. Wait cycles inserted until both IRDY# TRDY# asserted together. This signal internally connected pullup resistor. TRDY# Target Ready. TRDY# asserted indicate that target agent able complete current data phase transaction. TRDY# used conjunction with IRDY#. data phase complete clock which both TRDY# IRDY# sampled asserted. During read, TRDY# indicates that valid data present AD[31:0]. During write, indicates that target prepared accept data. Wait cycles inserted until both IRDY# TRDY# asserted together. This signal internally connected pullup resistor. STOP# Target Stop. STOP# asserted indicate that current target requesting that master stop current transaction. This signal used with DEVSEL# indicate retry, disconnect, target abort. STOP# sampled active master, FRAME# deasserted cycle stopped within three clock cycles. input, STOP# asserted following cases: master tries access memory that been locked another master. This condition detected FRAME# LOCK# asserted during address phase. write buffers full previously buffered cycle completed. read cycles that cross cache line boundaries. This conditional based upon programming module's Configuration Register, Index 41h[1].
This signal internally connected pullup resistor.
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Signal Definitions (Continued)
2.4.6 Interface Signals (Continued) BalL Signal Name LOCK# EBGA TEPBGA Type Description Lock Operation. LOCK# indicates atomic operation that require multiple transactions complete. When LOCK# asserted, non-exclusive transactions proceed address that currently locked least bytes must locked). grant start transaction does guarantee control LOCK#. Control LOCK# obtained under protocol conjunction with GNT#. possible different agents while single master retains ownership LOCK#. arbiter implement complete system lock. this mode, LOCK# active, other master gain access system until LOCK# de-asserted. This signal internally connected pullup resistor. DEVSEL# Device Select. DEVSEL# indicates that driving device decoded address target current access. input, DEVSEL# indicates whether device been selected. DEVSEL# also driven agent that ability accept cycles subtractive decode basis. master, DEVSEL# detected within subtractive decode clock, master abort cycle initiated (except special cycles which expect DEVSEL# returned). This signal internally connected pullup resistor. PERR# Parity Error. PERR# used reporting data parity errors during transactions except Special Cycle. PERR# line driven clocks after data which error detected. This clock after that attached data. minimum duration PERR# clock each data phase which data parity error detected. PERR# must driven high clock before being placed TRI-STATE. target asserts PERR# write cycles claimed cycle with DEVSEL#. master asserts PERR# read cycles. This signal internally connected pullup resistor. -BHE#
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Signal Definitions (Continued)
2.4.6 Interface Signals (Continued) BalL Signal Name SERR# EBGA TEPBGA Type Description System Error. SERR# asserted agent reporting errors other than parity, that central agent notifies processor. When Parity Enable Memory Controller Configuration register, SERR# asserted upon detection parity error read operations from DRAM. This signal internally connected pullup resistor. REQ1# REQ0# Request Lines. REQ[1:0]# indicate arbiter that agent requires bus. Each master REQ# line. REQ# priorities order) are: Channel Channel Audio External REQ0# External REQ1# -Mux
Each REQ# internally connected pullup resistor. GNT1# GNT0# Grant Lines. GNT[1:0]# indicate requesting master that been granted access bus. Each master GNT# line. GNT# retracted time higher REQ# received master does begin cycle within minimum period time clocks). Each these signals internally connected pull-up resistor. GNT0# must have pull-up resistor GNT1# must have pull-down resistor DID1 (Strap) DID0 (Strap)
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Signal Definitions (Continued)
2.4.7 Sub-ISA Interface Signals Ball Signal Name A[23:0] EBGA Table page Table page TEPBGA Table page Table page Type Description Address Lines AD[23:0]
D[7:0] BHE# IOCS1#
Data
STOP# IRDY# TRDY# C/BE3# C/BE2# C/BE1# C/BE0# AD[31:24]
AL12
Byte High Enable. With defines byte accessed wide cycl
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