Display Processor Scan Rate Converter using Embedded DRAM Technology U
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9410-B13 DAEDALUS
Display Processor Scan Rate Converter using Embedded DRAM Technology Units
Edition March 2001 6251-553-1PD
9410 Revision History: Previous Versions:
2000-05 1.0) 1998-08-01
Changes previous issue Version Edition 08.98, marked with change
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Micronas
SDA9410
Preliminary Data Sheet
5.4.1 5.4.2 5.4.3 5.4.4 5.4.5 5.6.1 5.6.2 5.6.3 5.6.4 5.6.5 5.6.6 5.6.7 5.6.8 5.6.9 5.7.1 5.7.2 5.7.3 5.7.4 5.10 5.11 5.12 5.12.1 5.12.2 5.12.3 5.12.4 5.12.5
Introduction Features Block diagram Description Diagram: P-MQFP-100 System description Introduction Input sync controller (ISCM/ISCS) Input format conversion (IFCM/IFCS) Input signal processing Adjustable delay Vertical horizontal compression (VHCOMM/VHCOMS) Noise reduction Noise measurement Letter detection Clock concept Application modes memory concept Introduction Configuration controlling mode configuration mode configuration Configuration switch Joint line free display Master slave switch Refresh still picture mode Memory management animation controlling Output sync controller (OSCM/S) HOUT generator VOUT generator Switching from H-and-V-freerunning H-and-V-locked mode Operation mode generator Motion estimation Motion compensation .100 Global motion, film mode phase detection .104 Vertical expansion .107 Display processing .109 Peaking .110 Digital luminance transition improvement .111 Digital colour transition improvement .113 Insertion facilities .115 Coarse delay .116
Micronas
SDA9410
Preliminary Data Sheet
5.12.6 5.13 5.13.1 5.13.2 5.13.3 5.13.4
Digital-to-Analog conversion .116 .117 slave address .117 format .117 commands .120 Detailed description .127 Electrical Characteristics .170 Absolute maximum ratings .170 Operating range .171 Characteristics (Under operating range conditions) .173 Application information .175 Wave forms .176 timing START/STOP .176 timing DATA .176 Timing diagram clock .177 Clock circuit diagram .177 Package Outlines .178
Micronas
SDA9410
Preliminary Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Block diagram Block diagram configuration Principles mode Principles mode Principles mode Input parameter. Field detection VINM delay Explanation format SYNCENM/SYNCENS signal Input timing Block diagram input processing blocks Block diagram VHCOMM/VHCOMS Principles panorama mode Block diagram noise reduction Block diagram motion detector motion detection Example noise measurement Principle letter detection Block diagram letter detection Histogram line type decision Visibility letter detection parameters Clock concept 9410 Application 9410 Supported data formats Switching from SRC-PIP mode mode Changing picture sizes double window display. Completing operations master slave exchange Example animation Equation position left upper picture corner Explanation memory management Explanation memory management Explanation memory management Block diagram OSCM/S Output parameter Output write parameter Ingenious configurations HOUT VOUT generator VOUT generation depending parameter RMODE Explanation field display line-scanning pattern Explanation operation mode timing Principle block matching Block diagram motion estimation compensation. Block diagram motion estimation
Micronas
SDA9410
Preliminary Data Sheet
Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure
Relative positions spatial predictors Timing scan rate conversion .100 Principles motion compensation .100 Principles motion compensation field (FILSEL=0). .101 Output sequence generation: Camera mode. .102 Output sequence generation: film mode .103 Output sequence generation: NTSC film mode .103 Calculation maximum VPAN value .108 Block diagram display processing .109 Block diagram peaking .110 Principles DCTI .114 Application 9410. .175
Micronas
SDA9410
Preliminary Data Sheet
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
definitions functions Input signals Input write parameter Input write parameter Input write parameter Input read parameter Input signals Input data formats Input sync formats DELM/DELS parameter Examples vertical filter adjustment Conversion table between dezV DEZVM DEZVS. Input write parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS Input write parameter Examples horizontal filter adjustment Conversion table between dezH DEZHM/DEZMS Input write parameter CHFILM/CHFILS Filter parameter case PANAON=1 parameter PANAST case PANAON=1 Input write parameter Input write parameter parameter TNRVAY/C parameter TNRHOY/C TNRKOY/C parameter TNRCLY Input write parameter Input write parameter Input read parameter Line Type Decision Evaluation reliability signal RELY Correction "start/end-line decision filter" block Input write parameter Input read parameter Input signals Output signals Clock concept switching matrix Input write parameter Definition MEMOP Definition CHRFORM/CHRFORS Definition ORGMEM Definition ORGMEMS Definition VERRESM/VERRESS Programmable data configurations Applications different data configurations
Micronas
SDA9410
Preliminary Data Sheet
Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Maximum picture sizes Definition MEMWRS Definition MEMWRM Input write parameter Definition WRFLDM/WRFLDS Input write parameter Definition ORGMEMM Definition ORGMEMS Definition MEMRDM Definition MEMRDS Definition MEMWRM Definition MEMWRS Switching from mode mode Changing picture sizes double window format. Performing master slave exchange Input write parameter Output read parameter Supported data formats Input write parameter Output read parameter Input write parameter Input write parameter Input write parameter Output signals Output write parameter Output write parameter INTMODE Output write parameter INTMODE Static operation modes (only valid ADOPMOM=0, RMODE=0) Static operation modes (only valid ADOPMOM=0, RMODE=1) Special combinations STOPMOM ADOPMOM Display line-scanning pattern sequence Static operation modes slave. Adaptive operation modes Output write parameter parameters motion estimation. Output write parameter Output write parameter Principles global motion film mode detection Definition scmin/scmax depending SFMINTH/SFMAXTH Output write parameter Output read parameter Output write parameter VERINT Examples reachable expansion factors
Micronas
SDA9410
Preliminary Data Sheet
Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Output write parameter Output signals Conversion table BCOF/HCOF gain_bp/gain_hp Output write parameters parameter THRESY parameter THRESY_UP parameter ASCENTLTI Output write parameters parameter THRESC parameter ASCENTCTI Output write parameters Output write parameters Output write parameter Output write parameter
Micronas
SDA9410
Preliminary Data Sheet
BLANK PAGE
Micronas
SDA9410
Preliminary Data Sheet
Introduction
Introduction
9410 component Micronas MEGAVISION set, which enables system reduce large area line flickering interlaced standards. scan rate conversion 100/120 interlaced 50/60 progressive scan motion vector based. 100/120 (50/60 conversion 9410 really calculates 100/120 (50/60 fields with continuous motion phases avoid double contour effects motion display. special case movie sources, which have non-continuous motion phase, 9410 generates output appropriate sequence with continuous motion phase (,,True Motion"). frame based signal processing, noise reduction been greatly improved. Furthermore different motion detectors luminance chrominance have been implemented. automatic controlling noise reduction parameters noise measurement algorithm included, which measures noise level picture blanking period. addition spatial noise reduction implemented, which reduces noise even case motion. 9410 input channels, which used different features like Picture-in-Picture (maximum approximately picture) "Double-window/Splitscreen". input signals scaled horizontally vertically with variable factors. Panorama modes will supported. Besides that algorithm detection letter pictures included. 9410 delivers start line active picture part input signal external calculates zoom factors displaying active picture part full screen sends this values back 9410. Picture sharpness greatly improved (luminance transition improvement) or/and peaking (colour transition improvement) algorithm. resolution output signals bit. 9410 analog output signals.
Micronas
SDA9410
Preliminary Data Sheet
Features
Features
Different application modes mode: High performance scan rate converter High performance scan rate converter plus high resolution frame based joint-linefree Picture-in-Picture (maximum approximately picture) mode: Split screen applications with signal sources (e.g. double window) mode: Multipicture display mode (e.g. tuner scan) amplitude resolution each input channel input channels Input frequency ITU-R data format wires data only additional sync information wires including sync information) 4:2:2 luminance chrominance parallel (2x8 wires) different representations input chrominance data complement code Positive dual code flexible input sync controllers Vertical peaking input signal Flexible scaling input signal Flexible digital vertical compression input signal (1.0, line resolution] 1/32) Flexible horizontal compression expansion input signal (2.0, pixel resolution] ,1.0 pixel resolution] 1/32) Panorama mode (programmable characteristic) Noise reduction Motion adaptive spatial temporal noise reduction (3D-NR) Temporal noise reduction luminance chrominance, frame based field based Different motion detectors luminance chrominance identical Flexible programming temporal noise reduction parameters Automatic measurement noise level value, readable motion estimation High performance motion estimation based block matching algorithm Film mode detector (PAL NTSC), Global motion flag (readable bus) Automatic detection letter formats (readable bus) mode detection counting line numbers (PAL, NTSC, readable bus) Embedded memory Mbit embedded DRAM core field memories Mbit embedded DRAM core line memories, vector memory, block-to-line
Micronas
SDA9410
Preliminary Data Sheet
Features converter kbit SRAM block matching, line-to-block converter Flexible clock synchronization concept Decoupling input output clock system possible Scan rate conversion Motion compensated 100/120 interlaced scan conversion (Micronas VDU) Motion compensated 50/60 progressive scan conversion (Micronas VDU) Simple interlaced modes: ABAB, AABB, AAAA, BBBB Simple progressive modes: AA*, True Motion: motion resolution even film sources motion resolution even NTSC film sources Large area line flicker reduction Flexible digital vertical expansion output signal (1.0, [1/64] 2.0) Sharpness improvement Digital colour transition improvement (DCTI) Digital luminance transition improvement (DLTI) Peaking (luminance only) Flexible output sync controller Flexible positioning output channels application modes Flexible height width output pictures Flexible programming output sync raster Signal manipulations Still frame field Insertion coloured background Insertion selection border Adjustable delay between signal (+4,.[1].,-3 input pixels) input side Adjustable delay between signal (+3,.[0.5].,- output pixels) output side Three converters amplitude resolution -(R-Y), -(B-Y) output maximal clock frequency Two-fold oversampling Simplification external analog post filtering differential analog outputs control (400 kHz) P-MQFP-100 package supply voltage
Micronas
SDA9410
Preliminary Data Sheet
Block diagram
Block diagram
TEST HINM VINM SYNCENM ISCM Input sync controller Master
Letter detection
Line memory
RESET
X1/CLKD
Vector memory
motion estimation
clock doubling PLLD
CLKOUT OSCM/S Output sync controller Master INTERLACED HOUT VOUT BLANK
CLKM
clock doubling PLLM
YINM UVINM
IFCM Input format conversion
VHCOMM Vertical horizontal compression/ expansion
TSNR Temporal, spatial noise reduction
YINS UVINS
IFCS Input format conversion
VHCOMS Vertical horizontal compression/ expansion
eDRAM Buffer Voltage control Testcontroller
Line memory
SRCM Scan rate conversion Master Vertical expansion SRCS
DLTI DCTI Peaking
4:4:4 8:8:8 Framing Delay
CLKS
clock doubling PLLS
Line memory
Figure
Block diagram
9410 contains blocks, which will briefly described below: ISCM/S Flexible input sync controller IFCM/S Input format conversion, Adjustable delay VHCOMM/S Vertical horizontal compression, horizontal expansion, panorama mode (only TSNR Temporal spatial noise reduction, noise measurement Letter detection Motion estimation, Film mode phase detection Memory controller OSCM/S Flexible output sync controller Output format conversion, 4:4:4, 8:8:8 interpolation, Adjustable delay SRCM/S Scan rate conversion, vertical expansion Combination output channels DLTI/DCTI/Peaking Luminance chrominance transition improvement, luminance peaking interface PLLM/S/D frequency doubling Line memory core, Vector memory core eDRAM core
Micronas
bd9410
HINS VINS SYNCENS
ISCS Input sync controller Slave
Memory Controller
SDA9410
Preliminary Data Sheet
Block diagram
INPUT PROCESSING MASTER MOTION ESTIMATION FILM MODE DETECTION
OUTPUT PROCESSING MASTER
YINM UVINM
VERTICAL HORIZONTAL COMPRESSION/ HORIZONTAL EXPANSION VERT. PEAKING
SPATIO TEMPORAL NOISE REDUCTION
eDRAM VECTOR MEMORY
LINE BLOCK CONVERSION
DISPLAY PROCESSING SCAN RATE CONVERSION VERTICAL ZOOM BLOCK LINE CONVERSION DLTI DCTI PEAKING 8:8:8 INTERPOLATION TRIPLE
INPUT PROCESSING SLAVE VERTICAL HORIZONTAL COMPRESSION/ HORIZONTAL EXPANSION VERT. PEAKING
LETTER DETECTION
eDRAM MAIN MEMORY
OUTPUT PROCESSING SLAVE
YINS UVINS
SCAN RATE CONVERSION
HINM VINM HINS VINS
INPUT SYNC CONTROLLER
MEMORY CONTROLLER
OUTPUT SYNC CONTROLLER
HOUT VOUT BLANK
Figure
Block diagram
Micronas
SDA9410
Preliminary Data Sheet
Description
Description
Diagram: P-MQFP-100 (top view)
RESET TEST IUQ_O IU_O VDDU IYQ_O IY_O VDDY IVQ_O IV_O VDDV VSSA4 RREF_I UREF_I VDDA5 VSSA5 VDDA1 VSSA1 VDDP7 VSSP8
VDDP1 VSSP1 VINS HINS SYNCENS VSSL4 VDDL4 YINS7 YINS6 YINS5 VSSP2 VDDP2 VDDL1 VSSE1 VDDE1 YINS4 YINS3 YINS2 YINS1 YINS0 VDDA2 VSSA2 CLKS VSSP3 UVINS7 UVINS6 VDDP3 UVINS5 UVINS4 UVINS3
DAEDALUS 9410
UVINS2 UVINS1 UVINS0 YINM7 YINM6 YINM5 YINM4 VSSP4 YINM3 YINM2 YINM1 YINM0 UVINM7 UVINM6 VDDP4 UVINM5 UVINM4 UVINM3 UVINM2 UVINM1
X1/CLKD CLKOUT HOUT VOUT
Figure
configuration
INTERLACED
BLANK VSSL3 VDDL3 VSSP7 VDDP6 VDDL2 VSSL2 VDDE2 VSSL9 VSSL8 VSSP6 CLKM VSSA3 VDDA3 VDDP5 VSSL7 VSSL6 VINM HINM SYNCENM VSSP5 UVINM0
Micronas
SDA9410
Preliminary Data Sheet
Description Table Symbol
VSSLx VDDLx VSSPx
definitions functions Num.
8,13,15,16, 22,23,75 9,12, 68,74
Input Outp.
Function
Supply voltage digital logic parts Supply voltage digital logic parts Supply voltage pads
10,17,29,43, 11,21,36,54, 80,99 14,66
VDDPx VSSE1 VDDEx VSSAx VDDAx YINM UVINM YINS UVINS RESET
Supply voltage pads Supply voltage embedded DRAM Supply voltage embedded DRAM Supply voltage analog analog parts Supply voltage analog analog parts Data input master channel
19,59,92,96, 20,60, 95,97 39,.,42; 44,.,47 30,.,35; 61,.,65; 71,.,73 48,.,53; 55;56 I/TTL
I/TTL Data input master channel I/TTL Data input slave channel I/TTL Data input slave channel I/TTL System reset. RESET input active. order ensure correct operation "Power Reset" must performed. RESET pulse must have minimum duration clock periods master (CLKM) slave clock (CLKS), respectively. H-Sync input master channel V-Sync input master channel Synchronization enable input master channel H-Sync input slave channel V-Sync input slave channel Synchronization enable input slave channel I2C-Bus data line I2C-Bus clock line Blanking signal V-Sync output H-Sync output
HINM VINM SYNCENM HINS VINS SYNCENS BLANK VOUT HOUT
I/TTL I/TTL I/TTL I/TTL I/TTL I/TTL O/TTL O/TTL O/TTL
Micronas
SDA9410
Preliminary Data Sheet
Description Table Symbol definitions functions (continued) Num.
Input Outp.
O/TTL I/TTL I/TTL I/TTL O/ANA O/TTL I/TTL O/ANA O/ANA O/ANA O/ANA O/ANA O/ANA I/ANA
Function
Interlace signal coupled vertical deflection System clock master channel System clock slave channel Crystal connection System clock display channel Crystal connection System clock output Test input, connect normal operation Analog luminance output Differential analog output, connect normal operation Supply voltage analog parts Analog luminance output Differential analog output, connect normal operation Supply voltage analog parts Analog luminance output Differential analog output, connect normal operation Supply voltage analog parts Analog reference voltage DACs Reference resistor DACs
INTERLACED CLKM CLKS CLKD CLK-OUT TEST IY_O IYQ_O VDDY IU_O IUQ_O VDDU IV_O IVQ_O VDDV UREF_I RREF_I
supply, input, output, TTL: digital (TTL) ANA: analog pull down (switched depending parameter FORMATM, FORMATS SLAVECON) placeholder number
Micronas
SDA9410
Preliminary Data Sheet
Introduction
System description
Introduction
9410 first single-chip Micronas MEGAVISION feature including scan rate conversion necessary field memories, second input channel split screen applications like picture-and-picture digital-to-analog converters. 9410 three application modes: (Scan Rate Conversion) mode, (Split SCreen) mode (MUlti Picture) mode. input channels 9410 equivalent. input channel always called "master" channel input channel always called "slave" channel. Both channels combined output side 9410 "MUX" block. master channel always "synchronization" master both channels. mode 9410 used high performance scan rate converter. Scan rate conversion done motion compensated algorithm known Micronas (Vector Driven conversion). addition high resolution frame based joint-linefree picture-and-picture (maximum approximately picture) displayed. figure below shows example mode.
Figure
Principles mode
Micronas
SDA9410
Preliminary Data Sheet
Introduction this usage Mbit eDRAM core separated luminance fields chrominance fields (either 4:2:0 4:1:1) memory area luminance chrominance fields (4:1:1) [maximum circa picture] picture-in-picture applications. vector based scan rate conversion possible master channel only. mode Mbit eDRAM core split Mbit areas, which able contain maximum luminance fields chrominance fields (either 4:2:0 4:1:1). figure below shows different applications ("Double window", "Zoom-in-zoomout"). this case only simple scan rate conversion (e.g. field doubling interlaced conversion: AABB) both output channels possible.
Figure
Principles mode
Micronas
SDA9410
Preliminary Data Sheet
Introduction mode allows combination life picture configuration still pictures. figure below shows application. this case only simple scan rate conversion (e.g. field doubling interlaced conversion: AABB AAAA) possible.
Figure
Principles mode
behaviour master slave channel does differ general. Therefore further description master slave channel figures also valid both unless pointed out.
Micronas
SDA9410
Preliminary Data Sheet
Input sync controller (ISCM/ISCS)
Input sync controller (ISCM/ISCS)
Signals HINM VINM SYNCENM HINS VINS SYNCENS
number
Description horizontal synchronization signal (polarity programmable, parameter HINPOLM, default: high active) vertical synchronization signal (polarity programmable, parameter VINPOLM, default: high active) enable signal HINM VINM signal, active ("Input format conversion (IFCM/IFCS)" page horizontal synchronization signal (polarity programmable, parameter HINPOLS, default: high active) vertical synchronization signal (polarity programmable, parameter VINPOLS, default: high active) enable signal HINS VINS signal, active ("Input format conversion (IFCM/IFCS)" page
Table
Input signals
input sync controller derives framing signals from V-Sync input data processing. framing signals depend different parameters mark active picture area.
HINM pixels line VINM lines field
NALIPM
(ALPFIPM*2)
(APPLIPM*8)*CLKM (NAPIPDLM*4 NAPIPPHM+PD)* CLKM Processing Delay
Figure
Input parameter
distance between incoming H-syncs system clocks CLKM/CLKS must even.
Micronas
inpar01
SDA9410
Preliminary Data Sheet
Input sync controller (ISCM/ISCS)
parameter [Default value] NALIPM [20] NALIPS [20] ALPFIPM [144] ALPFIPS [144] NAPLIPM NAPIPDLM NAPIPPHM NAPLIPS NAPIPDLS NAPIPPHS APPLIPM [180] APPLIPS [180]
address 03h,
Description Active Line InPut Master defines number lines from V-Sync first active line field Active Line InPut Slave defines number lines from V-Sync first active line field Active Lines Field InPut Master defines number active lines Active Lines Field InPut Slave defines number active lines Active Pixels Line InPut Master defines number pixels from H-Sync first active pixel line. number pixels combination NAPIPDLM NAPIPPHM. Active Pixels Line InPut defines number pixels from H-Sync first active pixel line. number pixels combination NAPIPDLS NAPIPPHS.
2Dh,
Active Pixels Line InPut Master defines number active pixels Active Pixels Line InPut Slave defines number active pixels
Table
Input write parameter
Inside 9410 field detection block necessary detection even field. Therefore incoming H-Sync (delayed HINM/HINS signal, delay depends NAPIPDLM/NAPIPDLS NAPIPPHM/NAPIPPHS) doubled signal). Depending phase position rising edge VINM/VINS signal (rising edge between (rising edge between field detected. proper operation field detection block, VINM/VINS must delayed depending delay HINM/HINS signal (H1). figure below explains field detection process functionality VINDELM/VINDELS parameter (inside 9410 delayed VINM/VINS signal called detected field signal called Ffd).
Micronas
SDA9410
Preliminary Data Sheet
Input sync controller (ISCM/ISCS)
CLKM VINM
(VINDELM Tclkm Field 1(A)
VINM
(VINDELM Tclkm Field 2(B)
Figure
Field detection VINM delay
parameter [Default value] VINDELM VINDELS FIEINVM Field [0]: Field FIEINVS Field [0]: Field VCRMODEM [1]: VCRMODES [1]:
address
Description Delay incoming V-Sync VINM (must adjusted depending delay HINM signal) Delay incoming V-Sync VINS (must adjusted depending delay HINS signal) Inversion internal field polarity master
Inversion internal field polarity slave
case standard interlaced signals (VCR, PlayStations) filtering internal field signal done (should also used normal signals) case standard interlaced signals (VCR, PlayStations) filtering internal field signal done (should also used normal signals)
Table
Input write parameter
case non-standard signals field order indeterminate (e.g. AAA. BBB. AAABAAAB., etc.). Therefore special filtering algorithm implemented, which switched parameter VCRMODEM/VCRMODES. recommended parameter VCRMODEM=1. other case (VCRMODEM=0) additional
Micronas
SDA9410
Preliminary Data Sheet
Input sync controller (ISCM/ISCS) internal signal VTSEQM generated. This signal level high (VTSEQM=1), least last fields were identical. fixed storage places fields internal memory block, this information necessary scan rate conversion processing ("Output sync controller (OSCM/S)" page recommended case VCRMODEM=0 choose adaptive operation mode). OPDELM parameter used adjust outgoing V-Sync VOUT relation incoming delayed V-Sync VINM. case mode recommended default value should changed.
parameter [Default value] OPDELM [170]
address
Description Delay number lines) internal V-Sync (delayed VINM) outgoing V-Sync (VOUT)
Table
Input write parameter
internal line counter used determine information about standard incoming signal.
parameter TVMODEM
address
Description standard incoming signal master: NTSC standard incoming signal slave: NTSC
TVMODES
Table
Input read parameter
Micronas
SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS)
Input format conversion (IFCM/IFCS)
Signals YINM0.7 UVINM0.7 YINS0.7 UVINS0.7
number 39,40,41,42,44,45,46,47 30,31,32,33,34,35,37.38 61,62,63,64,65,71,72,73 48,49,50,51,52,53,55,56
Description luminance input master chrominance input master luminance input slave chrominance input slave
Table
Input signals
9410 accepts input side sample frequency relations (B-Y) (R-Y): 4:2:2 CCIR 656.
Data
CCIR FORMA= FORMA=
4:2:2 Parallel FORMA=
YINM7 YINM6 YINM5 YINM4 YINM3 YINM2 YINM1 YINM0 UVINM7 UVINM6 UVINM5 UVINM4 UVINM3 UVINM2 UVINM1 UVINM0
Table
Input data formats
Xab: signal component sample number number
Micronas
SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS) case CCIR three modes supported (FORMATM/FORMATS=11 means full CCIR support, including V-Sync Field signal, FORMATM/FORMATS=01 means only data processing, V-Sync have added separately according PAL/NTSC norm, FORMATM/FORMATS=10 means only data processing, Vsync have added separately according CCIR656-PAL/NTSC norm). representation samples chrominance signal programmable positive dual code (unsigned, parameter TWOINM/TWOINS=0) two's complement code (TWOINM/TWOINS=1, Bus" page 117, parameter 0Bh,2Dh). Inside 9410 algorithms assume positive dual code.
FORMATM/ FORMATS (CCIR only data) (full CCIR 656)
HINS/HINS PAL/NTSC PAL/NTSC CCIR
VINM/VINS PAL/NTSC PAL/NTSC CCIR
YINM/YINS 4:2:2 CCIR CCIR CCIR
UVINM/UVINS 4:2:2
Table
Input sync formats
amplitude resolution each input signal component bit, maximum clock frequency MHz. Consequently 9410 dedicated application high quality digital video systems.
Micronas
SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS) Figure shows generation internal V-syncs case full CCIR mode. H656 sync generated after EAV. V656 F656 signals change synchronously with timing reference code.
CLK1 MHz) CCIR interface
Tclk1(PAL) Tclk1(NTSC) 1728 Tclk1(PAL) 1716 Tclk1(NTSC)
CLK1 MHz) H656 V656 (e.g.) F656 (e.g.)
11111111 00000000 00000000 1FV1P3P2P1P0
during field 1(A) during field 2(B)
11111111 00000000 00000000 1FV0P3P2P1P0
elsewhere during field blanking
Figure
Explanation format
Figure explains functionality SYNCENM/SYNCENS signal. 9410 needs SYNCENM/SYNCENS (synchronization enable) signal, which used gate YINM/YINS, UVINM/UVINS well HINM/HINS VINM/VINS signal. This implemented frontends which working with 13.5 large output delay time YINM/YINS, UVINM/UVINS, HINM/HINS VINM/VINS (e.g. Micronas VPC32XX, output delay: ns). this application half system clock CLKM/CLKS (13.5 MHz) from frontend should provided this pin. case frontend working 27.0 with sync signals having delay times smaller than this input level (SYNCENM/SYNCENS=VSS) (e.g. Micronas 9206, output delay: ns). Thus signals YINM/YINS, UVINM/UVINS, HINM/HINS VINM/VINS sampled with CLKM/CLKS system clock when SYNCENM/ SYNCENS input low. Figure shows gated inputs signals YINMen, UVINMen, HINMen VINMen.
Micronas
SDA9410
Preliminary Data Sheet
Input format conversion (IFCM/IFCS)
CLKM SYNCENM YINM UVINM YINMen UVINMen HINM/VINM HINMen/VINMen
Figure
SYNCENM/SYNCENS signal
Figure shows input timing functionality NAPIPDLM/NAPIPDLS NAPIPPHM/NAPIPPHS parameter case CCIR 4:2:2 parallel data input format example. signals HINMint, YINMint UVMint internal available sampled input signals.
CLKM HINM HINMint CCIR interface YINM
(NAPIPDLM* NAPIPPHM Tclkm Tclkm Tclkm (e.g.) YINMint UVINMint 4:2:2 interface YINM UVINM YINMint UVINMint
(NAPIPDLM* NAPIPPHM Tclkm Tclkm Tclkm (e.g.)
Figure
Input timing
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
Input signal processing
Figure shows detailed block diagram input processing blocks. input signal vertically horizontally compressed horizontally expanded large number factors. Furthermore input signal processed different noise reduction algorithms reduce noise signal. noise measurement block determines noise level input signal. letter detection block finds start line letter pictures. information used calculate zooming factors control resizing picture full screen display 16:9 tubes.
NMLINE, NMALG NOISEME MASTER
Letter detection Noise measurement
SNRON
NRON
DELM YINM UVINM
Delay -3/+4 Line memories
Vertical horizontal compression/ expansion
from Memory
Spatial noise reduction Temporal noise reduction
Memory Memory from Memory bdldr01 Memory Memory
SLAVE YINS UVINS
Delay -3/+4 Line memories
Vertical horizontal compression/ expansion
DELS
Figure
Block diagram input processing blocks
different blocks corresponding parameters will described more detail.
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.1
Adjustable delay
possible adjust luminance signal relation chrominance signal (CLKM/CLKS) steps. further processing important, that luminance signal chrominance signal adjusted. Adjustment necessary, luminance chrominance signal generated frontend processor adjusted.
DELM/DELS (04h,026h)
Delay between luminance chrominance data steps 27.0 (CLKM/CLKS)
Table
DELM/DELS parameter
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.2
Vertical horizontal compression (VHCOMM/VHCOMS)
Figure shows block diagram VHCOMM VHCOMS block. VHCOMM VHCOMS block able compress picture horizontal vertical direction continuously. minimal step size vertical direction lines, minimal step size horizontal direction four pixels. figure below shows also functionality formula, which shows relation between number input lines (pixels) output lines (pixels). horizontal direction expansion also possible. Panorama mode horizontal direction will supported.
INTVM, INTVS, DEZVM, DEZVS, CHFILM, CHFILS
Vertical compression
YPEAKM, CPEAKM, YPEAKS, CPEAKS
Vertical peaking
INTHM, INTHS, DEZHM, DEZHS
Horizontal compression/ expansion
vhcombd
YUVIN
YUVOUT
4*APPLIPM 4*APPLIPS pixels (CLKM/2)
4*APPLIPM 4*APPLIPS pixels (CLKM/2)
4*APPLM 4*APPLS pixels (CLKM/2)
2*ALPFIPM, 2*ALPFIPS lines
2*ALPFM 2*ALPFS lines
Number output lines (Number input lines) (512+INTVM) 1/(DEZVM)
INTVM 511; DEZVM INTHM 2048, 8191; DEZHM
Number output lines (Number input lines) 2048 (INTHM) 1/(DEZHM)
Figure
Block diagram VHCOMM/VHCOMS
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.2.1
Vertical compression peaking
overall reduction vertical compression block calculated formula:
INTVM DEZVM
user must specify vertical input picture size (defined parameter ALPFIPM/ALPFIPS) vertical output picture size (defined parameter APPLM/APPLS) well parameter INTVM/INTVS parameter, 09h,0Ah,2Bh,2Ch) DEZVM/DEZVS parameter, 0Ah,2Ch), which calculated with algorithm listed below (C-code). intV, dezV: variables for( intV=2*ALPFM/S, dezV=1; intV<=2*ALPFIPM/S; intV*=2, dezV*=2 intV dezV/=2; if(dezV>16) intV=intV*dezV/16; dezV=16; INTVM/S=intV-512;
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
Vertical line size 2*ALPFM/S (2*ALPFIPM/S=288)
INTVM/S
dezV/DEZVM/S
Comment
largest size, bypass recommended DEZVM/ DEZVS=0
16/7 16/7 smallest size (1/3 picture) Double window
Table
Examples vertical filter adjustment
dezV
DEZVM DEZVS
Table
Conversion table between dezV DEZVM DEZVS
vertical compression block switched setting DEZVM/DEZVS equal INTVM/INTVS=0. this case possible switch pass filter chrominance data path parameter CHFILM/CHFILS parameter, 03h, 25h). CHFILM/CHFILS equal vertical filter chrominance switched off. CHFILM/CHFILS equal vertical filter chrominance switched (Table "Input write parameter CHFILM/ CHFILS" page 38). addition vertical peaking input signal possible.
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
parameter YPEAKM/YPEAKS CPEAKM/CPEAKS
(minimum value) peaking peaking
(maximum value) maximum peaking factor maximum peaking factor
Table
Input write parameter YPEAKM/YPEAKS/CPEAKM/CPEAKS
parameter INTVM DEZVM INTVS DEZVS YPEAKM CPEAKM YPEAKS CPEAKS ALPFM ALPFS CHFILM CHFILS
address 09h,0Ah 2Bh,2Ch
Description Interpolation factor vertical compression master Decimation factor vertical compression master Interpolation factor vertical compression slave Decimation factor vertical compression master Vertical peaking factor luminance signal master Vertical peaking factor chrominance signal master Vertical peaking factor luminance signal slave Vertical peaking factor chrominance signal slave Number active lines field after vertical compression master Number active lines field after vertical compression slave Chrominance filter master channel on/off Chrominance filter slave channel on/off
Table
Input write parameter
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.2.2
Horizontal compression/expansion panorama mode
overall reduction horizontal compression block calculated formula:
2048 -INTHM DEZHM
user must specify horizontal input picture size (defined parameter APPLIPM/APPLIPS) horizontal output picture size (defined parameter APPLM/APPLS) well parameter INTHM/INTHS parameter, 07h, 08h, 29h, 2Ah) DEZHM/DEZHS parameter, 08h, 2Ah), which calculated with algorithm listed below (C-code). intV, dezV: variables for( intH=4*APPLM/S, dezH=1; intH<=4*APPLIPM/S; intH*=2, dezH*=2 intH dezH>16) intH= intH*dezH/16; dezH=16; INTHM/S intH
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
Horizontal pixel size (related CLKM/2) 4*APPLM (4*APPLIPM=720) 1440
intH
dezH/ DEZHM/S
Comment
2048 4073 2048 2731 4050 2048 4007 2048 4007 2048 3840 7680
16/7 16/7 16/7
largest size, only will stored largest size, only will stored bypass recommended DEZHM/DEZHS=0 picture 16:9 tube
Double window
smallest size
Table
Examples horizontal filter adjustment
dezH
DEZHM/S
Table
Conversion table between dezH DEZHM/DEZMS
horizontal compression/expansion block switched setting DEZHM/ DEZHS equal INTHM/INTHS=2048. this case possible switch pass filter chrominance data path parameter CHFILM/CHFILS parameter, 03h,25h). CHFILM/CHFILS equal horizontal filter chrominance switched off. CHFILM/CHFILS equal horizontal filter chrominance switched table below shows different settings CHFILM/S.
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
CHFILM/CHFILMS
Vertical pass filter (only valid DEZVM/DEZVS=0) Vertical filter Vertical filter Vertical filter Vertical filter
Horizontal pass filter (only valid DEZHM/DEZHS=0) Horizontal filter Horizontal filter Horizontal filter Horizontal filter
Table
Input write parameter CHFILM/CHFILS
case panorama mode compression/expansion factor varies over line. figure below shows some examples.
Compression
PANAST+1
Expansion
Figure
Principles panorama mode
Different settings parameters INTHM/INTHS DEZHM/DEZHS necessary. table below defines settings:
PANAON
dezH DEZHM/DEZHS
intH INTHM INTHM (4096 recommended)
Table
Filter parameter case PANAON=1
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
parameter PANAST
(minimum value) slight panorama
(maximum value) strong panorama
Table
parameter PANAST case PANAON=1
parameter INTHM DEZHM INTHS DEZHS APPLM
address 07h,08h 29h,2Ah
Description Interpolation factor horizontal compression/expansion master Decimation factor horizontal compression/ expansion master Interpolation factor horizontal compression/expansion slave Decimation factor horizontal compression/ expansion slave Number active pixels line input data stream after horizontal compression/ expansion master Number active pixels line input data stream after horizontal compression/ expansion slave Horizontal panorama mode on/off Gradient horizontal panorama mode
APPLS
PANAON PANAST
Table
Input write parameter
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.3
Noise reduction
figure below shows block diagram spatial temporal motion adaptive noise reduction (first order filter). spatial noise reduction only performed luminance signal. structure temporal motion adaptive noise reduction same luminance chrominance signal.
SNRON
TNRCLY, TNRHOY, TNRKOY, TNRVAY, TNRFIY, NRON TNRCLC, TNRHOC, TNRKOC, TNRVAC, TNRFIC, NRON UVIN UVSNR Spatial noise reduction YSNR Motion detector Frame delay Field delay DTNRON YOUT UVOUT Motion detector Field delay Frame delay TNRSEL DTNRON nr01
Figure
Block diagram noise reduction
5.4.3.1
Spatial noise reduction
Normally spatial noise reduction reduces resolution pass characteristic used filter. Therefore spatial noise reduction 9410 works adaptive picture content. filter process only executed homogeneous area.
parameter SNRON
address
Description Spatial noise reduction luminance signal
Table
Input write parameter
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
5.4.3.2
Motion adaptive temporal noise reduction
equation below describes behaviour temporal motion adaptive noise reduction filter. same equation valid chrominance signal. Depending motion input signal, K-factor (Kuv) adjusted between motion) (motion) motion detector. K-factor chrominance filter either (output luminance motion detector, TNRSEL=0) (output chrominance motion detector, TNRSEL=1). luminance chrominance signal delay feed back path either field delay (DTNRON=1) frame delay (DTNRON=0) (block diagram noise reduction).
Equation temporal noise reduction (luminance signal)
YOUT YSNR
Equation temporal noise reduction (chrominance signal)
UVOUT UVSNR ;Kuv
(compare "Block diagram noise reduction" page Figure shows motion detector more detail. Temporal noise reduction switched NRON (NRON=0). parameter TNRFIY/C switches between fixed noise reduction K-factor TNRVAY/C (TNRFIY/C=0) motion adaptive noise reduction K-factor (TNRFIY/C=1).
TNRCLY/C+1 TNRKOY/C+1 TNRFIY/C NRON
Motion DY/UV Motion detection
Ky/uv nr01
TNRHOY/C TNRVAY/C
Figure
Block diagram motion detector
case adaptive noise reduction K-factor depends detected "Motion" (see Figure 16). "Motion"-Ky/Kuv characteristic curve (LUT) fixed inside 9410, characteristic curve changed parameters: TNRHOY/ TNRKOY/C. TNRHOY/C shifts curve horizontally TNRKOY/C shifts
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing curve vertically. fixed characteristic curve, sensitivity motion detector adjustable TNRCLY/C.
TNRKOY/C=7 TNRHOY/C=0 TNRKOY/C=-1 TNRHOY/C=0 TNRKOY/C
Ky/Kuv
TNRKOY/C=-8 TNRHOY/C=0
Motion
Ky/Kuv
TNRKOY/C=-1 TNRHOY/C=15 TNRKOY/C=-1 TNRHOY/C=0
TNRHOY/C TNRKOY/C=-1 TNRHOY/C=-15
Motion
Figure
motion detection
nr03
Micronas
nr02
SDA9410
Preliminary Data Sheet
Input signal processing
parameter TNRVAY/C
(minimum value) strong noise reduction (not motion adaptive, Ky/Kuv=0)
(maximum value) noise reduction (not motion adaptive, Ky/Kuv=15)
Table
parameter TNRVAY/C
parameter TNRHOY/C TNRKOY/C
Range -32,
Table
parameter TNRHOY/C TNRKOY/C
parameter TNRCLY/C
(minimum value) maximum sensitivity motion strong noise reduction
(maximum value) minimum sensitivity motion weak noise reduction
Table
parameter TNRCLY
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
parameter NRON TNRSEL separate luminance motion detector DTNRON field frame TNRFIY/C TNRVAY/C TNRHOY/C TNRKOY/C TNRCLY/C
address
Description Temporal Noise Reduction Luminance Chrominance (SRC-Mode) Switch motion detection temporal noise reduction chrominance signal
Delay temporal noise reduction luminance chrominance signal Switch fixed K-factor value defined TNRVAY/C
18h/19h
18h/19h
Fixed K-factor temporal noise reduction luminance/chrominance Horizontal shift motion detector characteristic Vertical shift motion detector characteristic Classification temporal noise reduction
Table
Input write parameter
5.4.4
Noise measurement
noise measurement algorithm used change parameters temporal noise reduction processing depending actual noise level input signal. This done controller which reads NOISEME value, sends depending this value different parameter sets temporal noise reduction registers 9410. NOISEME value interpreted linear curve from noise strong noise (30). Value indicates overflow status handled different ways: strong noise measurement failed. measurement algorithms included, which chosen parameter NMALG. case NMALG=1 noise measured during vertical blanking period line defined NMLINE. NMALG=0 noise measured during first active line. latter case delay noise reduction algorithm must frame difference value (DTNRON=0, address 1Ah). both cases value determined averaging over several fields. Figure shows example noise measurement. NMLINE parameter determines line, which used 9410 measurement. case VINDEL=0 NMLINE=0 line field line field
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing chosen. case VINDEL=0 NMLINE=3 line field line field chosen.
Field1
H-sync V-sync
VINDEL=0 Measure NMLINE=0 NMLINE=3
Measure
H-sync V-sync
Field2 313-1
314-2
315-3
316-4
317-5
318-6
319-7
VINDEL=0 Measure NMLINE=0 NMLINE=3
Measure
Figure
Example noise measurement
parameter NMALG
address
Description Noise measurement algorithm measurement during vertical blanking period (measure line defined NMLINE) measurement first active line Line noise measurement (only valid NMALG=1)
NMLINE
Table
Input write parameter
Micronas
NM01
SDA9410
Preliminary Data Sheet
Input signal processing
parameter NOISEME NMSTATUS
address
Description Noise level input signal: noise), (strong noise) (strong noise measurement failed)] Signals value NOISEME value read current noise measurement been updated (compare chapter page 117)
Table
Input read parameter
5.4.5
Letter detection
Figure shows display letter source 16:9 tube. Black bars bottom well right left visible. possible vertical horizontal expansion display picture whole tube. Therefore only first line (Start Line Active Area SLAA) last line (End Line Active Area ELAA) active area must known. letter detection algorithm detects SLAA ELAA. Both parameters read Bus. chassis both values calculate corresponding zoom factor vertical expansion.
SLAA Vertical horizontal expansion ELAA
Figure
Principle letter detection
Figure shows block diagram letter detection. letter algorithm processes only luminance data. Each incoming field processed. default value SLAA NALPFIPM+PD ELAA 2*ALPFIPM+NALPFIPM+PD-1 Processing Delay), which means letter format source material.
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
TH_AA TH_LB
SLAA TH_DN_BN Line Type Decision Processing Start/Endline Decision Status_SLAA ELAA Status_ELAA Reliability Evaluation
lbdbd
YINM
Histogram
RELY
TH_MUNSL, TH_AUNS TH_ALB, TH_MA_AA
Figure
Block diagram letter detection
Each line input picture will assigned three line types (LT) "Histogram" "Line Type decision" block. figure below shows detail functionality both blocks. "Histogram" block counts amount pixels (BC), which larger equal 2*TH_DN_BN parameter, 1Ch). Depending counter value line assigned three line types "Line Type Decision" block. parameter TH_AA TH_LB used influence result "Line Type Decision" block.
Line Type (LT)
Priority
TH_AA TH_LB TH_AA TH_LB
Table
Line Type Decision
line type marks lines which belong active area, line type marks lines which belong letter area (maybe including logos, subtitles) line type marks lines which could assigned with security both line types mentioned before.
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
Histogram
Pixel Value TH_DN_BN Amount Pixels 2*TH_DN_BN
APPLIPM*4
Line Type Decision
TH_AA
line
lbdHLD
TH_LB
TH_DN_BN parameter)
Figure
Histogram line type decision
Based line types first line active area (SLAA, parameter 78h) last line active area (ELAA, parameter 79h) determined. Furthermore information about reliability SLAA ELAA value determined. reliability information readable parameters STATUS_SLAA STATUS_ELAA. STATUS_SLAA/STATUS_ELAA equal SLAA/ELAA value reliable, otherwise SLAA/ELAA value reliable. addition global reliability signal RELY exists, which also readable Bus. results letter detection reliable, RELY signal read "1". "Reliability evaluation" block determines RELY signal, which influenced parameter TH_MUNSL, TH_AUNS TH_ALB. table below explains generation RELY signal. thresholds TH_MUNSL, TH_AUNS TH_ALB compared with internal counter values UNSLENGTH, UNSAMOUNT LBAMOUNT, respectively. three conditions true, RELY signal reliable. UNSLENGTH contains maximum length consecutive lines with line type UNS. UNSAMOUNT contains amount lines with line type LBAMOUNT contains amount lines with line type
RELY (not reliable) (reliable) UNSLENGTH TH_MUNSL UNSAMOUNT TH_AUNS LBAMOUNT *TH_ALB otherwise
Table
Evaluation reliability signal RELY
parameter TH_MA_AA used force SLAA ELAA value their default values. Therefore amount active area line types counted
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing upper half input picture (AAFH) lower half input picture (AASH). both counter values greater 2*TH_MA_AA 112, SLAA ELAA parameters their default values.
Output signals SLAA=NALPIPM+PD ELAA=2*ALPFIPM+SLAA-1 Status_SLAA=TRUE Status_ELAA=TRUE change values (AAFH AASH) TH_MA_AA
otherwise
Table
Correction "start/end-line decision filter" block
possible make results letter detection visible screen real time optimize parameters. figure below explains different possibilities. parameter VOLBD used switch (VOLBD=1) (VOLBD=0) visibility function.
PANATV
SLAA, Status_SLAA=FALSE RELY=FALSE
PANATV
SLAA, Status_SLAA=TRUE RELY=FALSE
this letter
ELAA, Status_ELAA=FALSE
this letter
ELAA, Status_ELAA=TRUE
PANATV
SLAA, Status_SLAA=FALSE RELY=TRUE
PANATV
SLAA, Status_SLAA=TRUE RELY=TRUE
this letter
Figure
Visibility letter detection parameters
lbdvis
ELAA, Status_ELAA=FALSE
this letter
ELAA, Status_ELAA=TRUE
Micronas
SDA9410
Preliminary Data Sheet
Input signal processing
parameter [default] TH_DN_BN [15] TH_LB [12] TH_ALB TH_AA [50] TH_MUNSL TH_AUNS TH_MA_AA [14] VOLBD
address
Description
1Ch,1Dh
Darkness Brightness threshold Letter threshold Amount letter threshold Active area threshold Maximum length insecure threshold Amount letter insecure threshold Maximum amount active area threshold Makes result letter detection visible screen
Table
parameter SLAA ELAA
Input write parameter
address Description First line active area SLAA Last line active area ELAA Status SLAA SLAA reliable SLAA reliable Status SLAA ELAA reliable ELAA reliable Reliability signal: values letter detection reliable values letter detection reliable Signals values letter detection values read current letter detection measurement finalized (compare chapter page 117)
STATUS_SLAA
STATUS_ELAA
RELY
LBDSTATUS
Table
Input read parameter
Micronas
SDA9410
Preliminary Data Sheet
Clock concept
Clock concept
Signals CLKM CLKS X1/CLKD
number
Description System clock input master channel System clock input slave channel System clock input display channel
Table
Input signals
Signals CLKOUT
number
Description Clock output
Table
Output signals
9410 supports different clock concepts. Figure shows typical application 9410. frontend clock connected CLKM input. second frontend clock connected CLKS input. CLKOUT connected backend X1/CLKD input connected crystal oscillator. Figure explains clock switch, which used separate modes (see also Table "Ingenious configurations HOUT VOUT generator" page 80).
CLKS
PLLS
CLKS_pll clock3 CLKOUT
CLKM
PLLM
CLKM_pll
X1/CLKD
PLLD
CLKD_pll
CLKMDEN
Figure
Clock concept 9410
Micronas
SDA9410
Preliminary Data Sheet
Clock concept
CVBS Analog colour decoder 9206 ABACUS SYNC
YUVINM
HINM VINM CLKM
9380 9410 CVBS Analog colour decoder 9206 ABACUS SYNC YUVINS
DAEDALUS
VOUT
Deflection controller H-Drive processing
HINS
HOUT V-Drive
VINS CLKS
CLKOUT
Figure
Application 9410
CLKMDEN (5Fh)
PLLD input CLKM X1/CLKD
Clock CLKM_pll CLKS_pll CLKD_pll
Used block ISCM, IFCM, VHCOMM, TSNR, LBD, ISCS, IFCS, VHCOMS, OSCM/S, SRCM, SRCS, DLTI, DCTI, Peaking, DAC,
Table
Clock concept switching matrix
APPLIK01
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter PLLMOFF PLLMRA PLLSOFF PLLSRA PLLDOFF PLLDRA CLKOUTON enabled disabled CLKMDEN X1/CLKD CLKM
address
Description PLLM master channel off, only test purpose
PLLM range, only test purpose PLLS slave channel off, only test purpose
PLLS range PLLD display channel off, only test purpose
PLLD range Output system clock CLKOUT
Input clock PLLD
Table
Input write parameter
5.6.1
Application modes memory concept Introduction
Main Memory 9410 overall capacity Mbit. divided into identical independent Mbit parts. Main Memory completely independent data inputs (master slave channel) enable multitude features. general channels asynchronous having separate clock PLLs (CLKM, CLKS). Reading master slave data display performed using third asynchronous clock (CLKD). this decoupling input output clocks achieved. Main Memory supports different operation modes 9410 adapted data configurations. different modes defined parameter MEMOP address 53h).
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
MEMOP
Memory operation mode SRC-Mode (Sample Rate Conversion) SSC-Mode (Split screen) MUP-Mode (Multi picture) defined
Table
Definition MEMOP
operation mode capacity store fields luminance chrominance components master channel supplied (4:1:1 4:2:0 format, parameter CHRFORM/CHRFORS, 12h/34h).
CHRFORM
Data format 4:1:1 4:2:0 reserved
CHRFORS
Data format 4:1:1 4:2:0
Table
Definition CHRFORM/CHRFORS
Figure shows differences between 4:1:1, 4:2:2 4:2:0 data format.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
4:2:2 line
4:1:1
4:2:0
line
line
dataform
Figure
Supported data formats
Additionally fields decimated picture slave channel with size original format stored (4:1:1 4:2:0 format). this mode motion estimation compensation (Micronas algorithm) master channel supported clock frequency). parallel possible insert slave channel display position using frame mode without joint lines. Noise reduction algorithm recursive filtering supported only master channel SRC-Mode. SSC-Mode data configuration master slave channel different. Depending picture size possible store only field luminance chrominance data fields. data configuration defined parameters ORGMEMM ORGMEMS, respectively.
ORGMEMM
Data configuration memory fields (limited picture size SSC- MUP-Mode) field
Table
Definition ORGMEM
ORGMEMS
Data configuration memory fields (SRC-Mode), fields (restricted picture size, Mode) Slave channel blocked (SRC-Mode ORGMEMM=1) field (SSC- MUP-Mode; SRC-Mode ORGMEMM=0)
Table
Definition ORGMEMS
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept Having fields available master channel joint line free display activated. Storing fields both channels complete joint line free display possible. both cases suitable shift output raster phase necessary (especially 'Double Window' 'Split Screen' 'Picture Picture' 'Side Side'). mode field repetition (Simple 100Hz AABB; Field repetition AAAA BBBB) used interlaced scan (100/120 rate conversion, ABAB modes supported. progressive scan conversion also only field based algorithms possible (Simple 50Hz AA*, B*B; Field repetition AA*, B*B). definition different scan rate conversion algorithms compare "Operation mode generator" page Positioning pictures display done externally specifying start reading both channels. MUP-Mode configurations functions both channels programmable independently. fields master channel stored achieve joint line free display decimated live picture. Applying smaller decimation factors only field stored joint line free display possible more. These modes correspond configuration master channel, AABB mode supported. second channel both channels number decimated fields stored step step. horizontal positions pictures adjustable steps pixel, vertical positions also variable have step size lines. width height decimated picture depend corresponding decimation factors. maximum picture channel live. Only field repetition (AAAA, BBBB) supported this mode. Other display modes cause raster artefacts live pictures. Joint lines also removed live pictures. special MUP-Mode based memory configuration enables storing fields decimated still picture. fields calculated using only input field decimation. generated lines interpreted alternating B-lines. described method improves vertical resolution still pictures clearly without causing motion artefacts. limited memory capacity does allow fill complete display with decimated pictures created with described method using only channel. different configuration selected parameter VERRESM VERRESS, respectively.
VERRESM/VERRESS
Vertical resolution MUP-Mode (ORGMEMM/ORGMEMS=1 WRFLDM/WRFLDS=1) frame resolution field resolution
Table
Definition VERRESM/VERRESS
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
5.6.2
Configuration controlling
following Table Table summarize possible combinations memory data configurations master slave channel corresponding applications. main configurations motion compensated conversion insertion, joint line free Split Screen display high quality Multi Picture including live channel. Table shows possible picture sizes. data formats always 4:2:0 4:1:1. mode picture sizes influenced parameters MEMWRM MEMWRS.
Config.
MEMOP
ORGMEMM
ORGMEMS
Master Channel Fields
Slave Channel Fields
available
Table
Programmable data configurations
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
Config.
Mode
Application motion compensated conversion (4:1:1 4:2:0) (ABAB, frame based) motion compensated conversion with enlarged picture size, facility AABB conversion master slave channel, slave data written twice (PIPand SSC-configuration) used during switching from configuration configuration without artefacts independent synchronized full size channels, AABB conversion joint line free 'Double Window' 'Split Screen' 'PAP' display, AABB conversion display live channels, AABB conversion slave channel exceeds maximum double window size display live channels, AABB conversion master channel exceeds maximum double window size independent synchronized full size channels, AABB conversion high resolution Multi Picture master slave channel (one live picture possible) AABB conversion high resolution Multi Picture master channel, reduced resolution Multi Picture slave channel, AABB conversion reduced resolution Multi Picture master channel, high resolution Multi Picture slave channel, AABB conversion reduced resolution Multi Picture master slave channel, AABB conversion
Table
Applications different data configurations
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
Config.
Master Channel Size [Pixel Lines] MEMWRM=0 MEMWRM=1
Slave Channel Size [Pixel Lines] MEMWRS=0 available MEMWRS=1
Table
Maximum picture sizes
MEMWRS
Memory write mode slave channel max. pixel/line max. pixel/line
Table
Definition MEMWRS
MEMWRM
Memory write mode master channel (ORGMEM=01 Mode) max. pixel/line max. pixel/line
Table
Definition MEMWRM
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter [Default] CHRFORM CHRFORS ORGMEMM ORGMEMS MEMOP [00] VERRESM VERRESS MEMWRM MEMWRS
address
Description
Chrominance data format master channel Chrominance data format slave channel Data configuration memory master channel Data configuration memory slave channel Memory operation mode Vertical resolution master channel Vertical resolution slave channel Memory write mode master channel Memory write mode slave channel
Table
Input write parameter
5.6.3
mode configuration
Conditions:MEMOP=00, ORGMEMM=1, ORGMEMS=1 described data configuration typical normal mode with motion compensated ABAB conversion joint line free frame based insertion.
maximum picture size (master Channel) pixel lines
maximum picture size (slave channel) pixel lines
5.6.4
mode configuration
Conditions: MEMOP=01 ORGMEMM=1, ORGMEMS=1
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept This typical configuration needed joint line free 'Split Screen' 'Double Window' 'PAP' display 4:1:1 4:2:0 format using AABB conversion. same configuration used Multi Picture mode displaying joint line free live picture multiple high resolution still pictures.
maximum picture size (master slave) (768) pixel (170) lines MUP-Mode possible write only fields into memory. Therefore parameters WRFLDM WRFLDS used.
WRFLDM WRFLDS
Write field (MUP-Mode, MEMOP=10) only fields written fields written corresponding actual mode
Table
Definition WRFLDM/WRFLDS
parameter [Default] WRFLDM WRFLDS
address
Description
Write field master channel (MUP-Mode) Write field slave channel (MUP-Mode)
Table
Input write parameter
5.6.5
Configuration switch
This chapter deals with switching between different operation modes without causing visible picture artifacts. typical application concerns transition from SRC-PIP mode double window mode (see figure page figure page furthermore exchange master slave channel (see figure page 65).
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
ORGMEMM
Data configuration memory (Master Channel) mode, ORGMEMM=1: slave channel available mode, ORGMEMM=0, SSC- MUP-mode: field stored SRC-mode: fields stored SSC- MUP-mode: fields stored
Table
Definition ORGMEMM
ORGMEMS
Data configuration memory (Slave Channel) mode, ORGMEMM=1: slave channel available mode, ORGMEMM=0, SSC- MUP-mode: field stored SRC-mode: fields stored SSC- MUP-mode: fields stored
Table
Definition ORGMEMS
MEMRDM
Memory read mode master channel (SRC-Mode, MEMOP=00) Reading only field memory area AABB conversion Reading both field memory areas ABAB conversion
Table
Definition MEMRDM
MEMRDS
Memory read mode slave channel (SRC-Mode, MEMOP=00) Reading data PIP-configuration (joint line free, ABAB) Reading data SSC-configuration, decimated fields, AABB
Table
Definition MEMRDS
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
MEMWRM
Memory read mode master channel (only SSC- MUP-mode) pixel line pixel line
Table
Definition MEMWRM
MEMWRS
Memory read mode slave channel SRC-mode: writing data configuration SSC- MUP-mode: pixel line SRC-mode: writing data PIP- configuration SSC- MUP-mode: pixel line
Table
Definition MEMWRS
typical animated transition double window display divided into parts: changing operation mode from (figure page changing picture sizes positions continuously according double window display (figure page 64). mode vector driven conversion modes possible. Only field based algorithms supported. corresponding commands summarized Table Table
SRC-PIP Mode, ABAB (A+B)
SSC-Mode, AABB (A+B)
Figure
Switching from SRC-PIP mode mode
Micronas
JLC.vsd/10 SwMode1.WMF
SDA9410
Preliminary Data Sheet
Application modes memory concept
SSC-Mode, AABB (A+B): -master picure becomes smaller -slave picture becomes larger
SSC-Mode: Double Window, AABB (A+B)
Figure
Changing picture sizes double window display
Steps MEMOP
ORGMEMM
ORGMEMS
MEMWRM
MEMWRS
MEMRDS
MEMRDM
Operation mode with insertion field based conversion mode must programmed STOPMOM STOPMOS only field read master channel (reduced vertical resolution) memory capacity master channel reduced field memory organization slave channel prepared configuration slave channel reading switched memory configuration mode: full size master picture, size slave picture
Table
Switching from mode mode
Step left
Micronas
JLC.vsd/10 SwMode2.WMF
SDA9410
Preliminary Data Sheet
Application modes memory concept
Steps MEMOP
ORGMEMM
ORGMEMS
MEMWRM
MEMWRS
MEMRDS
Operation changing picture sizes master slave programming corresponding decimation parameters reducing width below pixel master picture fields stored
Table
Changing picture sizes double window format
Starting mode with insertion (step first field based conversion mode must chosen both channels, e.g. AABB conversion interlaced modes intrafield interpolation progressive modes (step capacity master channel reduced field (step free memory capacity used write slave data address areas parallel corresponding SRC-PIP configuration configuration. step reading slave channel data switched configuration. last step also master channel switched mode. this configuration store field master channel fields slave channel. Joint Line Controller activated joint line free display possible. Reducing size master picture enlarging slave picture size performed step table During this phase problems with joint line free display master picture until horizontal width below pixel. also master channel enabled store fields joint line free display possible again (step this configuration double window display performed. During steps positioning both pictures free programmable enable multiple variations animation.
JLC.vsd/11 SwMode3.WMF
SSC-Mode, AABB (A+B): -master picure becomes smaller -slave picture becomes larger
SRC-PIP Mode, ABAB (A+B)
Figure
Completing operations master slave exchange
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
Steps MEMOP
ORGMEMM
ORGMEMS
MEMWRM
MEMWRS
MEMRDS
Operation changing picture sizes master slave programming corresponding decimation parameters exceeding width pixel slave picture only field stored further changes picture sizes until full size slave picture size master picture displayed switching synchronization slave channel exchanging inputs switching mode using still field based conversion slave channel reading switched memory configuration also master channel works frame based programming STOPMOM STOPMOS frame based conversion
Table
Performing master slave exchange
Starting with double window configuration (figure page procedure continued with animation perform exchange master slave sources display like shown figure page step picture size master channel decreased size slave picture increased continuously. When width slave picture exceeds pixel only field stored (step Joint line free display slave channel always possible this configuration. When full size slave picture format master picture size reached (step exchange master slave channel possible. Unstable picture phases avoided when display raster phase adapted slave channel before hardware exchange both sources done. display phase raster shifting "Master slave switch" page activate mode again. first just change mode maintaining field based conversions (step 12). Then slave data configuration memory changed configuration (step last master channel memory capacity enlarged fields (step frame based conversion modes enabled (step 15).
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
5.6.6
Joint line free display
This chapter describes parameters joint line free display mode.
parameter [Default] RSHF[0]
address
Description
Joint line free display master channel shifting output raster phase (SSC-Mode) enabled disabled Joint line free display master slave channel shifting output raster phase (SSC-Mode, RSHFTM=1) enabled disabled Increment raster phase shift output frame (lines) Threshold display progressive without joint lines
RSHFTS
SHFTSTEP [0100]
PROG_THRES [0111100]
Table
Input write parameter
parameter SHIFTACT
Description indicates active shifting process display raster phase display phase shifting active display phase shift active
Table
Output read parameter
special circuit implemented achieve joint line free display mode (e.g. Double Window Display). This circuit synchronizes input sources removes joint lines automatic controlled shifting display raster phase. This procedure enlarges value OPDELM resulting delayed start output processing. parameters RSHFand RSHFTS enable joint line free display master slave channel, separately. SHFTSTEP fixes amount lines which added OPDELM with each output frame. readable parameter SHIFTACT signalizes progressing shifting operation. recommended enable registers RSHFand RSHFTS application modes.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
Mode
Input Master Channel 625/50i 525/60i 625/50i 525/60i 625/50i 525/60i 625/50i 525/60i
Input Slave Channel 625/50i 525/60i 525/60i 625/50i 625/50i 525/60i 525/60i 625/50i
Output Display Channel 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p 625/100i 625/50p 525/120i 525/60p
Comment
SSC/ SSC/ SSC/ SSC/
Motion compensation master channel possible Motion compensation master channel possible joint line free display slave channel possible (NEW) joint line free display slave channel possible (NEW) motion compensation possible motion compensation possible motion compensation possible, joint line free display slave channel possible motion compensation possible, joint line free display slave channel possible
Table
Supported data formats
5.6.7
Master slave switch
This chapter describes parameters used execute master slave exchange.
parameter [Default] MASTSLA address Description
Master Slave shift: Master slave input signals exchanged, reset display raster shift Display raster synchronized input master channel (vertical sync) Master Slave shift: Display raster shifted slave phase prepare master/slave switch Display raster synchronized input master channel (vertical sync)
MASLSHFT
Table
Input write parameter
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter [Default] SHIFTACT
address
Description
Shifting display raster phase active phase shift progress phase shift active
Table
Output read parameter
Master slave exchange means animated exchange master slave picture source without visible synchronization problems deflection compared with hard switch between both sources. avoid this synchronization problem display raster phase slowly shifted position that fits slave channel sync pulses. Then exchange done without visible artefacts. animation "Configuration switch" page What perform master slave switch: Parameter MASLSHFT must set. Shift process started. 2.The output signal SHIFTACT must observed. After setting MASLSHFT becomes signalizes that shift process active. When becomes shift process finished desired phase display raster obtained. 3.At same time exchanging master slave inputs setting parameter MASTSLA must performed. chip synchronized former slave channel that become master. 4.At last parameters MASLSHFT MASTSLA should reset.
5.6.8
Refresh still picture mode
master slave channel picture frozen parameter FREEZEM FREEZES, respectively. parameters REFRON REFRPER used activate memory refresh internal memory.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter [Default] FREEZEM FREEZES REFRPER [00]
address
Description
Freeze picture master freezed writing master channel) live Freeze picture slave freezed writing slave channel) live Refresh period memory (REFRON=1; lines standard) 10ms 5.5ms Refresh internal memory memory refresh activated memory refresh
REFRON
Table
Input write parameter
5.6.9
Memory management animation controlling
"Example animation" page shows possible application 9410. still pictures plus life picture (cup coffee) located around second life (boat) picture (see picture number still pictures plus life picture (cup coffee) located slave memory life picture (boat) master memory. user wants switch between coffee boat channel. possible animation could look like this. boat will compressed disappears (number number fact, that only background colour should visible, parts life picture, which disappear after compression, will overwritten with back ground colour. Afterwards channel expanded overwrites border colour (cup coffee, number number support this other features several parameters exists, which will described more detail afterwards.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
Still picture Life picture
Life picture
Figure
Example animation
parameters IPOSXM IPOSYM IPOSXS IPOSYS, respectively, specify position left upper corner stored picture. figure below explains functionality parameters. whole memory organized blocks, which have width pixels. position (x,y) defined parameters defined equation below:
Figure
IPOSXM
modulo
Equation position left upper picture corner
IPOSYM IPOSYS parameter specify vertical position with resolution line 4:1:1 format lines 4:2:0 format master slave channel, respectively. MSBs IPOSXM IPOSXS defines horizontal position with resolution pixels (block resolution). LSBs IPOSXM IPOSXS used fine positioning picture block with resolution pixels. fact, that only blocks written memory, pixels left fine positioning filled with border values (border values defined YBORDERM/ YBORDERS, UBORDERM/UBORDERS, VBORDERM/VBORDERS). number pixels smaller pixels (block size), missing pixels block also filled with border values.
vhcomba2
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
(IPOSXM)/8
IPOSYM
x/pixels
block
y/lines
(IPOSXM modulo
Figure
Explanation memory management
Figure shows picture (boat, number which located with left upper corner position (x1,y1). picture will compressed vertical horizontal direction stored position (x2,y2). vertical horizontal compression mechanism input signal explained before (compare "Vertical horizontal compression (VHCOMM/VHCOMS)" page 32). This result could look like showed picture number Parts original boat still visible. Therefore addition parameters LEBORDM/LEBORDS, RIBORDM/RIBORDS, UPBORDM/UPBORDS LWBORDM/LWBORDS exist. These parameters specify amount pixels left side right side amount lines bottom which written addition into memory with coloured border values parameters YBORDERM, YBORDERS, UBORDERM, UBORDERS, VBORDERM, VBORDERS). Then result could look like showed picture number (white border colour). amount pixels left side defined parameters LEBORDM/LEBORDS (amount border pixels LEBORDM/LEBORDS) amount pixels right side defined parameter RIBORDM/RIBORDS (amount border pixels RIBORDM/ RIBORDS). maximum amount pixels, which written addition, pixels each side. parameters UPBORDM/S LWBORDM/S specify amount lines which written addition into memory upper lower edge picture with coloured border values. maximum amount lines, which written addition, each side. there limitation that UPBORDM/UPBORDS LWBORDM/LWBORDS should exceed (PAL) lines. horizontal direction mentioned before only blocks pixels) written into memory. That means instance LEBORDM parameter value bigger zero LSBs IPOSXM parameter zero (start position begin block), that complete block left side block specified IPOSXM will filled with border colour.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
(X1,Y1) (X2,Y2) LEBORDM RIBORDM
UPBORDM
IPOSXM/8 (IPOSXM modulo
LWBORDM
Figure Explanation memory management animation shown Figure done following way. picture (boat) beginning defined size (defined parameters APPLM1, ALPFM1, INTHM1, DEZHM1, INTVM1, DEZVM1) left upper corner picture located position (x1,y1) (defined IPOSXM1, IPOSYM1). Specify picture size. corresponding parameters (APPLM2, ALPFM2, INTHM2, DEZHM2, INTVM2, DEZVM2) picture size. Specify vertical horizontal position (x2,y2) (defined IPOSXM2, IPOSYM2). Specify addition amount lines upper lower edge, which overwritten with border values. addition amount pixels left right edge, which overwritten with border values (LWBORDM, UPBORDM, LEBORDM, RIBORDM). Send values interface. Remember that reduction picture limited horizontal vertical direction, border should overwritten with border colour. Figure shows detail what happens means horizontal bar, which horizontally reduced. width pixels (compare Figure 33). position defined IPOSX1 instance, IPOSXM1=00001100b=12 parameters LEBORDM RIBORDM both equal first block last block filled with border values (black colour background value). compressed horizontally width pixels. position defined IPOSX2 after reduction step IPOSXM2=00010001b=17=>x2 That means actual picture size reduced pixels, pixels left side (Left Side pixels right side (Right Side 20). Therefore
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept parameter LEBORDM LEBORDM=5 (amount pixels 4*LEBORDM 20), pixels remaining memory should overwritten with border values. addition parameter RIBORDM RIBORDM=5 (amount pixels 4*RIBORDM 20), pixels remaining memory should overwritten with border values. position left edge begin block thus difference between begin actual block 68-64=4. That means that from additional pixels, which have written left bar, least pixels belong block which begins position That means, that complete block (begin position filled with border values. same argumentation valid right edge bar.
(IPOSXM)/8
IPOSYM
pixels
IPOSYM
(IPOSXM)/8
pixels
Reduction
vhcomba3
lines
lines
APPLM1 8*21/2 pixel IPOSX1 00001100=12 32*1 LEBORD1 RIBORD1 Reduction pixels IPOSX2 00010001 32*2 LEBORD2 RIBORD2
APPLM2 8*11/2 pixel
Figure
Explanation memory management
Repeating procedure described above must used animation explained Figure
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter [Default] UPBORDM LWBORDM LEBORDM RIBORDM UPBORDS LWBORDS LEBORDS RIBORDS IPOSXM IPOSXS IPOSYM IPOSYS
address
Description
Amount upper border lines vertical compression master Amount lower border lines vertical compression master Amount left border pixels horizontal compression master Amount right border pixels horizontal compression master Amount upper border lines vertical compression slave Amount lower border lines vertical compression slave Amount left border pixels horizontal compression slave Amount right border pixels horizontal compression slave Horizontal picture position memory master Horizontal picture position memory slave Vertical Picture Position Memory master Vertical Picture Position Memory slave
Table
Input write parameter
possible write border colours instead master slave channel different areas. Therefore parameters FORCOLM FORCOLS used.
Micronas
SDA9410
Preliminary Data Sheet
Application modes memory concept
parameter [Default] YBORDERM [0001] UBORDERM [1000] VBORDERM [1000] YBORDERS [0001]
address
Description
border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 00010000 16), YBORDERM defines MSB's value border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 10000000 128), UBORDERM defines MSB's value border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 10000000 128), VBORDERM defines MSB's value border value (Yborder(3) Yborder(2) Yborder(1) Yborder(0) 00010000 16), YBORDERS defines MSB's value border value (Uborder(3) Uborder(2) Uborder(1) Uborder(0) 10000000 128), UBORDERS defines MSB's value border value (Vborder(3) Vborder(2) Vborder(1) Vborder(0) 10000000 128), VBORDERS defines MSB's value Force colour master channel Force colour slave channel
UBORDERS [1000] VBORDERS [1000] FORCOLM FORCOLS
Table
Input write parameter
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Output sync controller (OSCM/S)
Signals HOUT VOUT BLANK
number
Description horizontal synchronization signal (polarity programmable, parameter HOUTPOL, default: high active) vertical synchronization signal (polarity programmable, parameter VOUTPOL, default: high active) free programmable horizontal blanking signal (polarity programmable, parameter BLANKPOL, default: high active) interlaced signal (can used coupled deflection circuits)
INTERLACED
Table
Output signals
output sync controller generates horizontal vertical synchronization signals scan rate converted output signal. figure below shows block diagram OSCM/S existing parameters.
HOUTPOL, HOUTFR, APPLOPD, NAPOPD, BLANLEN, PPLOP, RMODE, BLANDEL, HORPOSM, HORPOSS, HORWIDTHM, HORWIDTHS, HOUTDEL HOUT BLANK VOUT INTERLACED osc01
GMOTION, MOVMO, MOVPH, MOVTYP
OPERATION mode generator
HOUT generator
VOUT generator
STOPMOM, STOPMOS, VOUTPOL, VOUTFR, NALOPD, ALPFOPD, ADOPMOM LPFOP, VERPOSM, VERPOSS, VERWIDTHM, VERWIDTHS, INTMODE
Figure
Block diagram OSCM/S
Furthermore output sync controller derives framing signals from generated HOUT VOUT output data processing. framing signals depend different parameters. whole output picture combination three channels:
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S) Background channel Output channel master Output channel slave background channel always lowest priority. priority between output channel master slave defined parameter PRIORMS. figure below shows example combination three channels. background colour black lowest priority. picture content master channel phone picture content slave channel airplane. this case slave channel highest priority. enable disable display master slave channel parameters MASTERON SLAVEON used.
HOUT VOUT (PPLOP*2)*CLKD
(NALOPD+1)*2 VERPOSM
VERPOSS VERWIDTHS*4
4*LPFOP+1
ALPFOPD*8
VERWIDTHM*8
(HORWIDTHM*8)*CLKD (HORPOSM*4)*CLKD (HORPOSS*4)*CLKD (HORWIDTHS*4)*CLKD (APPLOPD*8)*CLKD
(NAPOPD*4)*CLKD
BLANK
(BLANLEN*8)*CLKD MSBs BLANDEL)*8 LSBs BLANDEL))*CLKD
Figure
Output parameter
outpar01
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
parameter [Default value] NALOPD [22] ALPFOPD [144] VERPOSM VERWIDTHM [72] VERPOSS VERWIDTHS [144] LPFOP [156] NAPOPD APPLOPD [90] HORPOSM HORWIDTHM [90] HORPOSS HORWIDTHS [180] PPLOP [432] BLANDEL BLANLEN [180] HOUTDEL PRIORMS
address
Description Active Line OutPut Display defines number lines from V-Sync first active line output frame Active Lines Field OutPut Display defines number active lines output frame VERtical POSition Master defines number lines from first active line background channel first active line master channel VERtical WIDTH Master defines number active lines master channel output frame VERtical POSition Slave defines number lines from first active line background channel first active line slave channel VERtical WIDTH Slave defines number active lines slave channel output frame Lines Frame OutPut defines number lines output frame (only valid VOUTFR=1) Active Pixel OutPut Display defines number pixels from H-Sync first active pixel Active Pixels Line OutPut Display defines number pixels line (background, master slave channel) HORizontal POSition Master defines number pixels from first active pixel background channel first active pixel master channel HORizontal WIDTH Master defines number active pixels master channel HORizontal POSition Slave defines number pixels from first active pixel background channel first active pixel slave channel HORizontal WIDTH Slave defines number active pixels slave channel Pixel Line OutPut defines number pixels between consecutive H-Syncs (only valid HOUTFR=1) BLANk DELay defines distance from H-Sync active edge BLANK signal number CLKD clocks BLANk LENgth defines length BLANK signal number CLKD clocks Horizontal delay HOUT VOUT signal clocks CLKD Priority master slave channel: master channel priority slave channel priority (SFCPR should fixed VSS).
45h,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
parameter [Default value] MASTERON SLAVEON address Description Display master channel: enabled disabled Display slave channel: enabled disabled
Figure
Output write parameter
next paragraphs describe HOUT VOUT generator more detail. Both generators have called "locked-mode" "freerunning-mode". combinations modi make sense. table below shows ingenious configurations.
Mode "H-and-V-locked" "H-freerunning-V-locked" "H-and-V-freerunning"
HOUTFR
VOUTFR
CLKMDEN
Figure
Ingenious configurations HOUT VOUT generator
5.7.1
HOUT generator
HOUT generator operation modes, which selected parameter HOUTFR. HOUT signal active high (HOUTPOL=0) clock cycles (X1/CLKD). freerunning-mode HOUT signal generated depending PPLOP parameter. locked-mode HOUT signal locked incoming H-Sync signal HIN. polarity HOUT signal programmable parameter HOUTPOL. BLANK signal used mark active part line. avoid transition artifacts digital filters number active pixels symmetrically reduced using CAPPM CAPPS parameter.
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
parameter HOUTFR free locked mode CAPPM CAPPS
address
Description HOUT generator mode select
Reducing factor HORizontal WIDTH Master value master channel Number active pixels line HORWIDTHM
Reducing factor HORizontal WIDTH Slave value master channel Number active pixels line HORWIDTHM
Table
Output write parameter
5.7.2
VOUT generator
VOUT generator operation modes, which selected parameter VOUTFR. VOUT signal active high (VOUTPOL=0) output lines. freerunning-mode VOUT signal generated depending LPFOP parameter. locked-mode VOUT signal synchronized incoming V-Sync signal (means internal delayed parameter OPDELM, compare "Input sync controller (ISCM/ISCS)" page 22). RMODE parameter (linescanning pattern mode progressive, interlaced) determines scan rate conversion mode. RMODE=1, then each incoming V-sync signal outgoing V-sync signal VOUT generated (e.g. interlaced progressive scan rate conversion). RMODE=0, then during incoming V-Sync signal, VOUT pulses have generated (e.g. interlaced interlaced scan rate conversion).
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
RMODE=1 VOUT RMODE=0 VOUT
conv
Figure
VOUT generation depending parameter RMODE
polarity VOUT signal programmable parameter VOUTPOL. VOUT signal delay CLKOUT clocks HOUT signal case interlaced delay half line plus CLKOUT clocks. INTERLACED signal used AC-coupled deflections. Depending parameter INTMODE value this signal will generated. Table shows definition this signal (compare "Operation mode generator" page 83).
output field phase INTMODE INTMODE(0)
output field phase INTMODE(1)
output field phase INTMODE(2)
output field phase INTMODE(3)
Table
Output write parameter INTMODE
parameter VOUTFR free locked mode RMODE progressive interlaced INTMODE
address
Description VOUT generator mode select
line-scanning pattern mode
Free programmable INTERLACED signal AC-coupled deflection stages
Table
Output write parameter INTMODE
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
5.7.3
Switching from H-and-V-freerunning H-and-V-locked mode
H-and-V-freerunning mode, generally, phase generated synchronization line-scanning pattern correlation input line-scanning pattern. hard switch from H-and-V-freerunning mode H-and-V-locked mode therefore would cause visible synchronization artefacts. avoid these problems 9410 enlarges line field lengths output sync signals HOUT VOUT defined procedure enable invisible synchronization freerunning output input. vertical synchronization maximum synchronization time interlaced progressive display modes. Horizontal synchronization performed maximum time best performance recommended change first vertical after mentioned delay times horizontal mode from free running locked.
5.7.4
Operation mode generator
VOUT generator determines VOUT signal. proper operation VOUT generator information about line-scanning pattern sequence necessary. parameters STOPMOM (STatic OPeration MOde Master), STOPMOS (STatic OPeration MOde Slave) parameter ADOPMOM (ADaptive OPeration MOde Master) define line-scanning pattern sequence scan rate conversion algorithms.
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
FRAME/FIELD
FRAME FIELD lines
FIELD even lines
Content picture
DISPLAY LINE-SCANNING PATTERN
Display raster lines Display line-scanning pattern
even lines
Display line-scanning pattern
Tube, Display raster
Figure
Explanation field display line-scanning pattern
interlaced input signal (e.g. NTSC) composed field (odd lines) field (even lines). Input signal, field time Input signal, field time field information describes picture content. output signal, which could contain different picture contents (e.g. field field displayed with display line-scanning pattern Output signal, field time displayed line-scanning pattern Output signal, field time displayed line-scanning pattern
fieldras01
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S) ((A*) Output signal, field line-scanning pattern interpolated into field time displayed line-scanning pattern
,+==Output signal, frame time progressive
table below describes different scan rate conversion algorithms corresponding line-scanning pattern sequences. delay between input field corresponding output fields depends OPDELM parameter default value delay half input field.
time
Fields available internal field stores
An-1, Bn-1
Bn-1,
Output fields
OPDELM lines
cn-1
Phase
dn-1
Phase
Phase
osc02
Input fields
Phase
Figure
Explanation operation mode timing
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Input field STOPMOM 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1100 1101 1110 1111 Scan rate conversion algorithm Output field phase p(c)*)= p(mc)= p(ma)= Bn-1= Bn-1= Bn-1= Bn-1= Bn-1= p(ma)= p(mc)= Output field phase p(d)= p(md)= p(mb)= Bn-1= Bn-1= =An= Bn-1= Bn-1= (A*)n= (B*)n-1= p(mb)= p(md)=
Input field Output field phase p(a)= p(ma)= p(mc)= (B*)n= (A*)n= p(ma)= p(mnc)= Output field phase p(b)= p(mb)= p(md)= p(mb)= p(mnd)=
VDU, camera mode VDU, film mode, phase VDU, film mode, phase Frame repetition, ABAB FRAME repetition, BABA Simple 100, AABB Simple 100, BBAA Field repetition, AAAA Field repetition, AAAA Field repetition, BBBB Field repetition, BBBB Simple 100, AA*B*B Simple 100, BB*A*A VDU, film mode, phase NTSC VDU, film mode, phase NTSC
Table
Static operation modes (only valid ADOPMOM=0, RMODE=0)
*)p(a): field motion compensated; p(b): field motion compensated
p(c): field motion compensated; p(d): field motion compensated p(ma): field motion compensated film mode; p(mb): field motion compensated film mode p(mc): field motion compensated film mode; p(md): field motion compensated film mode p(mnc): field motion compensated film mode NTSC p(mnd): field motion compensated film mode NTSC
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Input field STOPMOM 0000 0001 0010 0011 0100 0101 1100 1101 1110 1111 Scan rate conversion algorithm VDU, camera mode VDU, film mode, phase VDU, film mode, phase Frame repetition, Frame repetition, median Simple AA*, Field repetition, Field repetion, VDU, film mode, phase NTSC VDU, film mode, phase NTSC Output field phase p(cd)*)= p(mcd)= p(mab)=
Input field Output field phase p(ab)= p(mab)= p(mcd)= ((A*)n ((B*)n (A*)n= ((B*)n-1 Bn-1= p(mab)= p(mnc)=
(B*)n-1= (A*)n= (A*)n= ((B*)n-1 Bn-1= p(mab)= p(mcd)=
Table
Static operation modes (only valid ADOPMOM=0, RMODE=1)
*)p(ab): field motion compensated
p(cd): field motion compensated p(mab): field motion compensated film mode p(mcd): field motion compensated film mode p(mnc): field motion compensated film mode NTSC
STOPMOM=0000 (Micronas VDU) high performance motion compensation algorithm used scan rate conversion which results high performance line flicker reduction, double contour elimination perfect motion display. table Table "Special combinations STOPMOM ADOPMOM" page explains some important combinations both registers. possible force some modes like CAMERA, film mode NTSC film mode with manual automatic phase detection case film mode.
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
STOPMOM 0000 0001 0010 0001
ADOPMOM
Description force CAMERA mode force film mode Phase force film mode Phase force with automatic phase detection; film mode only once, detected; after that will fixed until another mode selected from user; STOPMOM 0001 0010 selected automatically
0010 1110
same STOPMOM 0001 ADOPMOM force NTSC film mode with automatic phase detection; NTSC film mode only once, detected; after that will fixed until another mode selected from user; STOPMOM 1110 STOPMOM 1111 selected automatically same STOPMOM 1110 ADOPMOM force with automatic phase detection; film mode only once, detected; after that will fixed until another mode selected from user; addition STOPMOM 0011 will selected GMOTION zero; STOPMOM 0001 0010 0011 selected automatically same STOPMOM 0001 ADOPMOM force NTSC film mode with automatic phase detection; NTSC film mode only once, detected; after that will fixed until another mode selected from user; addition STOPMOM 0011 will selected GMOTION zero;STOPMOM 1110 STOPMOM 1111 STOPMOM 0011 selected automatically same STOPMOM 1110 ADOPMOM
1111 0001
0010 1110
1111
Table
Special combinations STOPMOM ADOPMOM
table Table "Display line-scanning pattern sequence" page shows possible display line-scanning pattern sequences different static operation modes lines field value between consecutive output V-Syncs. assumed, that case freerunning-mode LPFOP=156 locked-mode number lines incoming field 312.5.
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Display line-scanning pattern sequence
312.5 312.5
312.5 312.5 312.5 312.5
312.5 312.5
5.(1.) 312.5 312.5 312.5 312.5
Table
Display line-scanning pattern sequence
table below defines static operation modes slave channel. slave channel synchronized master channel. Therefore only modes with same output line-scanning pattern chosen master channel mode allowed. Several modes depend parameter MEMOP.
STOPMOS Scan rate conversion algorithm allowed RMODE allowed output line-scanning pattern allowed MEMOP
Median, ABAB Frame repetition, ABAB Simple 100, AABB Field repetition, AAAA Field repetition, AAAA Field repetition, BBBB Field repetition, BBBB defined Median, Frame repetition, Line doubling, Line doubling, Intra field interpolation A+A* Line doubling, defined Intra field interpolation A+A*, B*+B
Table
Static operation modes slave
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S) adaptive operation modes (ADOPMOM) define dynamic switch between different static operation modes controlled several internal signals. start point modes actual chosen STOPMOM described before. tables below shows different adaptive operation modes. internal used control signals GMOTION, MOVTYP, MOVMO MOVPH (compare "Global motion, film mode phase detection" page 104). Furthermore internal control signal VTSEQ exists. case parameter VCRMODEM=1, VTSEQ still zero. VCRMODEM=0, VTSEQ equal (compare "Input sync controller (ISCM/ISCS)" page 22). this cases scan rate conversion forced simple field based scan rate conversion algorithm. internal control signals GMOTION, MOVTYP, MOVMO MOVPH also readable interface. Basic adaptive operation modes (RMODE (interlaced)):
off: ADOPMOM=000/001 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM STOPMOSint STOPMOS
VCRMODE off: ADOPMOM=010 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM Simple 100, AABB, 0101 STOPMOSint STOPMOS Simple 100, AABB,
Still picture mode: ADOPMOM=011 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS Simple 100, AABB,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Film mode ADOPMOM=100 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 VDU, film mode, phase NTSC, 1110 VDU, film mode, phase NTSC, 1111 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS
STOPMOS
STOPMOS
STOPMOS
Simple 100, AABB,
Film mode ADOPMOM=101 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 VDU, film mode, phase NTSC, 1110 VDU, film mode, phase NTSC, 1111 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
STOPMOS
STOPMOS
STOPMOS
Simple 100, AABB,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Film mode III: ADOPMOM=110 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS
STOPMOS
Simple 100, AABB,
Film mode ADOPMOM=111 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 Simple 100, AABB, 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
STOPMOS
Simple 100, AABB,
Adaptive operation mode (RMODE (progressive)):
off: ADOPMOM=000/001 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM STOPMOSint STOPMOS
VCRMODE off: ADOPMOM=010 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM Simple 0101 STOPMOSint STOPMOS Line doubling,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Still picture mode: ADOPMOM=011 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM Simple 0101 STOPMOSint STOPMOS STOPMOS Line doubling,
Film mode ADOPMOM=100 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 VDU, film mode, phase NTSC, 1110 VDU, film mode, phase NTSC, 1111 Simple 0101 STOPMOSint STOPMOS STOPMOS
STOPMOS
STOPMOS
STOPMOS
Line doubling,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Film mode ADOPMOM=101 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 VDU, film mode, phase NTSC, 1110 VDU, film mode, phase NTSC, 1111 Simple 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
STOPMOS
STOPMOS
STOPMOS
Line doubling,
Film mode III: ADOPMOM=110 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 Simple 0101 STOPMOSint STOPMOS STOPMOS
STOPMOS
Line doubling,
Micronas
SDA9410
Preliminary Data Sheet
Output sync controller (OSCM/S)
Film mode ADOPMOM=111 MOVMO MOVPH MOVTYP VTSEQM GMOTION STOPMOMint Frame repetition, ABAB, 0011 STOPMOM VDU, film mode, phase PAL, 0001 VDU, film mode, phase PAL, 0010 Simple 0101 STOPMOSint STOPMOS STOPMOS STOPMOS
STOPMOS
Line doubling,
Table
Adaptive operation modes
Example explanation adaptive operation modes: ADOPMOM Film mode RMODE=0 this case scan rate conversion algorithm controlled signal MOVMO, MOVTYP MOVPH. MOVMO equal scan rate conversion mode defined STOPMOM STOPMOS (e.g. Micronas VDU). MOVMO equal MOVTYP equal scan rate conversion algorithm changed depending MOVPH signal Micronas VDU, Film mode, PAL, phase MOVMO equal MOVTYP equal scan rate conversion algorithm changed depending MOVPH signal Micronas VDU, Film mode, NTSC, phase case film mode PAL, MOVPH signal constant applied material. case Film mode NTSC, MOVPH signal changes each field, respectively.
parameter STOPMOM STOPMOS ADOPMOM Table
address
Description STatic OPeration MOdes Master STatic OPeration MOdes Slave ADaptive OPeration MOdes Master
Output write parameter
Micronas
SDA9410
Preliminary Data Sheet
Motion estimation
Motion estimation
Recursive Search Block-Matching algorithm introduced high performance low-cost motion estimation algorithm suitable demanding scan rate conversion applications. figure below explains principle block matching algorithm. result best matching vector, which contains information about velocity direction block position (x,y).
(vx,vy)T
(x,y)
(x,y) time
time
Figure Principle block matching
main characteristics motion estimator inside 9410 listed table below.
parameter Horizontal range Vertical range Block size Accuracy Candidates Amount blocks +/-32 +/-24 (HxV) (2x3 90*72 (HXV) pels lines pels (frame grid) pels
Table
parameters motion estimation
Micronas
me01
SDA9410
Preliminary Data Sheet
Motion estimation Figure shows block diagram motion estimation motion compensation block. field information read line-wise from internal field store written line-to-block converter. motion estimation motion compensation block read field information parallel block wise from line-to-block converter. cache front blocks enables random access field information. result motion estimation stored vector memory, which also used vector field memory recursive block matching algorithm. that time only vector information block resolution available. post processing block computes vector information pixel resolution basis, which used from motion compensation block conversion process. Finally results motion compensation block written block-to-line converter block.
Vector memory
BVMRES
Cache Field Store eDRAM Line Block Converter Cache
Motion Estimation
Vector Post Processing
BVMCON MESMOOTHON
Motion Compensation
parameter
FILSEL VECDISON
Figure
Block diagram motion estimation compensation
Figure illustrates more detailed block diagram motion estimation block. motion estimation block separated branches. left only responsible still area detection right kind areas. additional left branch switched parameter MENULLFUNON parameter 4Bh). Different preprocessing blocks located both branches different tasks branches. After preprocessing input data main computation, block matching, executed. right branch, motion estimator applies concurrent recursive block matchers, that individually check three candidate vectors with different convergence directions. Among three candidates there spatial prediction vector taken from previously processed block temporal prediction vector. temporal prediction characteristic feature that position shifted with respect block currently processed opposite direction compared spatial prediction. Figure
me03
Block Line Converter
Micronas
SDA9410
Preliminary Data Sheet
Motion estimation illustrates this feature, shows that both types predictions differ estimators first estimator, second). Both estimators further test candidate that found their spatial prediction vector update vector. last candidate null vector. left branch contains only special null block matcher. best matching null vector from either branches assigned current block. overall best vector finally selected used scan rate conversion. Different penalty mechanism exist optimize behaviour both branches motion estimation block.
MEVPERTH MEANRG
Processing
Processing
MEANMP MEANBP
Block Matching
Block Matching
MEADDPEN MEPENUP MENULLPEN MENPTH MEHPERTH MEPERINF PERPEN MENVRTH
MENULLUNFON
Best result
Figure
Block diagram motion estimation
y+2Y
Convergence direction current block
block current field Convergence direction x-2X x+2X H-pos block previous field
Figure
Relative positions spatial predictors
parameters below used optimization purposes motion estimation block should changed customer.
me01
Micronas
SDA9410
Preliminary Data Sheet
Motion estimation
parameter MEANBP MEANMP MEANRG MEHPERTH MEVPERTH MEPERINF BVMRES
address
Description Penalty border lines additional null (dbd displaced block difference) Penalty middle lines additional null Range middle lines additional null Threshold horizontal periodicity detection Threshold vertical periodicity detection Defines influences periodicity Reset command block vector memory Channel switch switching channel remote control, switch BVMRES once release; note: reset film mode detection [RESMOV]) Freeze picture picture freeze switch BVMRES hold; alternative: switch motion compensated scan rate conversion [STOPMOM/ADOPMOM]) mode multipicture double window/split screen display switch BVMRES hold) Switch from SSC/MUP mode (switch mode, switch BVMRES, change master channel display size full screen [768x576], change back normal master channel screen size release BVMRES) Vector memory reset takes place only active master channel output size; reset whole vector memory switch maximum master channel size (768x576) Minimum hold time BVMRES have effect: CAMERA MODE: input field, FILM MODE: input fields; NTSC FILM MODE input fields Penalty periodic structures Minimum vector length null penalty Null vector reliability threshold, makes detection null vector homogenous areas more reliable. Threshold value adjust sensibility null vector reliability: 1111: insensible 0001: sensible motion noise 0000: Additional penalty null vector, vector length exceeds length given MENPTH null vector greater given threshold, which defined MENVRTH Penalty update vectors Additional penalty non-null vectors Vector smoothing on/off Unfiltered null on/off Vector correction on/off
PERPEN MENPTH MENVRTH
MENULLPEN
MEPENUP MEADDPEN MESMOOTHON MENULLUNFON BVMCON
Table
Output write parameter
Micronas
SDA9410
Preliminary Data Sheet
Motion compensation
Motion compensation
9410 motion estimation algorithm combined with advanced scan rate conversion algorithm. Figure shows position fields function time sequence sequence. information motion estimation (vector field) used generation additional fields. field directly used field. field right position, wrong phase. line-scanning pattern interpolation into field used field. field generated using vector field motion estimation.
sequence an+1 An+1 sequence
time
Figure
Timing scan rate conversion
Figure shows moving object function time. position object field exactly half position object field. That`s double contours visible.
sequence
sequence
me02
time
Figure
Principles motion compensation
principle conversion process illustrated Figure case field. Motion compensated pixels 5-tap median filter. background that case correct motion vector, expected that motion compensated pixels from both neighboring fields identical. Consequently, either selected correctly motion compensated intermediate field results. figure below vector ends existing line. Therefore pixels line before after existing line taken. vector unreliable current pixel,
Micronas
SDA9410
Preliminary Data Sheet
Motion compensation motion compensated pixels will different, chance that non-motion compensated field average output increases. result graceful degradation picture material case vector failure ("local fall back mode").
5-tap input, changed FILSEL (non-motion compensated linear interpolation)
Median
Figure
Principles motion compensation field (FILSEL=0)
generate output sequence with good motion portrayal estimated vectors actual film mode information used. Dependent film mode different output sequences generated. standard mode camera mode. this mode input source provides motion phase every field. other modes called film mode NTSC, respectively. arise from scanning cinematic source material which only frames second available. film mode material scanned standards always successive fields have same motion phase. film source reproduced with each image scanned twice interlaced video signal. NTSC film mode frames scanned using pulldown method resulting sequences, which contain alternating three successive fields with same motion phase. next figures three modes illustrated onedimensional motion. motion compensation create output field frame sequence, which good motion portrayal. Figure Figure Figure ideal motion portrayal displayed dashed line. output motion (solid line) should approach this ideal case. deviation m
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