Powerful Scan Rate Converter including Multistandard Color Decoder
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94x2A PRIMUS
Powerful Scan Rate Converter including Multistandard Color Decoder
Edition Oct. 2001 6251-552-3PD
94x2A (A32)
Preliminary Data Sheet 10.2001
Listen Your Comments information within this document that feel wrong, unclear missing all? Your feedback will help continuously improve quality this document. Please send your proposal (including reference this document) docservice@micronas.com 94x2A Revision History: Previous Versions: 2.0a 2.0f 2.0k 2.1a 10.2001 Preliminary
Micronas
Preliminary
Powerful scanRate converter Including MUltiStandard color decoder
94x2A
Version
CMOS
General Description
94x2A (PRIMUS) component Micronas MEGAVISION® CMOS embedded DRAM technology. 94x2A comprises main functions digital featurebox monolithic amount features limited favour low-cost solution. trade-off been made concerning picture quality. family ideally suited work conjunction with deflection processors SDA9380 (9402/32) DDP3315C (9412/42). combination with 'digital decoder' 9500 double-scan iDTV possible. package pin-upward compatible other medium-range high-end devices VSP94xy family. 50/60Hz derivative also available (9432, 9442).
Version Scan-rate- digital conversion input digital output analog output
P-MQFP-80-1
9402A 9412A
100i/120i 100i/120i 50i/60i 50i/60i
(X)1) (X)1)
(X)1) (X)1)
9432A 9442A2)
Input output used same time (pin sharing) under development
Table
Primus' versions
device comprises digital multistandard color decoder, interface with fastblank capability (SCART), digital ITU656 input, scaling units including panorama, embedded DRAM upconversion, picture improvements, temporal noise reduction well converter.
Micronas
94x2A (A32)
5.1.1 5.1.2 5.1.3 5.1.4 5.1.5 5.1.6 5.2.1 5.2.2 5.2.3 5.2.4 5.2.5 5.2.6 5.2.7 5.2.8 5.3.1 5.3.2 5.3.3 5.4.1 5.4.2 5.4.3 5.5.1 5.5.2 5.5.3 5.5.4 5.5.5 5.5.5.1 5.5.5.2 5.5.5.3 5.5.5.4
Micronas
Preliminary Data Sheet 10.2001
General Description General Description Features Block Diagram Description list Configuration P-MQFP80 System Description CVBS Frontend Source select Signal Magnitudes Gain Control Clamping Synchronization Chroma Decoder Luminance Processing RGB-Frontend Source Select Signal Magnitudes Gain Control Clamping Digital Prefiltering RGB->YUV Matrix Contrast, Brightness Saturation Control Input signal Soft activity overflow detection Input Processing Horizontal Prescaler (sample-rate-converter) Noise Reduction Noise Measurement Output Processing Horizontal Postscaler Panorama Mode Operation Modes Display processing Peaking Digital color transition improvement (DCTI) Coarse fine delay Oversampling Output-Sync Controller HOUT Generator VOUT Generator BLANK Generator Background Generator
94x2A (A32)
5.5.5.5 5.5.6 5.5.7 5.6.1 12.1
Preliminary Data Sheet 10.2001
General Description Window function Digital input Digital output Clock Concept Linelocked Clock Generator I2C-bus slave address format list alphabetical order Command Table Command Description
schematic Absolute Maximum Ratings Recommended Operating Range Characteristics Diagrams Application Circuit Application overview
Micronas
94x2A (A32)
List Figures Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure Figure 5-10 Figure 5-11 Figure 5-12 Figure 5-13 Figure 5-14 Figure 5-15 Figure 5-16 Figure 5-17 Figure 5-18 Figure 5-19 Figure 5-20 Figure 5-21 Figure 5-22 Figure 5-23 Figure 5-24 Figure 5-25 Figure 5-26 Figure 5-27 Figure 5-28 Figure 5-29 Figure 5-30 Figure 5-31 Figure 5-32 Figure 5-33 Figure 5-34 Figure 5-35 Figure 5-36 Figure 5-37
Micronas
Preliminary Data Sheet 10.2001
Page
Block Diagram Signal flow 940x, 943x Signal flow 941x, 944x, 942x P-MQFP-80 Package outlines P-MQFP-80 Input selection CVBS characteristic CVBS, amplitude characteristics Clamping signals NSRED characteristic Chroma decoding overview Chroma filter characteristics Color killer adjustment prefilter Filter characteristics NTSC, Filter characteristics B/G, NTSC44, PAL60 Filter characteristics SECAM (SECNTCH='01', 4.25 MHz) Filter characteristics mode Adjustment 'Black-' 'Blankingvalue' analog output. Signal Clamping organization Y/RGBF amplitude characteristics (with without sync) amplitude characteristics characteristic, Fast-blank with clamping (DCLMPF=0) Fast-blank characteristic without clamping (DCLMPF=1) Digital Prefiltering input Softmix: Visualization formulas Varied FBLOFFST output static operation mode Image format before memory. decimation filter characteristic standard operation (1.5) Temporal noise reduction Segments Predefined curve characteristics Expansion factor horizontal postscaler dependent HSCPOSC Visualization panorama segments Panorama expansion Explanation field display line-scanning pattern 50/60 interlaced 100/120 interlaced conversion (AABB). Block diagram Display processing Block diagram peaking. Peaking filter: Bandpass Highpass filter Principles DCTI output signals
94x2A (A32)
List Figures Figure 5-38 Figure 5-39 Figure 5-40 Figure 5-41 Figure 5-42 Figure 5-43 Figure Figure Figure 11-1 Figure 11-2 Figure 12-1 Figure 12-2 Figure 12-3
Preliminary Data Sheet 10.2001
Page
Image format behind memory Horizontal windowing Vertical windowing Horizontal vertical windowing Linelocked clock generation. Allowed operation area clock generation clock domains schematic. .143 timing data .151 timing start/stop. .151 Application Example .152 Application Overview with SDA9380 .153 Application Overview with 3315C .153
Micronas
94x2A (A32)
List Tables Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table
Preliminary Data Sheet 10.2001
Page
Primus' versions. Hardware compatibility suited backend Description modes Clamping adjustment Allowed combinations color-standard search Possible input signals Frontend Configurations input signals operation modes Horizontal expansion factors Examples panorama modes Operation modes scan-rate conversion Peaking filter adaption Conversion table between HCOF/BCOF GAINHP/GAINBP Ingenious configurations HOUT VOUT generator Display line scanning pattern sequence input output selection modes Clock system LL-PLL settings clock domains register characterization register overview
Micronas
94x2A (A32)
Features
Preliminary Data Sheet 10.2001
Features
Integrated Video Matrix switch seven CVBS inputs, inputs, three CVBS outputs (even when input) amplitude resolution CVBS, converter (Automatic Gain Control) Multi-standard color decoder PAL/NTSC/SECAM including substandards Automatic recognition chroma standard Only crystal necessary standards RGB-FBL YUV-H-V input amplitude resolution amplitude resolution ITU656 support (version dependent, refer next chapter) ITU656 input/output DS656 output (double-scan '656like' output) Noise reduction Motion adaptive temporal noise reduction Field-based temporal noise reduction luminance chrominance Different motion detectors luminance chrominance identical Flexible programming temporal noise reduction parameters Automatic measurement noise level Horizontal scaling signal Split-screen possible with additional Text processor Flexible digital horizontal scaling signal Scaling factors: pixel resolution], 0.75 including 16:9 compatibility zone panorama generator Embedded memory On-chip memory controller Embedded DRAM core field memory SRAM PAL/SECAM delay line Data format 4:2:2 Flexible clock synchronization concept Horizontal line-locked free-running mode Vertical locked free-running mode Scan-rate-conversion Simple interlaced modes (100/120 Hz): AABB, AAAA, BBBB (9402A/9412A only) scan-rate-conversion modes (50/60 Hz): (9432A/9442A only) Flexible output sync controller Flexible positioning output signal Flexible programming output sync raster 'Blank signal' generation
Micronas
94x2A (A32)
Preliminary Data Sheet 10.2001
Features Signal manipulations Still field Insertion colored background Windowing Vertical chrominance shift improved picture quality Sharpness improvement Digital color transition improvement (DCTI) Peaking (luminance) Three converters amplitude resolution -(R-Y), -(B-Y) output clock frequency Two-fold oversampling Anti-imaging Simplification external analog postfiltering 1920 active pixel/per line default configuration control (400 kHz) selectable address 1.8V± 3.3V supply voltages P-MQFP-80 package
Micronas
2-10
data buffer
bin1
(26) insert (30)
GAIN bypass
(33) UVin (25)
down sampling
main
noise reduction
(38) Ydelay
ADCG
Antialias, Deskew
clamping correction
fbl1
saturation
(13)
(18)
(22)
soft-mix
(34)
channel (31) Hprescaler H/Vacquisition
eDRAM noise reduction UVdelay
(37)
rin2
motion
Source Select 4:4:4 4:2:2
(36) (29) (28)
(16)
GAIN detection
ADCB
Antialias, Deskew
clamping correction
3-11
(27)
gin2 Offset, Gain
(14)
(19)
(23)
bin2
GAIN
ADCF
Antialias, Deskew
fbl2
(15)
(20)
CLAMP
656clk
Panorama generator
(43) Background generator (57)
CLKB36
656io0
GAIN Peaking
(45)
656io1
Hpostscaler
(42)
data buffer
Figure
Micronas
xout
clamped, filterd sync signal
cvbso1
cvbso2 cvbso3
reset
cvbs1 xtal oscillator
GAIN
generator
divider
(20.25, 40.5 MHz) Output Sync BLANK
cvbs2 Sync
ADC1 vout hout delay
(10) (36, MHz) (11)
CVBS/Y line-locked (40)
Notch Deskew LL-PLL divider line-locked clocks
clamping signals ADCs
free-running clocks
cvbs3 delay control
(PAL/SECAM)
Output Sync Controller
clkout
cvbs4
Source Select
GAIN
cvbs5
Input Sync
ADC2
Color Decoder
YCSEL
cvbs6 delay
(55) read control (39)
Output Data Controller memory controller
cvbs7
Block Diagram
94x2A (A32)
Block Diagram
(35)
CLAMP motion detection
rin1
brightness contrast
GAIN noise measure ment (32)
ADCR
Antialias, Deskew
clamping correction
gin1
(12)
(17)
(21)
656io2
Pixelmixer
(44)
Coarse Delay 4:4:4 DCTI
(46) (49)
8:8:8
(50)
(52) OFFSET Fine delay GAIN (53) OFFSET
656io3
PRIMUS (A32) VSP9402A VSP9432A
interface
(56)
ayout
ITU656 Decoder
656io4
(41)
auout
656io5
BLANEN
BLANK
656io6
ITU656 Encoder
(51)
CLKF20
testcontroller, memory bist
GAIN (54) line locked free-running OFFSET
det_block.vsd 1/.10.2000 D.Wendel
avout
656io7
CLKF2PAD
(55)
Preliminary Data Sheet 10.2001
Block Diagram
656hin/ 656vin/ clkf20 blank adr/tdi
tclk
94x2A (A32)
Description
analog output selectable
Preliminary Data Sheet 10.2001
Description
analog output
940xA 943xA 940xB 943xB single-scan output (943x) double-scan output (940x)
940xA 943xA 940xB 943xB
single-scan input
Figure
Signal flow 940x, 943x
single-scan input
941xA 944xA single-scan output (944x) double-scan output (941x) 941xB 944xB single-scan input
9425B 9427B
Figure
Signal flow 941x, 944x, 942x
Hardware compatible1) DDP3310B 9402A, 9432A
9405B, 9435B 9407B, 9437B 9409C
suited backend DDP3315C ITU656 input possible) SDA9380
9412A, 9442A
9415B, 9445B 9417B, 9447B 9419C 9425B, 9427B 9429C
with some restrictions. Please refer description and/or respective application note
Table
Hardware compatibility suited backend
Micronas
4-12
94x2A (A32)
Micronas
Preliminary Data Sheet 10.2001
Description
list
9402/32 9412/42 remark analog input analog input analog input analog input analog input analog input analog input analog output analog output analog output used,. connect connect connect connect connect connect connect leave open leave open leave open cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 cvbso1 cvbso2 cvbso3 xout vout hout
vssdacy ayout vdddacy vssdacu auout vdddacu vssdacv avout vdddacv
9402/32 9412/42
CVBS input CVBS input CVBS input CVBS input CVBS input CVBS input CVBS input CVBS output CVBS output CVBS output Crystal connection Crystal connection vertical output horizontal output output output output input (MSB) input input input input input input input (LSB) input clock
single double scan, dependent version
leave open leave open
i656i7 i656i6 i656i5 i656i4 i656i3 i656i2 i656i1 i656i0
leave open leave open nom. analog input analog input analog input analog input analog input analog input leave open connect connect connect connect connect connect
i656iclk
rin1 gin1 bin1 fbl1 rin2 gin2
Fast Blank input (H1) 4-13
94x2A (A32)
9402/32 9412/42 Micronas bin2 fbl2 reset clkout vdd33c vss33c vddac1 vssac1 vddac2 vssac2 vdd33rgb vss33rgb vddargb vssargb vddafbl vssafbl vddapll vddd1 vssd1 vddd2 vssd2 vddd3 vssd3 vddd4 vssd4 vddp1 vssp1 9402/32 9412/42 Fast Blank input (H2) vertical pulse input data testmode select address test data Reset input Output clock supply voltage CVBS supply voltage CVBS supply voltage CVBS1 supply voltage CVBS1 supply voltage CVBS2 supply voltage CVBS2 supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage supply voltage digital supply voltage digital supply voltage digital supply voltage digital supply voltage DRAM supply voltage digital supply voltage digital supply voltage digital supply voltage digital supply voltage digital 4-14
Preliminary Data Sheet 10.2001
Description
remark analog input analog input used,. connect connect connect
connect vdd33 reset, when digital digital digital digital digital digital digital digital leave open
94x2A (A32)
9402/32 9412/42 vddp2 vssp2 vddp3 vssp3 tclk h502) v503) 656io0 656io1 656io2 656io3 656io4 656io5 656io6 656io7 656clk 656hin/clkf20 9402/32 9412/42
Preliminary Data Sheet 10.2001
Description
remark connect (with skew)
used,.
supply voltage digital supply voltage digital supply voltage digital supply voltage digital testclock Hout Vout Digital input output Digital input output Digital input output Digital input output Digital input output Digital input output Digital input output Digital input output Digital input output clock separate input 20.25 clock output separate input BLANK output supply voltage digital
leave open leave open leave open leave open leave open leave open leave open leave open leave open
leave open leave open connect disable clock connect disable blank
656vin/blank4) vssd55)
connect
VSP94xxB VSP94xxC this shared intr (C800 controller output) VSP94xxB VSP94xxC this shared (Data-slicer-interrupt) VSP94xxB VSP94xxC this shared blank 9402 (and higher) VSP94xxA/B/C, this shared 656vin blank This used bonded VSP94xxA. this VSP94xxB/C will VSS. upgradability recommended leave this open.
Table
Description
Micronas
4-15
94x2A (A32)
Configuration P-MQFP80
Preliminary Data Sheet 10.2001
Description
vdddacy ayout vssdacy vssd2 vddd2 656vin/blank 656clk 656io7 vssp2 vddp2 656io6 656io5 hout adr/tdi
vssdacu auout vdddacu vssdacv avout vdddacv 656hin/clkf20 vssp1 vddp1 tclk xout vddapll vssd1 vddd1 vssac2 vddac2 cvbso1 cvbso2 cvbso3
PRIMUS 9402A 9432A
vss33c vdd33c cvbs7 cvbs6 cvbs5 cvbs4 cvbs3 cvbs2 cvbs1 vssac1 vddac1 (reserved) bin2 gin2 rin2 vss33rgb vdd33rgb vssargb vddargb bin1
Figure
P-MQFP-80
Figure
Micronas
Package outlines P-MQFP-80
4-16
656io4 656io3 vout reset vddp3 vssp3 clkout vddd3 vssd3 656io2 656io1 656io0 vssd4 vddd4 vddafbl vssafbl fbl1 fbl2 rin1 gin1
94x2A (A32)
System Description
Preliminary Data Sheet 10.2001
System Description
registers mentioned printed bold italics (e.g. YCDEL)
CVBS Frontend
CVBS frontend consists color-decoding circuit itself, sync processing circuit generation signals CVBS signal, luminance processing. main task luminance processing remove color carrier means notch filter. SECAM operation baseband delay line used signals. This used comb filter NTSC operation (only chrominance). input either used overlay CVBS channel (RGB+FBL) full master channel (RGB+H/V). overlay done means soft-mix used e.g. 'SCART' connector. This block incorporates matrix (for signals) which switched (e.g. YPbPr) input signals. (contrast, brightness, saturation) control makes input signal adjustable.
5.1.1
Source select
Figure shows analog frontend. analog CVBS signal inputs CVBS1.7 94x2A (amplitude 0.5.1.5Vpp). signal selected CVBSEL1 first ADC. second signal selected CVBSEL2 other ADC. CVBS4&5 CVBS6&7 intended separate inputs (YCSEL). After clamping back porch (switchable sync-tip clamping CLPSTGY) both signals AD-converted with amplitude resolution bit. conversion done using 20.25 free-running stable crystal clock. Before this signals lowpassed antialias filter. Three inputs looped back output CVBSO1-3 (CVBOSEL1, CVBOSEL2, CVBSELO3). signal addition performed output CVBS signal even when separate signals used input. Inputs that used roughly clamped allowed voltage region. stand-by operation (power-down mode), converter switched STANDBY keeping source-selector operational.
Micronas
5-17
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
CVBS CVBS CVBS CVBS CVBS CVBS CVBS
Clamping pulse ADC_CVBS1 ADC_CVBS2. Shifting signal required input voltage range CVBSO1.3
Filter
Filter
Buffer
Buffer
Buffer
ADC_CVBS1
ADC_CVBS2
CVBSO1
CVBSO2
CVBSO3
Figure
Input selection
5.1.2
Signal Magnitudes Gain Control
adjust different CVBS input voltages digitally working automatic gain control with linear steps implemented input voltages range from 1.8Vpp. best signal-to-noise ratio maximum available CVBS amplitude recommended. behavior chosen from four possible modes (AGCMD):
AGCMD Table
operation mode uses height sync pulse reference additionally reduces amplification when overflows uses height sync pulse reference uses only overflows disabled fits values given AGCADJ1 modes
When using sync height, gain rises falls depending incoming signal. When using overflow detection only, gain maximum reduced whenever 'overflow' occurs. signal lowpassed that chrominance noise used detection. threshold adjusted PWTHD. setting '11'
Micronas 5-18
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description equals means overflow ADC. Other settings react lower level. gain only becomes higher when change channel detected manually reset AGCRES. AGCFRZE holds current value. With AGCADJ1 AGCADJ2, both ADCs gain controlled manually.
Gain Control Characteristic
Conversion Range
AGCADJ1, AGCADJ2
Figure
CVBS characteristic
conversion range (CR) bigger than signal range (SRY, SRC) leaving headroom overshoots (Figure 5-3)
SRY(1V nom.) white SRC(0.89 nom.) (1.2V nom.) 100% chroma chroma
upper headroom
upper headroom
burst
black
burst
lower headroom
Figure
CVBS, amplitude characteristics
Micronas
5-19
94x2A (A32)
5.1.3 Clamping
Preliminary Data Sheet 10.2001
System Description
clamp timing analog inputs generated from corresponding CVBS signal. clamping algorithm works with split measurement pulse clamping pulse. measurement pulse used detect clamping error. clamping pulse used enable current sources reducing detected clamping errors. start length measurement signal adjustable independently both channels (CLMPST1, CLMPD1, CLMPST2, CLMPD2). start length clamping signal adjustable both channels independently (CLMPST1S, CLMPD1S, CLMPST2S, CLMPD2S). Clamping signals RGB-channel split. Clamping these controlled CLMPST2S CLMPD2S only. Clamping suppressed some lines CLMPLOW CLMPHIGH ignore copyprotection information. external sync signals required. signal
CLMPD1
description
measurement pulse duration ADC1
CLMPST1 measurement pulse start ADC1 CLMPST1S clamping pulse start ADC1 CLMPD1S clamping pulse duration ADC1 CLMPST2 (measurement pulse start ADC2) CLMPD2 (measurement pulse duration ADC2) CLMPST2S measure clamp start RGBF-ADC (clamping start ADC2) CLMPD2S measure clamp duration RGBF-ADC (clamping duration ADC2
Table
Clamping adjustment
CVBS/Y ADC1
clamp CLAMP1 signals measure
CLMPST1S
CLMPD1S CLMPST1 CLMPD1
ADC2
RGB/YUV frontend
CLAMP2 signals
clamp measure
CLMPST2S
CLMPD2S CLMPST2 CLMPD2
Figure
Micronas
Clamping signals
5-20
94x2A (A32)
5.1.4 Synchronization
Preliminary Data Sheet 10.2001
System Description
After elimination high frequency components CVBS signal pass filter, horizontal vertical sync pulses separated. Horizontal sync pulses generated digital phase locked loop. time constant adjusted between fast slow behavior four steps (PLLTC) accommodate different input sources (e.g. VCR). time-constant changed during normal operation without visible picture degradation. fine tuning time constant done NSRED.
multiplication before NSRED
phase deviation
Figure
NSRED characteristic
Additionally weak input signals from satellite dish ('fish') become more stable when SATNR enabled. Vertical sync pulses separated integration equalizing pulses. vertical flywheel mode improves vertical sync separation weak signals (VFLYWHL, VFLYWHLMD). Additionally, v-syncs gated VTHRL VTHRH reject invalid v-syncs. When input signal connected device switches freerunning mode. device configured switch-on background color when only weak signal applied (NOSIGB). operation sync separation forced separately selected work automatically (FLNSTRD)
Micronas
5-21
94x2A (A32)
5.1.5 Chroma Decoder
generator
Preliminary Data Sheet 10.2001
System Description
bell filter
demod. (cordic)
deemphase filter
SECAM
CVBSin
IF-prefilter
filter subsampling
chroma filter
chroma filter
burstakku
PAL/NTSC
PAL/SECAM delay line
UVout
colorkiller
SECAM only
SECAM
switch
PAL/NTSC/ SECAM
loop filter
lock detection
PAL/NTSC only
sin/cos
identification
Figure
Chroma decoding overview
digital multistandard chroma decoder able decode NTSC signals with subcarrier frequency 3.58MHz 4.43MHz (PAL B1)/M/N/602), NTSC M/4.4) well SECAM signals with automatic standard detection. Alternatively standard forced. demodulation done with regenerated color-carrier. nonstandard crystals factory adjustment, frequency free-running regenerated subcarrier adjusted SCADJ. this purpose crystal deviation (SCDEV) read after chroma locking (indicated SCOUTEN) stored SCADJ. test purposes, CPLLOF allows loop opening chroma adjustment specific operational area automatic norm detection selectable. Available color standards SECAM. Available color standards NTSC PAL60 NTSC44. each line standard, more color standards chosen automatic standard detection. addition, standard forced well. Within each line standard, standard detected consequently switching from another. This standard detection process slow fast behavior (LOCKSP). slow behavior, fields used detect standard, whereas fields used fast behavior. unsuccessful within this time period system tries detect another standard. SECAM detection, choice between different recognition levels possible (SCMIDL, SCMREL) evaluated burst position shiftable (BGPOS). Color standard (STDET), line standard (LNSTDRD) color killer status (CKSTAT) read out.
representative B/G/H/I/N PAL60 NTSC44 nonstandard signals which generated some player
Micronas
5-22
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
Standard
none PAL60 NTSC NTSC44 automatic NTSC automatic NTSC NTSC44/ PAL60
CSTAND
Standard
automatic SECAM
CSTAND
none SECAM
0(!)
Table
Allowed combinations color-standard search
Damping (dB)
Chroma filter
CHRF='001000' CHRF='001100' CHRF='001001' CHRF='111001'
Frequency (MHz)
CHRF='001110'
Figure
Chroma filter characteristics
Automatic Chroma Control (ACC) produces stable output input chroma variations from (approximately) compared nominal burst value.
Micronas 5-23
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description reference value programmable NTSC independently (NTSCREF, PALREF) ensure correct color saturation. With ACCFIX, disabled constant value (dependent NTSCREF PALREF) used instead. ACCFRZ holds current value. maximum amplification limited ACCLIM. This results smooth attenuation color intensity weak color carrier (Figure 5-8).
+0dB
CONS
+0dB
color +6dB -4dB
color
CKILL ACCLIM
attenuation color-carrier
+6dB
-4dB
attenuation color-carrier CKILLS
PAL, NTSC operation
SECAM operation
Figure
Color killer adjustment
chrominance signal below adjustable threshold (CKILL (PAL; NTSC) CKILLS (SECAM)) color switched off. prevent switching, hysteresis given CONS which value switching color. COLON switches color under circumstance. output colordecoder CrCb data CRCB. NTSC only, color impression (tint) adjusted Control between -88° steps 0.7° (HUE). chrominance values (+/- LSB) deleted UV-coring (UVCOR). Chroma bandwidth adjusted CHRF. value CHRF linear dependency effective bandwidth. proper constellations shown Figure 5-7. filter with asymmetrical characteristic around color carrier available (IFCOMP) (Figure 5-9).
Micronas
5-24
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
IFCOMP='000'
Prefilter
3.58 4.433
IFCOMP='100'
Damping (dB)
IFCOMP='010' IFCOMP='011'
IFCOMP='001'
Frequency (MHz)
Figure
prefilter
SECAM mode, de-emphasis filter adjusted DEEMPFIR DEEMPIIR. bell filter adjusted BELLFIR BELLIIR. delay between well aligned also adjusted steps 50ns (YCDEL). picture shifting occurs when switching between different color standards (e.g. SECAM PAL). delay-line implemented SECAM signals. acts simple chrominance comb-filter NTSC disabled COMB. This improves vertical chroma resolution, cross-color remains.
5.1.6
Luminance Processing
luminance notch filter implemented reject chroma information from luminance. Depending color standard, three different notch characteristics chosen ('PAL', 'NTSC', 'SECAM'). SECAM standards, five different characteristics available. NTSC standard, four different characteristics available. They selected NTCHSEL. Alternatively, notch should used input (NOTCHOFF). filter characteristics found Figure 5-10.Figure 5-13. SECAM operation, notch filter fixed frequency toggle between 4.25 depending transmitted color (Dr, (SECNTCH). simple
Micronas 5-25
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description lowpass-filter enabled LPPOST further reduce high-frequency noise component from CVBS signal.
attenuation [dB]
characteristic NTSC
3.58
NTCHSEL= 'x00' 'x01' 'x10' 'x11'
frequency [MHz]
Figure 5-10 Filter characteristics NTSC,
Micronas
5-26
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
attenuation [dB]
characteristic
4.43
NTCHSEL= '000' '100'
'010'
'011' '001'
frequency [MHz]
Figure 5-11 Filter characteristics B/G, NTSC44, PAL60
attenuation [dB]
characteristic SECAM (4.25 MHz)
4.25
NTCHSEL=
'100' '000' '001' '010' '011'
frequency [MHz]
Figure 5-12 Filter characteristics SECAM (SECNTCH='01', 4.25 MHz)
Micronas 5-27
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
attenuation [dB]
characteristic
LPPOST=0 LPPOST=1
frequency [MHz]
Figure 5-13 Filter characteristics mode applications which black offset desired, controlling done using LMOFST. positive negative offset added signal before scaling.
BLACK LMOFST='10' LMOFST='00' LMOFST='11' LMOFST='01'
BLANKING
BLACK LMOFST='10' LMOFST='00' LMOFST='11' LMOFST='01'
BLANKING
Input signals without 7.5IRE offset
Input signals with 7.5IRE offset
Figure 5-14 Adjustment 'Black-' 'Blankingvalue' analog output
RGB-Frontend
analog input port external source available. incoming signal clamped back porch clamping pulse. memory only able store 4:2:2 picture, input signal downconverted 4:2:2. There
Micronas 5-28
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description operation modes available. first uses this input overlay input (soft mix). signal must then synchronized main CVBS/YC signal. called independent mode uses including sync signals. This used, example, player set-top-box. When using sync from CVBS input (e.g. separate H-sync) this must indicated HINP. usage separate sync must VINP.
Input signal
(incl. sync) (incl. sync)
FBLIN
CVBS1) CVBS1)
sync separation remark
sync CVBS sync CVBS
Hinp Vinp
sync sync synchron CVBS/ synchron CVBS/ sync (maybe R/B) sync
e.g. set-top-box e.g. set-top-box soft soft external sync external sync e.g.
instead input, CVBS input used when Hinp=0 Possible input signals Frontend
Table
delay luminance fast-blank adjusted YFDEL, chrominance delay adjusted UVDEL. necessary, fast-blank adjusted fine FBLDEL.
Micronas
5-29
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
from VINP
from CVBS Source select
ADC2
AGCADJ2 Data HINP AGCADJ1 AGCMD
from CVBS Source select
ADC1
CLMPV1 CLAMPSIGNALS ADCSEL
Sync processing
VINP
from Source select
ADCR
AGCADJR CLMPVRB
DATAR
Processing
soft-mix RBOFFSET
CLAMPSIGNALS2 AGCADJG CLMPVG DATAG
from Source select
ADCG
Processing
soft-mix GOFFSET
from Source select
ADCB
AGCADJB CLMPVRB
DATAB
Processing
soft-mix RBOFFSET
from Source select
ADCF
AGCADJF DCLMPF
DATAF
Processing
soft-mix
Figure 5-15 Signal Clamping organization
5.2.1
Source Select
inputs available. choice between first second input made RGBSEL.
Micronas
5-30
94x2A (A32)
5.2.2 Signal Magnitudes Gain Control
Preliminary Data Sheet 10.2001
System Description
Each gain adjusted AGCADJR, AGCADJG, AGCADJB, AGCADJF.
upper headroom
upper headroom
lower headroom
lower headroom
Figure 5-16 Y/RGBF amplitude characteristics (with without sync)
CRUV
upper headroom
upper headroom
100% SRUV
100% SRUV CRUV
lower headroom
lower headroom
Figure 5-17 amplitude characteristics
Micronas
5-31
0.84
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
Conversion Range
Gain Control Characteristic
AGCADJR, AGCADJG, AGCADJB, AGCADJF
Figure 5-18 characteristic, Fast-blank with clamping (DCLMPF=0)
5.2.3
Clamping
When using dynamic softmix-mode with fast-blank, clamping fast-blank input must disabled DCLMPF. analog clamping value blue input resp.) adjusted CLMPVRB. analog clamping value green input resp.) adjusted CLMPVG. Depending input signal format (YUV, RGB, sync signal not) these bits must accordingly. digital side, correction analog clamping value must performed reconstruct blacklevel. This achieved RBOFST GOFST.
Gain Control Characteristic
output=255 conversion range
Conversion Range
output=0
AGCADJF
Figure 5-19 Fast-blank characteristic without clamping (DCLMPF=1)
Micronas 5-32
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
mode YUV, sync YUV, sync RGB, sync RGB, sync RGB, sync with fast-blank, synchron CVBS with fast-blank, synchron CVBS
CLMPVG
CLMPVRB
GOFST
RBOFST
DCLMPF don't care (clamping enabled) don't care don't care (clamping enabled) (clamping disabled) (clamping disabled)
Table
Configurations input signals
5.2.4
Digital Prefiltering
digital prefiltering enabled. This reduces bandwidth very steep input signals, such display characters. band limitation required, because succeeding deskewing filter performs best below MHz. filtering performed four channels disabled AABYP. signal conversion 4:2:2, additional chrominance lowpass enabled CHRSF. deskewing filter disabled SKEWSEL. This necessary when using HOUT50-pin connection with Micronas picture-in-picture device (e.g. SDA938x, SDA948x, SDA958x). this application, input (in1, in2, in3) used other signals (e.g. 'SCART' possible).
RGB-prefiltering
attenuation [dB]
Frequency [MHz]
Figure 5-20 Digital Prefiltering input
Micronas 5-33
94x2A (A32)
5.2.5 RGB->YUV Matrix
Preliminary Data Sheet 10.2001
System Description
signals selected YUVSEL. matrix coefficients according recommendations.
0,299 0,587 0,114 0,147 0,289 0,436 0,615 0,515 0,100
Formula matrix
5.2.7
Contrast, Brightness Saturation Control Input signal
signal manipulated order main channel. contrast adjusted between 1.97 steps (CONADJ). brightness adjustable steps (BRTADJ). independent chroma adjustment steps each, USAT, VSAT), well CrCb input signals both displayed correctly.
5.2.8
Soft
soft-mixing done means alpha-mixing. Alpha derived from fast blank input (FBL), which indicates signal insertion. value between '128'. means that only main signal through output. '128' means that only inserted signal becomes visible. Obviously formula
main inserted -128
mixing done once luminance once chrominance subsampled domain (4:2:2). displayed picture each main (CVBS) channel, channel softmix-mode, MIXOP used. operation modes possible (SMOP). first static operation mode where Fast-blank input effect. Considering MIXGAIN=3, obtained
FBLOFFST limited
function printed Figure 5-22 (right). mixing only controlled FBLOFFST. dynamic mode used mixing which dependent input. preprocessed digitized fast-blank input range from 0.127.
MIXGAIN FBLOFFST limited
manipulation done both luminance chrominance signal.
Micronas
5-34
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
MIXOP
SMOP
Softmix-mode
Table
dynamic Soft-Mix (DECTWO must '1') static Soft-Mix (DECTWO must '1') only RGB/YUV path visible only CVBS path visible
(reserved)
operation modes
SOFTMIX
SOFTMIX GAIN
SOFTMIX OUTPUT
ALPHA
ALPHA
Figure 5-21 Softmix: Visualization formulas There great variety signal manipulations. First, there delay adjustable FBLDEL range -2.4 clock cycles. Then offset applied signal (FBLOFFST). result multiplied adjustable factor (MIXGAIN).
ALPHA
SOFTMIX GAIN
ALPHA
Static mixer mode
FBOFFST
Figure 5-22 Varied FBLOFFST output static operation mode
Micronas 5-35
94x2A (A32)
5.2.9 activity overflow detection
Preliminary Data Sheet 10.2001
System Description
important know whether input used not. Therefore detection circuit gives information microcontroller. circuit uses value input. greater than threshold five clock cycles (FBLCONF), register FBLACTIVE set. This register reset when read microcontroller. PFBL, indicate overflow corresponding (upper limit: ADC=255) exceeding clock cycles duration. These signals also overflow reset reading only.
Input Processing
HSYNC Complete picture area NALPFIP (not active lines input)
VSYNC
Active picture
ALPFIP (Active lines input)
NAPPLIP (not active pixel line input)
APPLIP (active pixel line input)
Figure 5-23 Image format before memory
5.3.1
Horizontal Prescaler (sample-rate-converter)
main application conversion data coming from 40.5/20.25MHz pixel clock domain down number pixels stored memory (factor 2/3). Generally number incoming pixels decimated factor between granularity output pixels. horizontal scaler reduces number incoming pixels subsampling. prevent introduction alias distortion pass filters used luminance chrominance processing (Figure 5-24). case ITU656 input, lowpass filter must disabled HAAPRESC. horizontal prescaler consists main subsampling stages. first stage scaler rational decimation factors range controlled HSCPRESC.
Micronas 5-36
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description second stage (moving target average) filter integer decimation factors (1,2,3,4.32), controlled HDCPRESC. architecture filter automatically adapts pass filter characteristic used subsampling factor.
decimation filter
Attenuation (dB)
Attenuation (dB)
decimation filter
Frequency (MHz)
Frequency (MHz)
Figure 5-24 decimation filter characteristic standard operation (1.5)
5.3.2
Noise Reduction
Figure 5-25 shows block diagram motion adaptive temporal noise reduction (first order filter). structure temporal motion adaptive noise reduction same luminance chrominance signal. Noise reduction enabled NRON.
Ydelay
motion detection
Ydelay
noise reduction
Yout
TNRCLY TNRABS TNRCLC UVin UVdelay
TNRSxY NRON TNRSxC TNRSEL UVin UVdelay
motion detection
noise reduction
UVout
Figure 5-25 Temporal noise reduction equation below describes behavior temporal adaptive noise reduction filter. same equation valid chrominance signal. Depending motion input signal, K-factor (Kuv) adjustable between motion)
Micronas 5-37
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description (motion) motion detector. K-factor chrominance filter either (output luminance motion detector, TNRSEL=0) (output chrominance motion detector, TNRSEL=1). delay feedback path field delay.
delay delay
delay delay
output motion detector weighted TNRCLC TNRCLY. output mapped values look-up-tables (LUT input value range separated into segments, where segment covers range 0.3, segment covers range etc. segment covers range 48.63 motion value.
TNRSx=0000
TNRSx=0001
TNRSx=0010
TNRSx=0011
TNRSx=0100
TNRSx=0101
TNRSx=0110
TNRSx=0111
TNRSx=1000
TNRSx=1001
TNRSx=1010
TNRSx=1011
TNRSx=1100
TNRSx=1101
TNRSx=1110
TNRSx=1111
Figure 5-26 Segments
Micronas
5-38
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description possible define predefined curve characteristic each segment. curve characteristics programmed parameters TNRSxY luminance TNRSxC chrominance. curve-start defined TNRSSY (TNRSSC) last segment. overall curve constructed connecting segment beginning segment Negative values (Kuv) possible clipped zero. continuous mapping motion values (Kuv) values result.
Ky/Kc 0001
TNRSSY, TNRSSC
1111
1111
0100
0100
0100
0000
0000
TNRSY, TNRSC
motion
Figure 5-27 Predefined curve characteristics
5.3.3
Noise Measurement
noise measurement algorithm used change parameters temporal noise reduction processing depending actual noise level input signal. This done microcontroller which reads noise level (NOISEME), sends different parameter sets temporal noise reduction registers 94x2A depending this value (0=no noise, 30=strong noise). Value indicates overflow status which means that measurement failed. line taken noise measurement selected NMLINE. When NOISEME contains updated data which read far, NMSTATUS set. NMSTATUS reset when read.
Micronas
5-39
94x2A (A32)
5.4.1 Output Processing Horizontal Postscaler
Preliminary Data Sheet 10.2001
System Description
After field memory, display processing performed using different clock. this decoupling input output clocks achieved. conversion display clock done interpolation filter. This used horizontal expansion range steps pixels (HSCPOSC). increased clock frequency backend part instead 27MHz), horizontal expansion factors result 0.75 This ensures that factor 0.75 gives loss resolution. This used show picture 16:9 tube.
HSCPOSC
horizontal filter expansion
overall expansion
remark
1024 (minimum) 2048
1.33
biggest picture 16:9 picture 16:9 tube 16:9 picture tube picture tube picture 16:9 tube
3072 4095 (maximum) Table
0.75
Horizontal expansion factors
1024 Overall Expansion
Horizontal Postscaler
4095
0.75
1000
2000
3000
4000
Figure 5-28 Expansion factor horizontal postscaler dependent HSCPOSC
Micronas
5-40
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description Because nonlinear characteristic integer number pixel, sometimes different HSCPOSC values result same decimation factors.
5.4.2
Panorama Mode
picture geometrically distorted horizontal direction improved impression case expansions pictures 16:9 ratio tube. enabled HPANON. idea behind this panorama mode keep middle part picture ratio stretch left right fill entire width 16:9 screen. adjustment expansion process, picture divided into segments. each these segments increment value expansion factor defined separately.
INC_VAL 31.875 HINC0 HINC1 HINC2 HINC3 HINC4 HSEG1 HSEG2 HSEG3 HSEG4 max. output pixels
HSCALE 4095 3072 compression
expansion HSCPOSC
1024 HSEG1 HSEG2 HSEG3 HSEG4 max. output pixels
Figure 5-29 Visualization panorama segments Each segment defined individually granularity output pixels. every segment increment value defined (HINC0.HINC4) which indicates amount decimation/expansion. equivalent offset 0.125 HSCPRESC double pixel. This means that with HINC, HSCPRESC altered range from -32.31.875 double pixel. segments distributed among
Micronas 5-41
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description maximum number pixels, which adjusted PPLOP. first four segments defined (HSEG1.HSEG4). last goes from HSEG4 PPLOP.
16:9
max=3
expansion compression
min=0.75
HSEG1
HSEG2
HSEG3
HSEG4
Figure 5-30 Panorama expansion Examples given Table 5-8:
Micronas
5-42
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
Function
panorama
extreme pan.
lens
custom
HSCPOSC HSEG1 HSEG2 HSEG3 HSEG4 HINC0 HINC1 HINC2 HINC3 HINC4 APPLOP Table
2099d 192d 288d 384d 000d 492d 472d 960d
1023d 192d 288d 384d 000d 469d 427d 960d
3999d 192d 288d 384d 472d 492d 000d 960d
Examples panorama modes
5.4.3
Operation Modes
There four operation modes defined. first mode simple AABB, where each stored field memory displayed double times screen. second third mode AAAA BBBB, which only field phase will displayed screen. There also AAAA mode with raster possible. Figure 5-31 explains picture display raster.
Micronas
5-43
94x2A (A32)
FRAME/FIELD
FRAME
Preliminary Data Sheet 10.2001
System Description
FIELD lines
FIELD even lines
Content picture
DISPLAY LINE-SCANNING PATTERN
Display raster lines Display line-scanning pattern
even lines
Display line-scanning pattern
Tube, Display raster
Figure 5-31 Explanation field display line-scanning pattern interlaced input signal (e.g. NTSC) composed field (odd lines) field (even lines). Input signal, field time Input signal, field time
Micronas
fieldras01
5-44
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description field information describes picture content. output signal, which could contain different picture contents (e.g. field field displayed with display raster Output signal, field time displayed raster Output signal, field time displayed raster Table describes different scan rate conversion algorithms 94x2A corresponding raster sequences.
Input field STOPMODE Table
Input field
Scan rate Output field Output field Output field Output field conversion phase phase phase phase AABB mode AAAA mode AAAA mode BBBB mode
Operation modes scan-rate conversion
Figure 5-32 explains 50/60Hz interlaced 100/120 interlaced conversion including field signal, raster organization memory timing AABB.
Micronas
5-45
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
line number memory
An+1
write
time An+1
OPDEL
An+1
read
raster_org
field
Figure 5-32 50/60 interlaced 100/120 interlaced conversion (AABB) still field displayed using FREEZE command. improvement signals, chrominance shifted line upwards CHRSHFT
Display processing
display processing part contains integrated triple 9-bit performs digital enhancements manipulations digital video component signal. Figure shows block diagram display processing part.
Micronas
5-46
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
YCOR, HCOF, BCOF
COARSEDEL
CHROMAMP
FINEDEL
OFFSETDY, OFFSETDUV PKLY,PKLU,PKLV,
Peaking
Delay
Coarse Delay 8:8:8
Fine Delay
ayout auout avout
DCTI 4:4:4
THRESHC, ASCENTCTI
ITU656 Encoder
656out 656clk
SHIFTUV, ENABLE656
Figure 5-33 Block diagram Display processing
5.5.1
Peaking
luminance peaking filter improves overall frequency response luminance channel. consists filters working parallel. They have high pass (HP) band pass (BP) characteristics. Their gain factors programmable separately (BCOF, HCOF). Values greater than peak signal, whereas values less than attenuate signal. high pass band pass filters equipped with common coring algorithm. optimized achieve smooth display grey scales, improve signal-to-noise ratio. Therefore artifacts produced. Coring switched (YCOR). Figure 5-34 shows block diagram peaking block.
GAINB coring
GAINH
Peak_in
Peak_out
Figure 5-34 Block diagram peaking transfer function separate filters listed below:
Micronas
5-47
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
PEAKING GAINH AINB
Peaking filter characteristic
BCOF
HCOF
gain[dB]
normalized Frequency
Figure 5-35 Peaking filter: Bandpass Highpass filter peaking filter clock frequency CLKB36 MHz). maximum signal frequency picture stored memory 6.75 MHz. peaking after postscaler, frequency range peaking filter varies with expansion factor postscaler.
Micronas
5-48
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
expansion factor postscaler 0.75 Table
corresponding frequency corresponding frequency input signal center input signal center frequency bandpass (B=0.25) frequency highpass (B=0.5) 3.375 13.5 6.75
Peaking filter adaption
BCOF Table
GAINBP -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.50 3.00 4.00
HCOF
GAINHP -0.75 -0.50 -0.25 0.00 0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00 2.50 3.00 4.00
Conversion table between HCOF/BCOF GAINHP/GAINBP
Micronas
5-49
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
5.5.2
Digital color transition improvement (DCTI)
digital algorithm implemented improve horizontal transitions chrominance signals resulting better picture sharpness. correction signal proportional slope detected horizontal transition input signal added original input signal. Different correction signals selected according bandwidth input signal. amplitude correction signal adjustable parameter ASCENTCTI. exact position color transition calculated detecting corresponding zero transition second derivative both chrominance signals. pass filtering performed avoid noise sensitivity. parameter THRESHC modifies sensitivity DCTI circuit. High values THRESHC result improvement only significant color transitions. Small color variations remain unchanged. eliminate "wrong color" transitions, which caused over- undershoots chroma transition, sharpened chroma signals automatically limited proper value.
chrom inance signal
chrom inance signal plus correction signal
chrom inance signal plus correction signal itation
Figure 5-36 Principles DCTI
5.5.3
Coarse fine delay
Before digital-to-analog conversion adjustment phase luminance performed. coarse delay from steps pixel CLKB36 (~28 possible (COARSEDEL). FINEDEL shifts luminance CLKB72 (~14 pixel. This used compensate delays, when externally processed differently (e.g. lowpass filtered).
5.5.4
Oversampling
After conversion into 8:8:8 format (CLKB72=72MHz), three 9-bit digital-to-analog converters used analog output. This twofold-oversampling generates 1920 active pixels line (when using recommended settings) simplifies external
Micronas 5-50
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description postfiltering. Output voltage determined PKLY, PKLU PKLV range .1.9 (fullscale). value 'black' influenced OFFSETDY OFFSETDUV. When coupling backend processor (normally used), should zero.
PKLY upper headroom peaking conversion range
CHROMAAMP= PKLU PLLV
max.
max.
normal signal range
max. 0.95
max.
CHROMAAMP= color'
'black'
lower headroom peaking
OFFSETDY
OFFSTDUV
Figure 5-37 output signals bits luminance converter used entire signal. used over- undershoots caused peaking prevent reduce clipping artifacts. block seldomly produces such overshoots, full-scale operation activated CHROMAMP. output voltages calculated
PKLY OFFSETDY VoltageY 1.56V 0.36V signalY 160.400 signalY unpeaked signals max. 0.511 signalY peaked signals max.
PKLU, OFFSETDUV VoltageU, 1.56V 0.36V CHROMAMP signalUV 128.384 signalUV -512
5.5.5
Output-Sync Controller
output sync controller generates horizontal vertical synchronization signals scanrate-converted output signal.
Micronas
5-51
conversion range
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
HSYNC Complete picture area NALPFOP (not active lines output) LPFOP (lines output)
VSYNC
Active picture
ALPFOP (Active lines output)
NAPPLOP (not active pixel line output) PPLOP
APPLOP (active pixel line output) (pixel line output)
Figure 5-38 Image format behind memory number pixels line 4*PPLOP. default value results 1152 pixels/line. With CLKB=36MHz, horizontal output frequency 31.25 kHz, which twice horizontal frequency. these pixels, 16*APPLOP displayed active picture area, which default. position screen depends NAPPLOP. marks picture area active horizontal direction moves active picture horizontal direction. number lines field 2*LPFOP. This value only used vertical free-running mode. vertical locked mode, number lines field derived from CVBS signal itself adjustable. active non-active picture areas marked ALPFOP NALPFOP, respectively. Both generators have called "locked-mode" "freerunning-mode". combinations these modes make sense.The Table shows ingenious configurations.
Mode 'H-and-V-locked' mode 'H-freerunning V-locked' mode 'H-and freerunning' mode Table
HOUTFR
VOUTFR
Ingenious configurations HOUT VOUT generator
Micronas
5-52
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description freerun mode backend part works stand alone without analyzing input signals. clock domains, input data part output data part related each other. output processing works freerun mode, output signals generated depending settings. locked mode backend part works with line locked clock. This means that frontend backend depend each other. generation controlling signals depends output signals from frontend. This mode will default most used mode standard applications. With activated vertical freerun mode phase generated vsync signal correlation incoming vsync signal. hard switch from freerun mode locked mode would therefore cause visible synchronization problems deflection unit concerning vertical picture positioning. avoid these problems circuit implemented which synchronizes free running vsync signal vsync derived from CVBS signal, enable soft transition locked mode (PDGSR, LPFOPOFF). This synchronization only possible when number CVBS input lines corresponds programmed value LPFOP. When very weak signal connected CVBS input, configured automatically switch into freerunning mode. This stabilizes display which contain information, e.g. during channel-tune. configuration, whether switches H-freerun, V-freerun both configured AUTOFRRN.
5.5.5.1
HOUT Generator
HOUT generator operation modes, which selected parameter HOUTFR. HOUT signal active high clock cycles (CLKB36). freerunning-mode HOUT signal generated depending PPLOP parameter. locked-mode HOUT signal locked incoming H-Sync signal derived from CVBS. polarity HOUT signal programmable parameter HOUTPOL.
5.5.5.2
VOUT Generator
VOUT generator operation modes, which selected parameter VOUTFR. freerunning-mode (VOUTFR=1) VOUT signal generated depending LPFOP parameter. locked-mode VOUT signal synchronized incoming V-Sync signal derived from CVBS, delayed some lines (OPDEL). During incoming V-Sync signal, VOUT pulses have generated. polarity VOUT signal programmable parameter VOUTPOL. VOUT signal active high output lines.
Micronas
5-53
94x2A (A32)
Display line scanning pattern sequence Table 312.5 312.5 312.5
Preliminary Data Sheet 10.2001
System Description
312.5
5.(1.) 312.5 312.5
Display line scanning pattern sequence
5.5.5.3
BLANK Generator
BLANK signal used horizontally mark active picture area. enabled BLANEN polarity chosen BLANPOL. Referred hsync, start given BLANDEL length given BLANLEN, both adjustable pixel resolution.
5.5.5.4
Background Generator
This generator able realize automatic closing opening displayed picture. This means that with every picture displayed colored background, defined UBORDER, VBORDER YBORDER will bigger smaller. original picture data will replaced background values vice versa. There also possibility realize fixed border (BORDPOSH BORDPOSV). 4096 different colors available. BORDPOSH BORDPOSV also influence window generation. This means automatic opening closing picture will start position which defined with these values. border calculated with following formula: horizontal border left side screen 2*BORDPOSH 2*BORDPOSH right side screen. This means, that 4*BORDPOSH pixels overwritten with border values. same applies vertical direction. 4*BORDPOSV lines total overwritten with background values. BORDERV decides whether upper lower both borders displayed. BORDERH decides whether left right both borders displayed.
5.5.5.5
Window function
Figure 5-39 shows functionality horizontal window function. window closed opened.
Micronas
5-54
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
close window
open window
Figure 5-39 Horizontal windowing windowing feature enabled WINDHON parameter. WINDHST WINDHDR parameter determine, what status (opened closed) window has, what done with window (open close). With each enabling window function WINDHON parameter, status window will defined WINDHST WINDHDR. change from ,,close" ,,open" vice versa only WINDHDR parameter toggled. speed window defined WINDHSP parameter. Figure 5-40 shows functionality vertical window function.
close window
open window
Figure 5-40 Vertical windowing settings also available vertical direction. parameters exist both directions (e.g. WINDHON WINDVON horizontal vertical window enabling). Combinations both window functions (horizontal vertical) also possible.
Micronas
5-55
94x2A (A32)
close window
Preliminary Data Sheet 10.2001
System Description
open window
Figure 5-41 Horizontal vertical windowing
5.5.6
Digital input
decodes digital 8bit@27MHz data stream according ITU.BT656 standard. input selected EN656. EN_656 Table ENABLE656 operation input disabled output disabled input disabled output enabled input enabled output disabled (reserved)
input output selection
Four modes supported: IMODE operation full mode (automatic) information about active picture taken from data-stream full mode (manual) information about active picture taken from APLLIP, NAPPLIP, ALPFIP, NALPFIP ITU656 only data, H/V-sync according PAL/NTSC ITU656 only data, H/V-sync according ITU656 modes
Table
adjust input sources, which deviate from standard, field information inverted (F_POL) chrominance format chosen between unsigned
Micronas
5-56
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description complement format (CFORMAT). polarity inverted H_POL V_POL respectively.
5.5.7
Digital output
output data format corresponds CCIR (8-bit data rate MHz). Timing reference codes (SAV, EAV) inserted according specification. output enabled ENABLE656. display clock should linelockedclock (HOUTFR) with (PPLIP) pixels line (APPLOP). chrominance information inverted CHRMSIGN656. digital input output same pins, digital input possible when digital output chosen (9402/9432). versions 9412 9442 equipped with double-scan '656-like' output. frequencies data-rates doubled compared standard ITU656 signals.
Clock Concept
single 20.25 crystal fundamental mode used clock reference. other clocks derived from this source. CVBS frontend works with 20.25 MHz, frontend works with 40.5 MHz, oversampling DACs 72.0 memory parts behind memory clocked with MHz. Three different clock concepts supported. difference behavior clocking memory output. frontend part 94x2A uses free-running crystalstable clock (CLKF). After deskewing, orthogonal picture written into memory. read done using (CLKB) clock. horizontal sync-signal output (HOUT) derived from counter running with CLKB. VOUT directly derived from input vertical signal, which generated sync-separation block. This 'H-freerunning-V-locked mode' only possible together with coupled deflection controller. 'H-and-V-locked mode' CLKB line-locked incoming signal. freerunning picture data internal signal converted line-locked domain. HOUT sync signal domain directly coupled. case 'H-and-V-freerunning mode' HOUT VOUT signals derived from counters running with CLKB. There connection incoming signal. This mode used stable pictures when signal applied (e.g. channel search with insertion)
Micronas
5-57
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
name
clock
nominal frequency
'H-and-Vlocked' mode
'HfreerunningV-locked' mode
'H-and freerunning' mode
CLKF20 CVBS frontend
20.25
CLKF40 frontend, 40.5 input processing CLKB36 output display processing CLKB72 oversampling, 9402: (analog out) 9412: (digital out) 9432: (analog out) 9442: 13.5 (digital out) 9402: 9412: 9432: 9442: 9402: 9432: 13.5 (analog out) 9412: 20.26 9442: 10.13
CLKB27 CLKOUT-pin
Table
Clock system
clock output 27MHz version:13.5 MHz) possible (pin 27:clkout). This clock CLKB36. HOUT VOUT line with this sampling clock. clock output disabled CLKOUTON. Additionally 20.25 clock output (656hin/clkf20) supply other (e.g. PiP) with same clock (CLKF2PAD). When enabled, 656-input with separate H/V-sync possible. 656-output operation, CLKB36 given (656clk).
Micronas
5-58
94x2A (A32)
5.6.1 Linelocked Clock Generator
Preliminary Data Sheet 10.2001
System Description
clock generation system derives clocks from 20.25 crystal oscillator clock source. internal multiplies this generating clock which used reference clocks needed.
20.25
xtal
648MHz
frequency divider
freerunning clocks integer fractions 648MHz 20.25MHz freerunning
KINL, KPNL, KPL, KIL, FION, FILE, HSWIN CLKF20 CLKF40
analog CVBS
interpolation
syncseparation
phase detector
loop filter
216MHz frequency
CLKB27 CLKB36 CLKB72
divider
FMOD
freerun IICINC
Figure 5-42 Linelocked clock generation Linelocked horizontal sync pulses generated digital phase locked loop. time constant adjusted between fast slow behavior (KPL, KIL) accommodate different input sources (e.g. VCR). Noisy input signals become more stable when noise-reduction enabled (HSWIN). control frozen lines before v-sync (FION) duration lines (FILE). This used reduce disturbances h-phase errors which produced VCR's. Because delay between read write pointer field memory (Figure 5-32), incoming 50Hz v-sync lies active picture area. output frequency 100/120 version dependent IICINCR
display
IICINC 103Hz
value internally divided 50/60 version.
Micronas
5-59
94x2A (A32)
Preliminary Data Sheet 10.2001
System Description
nominal 50Hz operation (analog out)
13.5
nominal 50Hz operation (digital out) nominal 100Hz operation (analog out) nominal 100Hz operation (digital out)
Figure 5-43 Allowed operation area clock generation number pixels generated given PPLIP. linelocked clock generation following equation must fulfilled:
PPLIP PPLOP (9402A, 9412A) PPLIP PPLOP (9432A, 9442A)
Operation
100/120 (analog out) 50/60 (analog out) 100/120 (digital out) 50/60 (digital out)
PPLIP
2304 2304 1728 1728
IICINCR
349525 349525 262229 262229
PPLOP
1152 1152
CLKB36
13.5
31.25 15.625 31.25 15.625
Table
LL-PLL settings
settings different operation modes seen Table
Micronas
5-60
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
I2C-bus
slave address
When (adr/tdi) connected Vss, VSP94x2A reacts first address. second address active when connected Write Address1: Read Address1:
Write Address2:
Read Address2:
format
94x2A interface acts slave receiver slave transmitter provides different access modes (write, read). modes with subaddress auto increment. interface supports normal transmission speed well high speed transmission. write:
Start condition Repeated Start condition Acknowledge Stop condition Acknowledge read:
Subaddress
Data Byte
*****
Data Byte
Subad1 dress
Data Byte
Micronas
6-61
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus transmitted data internally stored registers. registers located four different clock domains. Figure shows four different clock domains 94x2A. clock domains called CVBS processing block (20.25 domain, clkf20), Front processing block (40.5 domain, clkf40), Back processing block (36.0 domain, clkb36) processing block (36.0 domain, clkf36).
Domain CP-CD CP-PP CP-I2C FP-PRE FP-MC FP-RGB FP-TNR FP-I2C PP-I2C BP-DP BP-PM BP-ODC BP-ODC/MC BP-POS BP-DAC BP-I2C Table clock domains
Description CVBS frontend LL-PLL read prescaler memory-controller Frontend temporal noise reduction read LL-PLL read display processing Pixel-Mixer output data control output data control/ memory-controller postscaler processing read
Clock CLKF20 CLKF20 CLKF20 CLKF40 CLKF40 CLKF40 CLKF40 CLKF40 CLKF36 CLKF36 CLKB36 CLKB36 CLKB36 CLKB36 CLKB36 CLKB72 CLKB36
registers themselves grouped interface block, each domain. transmitted data received kernel. kernel itself located domain. This means that working frequency 20.25 MHz. data transmitted interface blocks internal serial bus. write process, master write 'don't care' byte subaddress (store command) make register values available four
Micronas 6-62
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus interface blocks (except not-take-over registers). order have defined time step several blocks different domains, where data will available from interface blocks, data made valid with internal V-sync related signals (rising edge), depending different clock domains. subaddresses, where data made valid with V-sync signal 20.25 domain indicated overview subaddresses with ,,V20", others called "V40", "V36F" "V36B", respectively. parameter V20STAT, V40STAT V36BSTAT reflect state register values. these bits read '1', then store command sent, data made available yet. these bits then data made valid write read cycle start. bits V20STAT, V40STAT V36BSTAT checked before writing reading data, otherwise data lost overwriting. V36FSTAT register exist. make register values available four interface immediately after sending, master write 'don't care' byte subaddress (store command).
cvbs1 cvbs2 cvbs3 cvbs4 cvbs5 cvbs6 cvbs7 cvbso1 cvbso2 cvbso3 b/u1 g/y1 r/v1 fbl/hin1 b/u2 g/y2 r/v2 fbl/hin2
xout
36.0F
(PLL processing block)
72,0 27,0 36,0B
vout hout 27.0
20,25
(CVBS processing block)
40,5
(Back processing block) HPOSTSCALE PICIMPROVE DELAY
HPRESCALE
(Front processing block)
ayout auout avout
94x2A
hout50 vout50
Figure
clock domains
read process, master must send store command. order have defined time step interface blocks different domains, where data will available from different blocks, data made valid with same V-Sync related signals mentioned above write process. 94x2A distinguishes between different types read-registers. behavior "normal" read registers does differ from behavior write registers.Only direction data flow opposite. typ" read registers behave differently. They only (means value internal blocks using rising edge corresponding signal. After reading master, registers will automatically reset
Micronas 6-63
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus (means value kernel/interface. example register NMSTATUS belongs typ" read registers. NMSTATUS signalizes value NOISEME. NMSTATUS read current noise measurement been updated. NMSTATUS read noise measurement value read. other typ" read registers work same way. typ" read registers will marked overview with short "rstyp" will have additional hint "Note: reset automatically when read/write" detailed command description. default registers made valid internal V-Sync related signals and, addition, store command sent write registers. registers, which should also made available immediately writing reading, marked with short take over mechanism). Registers which need hand-shake mechanism between interface different blocks marked with shortcut (Hand shake mechanism). This means that bits registers used when last register written. After PPLIP9-2 written, PPLIP1-0 must written allow these bits have effect. registers write parameter STOPMODE directly connected read registers parameter SMMIRROR. possible check protocol writing reading register STOPMODE SMMIRROR, respectively. transmitted data internally stored registers. Writing reading from existant register permitted does generate fault After switching bits 94x2A defined states, (refer Table after reset stays '1', until cancled software PORCNCL. This used decide during operation, whether program registers (e.g. after power failure reset) only altered ones (normal operation).
Micronas
6-64
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress
Default
take-over
Subaddress
Default
(spare)
take-over
NTO/HS NTO/rstyp NTO/HS
V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B
Micronas
6-65
94x2A (A32)
Subaddress
Preliminary Data Sheet 10.2001
I2C-bus
Default
take-over
V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B V36B
Subaddress
Default
take-over
V36B V36B V36B
Micronas
6-66
94x2A (A32)
Subaddress
autoincrement)
Preliminary Data Sheet 10.2001
I2C-bus
Default
take-over
no/rstyp
Subaddress
86-8F 90h-95h A5h-F5h F7h-FDh
Default
(spare) (spare)
take-over
V36B
(spare) (spare)
autoincrement)
take-over mechanism take-over mechanism take-over with V-sync domain take-over with V-sync domain take-over with V-sync backend 36.0 domain hand-shake mechanism required
register types write register read register reset register after reading
Rrstyp
V36B
Table
register characterization
Micronas
6-67
94x2A (A32)
AABYP ACCFIX ACCFRZ ACCLIM ADCSEL ADLCK ADLCKCC ADLCKSEL AGCADJ1 AGCADJ2 AGCADJB AGCADJF AGCADJG AGCADJR AGCFRZE AGCMD AGCRES ALPFIP ALPFOP APENSEL APPLIP APPLOP ASCENTCTI AUTOFRRN BCOF BELLFIR BELLIIR BGPOS BLANDEL BLANEN BLANLEN BLANPOL BORDERH BORDERV BORDPOSH BORDPOSV BRTADJ CFORMAT CHRF CHRMSIGN656 CHROMAMP CHROMSIGN CHRSF CHRSHFT CKILL CKILLS CKSTAT CLKF2PAD CLKOUTON CLKT CLMPD1
Preliminary Data Sheet 10.2001
I2C-bus
list alphabetical order
CLMPD1S CLMPD2 CLMPD2S CLMPHIGH CLMPLOW CLMPST1 CLMPST1S CLMPST2 CLMPST2S CLMPVG CLMPVRB CLPSTGY CLRANGE COARSEDEL COLON COMB CONADJ CONS CPLLOF CPLLRES CRCB CSTAND CVBOSEL1 CVBOSEL2 CVBOSEL3 CVBSEL1 CVBSEL2 DCLMPF DECTWO DEEMPFIR DEEMPIIR DEEMPSTD DETHPOL DETVPOL DISALLRES DISCHCH DISRES EIA770 EN_656 ENABLE656 ENLIM F_POL FBLACTIVE FBLCONF FBLDEL FBLOFFST FHDET FHFRRN FIELDBINV FILE FINEDEL FIOFFOFF FION FKOI FKOIHYS FLDINV FLINE FLNSTRD FMOD FREEZE FREQSEL GOFST H_POL HAAPRESC HCOF HDCPRESC HDTOTEST HINC0 HINC1 HINC2 HINC3 HINC4 HINCREXT HINP HORPOS HORWIDTH HOUTDEL HOUTFR HOUTPOL HPANON HPOL HRES HSCPOSC HSCPRESC HSEG1 HSEG2 HSEG3 HSEG4 HSWIN HTESTW HWID IFCOMP IICINCR IMODE ISHFT KINL KOIH NTCHSEL NTSCREF OFFSETDUV OFFSETDY OPDEL OSCPD PALDEL PALDET PALID PALIDL0 PALIDL1 PALIDL2 PALINC1 PALINC2 PALREF PDGSR KOIWID KPNL LIMII LIMIP LIMLR LMOD LMOFST LNSTDRD LOCKSP LPCDEL LPFLD LPFOP LPFOPFF LPPOST MIXGAIN MIXOP NALPFIP NALPFOP NAPIPPHI NAPPLIP NAPPLOP NMLINE NMSTATUS NOISEME NOSIGB NOSYNC NOTCHOFF NRON NRPIXEL NSRED 72h/ SMMIRROR SMOP STAB STABLL PFBL PKLU PKLV PKLY PLLTC PORCNCL PPLIP PPLOFF PPLOP PWTHD RBOFST RDCTRLDIS REFRON REFRPER REFTRIM REFTRIMCV REFTRIMCVRD REFTRIMEN REFTRIMRD REFTRIMRGB REFTRIMRGBRD RGBSEL SATNR SCADJ SCDEV SCMIDL SCMREL SCOUTEN SECACC SECACCL SECDIV SECINC1 SECINC2 SECNTCH SETSTABL SHAPERDIS SHIFTUV SKEWSEL SLLTHD SLLTHDV SLLTHDVP 8Fh/
Micronas
6-68
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
STANDBY STDET STOPMODE THRESHC THRSEL TNRABS TNRCLC TNRCLY TNRS0C TNRS0Y TNRS1C TNRS1Y TNRS2C TNRS2Y TNRS3C TNRS3Y TNRS4C TNRS4Y TNRS5C TNRS5Y TNRS6C TNRS6Y TNRS7C TNRS7Y TNRSEL TNRSSC
TNRSSY TRAPBLU TRAPRED TSTSHAPERI UBORDER USATADJ UVCOR UVDEL V_POL V20STAT V36BSTAT V40STAT VBORDER VDEL_EN VDELF_EN VDETIFS VDETITC VERSION VFLYWHL VFLYWHLMD VINP VOUTFR VOUTPOL VPOL
8Fh/
VSATADJ VSHIFT VSIGNAL VTHRH VTHRL WINDHDR WINDHON WINDHSP WINDHST WINDVDR WINDVON WINDVSP WINDVST WRCTRLDIS YBORDER YCDEL YCOR YCSEL YFDEL YUVSEL
Command Table
Note: Bits written with grey background intended user adjustable should default value written this data sheet according updated list ('application note settings') available from Micronas.
Micronas
6-69
94x2A (A32)
Subadd (Hex)
Preliminary Data Sheet 10.2001
I2C-bus
Data Byte
APPLIP7
APPLIP6
APPLIP5 HSCPRESC9 HSCPRESC1 NAPPLIP4 NALPFIP4 ALPFIP8 ALPFIP4 BLANDEL4 BLANLEN4 HAAPRESC0 BRTADJ4 CONADJ4 FBLOFFST4 FBLDEL1 RBOFST2 MIXGAIN4 USATADJ4 VSATADJ4 YFDEL4 UVDEL4 AGCADJR4 AGCADJG4 AGCADJB4 AGCADJF4 CFORMAT NMLINE4
APPLIP4 HSCPRESC8 HSCPRESC0 NAPPLIP3 NALPFIP3 HDCPRESC3 ALPFIP3 BLANDEL3 BLANLEN3 MLL3 BRTADJ3 CONADJ3 FBLOFFST3 FBLDEL0 RBOFST1 MIXGAIN3 USATADJ3 VSATADJ3 YFDEL3 UVDEL3 AGCADJR3 AGCADJG3 AGCADJB3 AGCADJF3 F_POL NMLINE3 NMLINE8
APPLIP3 HSCPRESC7 NAPPLIP9 NAPPLIP2 NALPFIP2 HDCPRESC2 ALPFIP2 BLANDEL2 BLANLEN2 MLL2 BRTADJ2 CONADJ2 FBLOFFST2 MIXOP1 RBOFST0 MIXGAIN2 USATADJ2 VSATADJ2 YFDEL2 UVDEL2 AGCADJR2 AGCADJG2 AGCADJB2 AGCADJF2 H_POL NMLINE2 TNRABS TNRS1Y2 TNRS3Y2 TNRS5Y2 TNRS7Y2 TNRSSC2 TNRS1C2 TNRS3C2 TNRS5C2 TNRS7C2 TNRCLC2
APPLIP2 HSCPRESC6 NAPPLIP8 NAPPLIP1 NALPFIP1 HDCPRESC1 ALPFIP1 BLANDEL1 BLANLEN1 MLL1 BRTADJ1 CONADJ1 FBLOFFST1 MIXOP0 GOFST1 MIXGAIN1 USATADJ1 VSATADJ1 YFDEL1 UVDEL1 AGCADJR1 AGCADJG1 AGCADJB1 AGCADJF1 V_POL NMLINE1 NRON TNRS1Y1 TNRS3Y1 TNRS5Y1 TNRS7Y1 TNRSSC1 TNRS1C1 TNRS3C1 TNRS5C1 TNRS7C1 TNRCLC1
APPLIP1 HSCPRESC5 NAPPLIP7 NAPPLIP0 NALPFIP0 HDCPRESC0 ALPFIP0 BLANDEL0 BLANLEN0 MLL0 BRTADJ0 CONADJ0 FBLOFFST0 FBLCONF GOFST0
APPLIP8 APPLIP0 HSCPRESC4 VDELF_EN NALPFIP7 APENSEL ALPFIP7 BLANDEL7 BLANLEN7
Input processing
HSCPRESC11 HSCPRESC10 HSCPRESC3 NAPPLIP6 NALPFIP6 NALPFIP8 ALPFIP6 BLANDEL6 BLANLEN6 WRCTRLDIS HSCPRESC2 NAPPLIP5 NALPFIP5 ALPFIP9 ALPFIP5 BLANDEL5 BLANLEN5 HAAPRESC1 BRTADJ5 CONADJ5 FBLOFFST5 FBLDEL2 SKEWSEL MIXGAIN5 USATADJ5 VSATADJ5 YFDEL5 UVDEL5 AGCADJR5 AGCADJG5 CLKF2PAD AGCADJB5 AGCADJF5 VSIGNAL NMLINE5
BRTADJ7 DECTWO ADCSEL CLMPVRB1 YUVSEL RGBSEL CLMPVG STANDBY1
BRTADJ6 CHRSF AABYP CLMPVRB0 SMOP MIXGAIN6 DCLMPF STANDBY0
frontend
MIXGAIN0 USATADJ0 VSATADJ0 YFDEL0 UVDEL0 AGCADJR0 AGCADJG0 AGCADJB0 AGCADJF0 EN_656 NMLINE0 TNRSEL TNRS1Y0 TNRS3Y0 TNRS5Y0 TNRS7Y0 TNRSSC0 TNRS1C0 TNRS3C0 TNRS5C0 TNRS7C0 TNRCLC0
NAPIPPHI1 IMODE1 NMLINE7
NAPIPPHI0 IMODE0 NMLINE6
TNRS0Y3 TNRS2Y3 TNRS4Y3 TNRS6Y3 TNRSSY3 TNRS0C3 TNRS2C3 TNRS4C3 TNRS6C3 TNRCLY3
TNRS0Y2 TNRS2Y2 TNRS4Y2 TNRS6Y2 TNRSSY2 TNRS0C2 TNRS2C2 TNRS4C2 TNRS6C2 TNRCLY2
TNRS0Y1 TNRS2Y1 TNRS4Y1 TNRS6Y1 TNRSSY1 TNRS0C1 TNRS2C1 TNRS4C1 TNRS6C1 TNRCLY1
TNRS0Y0 TNRS2Y0 TNRS4Y0 TNRS6Y0 TNRSSY0 TNRS0C0 TNRS2C0 TNRS4C0 TNRS6C0 TNRCLY0
TNRS1Y3 TNRS3Y3 TNRS5Y3 TNRS7Y3 TNRSSC3 TNRS1C3 TNRS3C3 TNRS5C3 TNRS7C3 TNRCLC3
Noise reduction
Micronas
6-70
94x2A (A32)
Subadd (Hex)
Preliminary Data Sheet 10.2001
I2C-bus
Data Byte
IICINCR17 IICINCR9
IICINCR16 IICINCR8
IICINCR15 IICINCR7
IICINCR14 IICINCR6 DISRES
IICINCR13 IICINCR5 IICINCR2
IICINCR12 IICINCR4 IICINCR1
IICINCR11
IICINCR18 IICINCR10
Line-locked clock
IICINCR3 IICINCR0 HRES
HSWIN2 KOIWID1 PPLIP9
HSWIN1 KOIWID0 PPLIP8
HSWIN0 KOIH1 PPLIP7
SETSTABLL KOIH0 PPLIP6
HTESTW3 PPLIP5
HINCREXT HTESTW2 PPLIP4
LMOD HTESTW1 PPLIP3 PPLIP1
FMOD HTESTW0 PPLIP2 PPLIP0
FION3 CLKT
FION2 CLKT
FION1 HWID
FION0 HDTOTEST FILE3 FILE2 FILE1 FILE0
YCOR1 HCOF3 AUTOFRRN1 ALPFOP7 BORDPOSV7 BORDPOSH7 BLANPOL UBORDER3 HORWIDTH7 WINDVSP1 HORPOS7 WINDHSP1 NOSYNC CHRSHFT HOUTDEL7 NAPPLOP9 NAPPLOP7 PPLOP9 PPLOP7 LPFOP7 OPDEL7 BORDERV1 NALPFOP7
YCOR0 HCOF2 AUTOFRRN0 ALPFOP6 BORDPOSV6 BORDPOSH6 BLANEN UBORDER2 HORWIDTH6 WINDVSP0 HORPOS6 WINDHSP0 PPLOFF2 APPLOP6 HOUTDEL6 NAPPLOP8 NAPPLOP6 PPLOP8 PPLOP6 LPFOP6 OPDEL6 BORDERV0 NALPFOP6 PALDEL.1
CLKOUTON HCOF1 ALPFOP9 ALPFOP5 BORDPOSV5 BORDPOSH5 BORDPOSH9 UBORDER1 HORWIDTH5 WINDVST HORPOS5 WINDHST PPLOFF1 APPLOP5 HOUTDEL5 PDGSR NAPPLOP5 REFRPER PPLOP5 LPFOP5 OPDEL5 BORDERH1 NALPFOP5 PALDEL.0
THRESHC2 HCOF0 ALPFOP8 ALPFOP4 BORDPOSV4 BORDPOSH4 BORDPOSH8 UBORDER0 HORWIDTH4 WINDVDR HORPOS4 WINDHDR PPLOFF0 APPLOP4 HOUTDEL4 FREEZE NAPPLOP4 REFRON PPLOP4 LPFOP4 OPDEL4 BORDERH0 NALPFOP4 LOCKSP1
THRESHC1 BCOF3 FINEDEL ALPFOP3 BORDPOSV3 BORDPOSH3 YBORDER3 VBORDER3 HORWIDTH3 WINDVON HORPOS3 WINDHON LPFOPFF3 APPLOP3 HOUTDEL3 STOPMODE1 NAPPLOP3 HOUTPOL PPLOP3 LPFOP3 OPDEL3 RDCTRLDIS NALPFOP3 LOCKSP0
THRESHC0 BCOF2
ASCENTCTI1 BCOF1
ASCENTCTI0 BCOF0
COARSEDEL2 COARSEDEL1 COARSEDEL0 ALPFOP2 BORDPOSV2 BORDPOSH2 YBORDER2 VBORDER2 HORWIDTH2 HORWIDTH10 HORPOS2 HORPOS10 LPFOPFF2 APPLOP2 HOUTDEL2 STOPMODE0 NAPPLOP2 VOUTPOL PPLOP2 LPFOP2 OPDEL2 LPFOP8 NALPFOP2 BGPOS2 ALPFOP1 BORDPOSV1 BORDPOSH1 YBORDER1 VBORDER1 HORWIDTH1 HORWIDTH9 HORPOS1 HORPOS9 LPFOPFF1 APPLOP1 HOUTDEL1 HOUTDEL9 NAPPLOP1 HOUTFR PPLOP1 LPFOP1 OPDEL1 NALPFOP8 NALPFOP1 BGPOS1 ALPFOP0 BORDPOSV0 BORDPOSH0 YBORDER0 VBORDER0
Display processing CVBS
HORWIDTH0 HORWIDTH8 HORPOS0 HORPOS8 LPFOPFF0 APPLOP0 HOUTDEL0 HOUTDEL8 NAPPLOP0 VOUTFR PPLOP0 LPFOP0 OPDEL0 OPDEL8 NALPFOP0 BGPOS0
Micronas
6-71
94x2A (A32)
Subadd (Hex)
Preliminary Data Sheet 10.2001
I2C-bus
Data Byte
HSEG1_7 HSEG2_7 HSEG3_7 HSEG4_7 FIOFFOFF CHRMSIG656 SHIFTUV CHROMSIGN PKLY7 PKLU7 PKLV7 HSEG1_6 HSEG2_6 HSEG3_6 HSEG4_6 FIELDBINV VDEL_EN ENABLE656 CHROMAMP PKLY6 PKLU6 PKLV6 HSEG1_5 HSEG2_5 HSEG3_5 HSEG4_5 HSEG2_10 HSEG4_10 OFFSETDY5 HSCPOSC7 HSCPOSC6 HSCPOSC5 HINC0_7 HINC1_7 HINC2_7 HINC3_7 HINC4_7
HINC0_6 HINC1_6 HINC2_6 HINC3_6 HINC4_6
HINC0_5 HINC1_5 HINC2_5 HINC3_5 HINC4_5
HINC0_4 HINC1_4 HINC2_4 HINC3_4 HINC4_4 HINC4_8 HSCPOSC4 HPANON HSEG1_4 HSEG2_4 HSEG3_4 HSEG4_4 HSEG2_9 HSEG4_9 OFFSETDY4
HINC0_3 HINC1_3 HINC2_3 HINC3_3 HINC4_3 HINC3_8 HSCPOSC3 HSCPOSC11 HSEG1_3 HSEG2_3 HSEG3_3 HSEG4_3 HSEG2_8 HSEG4_8 OFFSETDY3
HINC0_2 HINC1_2 HINC2_2 HINC3_2 HINC4_2 HINC2_8 HSCPOSC2 HSCPOSC10 HSEG1_2 HSEG2_2 HSEG3_2 HSEG4_2 HSEG1_10 HSEG3_10 OFFSETDY2
HINC0_1 HINC1_1 HINC2_1 HINC3_1 HINC4_1 HINC1_8 HSCPOSC1 HSCPOSC9 HSEG1_1 HSEG2_1 HSEG3_1 HSEG4_1 HSEG1_9 HSEG3_9 OFFSETDY1
HINC0_0 HINC1_0 HINC2_0 HINC3_0
Panorama scaler control
HINC4_0 HINC0_8 HSCPOSC0 HSCPOSC8 HSEG1_0 HSEG2_0 HSEG3_0 HSEG4_0 HSEG1_8 HSEG3_8 OFFSETDY0
OFFSETDUV5 OFFSETDUV4 OFFSETDUV3 OFFSETDUV2 OFFSETDUV1 OFFSETDUV0 PKLY5 PKLU5 PKLV5 PKLY4 PKLU4 PKLV4 PKLY3 PKLU3 PKLV3 PKLY2 PKLU2 PKLV2 PKLY1 PKLU1 PKLV1 PKLY0 PKLU0 PKLV0
Micronas
6-72
94x2A (A32)
Subadd (Hex)
Preliminary Data Sheet 10.2001
I2C-bus
Data Byte
CONS1 CON1 PWTHD0 DEEMPIIR.0 CSTAND6 CKILL6 CKILLS6 VPOL0 HUE6 NTSCREF6 PALREF6 SLLTHD0 AGCMD0 AGCFRZE CLMPHIGH6 CVBOSEL1_2 FLDINV HPOL0 HINP PLLTC0 CVBSEL2_2 CVBOSEL2_2 FHFRRN6 SATNR VSHIFT6 VTHRL6 VTHRH6 REFTRIM6 REFTRIMCV2 THRSEL SCMIDL0 ACCLIM3 CLMPD2S2 SLLTHDV0 DEEMPFIR1 FLNSTRD0 SECDIV NTCHSEL2 ADLCKSEL
CONS0 CON0 CLRANGE1 CHRF5 CSTAND5 CKILL5 CKILLS5 LPPOST HUE5 NTSCREF5 PALREF5 SCADJ5 AGCADJ15 AGCADJ25 CLMPHIGH5 CVBOSEL1_1 CLPSTGY FHDET CLMPST1_5 CLMPST2_5 CVBSEL2_1 CVBOSEL2_1 FHFRRN5 VINP VSHIFT5 VTHRL5 VTHRH5 REFTRIM5 REFTRIMCV1 CLMPST1S5 CLMPST2S5 ACCLIM2 CLMPD2S1 EIA770 DEEMPFIR0 ENLIM SECINC1_1 NTCHSEL1 ADLCKCC
COLON UVCOR1 CLRANGE0 CHRF4 CSTAND4 CKILL4 CKILLS4 YCDEL4 HUE4 NTSCREF4 PALREF4 SCADJ4 AGCADJ14 AGCADJ24 CLMPHIGH4 CVBOSEL1_0 YCSEL DISCHCH CLMPST1_4 CLMPST2_4 CVBSEL2_0 CVBOSEL2_0 FHFRRN4 NSRED1 VSHIFT4 VTHRL4 VTHRH4 REFTRIM4
CPLLOF UVCOR0 LMOFST1 CHRF3 CSTAND3 CKILL3 CKILLS3 YCDEL3 HUE3 NTSCREF3 PALREF3 SCADJ3 AGCADJ13 AGCADJ23 CLMPHIGH3 CLMPLOW3 CLMPD1_3 CLMPD2_3 CLMPST1_3 CLMPST2_3 CVBSEL1_3 CVBOSEL3_3 FHFRRN3 NSRED0 VSHIFT3 VTHRL3 VTHRH3 REFTRIM3
CRCB NOTCHOFF LMOFST0 CHRF2 CSTAND2 CKILL2 CKILLS2 YCDEL2 HUE2 NTSCREF2 PALREF2 SCADJ2 AGCADJ12 AGCADJ22 CLMPHIGH2 CLMPLOW2 CLMPD1_2 CLMPD2_2 CLMPST1_2 CLMPST2_2 CVBSEL1_2 CVBOSEL3_2 FHFRRN2 LPCDEL2 VSHIFT2 VTHRL2 VTHRH2 REFTRIM2
ACCFIX SECNTCH1 VDETIFS CHRF1 CSTAND1 CKILL1 CKILLS1 YCDEL1 HUE1 NTSCREF1 PALREF1 SCADJ1 AGCADJ11 AGCADJ21 CLMPHIGH1 CLMPLOW1 CLMPD1_1 CLMPD2_1 CLMPST1_1 CLMPST2_1 CVBSEL1_1 CVBOSEL3_1 FHFRRN1 LPCDEL1 VSHIFT1 VTHRL1 VTHRH1 REFTRIM1
ACCFRZ SECNTCH0 VDETITC CHRF0 CSTAND0 CKILL0 CKILLS0 YCDEL0 HUE0 NTSCREF0 PALREF0 SCADJ0 AGCADJ10 AGCADJ20 CLMPHIGH0 CLMPLOW0 CLMPD1_0 CLMPD2_0 CLMPST1_0 CLMPST2_0 CVBSEL1_0 CVBOSEL3_0 FHFRRN0 LPCDEL0 VSHIFT0 VTHRL0 VTHRH0 REFTRIM0
CONS2 CON2 PWTHD1 DEEMPIIR.1 COMB CKILL7 CKILLS7 VPOL1 HUE7 NTSCREF7 PALREF7 SLLTHD1 AGCMD1 AGCRES CLMPHIGH7 CVBOSEL1_3 FLINE HPOL1 NOSIGB PLLTC1 CVBSEL2_3 CVBOSEL2_3 FHFRRN7 REFTRIMEN VSHIFT7 PALIDL1 PALIDL0 REFTRIM7 REFTRIMCV3 SLLTHDVP SCMIDL1 ACCLIM4 CLMPD2S3 SLLTHDV1 DEEMPFIR2 FLNSTRD1 SECACC PORCNCL ADLCK
CVBS Frontend
REFTRIMCV0 REFTRIMRGB3 REFTRIMRGB2 REFTRIMRGB1 REFTRIMRGB0 CLMPST1S4 CLMPST2S4 ACCLIM1 CLMPD2S0 SHAPERDIS BELLFIR1 ISHFT1 SECINC1_0 NTCHSEL0 CLMPST1S3 CLMPST2S3 ACCLIM0 CLMPD1S3 OSCPD BELLFIR0 ISHFT0 SECINC2_1 CPLLRES CLMPST1S2 CLMPST2S2 IFCOMP2 CLMPD1S2 TSTSHAPERI BELLIIR1 NSRED2 SECINC2_0 DISALLRES PALIDL2 DEEMPSTD CLMPST1S1 CLMPST2S1 IFCOMP1 CLMPD1S1 FREQSEL1 BELLIIR0 VLP1 SCMREL1 TRAPBLU SECACCL1 PALINC1 CLMPST1S0 CLMPST2S0 IFCOMP0 CLMPD1S0 FREQSEL0 VFLYWHL VLP0 SCMREL0 TRAPRED SECACCL0 PALINC2
VFLYWHLMD1 VFLYWHLMD0
Micronas
6-73
94x2A (A32)
Subadd (Hex)
Preliminary Data Sheet 10.2001
I2C-bus
Data Byte
KPNL3 KINL3 LIMIP7 LIMII7 FKOI VERSION2 KPNL2 KINL2 LIMIP6 LIMII6 FKOIHYS VERSION1 VERSION0 REV2 KPNL1 KINL1 LIMIP5 LIMII5 KPNL0 KINL0 LIMIP4 LIMII4 KPL3 KIL3 LIMIP3 LIMII3 KPL2 KIL2 LIMIP2 LIMII2 LIMLR2 REV1 KPL1 KIL1 LIMIP1 LIMII1 LIMLR1 REV0 DETHPOL LNSTDRD LPFLD7 NRPIXEL7 REFTRIMRD7 REFTRIMRD6 REFTRIMRD5 REFTRIMRD4 REFTRIMRD3 DETVPOL LPFLD6 NRPIXEL6 STDET2 SCDEV5 LPFLD5 NRPIXEL5 STDET1 SCDEV4 LPFLD4 NRPIXEL4 STDET0 SCDEV3 LPFLD3 NRPIXEL3 SCOUTEN SCDEV2 LPFLD2 NRPIXEL2 STAB REFTRIMRD2 REFTRIMRD1 SMMIRROR1 PALID SCDEV1 LPFLD1 NRPIXEL1 NOISEME4 PFBL NOISEME3 NOISEME2 NOISEME1
FBLACTIVE NOISEME0 NMSTATUS STABLL SMMIRROR0 CKSTAT SCDEV0 LPFLD0 NRPIXEL0 PALDET REFTRIMRD0
Read register
REFTRIMCVR REFTRIMCVR REFTRIMCVR REFTRIMCVR REFTRIMRGB REFTRIMRGB REFTRIMRGB REFTRIMRGB VERSION2 VERSION1 VERSION0 V40STAT (reserved) V36BSTAT V20STAT KPL0 KIL0
read
LIMIP0 LIMII0 LIMLR0
take-over-indication (immediately) take-over-indication (after V-pulse)
Table
register overview
Micronas
6-74
94x2A (A32)
Command Description
Preliminary Data Sheet 10.2001
I2C-bus
Underlined values initialized power-on.
Subaddress D7-D0 APPLIP8-1 [FP-PRE] Active Pixel Line Number pixels stored memory Granularity: pixel '000000000': pixel '101010101': pixel '111111111': 1022 pixel
Subaddress D6-D0 APPLIP0 [FP-PRE] HSCPRESC1 [FP-PRE] belongs Control Signal HSCALE Horizontal Pre-scaler '000000000000': subsampling factor scaler stage '100000000000': subsampling factor (720 pixel) '100101010110': subsampling factor 1.583 (682 pixel) '111111111111': subsampling factor (540 pixel)
Subaddress D7-D3 HSCPRESC4- belongs [FP-PRE] NAPPLIP9-7 [FP-PRE] Active Pixel Line Granularity: clock cycles (~50 '0000000000': clock cycles '0001001000': clock cycles (~7.2 '1111111111': 2046 clock cycles (~51
6-75
D2-D0
Micronas
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress VDELF_EN [FP-PRE] NAPPLIP6-0 [FP-PRE] Vertical pulse delay frontend '0': delay '1': delayed belongs
D6-D0
Subaddress D7-D0 NALPFIP7-0 [FP-PRE] Active Lines Field (Input Processing) '000000000': lines '000010110': lines '111111111': lines
Subaddress APENSEL [FP-PRE] NALPFIP8 [FP-PRE] ALPFIP9-8 [FP-PRE] Active Pixel Enable Select count clock cycles (recommended CVBS/RGB input) count active pixels (recommended ITU656 input) belongs Active Lines Field '0000000000': active line '0100100000': active lines '1111111111': 1023 active lines
D5-D4
Micronas
6-76
94x2A (A32)
Subaddress D3-D0 HDCPRESC
Preliminary Data Sheet 10.2001
I2C-bus
Horizontal Pre-Scaler Decimates '0000': '0001': '0010': '0011': '0100': '0101': '0110': '0111': '1000': '1001':
Subaddress D7-D0 ALPFIP7-0 belongs
Subaddress D7-D0 BLANDEL Blanking signal delay Delay pixels from hsync active edge blank signal: Blank_start=4*BLANDEL '00000000': delay '00000001': pixel delay '11111111': 1020 pixel delay
Micronas
6-77
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 BLANLEN Blanking signal length Length pixels from start active blank signal: Blank_length=4*BLANLEN '00000000': pixel '11110000': pixel '11111111': 1020 pixel length
Subaddress WRCTRLDIS [FP-MC] HAAPRESC [FP-MC] Memory Write Control Circuit Disable '0': enabled '1': disabled Horizontal Anti Alias Filter '00': filter bypassed '01': force characteristic weak '10': force characteristic strong '11': automatic characteristic (weak strong) Note: normal CVBS/RGB full-screen, filter should weak automatic characteristic. ITU656 full-screen input, filter should bypassed. Strong characteristic split-screen only. D3-D0 [FP-MC] Minimum Line Length effective number clock periods: MLL*128 1110: corresponds 2392 clock periods
D5-D4
Micronas
6-78
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 BRTADJ [FP-RGB] Brightness Adjustment RGB/YUV input '10000000':-128 (darkest picture) '00000000': '01111111':+127 (brightest picture)
Subaddress DECTWO [FP-RGB] Decimation decimation RGB/YUV signal before soft-mix '0': decimation '1': decimation Additional Chroma subsampling filter '0': disabled '1': enabled Contrast Adjustment RGB/YUV input '000000': '000001': 1/32 '100000': '111111': 63/32
CHRSF [FP-RGB] CONADJ [FP-RGB]
D5-D0
Subaddress ADCSEL [FP-RGB] AABYP [FP-RGB] Select sync signal conversion '0': ADC_G '1': ADC_FBL Bypass RGB/YUV Antialiasfilter '0': filter '1': bypass
Micronas
6-79
94x2A (A32)
Subaddress D5-D0 FBLOFFST [FP-RGB] Fast Blank Offset Correction '000000': offset '111111': offset
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D6 CLMPVRB [FP-RGB] Clamping Value Blue '00': (B/R signal without sync) '01': (B/R signal with sync) '10': (U/V signal) '11': (reserved) Fast Blank Delay RGB/YUV Input granularity: '000': delay '010': delay '110': +100 delay '111': (reserved) Mixing Configuration '00': enable Soft-Mix '01': only path visible '10': only CVBS path visible '11': (reserved) Configuration FBLACTIVE signal '0': react after clock (25ns) active input '1': react after clock (125ns) active input
D5-D3
FBLDEL [FP-RGB]
D2-D1
MIXOP [FP-RGB]
FBLCONF [FP-RGB]
Subaddress YUVSEL [FP-RGB] Input Selection '0': expected '1': expected
6-80
Micronas
94x2A (A32)
Subaddress SMOP [FP-RGB] SKEWSEL [FP-RGB] RBOFST [FP-RGB] Softmix Operation Mode '0':dynamic '1':static
Preliminary Data Sheet 10.2001
I2C-bus
SKEW Correction RGB/YUV Channel '0':SKEW correction enabled '1':SKEW correction disabled (for PiP3, PiP4 only) Clamping Correction '000': (R/B, pedestal offset visible) '001': '010': (R/B with sync, pedestal offset visible) '011': '100': negative pedestal offset) '101': (UV) '110': positive pedestal offset) '111': (reserved) Clamping correction '00': (G/Y, pedestal offset visible) '01': '10': (G/Y with sync, pedestal offset visible) '11':
D4-D2
D1-D0
GOFST [FP-RGB]
Subaddress RGBSEL [FP-RGB] MIXGAIN [FP-RGB] Input selection '0': RGB/YUV input1 '1': RGB/YUV input2 Gain Fast Blank Signal '1000000': '0000000': '0111111': Note: proper operation dynamic softmix mode, absolute value MIXGAIN must bigger than (e.g.
Micronas 6-81
D6-D0
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress CLMPVG [FP-RGB] DCLMPF [FP-RGB] USATADJ [FP-RGB] Clamping Value '0': '1': Clamping Fast Blank input '0': enable clamping '1': disable clamping coupling) Saturation Adjustment '000000': '000001': 1/32 '100000': '111111': 63/32
D5-D0
Subaddress D7-D6 STANDBY [FP-RGB] Standby Mode '00': analog cores active '01': RGB/FBL ADCs Stand-By mode '10': RGB/FBL CVBS ADCs DACs Stand-By mode '11': DACs Stand-By mode Saturation Adjustment '000000': '000001': 1/32 '100000': '111111': 63/32
D5-D0
VSATADJ [FP-RGB]
Micronas
6-82
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D5-D0 YFDEL [FP-RGB] Y/FBL Delay Adjustment Granularity: '000000': delay '111111': 3.15
Subaddress D5-D0 UVDEL [FP-RGB] Delay Adjustment Granularity: '000000': delay '111111': 3.15
Subaddress D5-D0 AGCADJR [FP-RGB] Conversion Range Adjustment '000000': input signal '111111': input signal
Subaddress D5-D0 AGCADJG [FP-RGB] Conversion Range Adjustment Green '000000': input signal '111111': input signal
Micronas
6-83
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress CLKF2PAD [FP-RGB] AGCADJB [FP-RGB] Frontend clock given used h-input ITU656 '1': CLKF20 (20.25 MHz) given Conversion Range Adjustment Blue '000000': input signal '111111': input signal
D5-D0
Subaddress D7-D6 D5-D0 NAPIPPHI [FP-RGB] AGCADJF [FP-RGB] CbYCrY-phase shift '0': phase shift Conversion Range Adjustment Fast Blank '000000': input signal '111111': input signal
Subaddress D7-D6 IMODE [FP-RGB] Input format '00': full mode (automatic) '01': full mode (manual) '10': ITU656 only data, H/V-sync according PAL/NTSC '11': ITU656 only data, H/V-sync according ITU656 Input signal '0': interlaced '1': interlaced Chrominance data format '0': unsigned '1': complement
6-84
VSIGNAL [FP-RGB] CFORMAT [FP-RGB]
Micronas
94x2A (A32)
Subaddress F_POL [FP-RGB] H_POL [FP-RGB] V_POL [FP-RGB] EN_656 [FP-RGB] Field polarity '0': Field A=0, Field '1': Field A=1, Field H656 polarity '0': H656 active '1': H656 active high V656 polarity '0': V656 active '1': V656 active high ITU656-Input Interface '0': ITUI disabled '1': ITUI enabled
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 NMLINE7-0 [FP-TNR] Line Noise Measurement line line 311d: line (PAL) 261d: line (NTSC) Note: lines 3-260 standard dependent
Subaddress NMLINE8 [FP-TNR] TNRABS [FP-TNR] belongs Motion Detector Works Absolute Values: '0': absolute values calculated '1': absolute values calculated
Micronas
6-85
94x2A (A32)
Subaddress NRON [FP-TNR] TNRSEL [FP-TNR] Temporal Noise Reduction '0': disabled '1': enabled
Preliminary Data Sheet 10.2001
I2C-bus
Chrominance Motion Values From: '0': luminance motion detector '1': separate chrominance motion detector
Subaddress D7-D4 D3-D0 TNRS0Y [FP-TNR] TNRS1Y [FP-TNR] Curve Characteristic Luma Segment default value: 0001 Curve Characteristic Luma Segment default value: 1111
Subaddress D7-D4 D3-D0 TNRS2Y [FP-TNR] TNRS3Y [FP-TNR] Curve Characteristic Luma Segment default value: 1111 Curve Characteristic Luma Segment default value: 0100
Subaddress D7-D4 D3-D0 TNRS4Y [FP-TNR] TNRS5Y [FP-TNR] Curve Characteristic Luma Segment default value: 0100 Curve Characteristic Luma Segment default value: 0100
6-86
Micronas
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D4 D3-D0 TNRS6Y [FP-TNR] TNRS7Y [FP-TNR] Curve Characteristic Luma Segment default value: 0000 Curve Characteristic Luma Segment default value: 0000
Subaddress D7-D4 D3-D0 TNRSSY [FP-TNR] TNRSSC [FP-TNR] Start Value Luma default value: 1111 Start Value Chroma default value: 1111
Subaddress D7-D4 D3-D0 TNRS0C [FP-TNR] TNRS1C [FP-TNR] Curve Characteristic Chroma Segment default value: 0001 Curve Characteristic Chroma Segment default value: 1111
Subaddress D7-D4 D3-D0 TNRS2C [FP-TNR] TNRS3C [FP-TNR] Curve Characteristic Chroma Segment default value: 1111 Curve Characteristic Chroma Segment default value: 0100
6-87
Micronas
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D4 D3-D0 TNRS4C [FP-TNR] TNRS5C [FP-TNR] Curve Characteristic Chroma Segment default value: 0100 Curve Characteristic Chroma Segment default value: 0100
Subaddress D7-D4 D3-D0 TNRS6C [FP-TNR] TNRS7C [FP-TNR] Curve Characteristic Chroma Segment default value: 0000 Curve Characteristic Chroma Segment default value: 0000
Subaddress D7-D4 TNRCLY [FP-TNR] TNRCLC [FP-TNR] Luminance Classification '0000': strong noise reduction '1111': slight noise reduction Chrominance Classification '0000': strong noise reduction '1111': slight noise reduction
D3-D0
Micronas
6-88
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 IICINCR18-11 [PP] HDTO frequency Granularity=103 33981d (minimum: nominal pixel clock= MHz) 349525d (nominal pixel clock= MHz) 388362d (maximum: nominal pixel clock= MHz)
Subaddress D7-D0 IICINCR10-3 [PP] belongs
Subaddress DISRES [PP] IICINCR2-0 [PP] Reset LL-PLL watchdog '0': reset disabled '1': reset enabled belongs
D2-D0
Subaddress HRES [PP] Reset LL-HPLL '0':no reset '1':reset Note: reset automatically when written
Micronas
6-89
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D5 HSWIN [PP] Width Noise Suppression Window LL-HPLL '000':+/-28µs '001':+/-24µs '010':+/-20µs '011':+/-16µs '100':+/-12µs '101':+/-8µs '110':+/-4µs '111':dynamic windowing. Note: PPLIP<269d (=1076 pixel) only '101' '110' allowed SETSTABLL [PP] [PP] Stability Signal LL_HPLL '0': STABLL generated HPLL '1': STABLL forced Phase Detector Steepness '0': steepness normal operation mode '1': steepness operations where PPLIP less than 288d HDTO testmode '0': normal mode '1': line-locked-clocks derived from frontend line-length Selects line locked mode '0': line locked-clocks derived from HPLL '1': line-locked-clocks derived from frontend line-length Selects freerun mode '0': freerun-clocks derived from crystal '1': freerun-clocks derived from HDTO Note: Adjustable frequency only possible when '1'. When '0', Backend clock always (9432/42: 18MHz)
HINCREXT [PP] LMOD [PP] FMOD [PP]
Micronas
6-90
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D6 KOIWID [PP] Window-Width coincidence detector '00': pixel 0.9µs application) '01': pixel 1.8µs application) '10': pixel 3.6µs application) '11': pixel 7.2µs application) Hysteresis coincidence detector '00': lines '01': lines '10': lines '11': lines Test bits HPLL default
D5-D4
KOIH [PP]
D3-D0
HTESTW [PP]
Subaddress D7-D0 PPLIP9-2 [PP] Pixel Line Input (Input-Processing) Granularity=4 pixel '175d': (minimum) '576d': 2304 '963d': 3852 (maximum)
Subaddress D1-D0 PPLIP1-0 [PP] belongs
Micronas
6-91
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D4 FION [PP] [PP] Increment Freeze before V-sync '0': freeze '15': freeze starts lines before V-sync Dynamic Time Constant Control '0': linear mode '1': linear mode
Subaddress D7-D6 CLKT [PP] Switch clkf20 clkf40 pads cvbs1 bin2 (test only) '00': clock '01': cvbs1 output clkf40 '10': bin2 output clkf20 '11': cvbs1 output clkf40 bin2 output clkf20 Minimum width H-sync '0': 60*Tclkllf36 '1': 15*Tclkllf36 Test-bit HPLL '0': normal mode '1': test mode Increment Freeze duration '0': freeze '15': increment frozen lines
HWID [PP] HDTOTEST [PP] FILE [PP]
D3-D0
Micronas
6-92
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D6 YCOR [BP-DP] Luminance Coring '00': '01': '10': '11': clkout Pad: '0': (tristate) '1': Slope DCTI function '000': (DCTI off) '001': '010': '011': '100': '101': '110': '111': Gain DCTI function '00': '01': '10': '11':
CLKOUTON [BP-DP] THRESHC [BP-DP]
D4-D2
D1-D0
ASCENTCTI [BP-DP]
Micronas
6-93
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D4 HCOF [BP-DP] Peaking: High-Pass Filter Adjustments '0000': '0001': '0100': '1100': 12/4 '1101': 14/4 '1110': 16/4 '1111': 20/4 Peaking: Band-Pass Filter Adjustments '0000': '0001': '0100': '1100': 12/4 '1101': 14/4 '1110': 16/4 '1111': 20/4
D3-D0
BCOF [BP-DP]
Subaddress D7-D6 AUTOFRRN [BP-DP] Automatic freerun when sync-separartion stable '00': disabled (keep locked, selected) '01': vertical freerun '10': horizontal freerun '11': horizontal vertical freerun Active Lines Field Output '0000000000': (minimum) '0100100000': (default) '1111111111': 1023 (maximum)
6-94
D5-D4
ALPFOP9-8 [BP-DP]
Micronas
94x2A (A32)
Subaddress FINEDEL [BP-DP] COARSEDEL [BP-DP]
Preliminary Data Sheet 10.2001
I2C-bus
Luminance Fine Delay output '0': delay '1': CLKB72 (13.9 signal) Luminance Coarse Delay output Granularity: CLKB36 (27.8 signal) '000': CLKB36 '100': delay '111': CLKB36
D2-D0
Subaddress D7-D0 ALPFOP7-0 [BP-PM] belongs
Subaddress D7-D0 BORDPOSV [BP-PM] Borderposition Vertical Granularity: lines '00000000': border '11111111': border lines bottom
Subaddress D7-D0 BORDPOSH7 [BP-PM] Borderposition Horizontal Granularity: pixel '0000000000': border '1111111111': border 2048 pixel left right
Micronas
6-95
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress BLANPOL [BP-PM] BLANEN [BP-PM] BORDPOSH [BP-PM] YBORDER [BP-PM] Blanking signal polarity '0': active high '1': active Blanking signal enable '0': disabled (pin used 656vin) '1': enabled belongs
D5-D4
D3-D0
Luminance Value Border '0000':sub black '0001':black '1111':white
Subaddress D7-D4 UBORDER [BP-PM] Chrominance Value Border '1000': '0000': color' '0111': Chrominance Value Border '1000': '0000': color' '0111':
D3-D0
VBORDER [BP-PM]
Micronas
6-96
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HORWIDTH70 [BP-PM] Horizontal Picture Width Granularity: pixel '00000000000': display '00111100000': pixel '11111111111': 4094 pixel Note: Should equal APPLOP (3Dh)
Subaddress D7-D6 WINDVSP [BP-PM] Vertical Windowing: Speed '00': slow '01': medium '10': fast '11': very fast Vertical Windowing: Start '0': window closed '1': window open Vertical Windowing: Direction '0': open vertical window '1': close vertical window Vertical Windowing: Enable '0': '1': belongs
WINDVST [BP-PM] WINDVDR [BP-PM] WINDVON [BP-PM] HORWIDTH 10-8 [BP-PM]
D2-D0
Micronas
6-97
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HORPOS7-0 [BP-PM] Horizontal Position inside active picture area Granularity: pixel '00000000000': most left display position '11111111111': most right display position
Subaddress D7-D6 WINDHSP [BP-PM] Horizontal Windowing: Speed '00': slow '01': medium '10': fast '11': very fast Horizontal Windowing: Start '0': window closed '1': window open Horizontal Windowing: Direction '0': open horizontal window '1': close horizontal window Horizontal Windowing: Enable '0': '1': belongs
WINDHST [BP-PM] WINDHDR [BP-PM] WINDHON [BP-PM] HORPOS10-8 [BP-PM]
D2-D0
Micronas
6-98
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress NOSYNC [BP-ODC] PPLOFF [BP-ODC] horizontal synchronization '0': horizontal synchronization '1': horizontal synchronization Synchronization offset (for switching from hor. freerun mode locked mode) Granularity: pixel '000': '010': '111': Lines field offset: (for switching from vertical freerun mode locked mode) Granularity: lines '0000': '0110':12 '1111':31
D6-D4
D3-D0
LPFOPFF [BP-ODC]
Subaddress CHRSHFT [BP-O/M] Chrominance Shift shifts chrominance signal '0': shift '1': line upward Active Pixel Line Output: Granularity: pixel '0000000': pixel '0111100': pixel '1111111': 2032 pixel
D6-D0
APPLOP [BP-O/M]
Micronas
6-99
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HOUTDEL7-0 [BP-ODC] Sync output Delay: Granularity: pixel '0000000000':no delay '0000000001': pixel delay '1111111111':4092 pixel delay
Subaddress D7-D6 NAPPLOP9-8 [BP-O/M] Active Pixel Line Output: Granularity: pixel '0000000100': active pixel '1111111111': 4092 active pixel Switch Vsync transfer algorithm: '0': Vsync transfer algorithm enabled '1': Vsync transfer algorithm disabled Freeze picture '0': live '1': frozen (data writing disabled) Operation mode scan rate conversion: '00': AABB (Raster '01': AAAA (Raster '10': AAAA (Raster '11': BBBB (Raster belongs
PDGSR [BP-O/M] FREEZE [BP-O/M] STOPMODE [BP-O/M]
D3-D2
D1-D0
HOUTDEL9-8 [BP-O/M]
Micronas
6-100
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 NAPPLOP7-0 [BP-ODC] belongs
Subaddress D7-D6 PPLOP9-8 [BP-O/M] Pixel Line Output: Granularity:4 '0000000000': pixel '0100100000': 1152 pixel '1111111111': 4092 pixel Refresh period memory '0': '1': ~2,5 Refresh '0': memory refresh '1': memory refresh active HOUT polarity: '0': high active '1': active VOUT polarity: '0': high active '1': active HOUT freerun '0': locked mode '1': freerun mode VOUT freerun '0': locked mode '1': freerun mode
REFRPER [BP-O/M] REFRON [BP-O/M] HOUTPOL [BP-O/M] VOUTPOL [BP-O/M] HOUTFR [BP-O/M] VOUTFR [BP-O/M]
Micronas
6-101
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 PPLOP7-0 [BP-O/M] belongs
Subaddress D7-D0 LPFOP7-0 [BP-ODC] Lines Field Output: Only used freerun mode Granularity: lines '000000000': lines '010011100': lines '111111111:' 1022 lines
Subaddress D7-D0 OPDEL7-0 [BP-ODC] delay output operation: '000000000': delay '010101010': lines '111111111': lines
Subaddress D7-D6 BORDERV [BP-O/M] Border '00': both borders displayed '01': only lower border displayed '10': only upper border displayed '11': (reserved)
Micronas
6-102
94x2A (A32)
Subaddress D5-D4 BORDERH [BP-O/M]
Preliminary Data Sheet 10.2001
I2C-bus
Border '00': both borders displayed '01': only right border displayed '10': only left border displayed '11': (reserved) Memory read control circuit disable '0': enabled '1': disabled belongs Active Lines Output NALPFOP-1 lines active lines. '000000001':all lines active '000011001':24 lines active '111111111':510 lines active belongs
RDCTRLDIS [BP-O/M] LPFOP8 [BP-O/M] NALPFOP8 [BP-O/M]
OPDEL8 [BP-O/M]
Subaddress D7-D0 NALPFOP7-0 [BP-ODC] belongs
Subaddress D6-D5 PALDEL [CP-CD] PAL/NTSC delay SECAM (chrominance) '00': PAL/NTSC most left '11': PAL/NTSC most right
Micronas
6-103
94x2A (A32)
Subaddress D4-D3 LOCKSP [CP-CD]
Preliminary Data Sheet 10.2001
I2C-bus
Duration Chroma Search '00': fields '01': fields '10': fields '11': fields Burstgate Delay (SECAM only) Granularity: '000': most left (-400 '011': delay '111': most right
D2-D0
BGPOS [CP-CD]
Subaddress D7-D0 HINC0_7-0 [BP-POS] Horizontal Post-Scaler Increment '100000000': pixel '000000000': pixel '011111111':31.875 pixel
Subaddress D7-D0 HINC1_7-0 [BP-POS] Horizontal Post-Scaler Increment '100000000': pixel '000000000': pixel '011111111':31.875 pixel
Micronas
6-104
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HINC2_7-0 [BP-POS] Horizontal Post-Scaler Increment '100000000': pixel '000000000': pixel '011111111':31.875 pixel
Subaddress D7-D0 HINC3_7-0 [BP-POS] Horizontal Post-Scaler Increment '100000000': pixel '000000000': pixel '011111111':31.875 pixel
Subaddress D7-D0 HINC4_7-0 [BP-POS] Horizontal Post-Scaler Increment '100000000': pixel '000000000': pixel '011111111':31.875 pixel
Subaddress HINC4_8 [BP-POS] HINC3_8 [BP-POS] belongs belongs
Micronas
6-105
94x2A (A32)
Subaddress HINC2_8 [BP-POS] HINC1_8 [BP-POS] HINC0_8 [BP-POS] belongs belongs belongs
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HSCPOSC7-0 [BP-POS] Horizontal Scaling Factor Post Scaler '010000000000': factor '101101010101': factor 1.407 (682 960) '110000000000': factor (720 960) '111111111111': factor
Subaddress HPANON [BP-POS] HSCPOSC 11-8 [BP-POS] Panorama Mode enable '0': panorama mode disabled '1': panorama mode enabled belongs
D3-D0
Micronas
6-106
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 HSEG1_7-0 [BP-POS] Beginning Segment Panorama Mode Granularity: pixel '00000000000': pixel behind picture start '11111111111': 4094 pixel behind picture start
Subaddress D7-D0 HSEG2_7-0 [BP-POS] Beginning Segment Panorama Mode Granularity: pixel '00000000000': pixel behind picture start '11111111111': 4094 pixel behind picture start
Subaddress D7-D0 HSEG3_7-0 [BP-POS] Beginning Segment Panorama Mode Granularity: pixel '00000000000': pixel behind picture start '11111111111': 4094 pixel behind picture start
Subaddress D7-D0 HSEG4_7-0 [BP-POS] Beginning Segment Panorama Mode Granularity: pixel '00000000000': pixel behind picture start '11111111111': 4094 pixel behind picture start
Micronas
6-107
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress FIOFFOFF [BP-POS] FIELDBINV [BP-POS] HSEG2_10-8 [BP-POS] HSEG1_10-8 [BP-POS] Fieldoffset ITU656 NTSC signals '0': disabled '1': enabled Backend field inversion '0': inversion '1': inversion belongs belongs
D5-D3 D2-D0
Subaddress CHRMSIG656 [BP-POS] VDEL_EN [BP-POS] HSEG4_10-8 [BP-POS] HSEG3_10-8 [BP-POS] Chrominance format output '0': (R-Y), (B-Y) output '1': -(R-Y), -(B-Y) output Vertical pulse delay backend (test only) '0': delay '1': delayed belongs belongs
D5-D3 D2-D0
Micronas
6-108
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress SHIFTUV [BP-DAC] Shift subsampling digital output '0': take first couple '1': take second couple Note: VSP9432/42 only ENABLE656 [BP-DAC] Enable digital Output '0': disable output '1': enable output Note: VSP9432/42 only D5-D0 OFFSETDY [BP-DAC] Offset Voltage '000000': offset '111111': high offset Note: Should when backend coupled 94x2A
Subaddress CHROMSIGN [BP-DAC] CHROMAMP [BP-DAC] OFFSETDUV [BP-DAC] Chrominance sign '0': (R-Y), (B-Y) output '1': -(R-Y), -(B-Y) output Chrominance amplification '0': amplification '1': amplification Offset Voltage '000000': offset '111111': high offset Note: Should when backend coupled 94x2A
D5-D0
Micronas
6-109
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 PKLY [BP-DAC] Voltage Level Output '00000000': '10000000': '11111111': Note: including peaking overshoots. 0.9V white max.
Subaddress D7-D0 PKLU [BP-DAC] Voltage Level Output '00000000': '10000000': '11111111':
Subaddress D7-D0 PKLV [BP-DAC] Voltage Level Output '00000000': '10000000': '11111111':
Subaddress D7-D5 CONS [CP-CD] Color Switched (SECAM) level=CKILLS+CONS '000': value '010': default '111': value
6-110
Micronas
94x2A (A32)
Subaddress COLON [CP-CD] CPLLOF [CP-CD] CRCB [CP-CD] ACCFIX [CP-CD] ACCFRZ [CP-CD]
Preliminary Data Sheet 10.2001
I2C-bus
Force Color '0': color depends color decoder status '1': color always Chroma Open '0': normal operation '1': chroma opened CrCb Output '0': color space '1': CrCb color space Nominal Value '0': working '1': fixed Freeze '0': working '1': frozen
Subaddress D7-D5 [CP-CD] Color Switched (PAL/NTSC) level=CKILL+CON '000': value '010': default '111': value Chrominance coring '00': '01':+/- 1LSB '10':+/- 2LSB '11':+/- 3LSB Luminance notch-filter '0': notch-filter enabled '1': notch-filter bypassed
6-111
D4-D3
UVCOR [CP-CD]
NOTCHOFF [CP-CD]
Micronas
94x2A (A32)
Subaddress D1-D0 SECNTCH [CP-CD]
Preliminary Data Sheet 10.2001
I2C-bus
Selection Notch filter behavior SECAM mode '00':4.406 '01':4.250 '10':4.33 '11':4.406 4.25 dependent transmitted color
Subaddress D7-D6 PWTHD [CP-CD] Selection 'Peak-White' Threshold '00': (e.g. SECAM) '01': (e.g. NTSC sync-tip clamping) '10': (e.g. NTSC back-porch clamping) '11': Chroma lock-range '00':+/- '01':+/- '10':+/- '11':+/- Luminance Offset color decoder during visible picture '00':no offset '01':-32 IRE) '10':+32 IRE) '11':-16 3.75 IRE) Note: offset added during blanking display processing. When choosing '10', luminance offset equal offset CVBS input both picture blanking same offset used. VDETIFS [CP-CD] Vertical Sync-Detection Slope '0': normal '1': slow
D5-D4
CLRANGE [CP-CD]
D3-D2
LMOFST [CP-CD]
Micronas
6-112
94x2A (A32)
Subaddress VDETITC [CP-CD]
Preliminary Data Sheet 10.2001
I2C-bus
Vertical Sync-Detection Integration Time Constant '0': long '1': short
Subaddress D7-D6 DEEMPIIR [CP-CD] Deemphase filter component '00':5 '01':6 '10':7 '11':8 Chroma Bandwidth selects chroma bandwidth '011100': nominal bandwidth
D5-D0
CHRF [CP-CD]
Subaddress COMB [CP-CD] CSTAND [CP-CD] Delay Line '0':use delay line '1':do delay line (only suited NTSC) Color Standard Assignment '0000000': color standard chosen '0000001':PAL '0000010':PAL '0000100':SECAM '0001000':PAL '0010000':PAL '0100000':NTSC '1000000':NTSC allowed combinations please refer chapter "Chroma Decoder" page 5-22 '1100110': PALB/SECAM/NTSCM/NTSC44/PAL60
6-113
D6-D0
Micronas
94x2A (A32)
Preliminary Data Sheet 10.2001
I2C-bus
Subaddress D7-D0 CKILL [CP-CD] Chroma Level Color (PAL/NTSC) '00
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