Edition March 2001 6251-550-1PD Digital Picture-in-Picture (PIP)

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Edition March 2001 6251-550-1PD Digital Picture-in-Picture (PIP)

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9389X Plus Digital Picture-in-Picture Processor
Edition March 2001 6251-550-1PD
Digital Picture-in-Picture (PIP) Processor IIIplus
9389X
Version 1.04
General Description:
CMOS
9389X single chip Picture-in-Picture Processor which generates picture reduced size from video signal (inset channel) purpose combining with another video signal (parent channel). easy implementation into existing system needs only additional external components. Micronas, fundamental idea P-DSO-28-1 behind developing generation create single-chip solution with integrated digital color decoder data-slicer violence blocking capability. NTSC-M PAL-M color decoder 9389X 'PIP IIIplus' especially suited american, korean japanese market. PAL-N signals also processed certain extent. single chip, 'PIP IIIplus' integrates analog functions (A/D converter, converter, clock generation) with kbit memory digital signal processing logic (color decoding, horizontal vertical filtering, signal processing after storage).
Figure
Picture-in-Picture
picture reduction 1/9, 1/16 1/36 original size possible. transfer functions decimation filters optimally matched selected picture size reduction furthermore adjusted viewer's requirements selectable peaking. maximum luminance 2x28 chrominance pixels line stored memory
Type
Ordering Code
Package P-DSO-28-1
9389X(Tape Reel) Q67107-H5218
Micronas
9389X
Content
5.10 5.11 5.12 5.13 5.14 5.15 5.16 5.17 5.18 5.19 5.20 10.1 10.2
Features: Application Environment Configuration Description Block Diagram System Description AD-Conversion, Clock Generation Automatic Gain Control Inset Synchronization Chroma Decoding Filtering Scaling Luminance Peaking-Filter Offset correction Closed Caption Data Slicer Class Type Filter Indication data Memory Control Picture Positioning Postprocessing Matrix Framing colored Background Blanking DA-Conversion external RGB-insertion Pedestal Level adjustment Parent Clock Generation Display Features I2C-bus Address I2C-bus Format: I2C-Bus Commands: Absolute Maximum Ratings Recommended Operating Range Characteristics Diagrams Output Voltage Converters Three level input characteristic (SCP, VP/SCP)
Micronas
9389X
Application Circuit Clock Circuitry Diagram Package
Micronas
9389X
Features:
Single chip solution: CVBS-Clamping, AD-conversion, AGC, chroma decoding, sync separation, filtering, field memory, RGB-matrix, DA-Conversion, RGB-switch clock generation integrated chip Analog inputs: CVBS; selectable analog-digital conversion Automatic Gain Control (AGC) adjustment input amplitude range alternatively Chroma Decoder NTSC Automatic standard detection Automatic Chroma Control (-24dB Adjustable Chroma Saturation Control Only crystal necessary color standards Data slicing achieve violence blocking capability Closed Caption data sliced type class filter adjusted Decimation picture sizes: 1/9, 1/16 1/36 normal size Horizontal vertical filtering Display: Resolution luminance chrominance pixels inset line picture size 1/36 6-bit amplitude resolution Digital interpolation anti imaging Field frame-mode display Adjustable transient improvement (peaking) Contrast, brightness pedestal level adjustable Offset correction (blacklevel blanking level) display pictures live still, pictures source only) 16:9 compatibility: Operation 16:9 sets Colored background Line doubling mode progressive scan applications Freeze picture Analog outputs: mode:Y, +(B-Y), +(R-Y) -(B-Y), -(R-Y) matrices: NTSC (Japan, USA) Insertion external source possible Programmable position inset picture: Coarse positioning corners parent picture
Micronas
9389X
Features:
Fine positioning steps pixels lines Programmable framing: frame colors Variable frame width Variable frame height Frame giving three dimensional impression I2C-Bus control High stability clock generation PDSO 28-1 package (SMD) fully 9388X compatible 9488X SDA9489X compatible supply voltage
Micronas
9389X
Application Environment
TUNER1
CVBS CVBS 2(e.g. VCR) CVBS 3(e.g. SAT)
Teletext processor (optional)
plus 9389X
HSYNC VSYNC
Select R(V) G(Y) B(U)
Processor
CVBS
TUNER2
Figure
Application overview
Micronas
9389X
Configuration
Configuration
VP/SCP
XFREQ
CVBS1
VREFH CVBS2
VREFL CVBS3
PDSO
VSSA1
VDDA1 UREF VSSA2
VDDA2 OUT1 OUT2 OUT3
Figure
Pinout
Micronas
9389X
Description
Symbol
VP/SCP XFREQ OUT3 OUT2 OUT1 VDDA2 VSSA2 UREF VDDA1 VSSA1 CVBS3 VREFL CVBS2 VREFH CVBS1
Type
I3-L I3-L I/ana I/ana I/ana Q/ana Q/ana Q/ana I/ana I/ana I/ana I/ana
Description
crystal oscillator (input) crystal clock (from another crystal oscillator (output) horizontal sync parent channel sandcastle including V-sync vertical sync parent channel sandcastle including V-sync I2C-bus data I2C-bus clock digital supply voltage digital ground connect crystal frequency Input external source Input external source Input external source fast blanking input switch, outputs switched high fast blanking output mode (Tristate), high also output high analog output: chrominance signal +(B-Y) -(B-Y) analog output: luminance signal analog output: chrominance signal +(R-Y) -(R-Y) analog supply voltage (VDDA) analog ground (VSSA) reference voltage DA-converters analog supply voltage (VDDA) analog ground (VSSA) CVBS Input (selectable I2C-bus) reference voltage (low) CVBS Input (selectable I2C-bus) reference voltage (high) CVBS Input (selectable I2C-bus) Input ana=analog /3-L=3 level Output TTL=Digital (TTL) S=Supply voltage
Table
Pinout description
Micronas
9389X
Block Diagram
Block Diagram
VDDA1 VSSA1 VDDA2 VSSA2
DCVBS CVBS1 CVBS2 CVBS3
Source Select Clamp 7bit Gain Control
Lowpass Decimation
Line Memory Field Memory Output Signal Processing, Matrix, Framing
UREF
Triple 6bit
NTSC Chroma Decoder
VREFH VREFL
Closed Caption Data Slicer
Inset Synchronization Read Write Controller Picture Position Control Parent Clock Generation Switch
Clock Generation (Quarz Oszillator) Parent Clock Gen.
Controller
Parent Sync Signal Processing
XFREQ
VP/SCP
Figure
Block Diagram
Micronas
9389X
System Description
AD-Conversion, Clock Generation
analog inset CVBS signal inputs CVBS1-3 9389X (amplitude 0.7-2 Vpp). Each these input signals selected (CVBSEL). After clamping sync bottom signal AD-converted with amplitude resolution 7bit. conversion done using clock which related incoming CVBS signal. clamp timing analog input generated from CVBS signal. external sync signals required inset channel. Three different types crystals chosen: 13.5 fundamental mode, fundamental mode, third overtone mode. crystal chosen XFREQ. When XFREQ connected initialized 13.5 crystal. When using crystal, XFREQ must connected Vss. crystal specifications, please refer section
Automatic Gain Control
accommodate different CVBS input voltages automatic gain control been implemented. avoid control oscillation, adjustment carried only after power resynchronisation video source. chip works correctly input voltages range from Vpp. best signal-to-noise ratio, maximum amplitude recommended when available. Alternatively fixed adjustment input range possible (AGC[3:0]; AGCFIX=1). characteristic Uref=5V shown picture below.
Micronas
9389X
System Description
Figure
Expected input voltage using adjustment
correct setting 1Vpp input signals AGC[3:0]= '0101' AGCFIX='1'.
Inset Synchronization
Horizontal vertical sync pulses separated after elimination high frequency components CVBS signal pass filter. Horizontal sync pulses generated digital phase-locked-loop. time constant adjusted between fast slow behavior four steps (PLLITC[1:0]) accommodate different input sources (e.g. VCR).
Chroma Decoding
order obtain chrominance information digitized video signal multiplied with re-generated color subcarrier once in-phase once phase-shifted 90°. After lowpass filtering digital available. subcarrier regenerated digital PLL. Reference subcarrier generation crystal stable clock 27.000 MHz. order avoid color standard detection problems, maximum deviation this frequency should exceed 100ppm should possible. small frequency adjustment (-50 +110 ppm) possible when using crystal with small frequency deviations (INCRA[4:0]).
Micronas
9389X
system able decode NTSC signals with subcarrier frequency about 3.58 MHz. Phase demodulation influenced Control (HUE[5:0]) between -44.8° 43.4° steps 1.4°(NTSC only). variations chroma signal upto 30dB, stable output amplitude after chroma decoding achieved (Automatic Chroma Control). When chroma signal (color burst) below selectable threshold (CKILL: dB), color will switched off. Alternatively color-killer bypassed color switched under conditions.
Color killer theshold1) NTSC color color color color color color -9.3 -15.8 -19.3 -21.2 -26.8 color
PAL-M -12.5 -16.7 -20.5 -21.9 -27.9 color
CKILL
typical values, assuming standard signals according ITU-R BT.470-3 recommended operating range
automatic norm detection preset mode chosen (CSTAND[1:0]).
Filtering Scaling
Luminance chrominance signals filtered horizontal vertical direction. horizontal vertical picture size freely programmable (SIZEHOR, SIZEVER). transfer functions decimation filters optimally matched according selected reduction picture size. small reduction horizontal picture size accessible with PICSZE.
Micronas
9389X
System Description
PICSZE=0 SIZEHOR1 SIZEHOR0
Table
PICSZE=1 (B-Y) (R-Y)
horizontal scaling (reserved)
(B-Y) (R-Y) 20.5 20.5
Number stored pixel
SIZEVER1
Table
SIZEVER0
vertical scaling (reserved)
lines
Number stored lines
Luminance Peaking-Filter
improve picture sharpness, peaking filter provided, which amplifies higher frequencies input signal. amount peaking varied seven steps from '000' '111'. setting '000' switches peaking off; '100' recommended value. characteristic possible settings shown Table characteristic Figure 5-2.
Micronas
9389X
YPEAK2
Table
YPEAK1
YPEAK0
peaking off) weak
nominal (recommended)
strong
Peaking values
Figure
Characteristic various peaking factors
Coring should switched (YCOR) reduce noise, which also amplified when peaking chosen. coring stage front peaking filter, 1LSB noise will peaked.
Micronas
9389X
System Description
Yout
Figure
Coring Characteristic
With YDEL phase between luma chroma adjusted pixel.
Offset correction
According ITU-R BT.470-3 difference between black blanking level occurs NTSC signals. When necessary, this offset reduced LMOFST. adjustment offset correction decoder main channel, three settings available (approximately resp.)
Received signal
BLACK value BLANK value
Processed signal
Processed signal
BLACK value BLANK value
BLACK value BLANK value
LMOFST='00'
LMOFST='10'
Figure
Without with offset correction
signals (Argentina) include this offset.
Micronas
9389X
Closed Caption Data Slicer
Closed Caption data ('Line 21') sliced digital data slicer readable from I2C. well prefiltered data provided. With built programmable XDSFilter, program-rating information ('V-chip') filtered out. linenumber sliced data selectable with SELLNR between line line Closed Caption data assumed conform standards EIA-608 EIA-744.
Class Type Filter
well prefiltered data provided alternatively. With built programmable XDS-Filter, program-rating information well others filtered out. extensions Closed Caption sent only second field Line following table selectable Class filter shown.They used reduce traffic reduce calculation power main controller. When Class selected, incoming data (both fields) sliced output. When more class filter chosen, only data field sliced. combination class filter allowed.
XDSCLS4
Table
XDSCLS3
XDSCLS2
XDSCLS1
XDSCLS0
selcted Class Class selected (transparent mode) 'Current Class' 'Future Class' 'Channel Class' 'Misc. Class' 'Public Class'
selectable CLASS filter
Each 'CLASS' divided into 'TYPES' which sorted XDS-secondary filter(XDSTPE[2.0]). combination type filter allowed. Type filter often make sense only with appropriate class filter.
Micronas
9389X
System Description
XDSTPE2
XDSTPE1
XDSTPE0
Type number (according 608)
selcted Type (examples) data filtered out.
01h,04h 01h,02h,03h, 04h,0Dh,40h 01h, 04h,05h 05h,40h 01h,02h,03h, 04h,05h,0Dh,40h
program rating (PR) only Time information only band only information Time information only band only information
Table
selectable TYPE filter
5.10
Indication data
sliced filtered data available DATAA[7.0] DATAB[7.0]. Every time data arrives, DATAV becomes Every time both databytes read DATAV becomes until data arrives. must ensured that data polling activated once field (16.7 every second field (33.3 ms), depending slicer configuration program field frequency. When ACQNEW equals '0', data line buffered allow later polling access.
5.11
Memory Control
embedded memory stores decimated field inset picture. capacity 70560 bits. field-mode display just every second inset field written into memory whereas frame-mode display memory continuously written with every incoming field. Data processed with lower memory clock frequency depending horizontal decimation factor. progressive scan conversion systems HDTV displays line doubling mode available (LINEDBL). Every line inset picture read twice.
Micronas
9389X
scan conversion modes only horizontal scaling field-mode used. Memory writing stopped FREEZE register; unchanged field permanently read memory. Frame-mode display possible standard (NTSC video sources inset parent channel both (PAL respectively). result higher vertical time resolution every incoming field displayed. this purpose inset parent channel internally analyzed activation frame-mode display blocked automatically when least following conditions fulfilled: inset parent channel have equal field frequencies number lines between (310 resp.) (standard signals according ITU) interlace detected inset parent Depending phase between inset parent signals correction display raster read data performed. Synchronization memory reading with parent channel achieved processing parent horizontal vertical synchronization signals. Either separated horizontal vertical pulses sandcastle pulse possible. signals horizontal synchronization VP/SCP vertical synchronization. sandcastle pulse used pins VP/SCP fulfills specification input (PARSYN).
PARSYN
Table
parent sync. signals read pins VP/SCP parent sync. sandcastle double frequency read VP/SCP parent sync. signals read pins VP/SCP (burstgate) parent sync. sandcastle
Parent Synchronization
setting '10' used burstgate pulse from color decoder main channel. other settings timed using horizontal pulse timing information. From these external signals (horizontal sync pulse) (vertical sync pulse) derived. timing between used obtain parent field number. external signals come from different devices with different delay paths, phase between both adjusted correct field identification (VSPDEL).
Micronas
9389X
System Description
63.56ms (31.78ms)
VSPD VSPDEL VSPDELmax=75.8ms (37.9ms)
Figure
Phase adjustment vertical pulse
Usually noise reduction incoming parent vertical pulse performed. With this function missing vertical pulse inserted. disabled with VSPISQ.
Micronas
9389X
great variety combinations inset parent settings possible. following table shows usual unusual constellations
Inset Parent Frequency Frequency frame- field-mode possible mode possible correct aspect ratio picture picture size 1/9, size 1/36 READD LINEDBL
(progr.) (progr.) (progr.) (progr.) 1001) 1201 1001 1201 1002) 1202 1002 1202
combination before upconversion combination after upconversion (upconversion done PIP)
Combinations inset parent vertical frequency
Table
Micronas
9389X
System Description
5.12
Picture Positioning
display position inset picture programmable corners parent picture (CPOS[1:0]). From there moved middle Picture with POSHOR[7:0] POSVER[6:0]. standard signals used synchronization values POSHOR POSVER same each coarse position. frame elements always placed outside Inset Picture, except inner shade three dimensional frame. There shift inset picture position inset frame width modified. Depending coarse position, corner remains stable when changing picture size
CPOS[1:0]
POSITION
REFERENCE CORNER Inset Picture upper left upper right lower left lower right
increasing POSVER= moving direction down down
increasing POSHOR moving direction right left right left
Table
upper left upper right lower left lower right
coarse positioning
Micronas
9389X
POSHOR
CPOS='01' CPOS='00'
POSVER POSVER
CPOS='10'
POSHOR
CPOS='11'
Figure
Positioning
Starting every coarse position, picture moved horizontal locations pixel increments) vertical locations line increments). Even POP-positions (Picture Outside Picture) 16:9 applications possible.
5.13
Postprocessing
postprocessing improves transient behavior signals. multiplier signal path adjusts color saturation depending register steps between 1.875 (SAT[3:0]). read frequencies signals changing with picture size. double line frequency 100/120 applications possible picture sizes except 1/36.This done setting READD '1'. Doubling horizontal size possible using PIXDBL.
5.14
Matrix
chip contains different matrices, Japan USA, which selectable I2C-signal MAT. matrices differ magnitudes angles color-difference signals derived from original matrix defined television
Micronas
9389X
System Description
standards. This modification should give better reproduction skin color adjusts color reproduction used colorimetry transmission chromaticity picture tube.
NTSC-USA (MAT=0):
0,5312 1,9687 0,1875 0,5625
NTSC-Japan (MAT=1):
0,125 1,5625 0,3125 0,5312
5.15
Framing colored Background
colored frame added inset picture. chip display different types frames: simple monochrome frame more sophisticated three dimensional frame (FRSEL)
Micronas
9389X
Figure
Normal frame (left) frame with three dimensional impression (right)
frame colors programmable, bits each component (B-Y), (R-Y) through FRY[1:0], FRU[1:0] FRV[1:0].
Frame Color blue green white yellow cyan magenta black
Table
Examples frame color
horizontal vertical width frame independently programmable (FRMWIDV[1:0] FRMWIDH[2:0]). 100/120 applications frame width only changed steps pixel. Frame color displayed over whole
Micronas
9389X
System Description
size whole picture size main channel. Alternatively colored background displayed with visible (PBGRD[1:0]). colored background blanked vertically lines (VERBLK). horizontal blanking adjustable.
vert. blanking (off screen) blanking lines blanked Picture (frame color) (RGB input) pixel (live) pixel (freezed)
frame (background visible) frame color shades frame) (background (outside) picture (inside) visible.) darkness brightness hor. blanking (off screen) variable width start matching burstgate horizontal sync background (blanked) frame color input
Figure
Framing blanking
Micronas
9389X
5.16
Blanking
Parent signal
Clamping CLAMP input (horizontal pulse, Burstgate Super Sandcastle) output
Colored Background picture
Blanking
Figure
horizontal blanking timing
Micronas
9389X
System Description
HZOOM READD CLPDEL PARSYN (µs) (µs) (µs) (µs) [2.0] [1.0] (Blanking (Blanking Start, (Clamping Start, (Clamping Duration) negative value negative value Duration) before HSP) before HSP)
10.4 10.4 10.4 10.4 10.4 10.4 -8.7 -6.6
0.07 -2.8 0.01 -0.88 -1.3 -3.5 -1.4
Table 5-10
horizontal blanking timing
5.17
DA-Conversion external RGB-insertion
9389X includes three 6-bit DA-converters. Brightness (BRIGTH[3:0]), Contrast(CON[3:0]) Pedestal Level output signal controlled bus. output amplitude controlled YAMP, UAMP, VAMP. controlling external switch select signal provided. delay this select signal compared RGB/YUV output programmable adaptation different external output signal processing (SELDEL[3:0]). oversampling stage inverts sign signals UVPOLAR active. signals bypassed internally depending OUTFOR yield Y-U-V instead signals. External signals inputs IN1-3. forcing input high level these signals switched outputs OUT1-3 while internal signals switched off. input signal passed through output. This feature only available, output signal mode.
Micronas
9389X
RGBIN='1' PIPON='1'
RGBIN='0' PIPON='1'
RGBIN='1' PIPON='0'
9389X
Figure 5-10 Insertion external When IN1-3 used, they must left open connected ground capacitor.
5.18
Pedestal Level adjustment
pedestal level adjustment controlled signals BLKLR, BLKLG, BLKLB enables correction small offset errors. This adjustment effect setup level during active line interval each channel like brightness adjustment enhanced resolution LSB. maximum possible offset amounts LSBs. mode action depends setting BLKINVR BLKINVB. BLKINVR (BLKINVB) active offset applies blank level (BU) channel during clamping interval shifting setup level negative direction. mode BLKINVR BLKINVB necessary.
Micronas
9389X
System Description
Mode BLKINVR BLKINVB
BLKLR BLKLB
BLKLR BLKLB
Mode BLKINVR BLKINVB
BLKLR BLKLB
BLKLR BLKLB
Mode
BLKLR BLKLB BLKLG
BLKLR BLKLB BLKLG
Figure 5-11 Pedestal level adjustment
Micronas
9389X
5.19
Parent Clock Generation
phase output signals locked rising edge horizontal parent sync pulse. nominal internal read data frequency 13.5 MHz. With respect different displays, this changed values shown following table.
HZOOM
Table 5-11
READD XFREQF
Frequency 13.5 13.8 27.0 28.6 9.45 9.75 18.9 19.5
remark
(can used with crystal only)
(can used with crystal only)
(can used with crystal only)
(can used with crystal only)
Memory-read-out frequency
Micronas
9389X
System Description
5.20
Display Features
Figure 5-12 Picture size
Figure 5-13 Picture size active
Figure 5-14 Picture size 1/16
Figure 5-15 Picture size 1/16 active
Micronas
9389X
Figure 5-16 Picture size 1/36
Figure 5-17 Picture size 1/36 active
Figure 5-18 Picture size PIXDBL='1'
Figure 5-19 Picture size PIXDBL='1' LINEDBL='1'
Micronas
9389X
System Description
decimation memory circuits PIPIIIplus optimized NTSC signals. colordecoder also able handle signals, additional lines omitted. share omitted lines over upper lower part picture, visible picture section centered vertically.
Inset picture with lines
Parent picture with lines
Inset picture with lines (VCENTER='1')
Inset picture with lines (VCENTER='0')
Figure 5-20
Display line inset signals
Micronas
9389X
I2C-bus
Address
Write Address: 11011100 (DCh) Read Address: 11011101 (DDh)
I2C-bus Format:
Start condition
Acknowledge
Stop condition
Acknowledge
WRITE
11011100
Subaddress
Data Byte
****
READ
11011100
11011101
Data Byte
Only write operation possible registers 00h-15h 1Bh-1Dh, only read operation registers 16h-1Ah. automatic address increment function implemented. Register left blank.
Micronas
9389X
I2C-bus
SubAddr Hex.
I2C-Bus Commands:
Data Bytes FIESEL1 FIESEL0 FREEZE SELDEL2 PIXDBL SELDEL1 READD SELDEL0 LINEDBL HZOOM CPOS1 PIPON CPOS0
SELDOWN SELDEL3
POSHOR7 POSHOR6 POSHOR5 POSHOR4 POSHOR3 POSHOR2 POSHOR1 POSHOR0 CVBSEL1 SELLNR POSVER6 POSVER5 POSVER4 POSVER3 POSVER2 POSVER1 POSVER0 CVBSEL0 ACQNEW AGC3 AGC2 AGC1 AGC0 AGCADST AGCFIX
SIZEVER1 SIZEVER0 LMOFST1 BLKINVR BLKINVB BLKLG0 BLKLR3 BLKLB3
LMOFST0 SIZEHOR1 SIZEHOR0 BLKLR2 BLKLB2 CLPDEL2 BLKLR1 BLKLB1 CLPDEL1 VSPDEL1 BRIGHT1 FRU5 FRWIDH1 UVPOLAR HUE1 CSTAND0 INCRA1 YPEAK1 YDEL1 INCRA0 YPEAK0 YDEL0 YAMP0 UAMP0 VAMP0 SYNCSTAT BLKLR0 BLKLB0 CLPDEL0 VSPDEL0 BRIGHT0 FRU4 FRWIDH0 OUTFOR HUE0
BLKLG3 PARSYN1 STDP CON3 RGBIN FRSEL SAT3 ACCFIX PLLITC1 CKILL1
BLKLG2 PARSYN0 STATPQ CON2 VERBLK PBGRD1 SAT2 COLON PLLITC0 CKILL0
BLKLG1
VSPISQ CON1 FRY5 PBGRD0 SAT1 HUE5 STATIQ CPLLOF
VSPDEL4 CON0 FRY4 FRWIDV1 SAT0 HUE4
VSPDEL3 BRIGHT3 FRV5 FRWIDV0
VSPDEL2 BRIGHT2 FRV4 FRWIDH2
HUE3
HUE2 CSTAND1
INCRA4
INCRA3 YCOR
INCRA2 YPEAK2
VCENTER YAMP7 UAMP7 VAMP7 DEVICE
XFREQF YAMP6 UAMP6 VAMP6 DATAV
WTCHDG YAMP5 UAMP5 VAMP5 LINESTD
PICSIZE YAMP4 UAMP4 VAMP4 STDET1 YAMP3 UAMP3 VAMP3 STDET0 YAMP2 UAMP2 VAMP2 DISPSTAT
YAMP1 UAMP1 VAMP1 SCSTAT
Micronas
9389X
DATAA7 DATAB7
DATAA6 DATAB6
DATAA5 DATAB5
DATAA4 DATAB4
DATAA3 DATAB3
DATAA2 DATAB2
DATAA1 DATAB1
DATAA0 DATAB0 SLFIELD
XDSCLS4 NONSED
XDSCLS3 NOCRID
XDSCLS2 FCBEOK
XDSCLS1 CRIBEOK HFP4
XDSCLS0 HFP3
XDSTPE2 DSTDET HFP2
XDSTPE1
XDSTPE0
HFP1
HFP0
After power grey marked data bits '1', other `0`. used reserved bits must software register written. Subaddress Name
Function insertion '0': insertion '1': insertion
PIPON
HZOOM Horizontal Zooming '0': horizontal Scaling Factor '1': horizontal Scaling Factor 1.43 LINEDBL Lindedouble mode '0': each line memory read once (normal operation) '1': each line memory read twice (progressive scan conversion systems parent channel) READD Readdouble mode '0': display with single read frequency '1': display with double read frequency Note: When enabled, should 'frame-mode' (FIESEL='00') progressive scan 'field mode' (FIESEL='01' '10') 100/120 applications
PIXDBL
Pixdouble mode '0': normal display '1': each pixel read twice Note: Peaking automatically '000' peaking) when enabled
FREEZE Picture freezing '0': live picture '1': freeze picture
Micronas
9389X
I2C-bus D7D6 FIESEL Field selection '00': display both fields (frame-mode) '01': display field '10': display field '11': (reserved)
Subaddress Name
Function Coarse positioning picture '00': upper left '01': upper right '10': lower left '11': lower right Delay output signal SELECT '1000':-8 periods read frequency clock '0000': periods read frequency clock '1111': periods read frequency clock (select) output condition '0': open source output '1': output pins
D1D0
CPOS
D6D3
(reserved) SELDEL
SELDOWN
Subaddress
D7D0
Name
Function
POSHOR Horizontal position picture (raster: pixel) '00000000': coarse position '11111111': opposite coarse position Note: Positioning outside visible picture area allowed
Subaddress
Name
Function
Micronas
9389X
D6D0
POSVER Vertical position picture (raster: lines); '00000000': coarse position '11111111': opposite coarse position Note: Positioning outside visible picture area allowed
mode '0': single mode '1': three identical pictures lined vertically with same content
Subaddress Name
Function Automatic Gain Control '0': automatic Gain Control '1': automatic Gain Control (manual mode)
AGCFIX
AGCADST Automatic Gain Control restart '0'-> '1': manual start automatic adjustment input amplitude range Automatic Gain Control setting manual mode '0000' :maximum input amplitude CVBS signal 0.7Vpp '1111': maximum input amplitude CVBS signal 2Vpp
D5D2
D7D6
CVBSEL CVBS input selection '00': Input CVBS1 active '01': Input CVBS2 active '10': (reserved) '11': Input CVBS3 active
Subaddress Name
Function
D1D0
SIZEHOR Horizontal size reduction '00': horizontal size reduction '01': horizontal size reduction '10': (reserved) '11': horizontal size reduction
Micronas
9389X
I2C-bus D3D2 LMOFST Luminance offset '00': offset '01': offset '10': offset -7.5 '11': offset SIZEVER Vertical size reduction '00': vertical size reduction '01': vertical size reduction '10': (reserved) '11': vertical size reduction ACQNEW Acquisition '0': data packet saved '1': data overwrites current data SELLNR Select linenumber '0': data slicer line '1': data slicer line
D5D4
Subaddress Name
Function Adjustment blanking level output (steps LSB) '0000': '1111':
D3D0
BLKLR
BLKINVB Pedestal adjustment output '0': offset current OUT3 output added during active picture '1': offset current OUT3 output added during blanking BLKINVR Pedestal adjustment output '0': offset current OUT1 output added during active picture '1': offset current OUT1 output added during blanking (reserved)
D7D6
Subaddress Name
Function
Micronas
9389X
D3D0
BLKLB
Adjustment blanking level output (steps LSB) '0000': '1111': Adjustment blanking level output (steps LSB) '0000': '1111':
D7D4
BLKLG
Subaddress Name
Function
D2D0
CLPDEL Delay clamping pulse inputs '000': delay) '001': (100/120 resp. 296ns (50/60 '111': 1036 (100/120 resp. 2072 (50/60
D5D3 D7D6
(reserved) PARSYN Parent synchronization input '00': parent sync. signals read pins VP/SCP '01': parent sync. sandcastle '10': parent sync. signals read pins VP/SCP '11': parent sync. sandcastle VP/SCP Note: '10' must used burstgate input '00' horizontal sync pulse
Subaddress Name
Function
D4D0
VSPDEL delay vertical synchronization pulse (parent signal) '00000':in steps 2.37µs 1.68µs 100Hz) '11111': VSPISQ Noise reduction pulse '0': '1':
Micronas
9389X
I2C-bus STATPQ Frame-mode activation non-standard parent sources '0': Frame-mode only active standard NTSC, sources '1': Frame-mode active also non-standard sources, (disturbances possible) STDP Parent standard '0': 60Hz (resp. '1': 50Hz (resp.
Subaddress
D3D0
Name
Function
BRIGHT Brightness adjustment picture '0000': nominal brightness '0001': added '1111': added Contrast adjustment picture '0000': nominal contrast '1111': max. contrast increase
D7D4
Subaddress Name
Function Chrominance component (B-Y) frame color Chrominance component (R-Y) frame color Luminance component frame color NOTE: FRY='00' suited three dimensional frame
D1D0 D3D2 D5D4
VERBLK Vertical Blanking outputs '0': clamping level only during line-blanking intervals '1': clamping level during line-blanking intervals field-blanking intervals complete lines following vertical synchronization pulse parent channel)no external insertion posssible, signal ineffective external insertion posssible during high periode signal
Micronas
9389X
RGBIN
insertion permission '0': external insertion posssible, signal ineffective '1': external insertion posssible during high period signal
Subaddress Name
Function
D2D0
FRWIDH Horizontal width frame '000': horizontal frame width pixel '111': horizontal frame width 7pixel Note: Even with FRWIDH='0000' shade remains three dimensional frame
D4D3
FRWIDV Vertical width frame '00': vertical frame hight line '11': vertical frame hight lines Note: Even with FRWIDV='00' shade remains three dimensional frame
D6D5
PBGRD
Picture background '00': background color '01': picture invisible, background display same frame color '10': background display with frame color instead main picture, visible '11': background display with frame color instead picture Frame selection '0': standard frame '1': three dimensional frame
FRSEL
Subaddress Name
Function
OUTFOR Output format '0': format output signals: '1': format output signals: (B-Y), (R-Y)
Micronas
9389X
I2C-bus UVPOLAR Polarity '0': chrominance output signals: +(B-Y), +(R-Y) '1': inverted chrominance output signals: -(B-Y), -(R-Y) Matrix '0': Matrix '1': Matrix Japan Saturation Control chroma signal '0000': (color off) '0001': Saturation nominal value '1000': nominal value '1111': Saturation 15/8 nominal value
D7D4
(reserved)
Subaddress Name
Function Control chroma signal Demodulation phase angle NTSC color adjustment '000000': '000001': '011111': Color killer '0': chroma killer active '1': chroma always Automatic Chroma Control disabling '0': active '1': fixed nominal value
D5D0
COLON
ACCFIX
Subaddress Name
Function
(reserved)
Micronas
9389X
D2D1
CSTAND Chroma standard selection '00': Automatic standard detection '01': NTSC fixed '10': fixed '11': fixed (reserved) STATIQ Frame-mode activation non-standard inset sources '0': Frame-Mode possible case proper input signals '1': Frame-Mode always active Time constant inset synchronization '00': fast time constant sync separation (e.g. VCR) '11': slow time constant sync separation (e.g.
D4D3
D7D6
PLLITC
Subaddress Name
Function Adjustment regenerated color carrier frequency '00000': adjustment '00111': nominal value '11100': adjustment +110 Note: maximum input allowed '11100'
D4D0
INCRA
CPLLOF Opening Chroma '0': Chroma active '1': Loop chroma opened CKILL Color killer threshold '00': color killer threshold -12db amplitude '01': color killer threshold -18db amplitude '10': color killer threshold -24db amplitude '11': color Note: values approximative
D7D6
Subaddress Name
Function
Micronas
9389X
I2C-bus D2D0 YPEAK Luminance Peaking '000': peaking '111': maximum peaking NOTE: peaking greater than ('100') recommended Coring '0': coring '1': coring active, peaking small luminance steps
YCOR
D7D4
(reserved)
Subaddress Name
Function Luminance delay '00': signal delayed '01': pixel '10': pixel '11': (reserved)
D1D0
YDEL
D3D2
(reserved) PICSZE Picture size '0': 216/164/108 pixel visible '1': 224/168/112 pixel visible
WTCHDG Watchdog control '0': slow response '1': fast response Note: should normal operation XFREQF Read frequency Offset '0': display clock frequency without offset '1': display clock frequency with offset +2.5% Note: horizontal picture position varies with this setting Note: function only available when using crystal
Micronas
9389X
VCENTER Vertical centering lines inset signals '0': additional lines omitted lower picture (suited NTSC PAL-M) '1': additional lines omitted half upper lower picture Note: When enabled, display line signals disturbed
Subaddress Name
Function Amplitude output signal (OUT2) '00000000': '10000000':default '11111111':max
D7D0
YAMP
Subaddress Name
Function Amplitude output signal (OUT3) '00000000':min '10000000':default '11111111':max
D7D0
UAMP
Subaddress Name
Function Amplitude output signal (OUT1) '00000000':min '10000000':default '11111111':max
D7D0
VAMP
Subaddress (Read) Name
Function
Micronas
9389X
I2C-bus
SYNCSTAT Inset synchronisation status
'0': Internally generated sync locked CVBS signal '1': Internally generated sync locked CVBS signal SCSTAT Choma display '0': chroma '1': chroma DISPSTAT Display status '0': Field mode '1': Frame mode STDET Detected chroma standard '00': non-standard '01': NTSC '10': '11': Note: SYNCSTAT equals STDET invalid LINESTD Linestandard '0': Internal generated sync locked CVBS signal '1': Internal generated sync locked CVBS signal Note: SYNCSTAT equals LINESTD invalid DATAV Data valid '0': Data read Data invalid '1': Data available DATA output Device identification '0': 9388X (PIP III) '1': 9389X (PIP IIIplus)
D4D3
DEVICE
Subaddress Name
Function
D7D0
(reserved)
Subaddress (Read) Name
Function
D7D0
DATAA
First Data Byte Closed Caption Data
Micronas
9389X
Subaddress 19(Read) Name
Function
D7D0
DATAB
Second Data Byte Closed Caption Data
Subaddress Name
Function
SLFIELD Field Number sliced data Field fits content DATAA DATAB '0': First Field '1': Second Field (reserved)
D7D1
Subaddress Name
Function
D2D0
XDSTPE Type Select XDS-Secondary Filter (Type) '000':ALL filtering) '001': (program rating) '010': 01h, (Time information only) '011': (out band only) '100': 01h,02h,03h,04h,0Dh,40h (VCR information) '101': 01h, 04h,05h (Time information only '110': 05h,40h (out band only '111': 01h,02h,03h,04h,05h,0Dh,40h (VCR information XDSCLS Class Select Closed Caption XDS-Primary Filter (Class) '00000': Transparent (all sliced data, both fields) '1xxxx' :'Current' Selected (only second field) 'x1xxx' :'Future' Selected (only second field) 'xx1xx' :'Channel' Selected (only second field) 'xxx1x' :'Miscellenious' Selected (only second field) 'xxxx1' :'Public Services' Selected (only second field)
D7D3
Subaddress Name
Function
Micronas
9389X
I2C-bus D1D0 (reserved) DSTDET Data start Detection '0': additional data plausibility checking disabled '1': additional data plausibility checking enabled (reserved) normal operation CRIBEOK Clock-run-in error '0': check correct clock-run-in '1': allow deviation clock-run-in FCBEOK Framing code error behaviour '0':check correct framing code '1':allow deviation framing code NOCRID clock-run-in detection '0': check clock-run-in according CRIBEOK '1':do check clock-run-in NONSED Noise data '0': only data change allowed closed caption cycle '1': data allowed
Subaddress Name
Function Horizontal Fine Positioning '10000': shift right (2.2 '00000': shifting '01111': max. shift left (-2.2
D4D0
D7D5
(reserved)
Micronas
9389X
Absolute Maximum Ratings
Parameter Symbol Tstg Tsold -0.3V -0.3 -0.3V -0.3 -0.3 -0.25 Ptot -100 VESD -2000 Limit Values min. max. VDD+ 0.3V VDD+ 0.3V 0.25 0.720 2000 duration <10s CVBS1.3,IN1.3, SCP, VP/SCP other pins pins OUT1, OUT2, OUT3, other pins Unit Unit
Ambient Temperature Storage Temperature Junction Temperature Soldering Temperature Input Voltage
Output Voltage
Supply Voltages Supply Voltage Differentials Total Power Dissipation Latch-Up Protection robustness HBM: 1.5k, 100pF
voltages listed referenced ground (0V, VSS) except where noted. Note: Stresses above those listed here cause permanent damage device. Exposure absolute maximum rating conditions extended periods affect device reliability. Maximum ratings absolute ratings; exceeding only these values cause irreversible damage integrated circuit.
Micronas
9389X
Recommended Operating Range
Recommended Operating Range
Parameter Symbol VDDxx Limit Values min. typ. max. 5.25 4.75 Unit Remark
Supply Voltages Ambient Temperature Inputs Low-Level Input Voltage High-Level Input Voltage
-0.25
+0.2 15.734 31.468 16.6 33.2
Parent horizontal vertical Sync Inputs: VP/SCP, Sync H-Frequency Single Frequency Display Mode Sync H-Frequency Double Frequency Display Mode Signal Rise Time Signal High Time (horizontal) Signal Time (horizontal) Sync V-Frequency Single Frequency Display Mode Sync V-Frequency Double Frequency Display Mode Signal High Time (vertical) Signal Time (vertical) fP2H 14.9 29.8
noisefree transition
STDP dependent STDP dependent
Fast (All values referred min(VIH) max(VIL)) This specification lines need identical with stages specification because optional series resistors between lines pins. Clock Frequency Inactive Time Before Start Transmission Set-Up Time Start Condition Hold Time Start Condition fSCL tBUF tSU;STA tHD;STA
Micronas
9389X
Parameter Time High Time Set-Up Time DATA Hold Time DATA SDA/SCL Rise/Fall Times Set-Up Time Stop Condition Capacitive Load/Bus Line
Symbol tLOW tHIGH tSU;DAT tHD;DAT tSU;STO
Limit Values min. typ. max.
Unit
Remark
20+$
$=0.1Cb/pF
Inputs/Output: SDA, High-Level Input Voltage Low-Level Input Voltage Spike Duration Inputs Low-Level Output Current VDD+ 0.5V
-0.25V
also SDA/SCL input stages
Analog digital converter bit) Input Coupling Capacitors
necessary proper clamping
dependent layout values only with optional external resistors gain control active
CVBS Source Resistance Reference Voltage Reference Voltage High Input Voltage Range inputs CVBS1-3 VREFL VREFH
Digital Analog Converters (6-bit) Full Range Output Voltage Load resistance VOFR
peak peak
Micronas
9389X
Recommended Operating Range Parameter Crystal Specification Maximum Permissible Frequency Deviation Frequency (27.0 crystal) Frequency (13.5 crystal) Permissible Frequency Deviation Permissible Frequency Deviation with Temperature fmax/ fxtal fxtal27 -100 10-6
deviation outside this range will cause color decoding failures this range will cause color decoding failures this range will cause color decoding failures
Symbol
Limit Values min. typ. max.
Unit
Remark
26.9973
27.0027 deviation outside
fxtal13
13.4987
13.5
13.5013 deviation outside
f/fxtal fT/fxtal
10-6 recommen-
10-6 recommen-
13.5 20.5
13.5 (fundamental mode) Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance 27.0 (fundamental mode) Load Capacitance Series resonance resistance Motional capacitance Parallel capacitance 27.0 (third overtone mode) Load Capacitance Series Resonance Resistance Motional Capacitance Parallel Capacitance
Micronas
9389X
Note: operating range functions given circuit description fulfilled.
Micronas
9389X
Characteristics
Characteristics
(Assuming Recommended Operating Conditions)
Parameter Average total supply current Input Capacitance Input Leakage Current Symbol IDDtot Limit Values min. typ. max. Unit Remark
Digital Inputs (TTL, tested including leakage current output stage tested VDD(min)< VDD<VDD(max) VDD(min)< VDD<VDD(max) VDD(min)< VDD<VDD(max) Threshold difference between rising falling edge IOH=-200µA IOH=-4.5mA IOL=1.6mA, only valid SELDOWN=1 VO=0V.VDD tested
Three Level Input (3-L) SCP, VP/SCP Input Capacitance Low-Level Input Voltage Medium-Level Input Voltage High-Level Input Voltage Hysteresis VIMH, VILM -0.25 +0.5
High-Level Output Voltage High-Level Output Voltage Low-Level Output Voltage Leakage Current Output Capacitance 1.5V
Micronas
9389X
Parameter Low-Level Input Voltage High-Level Input Voltage Delay Inputs: SDA/SCL Schmitt Trigger Hysteresis Low-Level Output Voltage Low-Level Output Voltage Output Fall Time from min(VIH) max(VIL)
Symbol
Limit Values min. typ. max. VDD+
Unit
Remark
-0.25
VDD(min)<VDD< VDD(max) VDD(min)<VDD< VDD(max)
Vhys
tested
Input Output: (Referenced SCL; Open Drain Output) 20+0. 1*Cb IOL=3mA IOL=max 10pFCb400pF
Analog Inputs CVBS1.3 Note: VDDA=nom, TA=nom CVBS Input Leakage Current CVBS Input Capacitance Input Clamping Error Input Clamping Current max. Input Clamping Current deviation Reference Voltage Difference D.C. Differential Nonlinearity |ICLP| |ICLPx|/ |ICLP| VREFHVREFL -100 clamping inactive tested
settled state VDDA1=5V dependent clamping error
VREFH-VREFL
Micronas
9389X
Characteristics Parameter Crosstalk between CVBS Inputs Symbol Limit Values min. typ. max. Unit Remark
Digital Analog Converters (6-bit): Outputs OUT1, OUT2, OUT3 Note: VDDA=nom, TA=nom D.C. Differential Nonlinearity Full Range Output Voltage Full Range Output Voltage Output Voltage DNLE +/-0.5 CON, UAMP, VAMP, YAMP CON, UAMP, VAMP, YAMP CON, UAMP, VAMP, YAMP default, VREF const.
Deviation OUT1-3 (matching) Contrast Increase Output Amplitude Ratio (UOH-UOL)/UOL Brightness Increase Pedestal Level variation Reference Voltage Dependence Output Voltage Temperature Dependence Output Voltage switch Input Voltage Range Bandwith (-3dB) Gain
please refer figure 10-3 please refer figure 10-3
please refer figure 10.3 please refer figure 10-2 please refer figure 10-1
RL>10k; CL=20pF
Micronas
9389X
Parameter Gain Difference Crosstalk Between Inputs Isolation (off state) Clamping Level Difference Output Clamping Capacitor Colordecoder Horizontal Permissible Static Deviation Horizontal Permissible Static Deviation Chroma pull-inrange Color Killer
Symbol
Limit Values min. typ. max.
Unit
Remark f<4MHz f=5MHz, f=5MHz
between external internal source VCR1 VCR2 (PLLITC='00' '01') (PLLITC='10' '11') nominal crystal frequency CKILL='00' CKILL='01' CKILL='10'
fHf/fH
fHf/fH
+/500
Note: listed characteristics ensured over operating range integrated circuit. Typical characteristics specify mean values expected over production spread. otherwise specified, typical characteristics apply given supply voltage.
Micronas
9389X
Diagrams
10.1
Diagrams
Output Voltage Converters
Nominal values: VDDA=5V; TA=25°C
Figure 10-1 Output voltage dependency temperature
Micronas
9389X
Figure 10-2 Output voltage dependency Uref
Micronas
9389X
Diagrams
BRIGHT
Figure 10-3 Output voltage dependency YAMP, BRIGHT
Micronas
9389X
10.2
Three level input characteristic (SCP, VP/SCP)
2V.3V 4V.V DD+0.5V
-0.25V.1V
Figure 10-4 input voltages VP/SCP
Micronas
9389X
*crystal dependent only used third overtone crystal
13.5 10p* 10p*
Application Circuit
100n 330R 100n 100n
CVBS1 VREFH CVBS2 VREFL CVBS3 VSSA1 VDDA1 VREF VSSA2 XFREQ VDDA2 OUT1 OUT2 OUT3 SDA9388 SDA9389X
100n
100n
100n
100R
100R
BLKin
CVBS3in CVBS2in CVBS1in
HP/SCP
Micronas SIEMENS
Title
PIP3-Board C-DSO-28 Size Date:
2916sie234 Sheet
Application Circuit
Micronas
9389X
Clock Circuitry Diagram
more details, please refer chapter 5.1. crystal (third overtone mode)
xtal
10pF 10pF
Figure 12-1 crystal (third overtone mode)
xtal
Figure 12-2 13.5 crystal fundamental mode)
Micronas
9389X
Package
Package
P-DSO-28-1
Micronas
9389X
Micronas GmbH Hans-Bunte-Strasse D-79108 Freiburg (Germany) P.O. D-79008 Freiburg (Germany) Tel. +49-761-517-0 +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed Germany Order 6251-550-1PD
information data contained this data sheet without commitment, considered offer conclusion contract, shall they construed create liability. issue this data sheet invalidates previous issues. Product availability delivery exclusively subject respective order confirmation form; same applies orders based development samples delivered. this publication, Micronas GmbH does assume responsibility patent infringements other rights third parties which result from use. Further, Micronas GmbH reserves right revise this publication make changes content, time, without obligation notify person entity such revisions changes. part this publication reproduced, photocopied, stored retrieval system, transmitted without express written consent Micronas GmbH.
Micronas

Edition March 2001 6251-550-1PD Digital Picture-in-Picture (PIP)

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